Dynamic comparator and voltage calibration method thereof

Abstract

The invention discloses a dynamic comparator and a voltage calibration method thereof, relates to the field of dynamic comparators, and is used for improving the comparison precision of the dynamic comparator in a mode of not sacrificing the power consumption and the efficiency of the dynamic comparator. A kickback noise suppression circuit is connected to a tail current tube of an input geminate transistor to adjust the switching time of a clock signal, a calibration crystal geminate transistor is connected to a regeneration node of the input geminate transistor, and a reference voltage is adjusted through a resistor string DAC to calibrate an offset voltage. The kickback noise is effectively suppressed by adjusting the slew rate of the clock signal of the tail current tube, the calibration speed is increased through the two-stage resistor string DAC, the crystal pair tube is controlled and calibrated by multiplexing the adjusted clock signal, and the calibration precision is improved.

Description

Technical Field

[0001] The present invention relates to the field of dynamic (latch) comparators, and in particular to a dynamic comparator and its voltage calibration method. Background Art

[0002] With the continuous pursuit of improving the information processing speed in modern digital systems such as digital signal processing chips and communication infrastructures, as a core device in these systems, the performance requirements for ADC (Analog-to-Digital Converter) are getting higher and higher. As one of the basic modules of ADC, the circuit design and performance optimization of the comparator also affect the overall performance of ADC. Among them, the dynamic comparator is widely used in the circuit design of high-performance ADCs due to its advantages of low power consumption, high speed, and good process compatibility.

[0003] Although with the continuous reduction of the CMOS process size, the speed of the dynamic comparator has been improved, and the power consumption and area have been continuously reduced, the reduction in size has also led to more serious device mismatches, resulting in a larger offset of the dynamic comparator. In addition, the severe kickback noise of the dynamic comparator also restricts its application in high-precision ADCs. The kickback noise is caused by the voltage fluctuations at the drain and source of the input crystal pair transistors. A large voltage swing reaches the input terminal through the drain-gate parasitic capacitance or source-gate, causing fluctuations in the input terminal voltage. Therefore, in a small-amplitude input, the influence of the kickback noise will change the output of the comparator, thereby reducing the resolution of the ADC.

[0004] Currently, the commonly used methods for reducing kickback noise are mainly divided into two categories: The first category is to split the traditional comparator into two parts and add a dual transistor on the input crystal pair transistors in the dual-tail dynamic latch comparator to reduce the direct coupling of the parasitic capacitance from the output node of the first stage to the input node of the comparator. Therefore, these nodes are isolated from each other to reduce the kickback noise. However, these additional transistors will also introduce offset and increase the overall power consumption of the comparator. The other category is to remove the tail transistor in the traditional dynamic latch comparator and add two clock transistors between the input pair and the latch transistor, which can eliminate the common-mode kickback noise caused by the source grounding of the input pair transistors. However, due to the addition of the clock pair, the offset error of this structure will be accumulated. There are also some methods that add a preamplifier to reduce the equivalent input noise of the comparator. This way of adding a preamplifier will increase the overall power consumption and is not suitable for the application of low-power ADCs.

[0005] There are mainly two types of commonly used comparator offset calibration methods: load capacitance adjustment offset calibration and input / output offset storage technology. Load capacitance adjustment offsets the offset voltage of the comparator by adjusting the load capacitance at the differential output of the preamplifier stage of the comparator, so that the charging and discharging speeds at the differential output of the preamplifier stage are different during the initial amplification stage. Among them, the adjustment of the load capacitance can be achieved by a configurable capacitor array or a voltage-controlled MOS capacitor. The capacitor array is realized by connecting multiple capacitors in series with switches, and different-sized load capacitors are connected to the differential output by selecting the switches. The voltage-controlled MOS capacitor is realized by a MOS transistor with its gate connected to the differential output and its source, drain, and body terminals all connected to the auxiliary calibration voltage. Calibration is achieved by controlling the switches or calibration voltage with the calibration information stored in the memory in the calibration mode. The offset voltage calibration range and accuracy of this method depend on the corresponding number of capacitors. The more the number, the better the calibration performance, and additional storage units and control logic are required. This method consumes a large area, and the added capacitors will affect the speed of the comparator, and the preamplifier stage will increase power consumption. Another input / output offset storage technology adds a combination of switches and capacitors to the input path or output path, additionally introducing a clock tree, increasing complexity, and the capacitors in the signal path will affect the operating speed of the comparator. In addition, input offset storage requires a large capacitor to overcome the clock feedthrough effect caused by the switch opening, which will also affect the establishment time of the comparator input voltage. Summary of the Invention

[0006] The object of the present invention is to provide a dynamic comparator and its voltage calibration method to improve the comparison accuracy of the dynamic comparator without sacrificing the power consumption and efficiency of the dynamic comparator for all or part of the above-mentioned problems.

[0007] The technical solution adopted by the present invention is as follows:

[0008] A dynamic comparator, the dynamic comparator includes a negative input terminal VIN, a positive input terminal VIP, a negative output terminal VOUTN and a positive output terminal VOUTP; the negative input terminal VIN is connected to the gate of an NMOS transistor M1, the positive input terminal VIP is connected to the gate of an NMOS transistor M2, the sources of the NMOS transistor M1 and the NMOS transistor M2 are connected in parallel to the drain of an NMOS transistor M3, the source of the NMOS transistor M3 is grounded, and the gate of the NMOS transistor M3 is connected to a clock signal; the drain of the NMOS transistor M1 is connected to the source of an NMOS transistor M5 and the drain of a PMOS transistor M11; the drain of the NMOS transistor M2 is connected to the source of an NMOS transistor M6 and the drain of a PMOS transistor M12; the gate of the NMOS transistor M5 is respectively connected to the gate of a PMOS transistor M7, the drain of a PMOS transistor M8, the drain of a PMOS transistor M10, the positive output terminal VOUTP and the drain of the NMOS transistor M6; the gate of the NMOS transistor M6 is respectively connected to the gate of the PMOS transistor M8, the drain of the PMOS transistor M7, the drain of a PMOS transistor M9, the negative output terminal VOUTN and the drain of the NMOS transistor M5; the sources of the PMOS transistor M7, the PMOS transistor M8, the PMOS transistor M9, the PMOS transistor M10, the PMOS transistor M11 and the PMOS transistor M12 are all connected to a power supply AVDD; the gates of the PMOS transistor M9, the PMOS transistor M10, the PMOS transistor M11 and the PMOS transistor M12 are respectively connected to the clock signal;

[0009] The clock signal is connected to the gate of the NMOS transistor M3 through a kickback noise suppression circuit, and the kickback noise suppression circuit is configured to increase the time of the rising edge of the clock signal.

[0010] Further, the kickback noise suppression circuit is formed by connecting multiple levels of CMOS transmission gates in parallel.

[0011] Further, each level of the CMOS transmission gate includes at least a pair of PMOS transistors and NMOS transistors connected in parallel, the drains of the PMOS transistor and the NMOS transistor are connected in parallel to the clock signal; the sources of the PMOS transistor and the NMOS transistor are connected in parallel to the gate of the NMOS transistor M3; the gates of the PMOS transistor and the NMOS transistor are respectively connected to control signals with opposite polarities.

[0012] Further, the number of PMOS transistors and NMOS transistors connected in parallel included in each level of the CMOS transmission gate is different.

[0013] Further, an offset voltage calibration circuit is connected to the drains of the NMOS transistor M1 and the NMOS transistor M2. The offset voltage calibration circuit is configured to compensate the voltages of the drains of the NMOS transistor M1 and the NMOS transistor M2 by comparing a reference voltage VREF and a common-mode voltage VCM, and adjust the reference voltage VREF through a resistor string DAC.

[0014] Further, the offset voltage calibration circuit includes an NMOS transistor MC1, an NMOS transistor MC2, and an NMOS transistor M4. The drain of the NMOS transistor MC1 is connected to the drain of the NMOS transistor M1, and the drain of the NMOS transistor MC2 is connected to the drain of the NMOS transistor M2. The sources of the NMOS transistor MC1 and the NMOS transistor MC2 are connected in parallel to the drain of the NMOS transistor M4. The source of the NMOS transistor M4 is grounded, and the gate of the NMOS transistor M4 receives the clock signal. The gate of the NMOS transistor MC1 receives the reference voltage VREF, and the gate of the NMOS transistor MC2 receives the common-mode voltage VCM.

[0015] Further, the gate of the NMOS transistor M4 is connected in parallel to the gate of the NMOS transistor M3.

[0016] Further, the resistor string DAC includes a first resistor string DAC branch, a second resistor string DAC branch, and a third resistor string DAC branch. One end of the first resistor string DAC branch is connected to a positive reference voltage VREFP, and the other end is connected to the common-mode voltage VCM. One end of the second resistor string DAC branch is connected to a negative reference voltage VREFN, and the other end is connected to the common-mode voltage VCM. The output ends of the first resistor string DAC branch and the second resistor string DAC branch are connected in parallel to one end of the third resistor string DAC branch. The other end of the third resistor string DAC branch is connected to the common-mode voltage VCM. The output end of the third resistor string DAC outputs the reference voltage VREF.

[0017] Further, the switches in the resistor string DAC all adopt CMOS transmission gates.

[0018] The present invention also provides a voltage calibration method for the above dynamic comparator, which includes:

[0019] S1. Input the common-mode voltage VCM into the negative input terminal VIN and the positive input terminal VIP of the dynamic comparator respectively, connect the reference voltage VREF and the common-mode voltage to the offset voltage calibration circuit respectively, and run for one clock signal period;

[0020] S2. Compare the voltages of the negative output terminal VOUTN and the positive output terminal VOUTP to determine the polarity of the offset voltage; judge the magnitude relationship between the common-mode voltage VCM and the reference voltage VREF according to the polarity of the offset voltage;

[0021] S3. Adjust the reference voltage VREF by using the offset voltage calibration circuit according to the magnitude relationship between the common-mode voltage VCM and the reference voltage VREF;

[0022] S4. Repeat steps S2 and S3 until the voltages output by the negative output terminal VOUTN and the positive output terminal VOUTP each account for half of the high and low levels for a long time.

[0023] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention are as follows:

[0024] 1. For the traditional kickback noise suppression technology of dynamic comparators, it will split the comparator structure and add transistors connected to the input pair transistors of the comparator to form a double-tail current comparator, which can isolate the input and output nodes. However, the additional structure introduced will increase power consumption and area. The kickback noise suppression circuit adopted by the present invention controls the slew rate of the rising edge of the clock signal CLK of the tail current source (NMOS transistor M3) to more smoothly control the voltage slew rate of the dynamic comparator node, thereby greatly reducing the kickback noise of the dynamic comparator without introducing additional power consumption and improving the suppression efficiency.

[0025] 2. For the traditional offset voltage calibration method of dynamic comparators, it will adopt the means of adjusting the load capacitance. Adjusting the load capacitance of the pre-amplification stage will cause the time of the amplification stage of the comparator to become longer, resulting in the problem of reduced comparison speed. The present invention uses the gate voltage of the input transistor of the offset voltage calibration circuit. In order to accelerate the calibration speed, two quantization intervals with different step sizes, namely the coarse quantization of the first / second resistor string DAC branch and the fine quantization of the third resistor string DAC branch, can greatly shorten the calibration time.

[0026] 3. For the existing technology of adjusting the gate voltage of the calibration input transistor, it does not consider that the kickback noise will also act on the drain and source of the calibration input pair transistors, introducing errors into the calibration circuit. The present invention multiplexes the clock signal CLK slew rate circuit on the tail current transistor (NMOS transistor M4) of the calibration crystal pair transistors of the offset voltage calibration circuit, which can effectively reduce the influence of the kickback noise on the calibration circuit and greatly improve the calibration accuracy. Description of the Drawings

[0027] The present invention will be described by way of examples and with reference to the drawings, where:

[0028] Figure 1 is the structural diagram of the dynamic comparator provided by the embodiment of the present application.

[0029] Figure 2 It is a structural diagram of a kickback noise suppression circuit provided by an embodiment of the present application.

[0030] Figure 3 It is a structural diagram of an offset voltage calibration circuit provided by an embodiment of the present application. Detailed implementation manners

[0031] All features disclosed in this specification, or all steps in the disclosed methods or processes, except for mutually exclusive features and / or steps, can be combined in any manner.

[0032] Any feature disclosed in this specification (including any additional claims, abstract) can be replaced by other equivalent or similar-purpose alternative features unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is only an example of a series of equivalent or similar features.

[0033] In view of the phenomenon that kickback noise and offset voltage naturally exist in a dynamic comparator, and the current situation that it is difficult for the prior art to balance reducing kickback noise and offset voltage calibration without causing additional burdens (such as reducing the operating efficiency of the comparator, increasing the area of the comparator, etc.), an embodiment of the present application proposes a dynamic comparator and its voltage calibration method, aiming to reduce the overall kickback noise of the comparator while calibrating the offset voltage.

[0034] Such as Figure 1As shown, the dynamic comparator proposed in this application includes a negative input terminal VIN, a positive input terminal VIP, a negative output terminal VOUTN, and a positive output terminal VOUTP. The negative input terminal VIN is connected to the gate of NMOS transistor M1, the positive input terminal VIP is connected to the gate of NMOS transistor M2. The sources of the NMOS transistor M1 and the NMOS transistor M2 are connected in parallel to the drain of NMOS transistor M3. The source of the NMOS transistor M3 is grounded, and the gate of the NMOS transistor M3 is connected to a clock signal. The drain of the NMOS transistor M1 is connected to the source of NMOS transistor M5 and the drain of PMOS transistor M11. The drain of the NMOS transistor M2 is connected to the source of NMOS transistor M6 and the drain of PMOS transistor M12. The gate of the NMOS transistor M5 is respectively connected to the gate of PMOS transistor M7, the drain of PMOS transistor M8, the drain of PMOS transistor M10, the positive output terminal VOUTP, and the drain of the NMOS transistor M6. The gate of the NMOS transistor M6 is respectively connected to the gate of the PMOS transistor M8, the drain of the PMOS transistor M7, the drain of PMOS transistor M9, the negative output terminal VOUTN, and the drain of the NMOS transistor M5. The sources of the PMOS transistor M7, PMOS transistor M8, PMOS transistor M9, PMOS transistor M10, PMOS transistor M11, and PMOS transistor M12 are all connected to the power supply AVDD. The gates of the PMOS transistor M9, PMOS transistor M10, PMOS transistor M11, and PMOS transistor M12 are respectively connected to the clock signal CLK. This clock signal CLK is a TTL signal, that is, an alternating high and low level signal.

[0035] The dynamic comparator provided by the embodiment of this application further includes a kickback noise suppression circuit for reducing the kickback noise of the dynamic comparator, including common-mode kickback noise and differential-mode kickback noise. This kickback noise suppression circuit is connected between the clock signal CLK and the gate of the NMOS transistor M3. This kickback noise suppression circuit is configured to increase the time of the rising edge of the clock signal.

[0036] The operation of the dynamic comparator is divided into two stages. In the first stage, the clock signal CLK is at a low level. At this time, the PMOS transistors M9, M10, M11, and M12 are in the on state as switches, and the dynamic comparator is reset, that is, the dynamic comparator does not work. In the second stage, the clock signal CLK changes from low level to high level, and the dynamic comparator starts to work. The PMOS transistors M, M10, M11, and M12 are in the off state as switches. According to the differential-mode signal of the input pair transistors (NMOS transistors M1 and M2) of the dynamic comparator, two cross-coupled positive feedback units start to work, causing the output voltage of the dynamic comparator to tend to reach zero or the power supply voltage from a small original voltage.

[0037] The kickback noise of the dynamic comparator is generated during this stage, thus affecting the correct result of the dynamic comparator output. The specific process analysis is as follows: Refer to Figure 2 As shown, when the input signal is applied to the dynamic comparator, the regeneration nodes VP and VQ, which are the drains of the input pair transistors NMOS M1 and M2 and also the sources of the cross-coupled positive feedback transistors - NMOS M5 and M6, decrease towards the ground at unequal rates. Eventually, the voltage values at points VP and VQ fluctuate significantly from zero to the supply voltage. This voltage fluctuation is coupled to the gates of the input pair transistors - NMOS M1 and M2 through the parasitic capacitances CGD1 and CGD2, generating differential-mode kickback noise. The reason for the common-mode kickback noise is that when the clock signal CLK transitions from low to high and the tail current transistor (NMOS M3) conducts, the fluctuation of the clock signal CLK is coupled to the source VA of the input pair transistors M1 and M2 through the parasitic capacitance CGD3, and the tail current transistor M3 then draws drain current from the parasitic capacitances CGS1 and CGS2 to generate common-mode kickback noise. When the rising edge of the clock signal CLK acts, the tail current transistor M3 conducts and the node VA is grounded, and the input pair transistors M1 and M2 enter the saturation region. At this time, the channel charge Q ch is:

[0038]

[0039] where, W is the channel depletion capacitance, L is the effective channel length, C ox is the gate oxide capacitance per unit area, V cm is the voltage value of the common-mode voltage VCM of the dynamic comparator, V th is the threshold voltage of NMOS transistors M1 and M2. Therefore, the charge Q G on the gates of NMOS transistors M1 and M2 can be sensed as:

[0040]

[0041] C GSO is the capacitance value of the parasitic capacitance CGS1 / CGS2, and C GDO is the capacitance value of the parasitic capacitance CGD1 / CGD2. Following that the differential of charge with respect to time is current, the kickback current can be obtained as:

[0042]

[0043] It is analyzed from formula (3) that the kickback current is the conclusion of the reciprocal of the voltages of nodes VA and VP with respect to time. Based on this conclusion, a load capacitor can be added to reduce the voltage slew rate of nodes VA and VP in exchange for a reduction in kickback noise. However, this will also reduce the output speed of the comparator. In some embodiments of the present application, by controlling the conversion speed of the clock signal CLK of the dynamic comparator, the conversion rate of the source and drain voltages of the input pair of transistors M1 and M2 is controlled to reduce the voltage slew rate of the clock signal CLK, so that the voltage slew rates of nodes VP, VQ, and virtual ground VA during the regeneration stage are also reduced, thereby significantly reducing the common-mode kickback noise and differential-mode kickback noise of the dynamic comparator.

[0044] As an alternative implementation, the kickback noise suppression circuit is formed by connecting multiple levels of CMOS transmission gates in parallel. The multiple levels of parallel-connected CMOS transmission gates form an equivalent resistance and parasitic capacitance, thereby controlling the rise and fall times of the clock signal CLK. In some specific implementations, the number of CMOS transmission gates in each level is different, and the number increases sequentially, so as to sequentially increase the CMOS switch size to more smoothly control the rise and fall times of the clock signal CLK. During the falling time of the clock signal CLK, the switch conducts to discharge the output capacitance. Although the falling edge of the clock signal CLK will also be controlled, it does not affect the improvement of the kickback noise because the dynamic comparator is entering the reset stage at this time.

[0045] As an alternative implementation, in each level of the parallel-connected CMOS transmission gates, except for one level that includes 1 CMOS transmission gate, the number of CMSO transmission gates included in other levels is in arithmetic progression. For example, for 5 levels of CMOS transmission gates, the other levels are 2, 4, 6, and 8 CMOS transmission gates in sequence. A series of switch sizes in arithmetic progression are used to form a slow conversion rate control, and the conduction order is from small size to large size (i.e., the levels with a small number of CMOS transmission gates conduct first), so a smoother power / ground current absorption can be obtained, effectively reducing the kickback noise.

[0046] As shown in Figure 2 In some alternative implementations, each level of the CMOS transmission gate includes at least a pair of PMOS transistors and NMOS transistors connected in parallel, that is, each CMOS transmission gate is formed by connecting a PMOS transistor and an NMOS transistor in parallel. The drains of the PMOS transistor and the NMOS transistor are connected in parallel to the clock signal; the sources of the PMOS transistor and the NMOS transistor are connected in parallel to the gate of the NMOS transistor M3; the gates of the PMOS transistor and the NMOS transistor are respectively connected to control signals with opposite polarities.

[0047] As an alternative implementation, as shown in Figure 3As shown, an offset voltage calibration circuit is connected to the drains of NMOS transistor M1 and NMOS transistor M2. The offset voltage calibration circuit is configured to compensate the voltages at the drains of NMOS transistor M1 and NMOS transistor M2 by comparing a reference voltage VREF and a common-mode voltage VCM, and to adjust the reference voltage VREF through a resistor string DAC (digital-to-analog converter).

[0048] As an alternative implementation, referring to Figure 3 , the offset voltage calibration circuit includes NMOS transistors MC1, MC2, and M4. The drain of NMOS transistor MC1 is connected to the drain of NMOS transistor M1, and the drain of NMOS transistor MC2 is connected to the drain of NMOS transistor M2; the sources of NMOS transistor MC1 and NMOS transistor MC2 are connected in parallel to the drain of NMOS transistor M4, the source of NMOS transistor M4 is grounded, and the gate of NMOS transistor M4 receives the clock signal CLK. The gate of NMOS transistor MC1 receives the reference voltage VREF, which is adjusted and output by the offset voltage calibration circuit mentioned in the previous embodiment. The gate of NMOS transistor MC2 receives the common-mode voltage VCM. By adjusting the reference voltage VREF applied to the gate of NMOS transistor MC1 through the offset voltage calibration circuit, the voltage difference between the gate voltage of NMOS transistor MC1 and the gate voltage of NMOS transistor MC2 is adjusted, thereby compensating for the offset voltage at the drains of input pair transistors M1 and M2.

[0049] In some alternative embodiments, the gate of NMOS transistor M4 is connected in parallel to the gate of NMOS transistor M3, that is, the clock signal CLK processed by the kickback noise suppression circuit is reused in the offset voltage calibration circuit, and the rising edge of the adjusted clock signal CLK is reused in NMOS transistor M4 of the offset voltage calibration circuit, thereby avoiding errors generated by the offset voltage calibration circuit and affecting the accuracy of the dynamic comparator.

[0050] In some alternative implementations, the resistor string DAC includes a first resistor string DAC branch, a second resistor string DAC branch, and a third resistor string DAC branch. One end of the first resistor string DAC branch is connected to the positive reference voltage VREFP, and the other end is connected to the common-mode voltage VCM; one end of the second resistor string DAC branch is connected to the negative reference voltage VREFN, and the other end is connected to the common-mode voltage VCM; the output ends of the first resistor string DAC branch and the second resistor string DAC branch are connected in parallel to one end of the third resistor string DAC branch, and the other end of the third resistor string DAC branch is connected to the common-mode voltage VCM; the output end of the third resistor string DAC outputs the reference voltage VREF.

[0051] AsFigure 3 As shown in Figure 3 , the first resistor string DAC branch includes resistors R1, R2, and R3 connected in series. Resistor R1 is connected to the positive reference voltage VREFP, and resistor R3 is connected to the common mode voltage VCM. Between resistor R1 and resistor R2, and between resistor R2 and resistor R3, first-stage switches are respectively connected, and these two first-stage switches are connected in parallel to the second-stage switch. The second resistor string DAC branch includes resistors R4, R5, and R6 connected in series. Resistor R4 is connected to the common mode voltage VCM, and resistor R6 is connected to the negative reference voltage VREFN. Between resistor R4 and resistor R5, and between resistor R5 and resistor R6, first-stage switches are respectively connected, and these two first-stage switches are connected in parallel to the second-stage switch. The third resistor string DAC includes resistors R7, R8, R9, R10, R11, R12, R13, R4, and R15 connected in series. The two aforementioned second-stage switches are connected in parallel to resistor R7, and resistor R15 is connected to the common mode voltage VCM. Between every two adjacent resistors in the third resistor string DAC branch, a third-stage switch is connected, and each third-stage switch outputs the reference voltage VREF in parallel. Each switch is controlled by a control signal to change its switch state.

[0052] The resistor string DAC composed of the first resistor string DAC branch, the second resistor string DAC branch, and the third resistor string DAC branch as described above, wherein the first resistor string DAC branch and the second resistor string DAC branch can achieve coarse quantization of the reference voltage VREF, and the third resistor string DAC branch can achieve fine quantization of the reference voltage VREF. The cooperation of coarse quantization and fine quantization can improve the speed of offset voltage calibration.

[0053] As an optional implementation manner, the switches in the resistor string DAC all adopt CMOS transmission gates, that is, the first-stage switches, the second-stage switches, and the third-stage switches in the foregoing embodiments are all CMOS transmission gates, and each CMOS transmission gate is controlled by a control signal to change its switch state.

[0054] Based on the dynamic comparator in the foregoing embodiments, the embodiments of the present application provide a voltage calibration method for a dynamic comparator, and the method includes:

[0055] S1. Input the common mode voltage VCM into the negative input terminal VIN and the positive input terminal VIP of the dynamic comparator respectively, connect the reference voltage VREF and the common mode voltage to the offset voltage calibration circuit respectively, and run for one clock signal cycle;

[0056] S2. Compare the voltages of the negative output terminal VOUTN and the positive output terminal VOUTP to determine the polarity of the offset voltage; judge the magnitude relationship between the common mode voltage VCM and the reference voltage VREF according to the polarity of the offset voltage;

[0057] ​S3. Adjust the reference voltage VREF by using the offset voltage calibration circuit according to the magnitude relationship between the common-mode voltage VCM and the reference voltage VREF;

[0058] S4. Repeat steps S2 and S3 until the voltages output at the negative output terminal VOUTN and the positive output terminal VOUTP are each at a high level and a low level for half of the long time (it is sufficient that they are approximately each at half, and the judgment criterion for the high and low level ratios tending to be the same can be defined by the threshold of the difference between the high and low ratios).

[0059] In the calibration mode, both input terminals of the dynamic comparator are connected to the common-mode voltage VCM, the gate of the NMOS transistor MC2 is connected to the common-mode level VCM, and the gate of the NMOS transistor MC1 is connected to the reference voltage VREF output after voltage division by the resistor string DAC. The resistor string DAC is divided into coarse quantization and fine quantization, and the calibration voltages with two step sizes can greatly improve the calibration speed. Due to the existence of the offset voltage, the comparison result of the dynamic comparator will always be at a high level or a low level. First, the dynamic comparator operates for one cycle to determine the polarity of the offset voltage, with one output being high and one output being low. Secondly, according to the polarity of the offset voltage, it is determined whether the value of the reference voltage VREF is greater than or less than the common-mode voltage VCM. Subsequently, according to whether the result of the dynamic comparator flips each time, the coarse quantization interval and the fine quantization interval of the resistor string DAC are determined. If the offset voltage calibration of the dynamic comparator is finally completed, the long-time output result of the dynamic comparator should be close to half high level and half low level. At this time, the current difference caused by the mismatch of the input pair transistors M1 and M2 is compensated by the mismatch current generated by the deviation of the gate voltages of the calibration crystal pair transistors MC1 and MC2.

[0060] The present invention is not limited to the foregoing specific embodiments. The present invention extends to any new feature or any new combination disclosed in this specification, as well as any new method or process step or any new combination disclosed.

Claims

1. A dynamic comparator, characterized in that: The dynamic comparator comprises a negative input terminal VIN, a positive input terminal VIP, a negative output terminal VOUTN and a positive output terminal VOUTP; the negative input terminal VIN is connected to the gate of the NMOS tube M1, the positive input terminal VIP is connected to the gate of the NMOS tube M2, the source of the NMOS tube M1 and the source of the NMOS tube M2 are connected in parallel to the drain of the NMOS tube M3, the source of the NMOS tube M3 is grounded, and the gate of the NMOS tube M3 is connected to the clock signal; the drain of the NMOS tube M1 is connected to the source of the NMOS tube M5 and the drain of the PMOS tube M11; the drain of the NMOS tube M2 is connected to the source of the NMOS tube M6 and the drain of the PMOS tube M12; the gate of the NMOS tube M5 is connected to the source of the NMOS tube M5 and the drain of the PMOS tube M11; the drain of the NMOS tube M2 is connected to the source of the NMOS tube M6 and the drain of the PMOS tube M12; the gate of the NMOS tube M5 is connected to the source of the NMOS tube M5 and the drain of the PMOS tube M12; the gate of the NMOS tube M5 is connected to the source of the NMOS tube M5 and the drain of the PMOS tube M11; the gate of the NMOS tube M5 is connected to the source of the NMOS tube M5 and the drain of the PMOS tube M12 ... The gate of the PMOS tube M7, the drain of the PMOS tube M8, the drain of the PMOS tube M10, the positive output terminal VOUTP and the drain of the NMOS tube M6 are respectively connected; the gate of the NMOS tube M6 is respectively connected to the gate of the PMOS tube M8, the drain of the PMOS tube M7, the drain of the PMOS tube M9, the negative output terminal VOUTN and the drain of the NMOS tube M5; the sources of the PMOS tube M7, the PMOS tube M8, the PMOS tube M9, the PMOS tube M10, the PMOS tube M11 and the PMOS tube M12 are all connected to the power supply AVDD; the gates of the PMOS tube M9, the PMOS tube M10, the PMOS tube M11 and the PMOS tube M12 are respectively connected to the clock signal; The clock signal is connected to the gate of the NMOS transistor M3 via a kickback noise suppression circuit, and the kickback noise suppression circuit is configured to increase the time of the rising edge of the clock signal.

2. The dynamic comparator according to claim 1, characterized in that: The kickback noise suppression circuit is formed by connecting multiple stages of CMOS transmission gates in parallel.

3. The dynamic comparator according to claim 2, characterized in that: Each level of the CMOS transmission gate includes at least a pair of PMOS tubes and NMOS tubes connected in parallel, the drain of the PMOS tube and the drain of the NMOS tube are connected in parallel to the clock signal; the source of the PMOS tube and the source of the NMOS tube are connected in parallel to the gate of the NMOS tube M3; the gate of the PMOS tube and the gate of the NMOS tube are respectively connected to control signals with opposite polarities.

4. The dynamic comparator according to claim 3, characterized in that: The numbers of PMOS tubes and NMOS tubes connected in parallel in each stage of the CMOS transmission gate are different.

5. The dynamic comparator according to any one of claims 1 to 4, characterized in that: An offset voltage calibration circuit is connected to the drain of the NMOS tube M1 and the drain of the NMOS tube M2. The offset voltage calibration circuit is configured to compensate the voltage of the drain of the NMOS tube M1 and the drain of the NMOS tube M2 respectively by comparing the reference voltage VREF and the common mode voltage VCM, and adjust the reference voltage VREF through a resistor string DAC.

6. The dynamic comparator according to claim 5, characterized in that: The offset voltage calibration circuit includes an NMOS tube MC1, an NMOS tube MC2 and an NMOS tube M4; the drain of the NMOS tube MC1 is connected to the drain of the NMOS tube M1, and the drain of the NMOS tube MC2 is connected to the drain of the NMOS tube M2; the source of the NMOS tube MC1 and the source of the NMOS tube MC2 are connected in parallel to the drain of the NMOS tube M4, the source of the NMOS tube M4 is grounded, and the gate of the NMOS tube M4 is connected to the clock signal; the gate of the NMOS tube MC1 is connected to the reference voltage VREF, and the gate of the NMOS tube MC2 is connected to the common mode voltage VCM.

7. The dynamic comparator according to claim 5, characterized in that: The gate of the NMOS transistor M4 is connected in parallel to the gate of the NMOS transistor M3.

8. The dynamic comparator according to claim 5, characterized in that: The resistor string DAC includes a first resistor string DAC branch, a second resistor string DAC branch and a third resistor string DAC branch; one end of the first resistor string DAC branch is connected to a positive reference voltage VREFP, and the other end is connected to the common mode voltage VCM; one end of the second resistor string DAC branch is connected to a negative reference voltage VREFN, and the other end is connected to the common mode voltage VCM; the output ends of the first resistor string DAC branch and the second resistor string DAC branch are connected in parallel to one end of the third resistor string DAC branch, and the other end of the third resistor string DAC branch is connected to the common mode voltage VCM; the output end of the third resistor string DAC outputs the reference voltage VREF.

9. The dynamic comparator according to claim 8, characterized in that: The switches in the resistor string DAC are all CMOS transmission gates.

10. The voltage calibration method of a dynamic comparator according to any one of claims 5 to 9, characterized in that: include: S1, input the common mode voltage VCM into the negative input terminal VIN and the positive input terminal VIP of the dynamic comparator respectively, connect the reference voltage VREF and the common mode voltage to the offset voltage calibration circuit respectively, and run one clock signal cycle; S2, comparing the voltage of the negative output terminal VOUTN and the voltage of the positive output terminal VOUTP to determine the polarity of the offset voltage; judging the magnitude relationship between the common mode voltage VCM and the reference voltage VREF according to the polarity of the offset voltage; S3, adjusting the reference voltage VREF by using an offset voltage calibration circuit according to the magnitude relationship between the common mode voltage VCM and the reference voltage VREF; S4, repeating the steps S2 and S3 until the voltage outputted by the negative output terminal VOUTN and the positive output terminal VOUTP is half high and half low for a long time.

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