Special large model aided design method and system for hardware design

Abstract

The invention belongs to the technical field of cross application of an artificial intelligence large language model and hardware design, and provides a hardware design-oriented special large model aided design method and system, and the method comprises the steps: obtaining an original code data set; the original code data set is preprocessed, and a hardware description language code database meeting the hardware design requirement is constructed and obtained; generating a multi-level code description pair data set based on the hardware language code database meeting the hardware design requirements and the constructed multi-level description mechanism; wherein the construction process of the multi-level description mechanism comprises the step of constructing a special large language model designed for hardware on the basis of a multi-level code description pair data set. The large language model can better meet the requirements of the hardware design field, the accuracy and reliability of the generated content are improved, and powerful support is provided for development of hardware design.

Description

Technical Field

[0001] The present invention belongs to the technical field of the cross - application of artificial intelligence large language models (LLMs) and hardware design, and particularly relates to a dedicated large - model assisted design method and system for hardware design. Background Technique

[0002] The statements in this part merely provide background technical information related to the present invention and do not necessarily constitute prior art.

[0003] Against the background of the rapid development of current integrated circuits (ICs) and electronic design automation (EDA) tools, the complexity and scale of hardware design continue to grow. Traditionally, the hardware design process relies on engineers' experience and manual operations, which is not only inefficient but also prone to introducing human errors. To address these challenges, intelligent assisted design based on large language models (LLMs) has gradually become possible, providing a new opportunity to improve the efficiency and quality of hardware design.

[0004] In recent years, the progress of deep learning and natural language processing technologies has made intelligent assisted design based on LLMs possible. These models can understand natural - language descriptions and convert them into hardware description languages (HDLs), such as Verilog or VHDL, thus enabling the automatic generation of RTL (register transfer level) code from specifications. This method can not only reduce manual intervention but also significantly improve the speed and accuracy of the design process. However, the main challenge in the development of large language models for hardware design lies in the lack of high - quality, publicly accessible hardware - code datasets. This scarcity limits the effective fine - tuning of large language models, making it difficult for them to acquire the necessary hardware - domain knowledge, and thus affecting the security and reliability of the generated content. Any minor mistake in hardware design can lead to serious consequences, such as chip failure or system crash. Therefore, ensuring the security and reliability of the design code generated by AI is of crucial importance, which is one of the problems faced by current technologies.

[0005] Moreover, the application of LLM in the hardware field, especially in the construction of hardware description languages such as Verilog, still has deficiencies. This is mainly due to the fact that hardware description languages usually have higher domain specificity and complexity, and there are relatively few high-quality hardware design datasets available for training. Previous studies have attempted to bridge this gap through prompt engineering and supervised fine-tuning methods, but have failed to find a balance between the diversity and quality of the datasets, and single-round domain adaptation fine-tuning limits the ability of LLM to generate diverse outputs while maintaining high code quality. At the same time, LLM also faces the problem of hallucination and may incorporate software programming habits into Verilog code generation, thus causing syntax and functional errors. Summary of the Invention

[0006] To solve at least one of the technical problems existing in the above background art, the present invention provides a dedicated large model-assisted design method and system for hardware design, which, in response to the requirements of hardware design and in combination with a rich dataset constructed with multi-level descriptions, improves the credibility of the pre-trained large language model generated.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] The first aspect of the present invention provides a dedicated large model-assisted design method for hardware design, including the following steps:

[0009] Obtain the original code dataset;

[0010] Preprocess the original code dataset to construct a hardware description language code database that meets the requirements of hardware design;

[0011] Generate a multi-level code description pair dataset based on the hardware language code database that meets the requirements of hardware design and the constructed multi-level description mechanism; wherein, the construction process of the multi-level description mechanism includes:

[0012] Generate a description for each line of code, and use all the lines of code included in each hardware module and the corresponding line-by-line descriptions as the input of the large language model to generate an overall description of each module;

[0013] Use the code of all the modules included in the integrated module composed of each hardware module and the corresponding module descriptions as the input of the large language model to generate an integrated description;

[0014] Use the overall code and the integrated description as the input of the large language model to generate a global description;

[0015] Fine-tune the large language model based on the multi-level code description pair dataset to generate a dedicated large language model for hardware design.

[0016] Further, the preprocessing of the original code dataset includes syntax verification, length verification, and content verification of the code, and then removing comments, leading and trailing lines from the code that passes the verification, and further screening and splitting code snippets.

[0017] Further, the method further includes filtering the dataset after generating the multi-level code description pair dataset, removing defective or redundant code samples, and obtaining the filtered multi-level code description pair dataset.

[0018] Further, all the lines of code between the start declaration and the end declaration of each hardware module are used as the code of a module, or, based on a set number of lines of code as a module.

[0019] Further, the overall description of each module includes the input, output, working principle, and structural relationship with other parts of each module;

[0020] The comprehensive description includes the interaction method, data flow path, and control signal between each sub-module;

[0021] The global description includes the architecture design and overall goal of the entire hardware system. Further, when fine-tuning the large language model based on the multi-level code description pair dataset, the constructed loss function is:

[0022]

[0023] where x 1i , x 2i , x 3i , x 4i are the input description sequences of the per-line, module, comprehensive, and global four levels of sample i respectively, N is the total number of samples, y i is the corresponding target code sequence, θ represents the parameters of the model, P(y i |f(x 1i , x 2i , x 3i , x 4i ); θ) is the probability of outputting y 1i , x 2i , x 3i , x 4i ) given the input f(x i and the parameters θ, and f(x 1i , x 2i , x 3i , x 4i ) represents the concatenated combination of the multi-level input description.

[0024] The second aspect of the present invention provides a dedicated large model assisted design system for hardware design, including:

[0025] A dataset acquisition module for acquiring an original code dataset;

[0026] A data preprocessing module for preprocessing the original code dataset to construct a hardware description language code database that meets the hardware design requirements;

[0027] A multi-level description generation module for generating a multi-level code description pair dataset based on the hardware language code database that meets the hardware design requirements and the constructed multi-level description mechanism; wherein, the construction process of the multi-level description mechanism includes:

[0028] Generating a description for each line of code, and using all the lines of code included in each hardware module and the corresponding line-by-line descriptions as the input of a large language model to generate an overall description of each module;

[0029] Using the code of all the modules included in the integrated module composed of each hardware module and the corresponding descriptions of the modules as the input of a large language model to generate an integrated description;

[0030] Using the overall code and the integrated description as the input of a large language model to generate a global description;

[0031] An auxiliary design module for fine-tuning a large language model based on the multi-level code description pair dataset to generate a dedicated large language model for hardware design.

[0032] The third aspect of the present invention provides a computer-readable storage medium.

[0033] A computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the steps in the dedicated large model assisted design method for hardware design as described above.

[0034] The fourth aspect of the present invention provides a computer device.

[0035] A computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, it implements the steps in the dedicated large model assisted design method for hardware design as described above.

[0036] The fifth aspect of the present invention provides a program product.

[0037] A program product, which is a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the steps in the dedicated large model assisted design method for hardware design as described above.

[0038] Compared with the prior art, the beneficial effects of the present invention are:

[0039] 1. When designing complex circuits and chips, the present invention generates a dedicated large language model according to the design requirements and the constructed multi-level description mechanism, which can realize efficient and accurate automatic generation of hardware code, without worrying about low-level manual coding tasks or interface consistency issues, greatly reducing the error rate caused by human negligence or misunderstanding of design specifications, and significantly optimizing the efficiency of the entire design cycle.

[0040] 2. The present invention fine-tunes the model by combining multi-level code descriptions of the dataset to ensure that the model can not only master the specific hardware implementation details but also understand the high-level system architecture design, significantly improving the accuracy and reliability of the code generation task in the hardware design process.

[0041] Advantages of additional aspects of the present invention will be given in part in the following description, will become apparent in part from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings constituting a part of this specification are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention.

[0043] Figure 1 It is a flowchart of a dedicated large model-assisted design method for non-hardware design provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0045] It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0046] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0047] In the face of the challenges in the development of large language models for hardware design mentioned in the background technology, the present invention proposes an innovative multi-granularity hardware design code data construction technology, aiming to establish a basic framework to support the fine-tuning of large models for hardware design and overcome the limitations in the prior art. This framework not only focuses on creating high-quality data sets, but also develops a series of training technologies and evaluation metrics optimized for hardware design, enabling large language models to better meet the requirements of the hardware design field, improving the accuracy and reliability of the generated content, and providing strong support for the development of hardware design. LoRA (Low-Rank Adaptation) fine-tuning is an efficient fine-tuning method for large pre-trained models (such as large language models). Without changing the original model weights, LoRA approximates the modified weight matrix by introducing two low-rank matrices, thereby achieving the adaptation or adjustment of the model.

[0048] Embodiment 1

[0049] As Figure 1 shown, this embodiment provides a dedicated large model-assisted design method for hardware design, including the following steps:

[0050] Step 1: Obtain the original code data set;

[0051] In this embodiment, the original code data set includes relevant open-source code resources such as the Internet and textbooks;

[0052] Step 2: Preprocess the original code data set to construct a hardware description language code database that meets the hardware design requirements;

[0053] In this embodiment, preprocessing the original code data set includes performing syntax verification, length verification, and content verification on the code, then removing comments, leading and trailing lines from the verified code, and further screening and splitting code fragments to ensure the quality and consistency of the data set.

[0054] The code description of the training data set of the hardware description language code database that meets the hardware design requirements is determined by engineers for the basic definition description requirements, and the large model is used to assist in generating the filling description.

[0055] Step 3: Generate a multi-level code description pair data set based on the hardware language code database that meets the hardware design requirements and the constructed multi-level description mechanism;

[0056] In order to enable large language models (LLMs) to effectively learn hardware design patterns at different abstraction levels, a multi-level description mechanism is introduced. This mechanism aims to guide LLMs to understand the design ideas from individual logical operations to the entire system architecture through four levels of annotations.

[0057] Among them, the construction process of the multi-level description mechanism includes: generating a description for each line of code, taking all the lines of code included in each hardware module and the corresponding line-by-line descriptions as the input of the large language model to generate the overall description of each module; taking the code of all modules included in the integrated module composed of each hardware module and the descriptions of the corresponding modules as the input of the large language model to generate the integrated description; taking the overall code and the integrated description as the input of the large language model to generate the global description; specifically including the following steps:

[0058] Step 301, Generation of line-level description

[0059] Generate a description for each line of code to help understand the purpose of individual logical operations and how these operations work together to achieve more complex functions.

[0060] Taking the Arithmetic and Logic Unit (ALU) as an example, generate annotation descriptions for each line of code of the ALU, and collect all the corresponding annotations of all lines as the line-level description of the ALU.

[0061] Step 302, Generation of module-level description

[0062] The module division takes all the lines between module (module start declaration) and end module (module end declaration) as a module code, or every fixed number of lines can also be used as a module.

[0063] For each module, take all the code of the module and its corresponding line-by-line description as the input, and require the large model to generate the overall description of the module.

[0064] Generate descriptions of each functional module of the hardware, and the descriptions include the input, output, working principle of each module or subsystem, and the interface relationship with other parts;

[0065] Taking the Arithmetic and Logic Unit (ALU) as an example, the ALU consists of multiple sub-modules, including but not limited to adders, multipliers, shifters, etc. Generate annotation descriptions for the code of each of its sub-modules, and collect all the corresponding annotations of all sub-modules of the ALU as the module-level description of the ALU to help understand the working principle of each of its sub-modules.

[0066] Step 303, Generation of integrated-level description

[0067] The generation of the integrated-level description takes the code of all modules and their corresponding module descriptions as the input, and requires the large model to generate the integrated description.

[0068] Combining the descriptions of each generated module to obtain a comprehensive-level description, which includes key description information such as the interaction methods between modules, data flow paths, control signals, etc.;

[0069] In the case of an Arithmetic and Logic Unit (ALU), the comprehensive-level description explains how data flows internally and interacts with each sub-module, as well as the signal transmission mechanism between sub-modules, providing a valuable perspective for understanding the entire operation process of the ALU.

[0070] Step 304: Generate global-level description;

[0071] The global-level description takes the overall code and the comprehensive-level description as inputs and requires the large model to generate a global description.

[0072] The global-level description includes the architecture design and overall objectives of the entire hardware system.

[0073] Taking the Arithmetic and Logic Unit (ALU) as an example, this level of description emphasizes that it not only supports basic arithmetic and logic operations, but also works closely with the instruction decoder, register file, and memory management unit to jointly ensure an efficient instruction execution cycle. In this way, the CPU can quickly and accurately process complex algorithm tasks, thereby achieving the predetermined functions. The global-level description depicts how all components cooperate with each other to achieve the best performance.

[0074] Through this progressive description method, it is ensured that the LLM not only understands the code details, but also masters the cooperation between modules and the overall architecture, thereby comprehensively improving its learning and replication ability of the hardware design pattern.

[0075] Step 4: Filter the multi-level code description pair dataset generated in Step 3 to obtain the filtered multi-level code description pair dataset;

[0076] In this embodiment, combining the static analysis tool verilator and the artificial intelligence judgment of gpt-4, code samples with obvious defects or redundancies are removed. We not only rely on automated tools, but also establish our own machine learning model decision tree to improve the effectiveness and efficiency of automatic screening. This model is trained based on carefully selected good and bad code samples to achieve more accurate code quality evaluation.

[0077] Step 5: Fine-tune the large language model based on the filtered multi-level code description pair dataset to generate a dedicated large language model for hardware design; specifically including:

[0078] In this embodiment, during the model fine-tuning stage, a set of algorithm frameworks specifically designed for training LLM is designed by using the verified and filtered dataset together with the multi-level description information, which can optimize the model parameters at different granularities: this framework provides a customized learning path by combining the description information at the line-by-line, module, comprehensive, and global levels, allowing the model to learn from the input data at multiple description levels in the same round to optimize the parameters, that is, given the training dataset where x 1i , x 2i , x 3i , x 4i are the input description sequences at the line-by-line, module, comprehensive, and global levels of sample i respectively, N is the total number of samples, and y i is the corresponding target code sequence. The maximum likelihood estimation (MLE) loss function is used and optimized by the LoRA method, and the goal is to minimize the following loss function:

[0079]

[0080] where θ represents the parameters of the model, and P(y i |f(x 1i , x 2i , x 3i , x 4i ); θ) is the probability of outputting y 1i , x 2i , x 3i , x 4i ) given the input f(x i and the parameters θ,

[0081] where f(x 1i , x 2i , x 3i , x 4i ) represents the concatenation combination of the multi-level input descriptions, as follows:

[0082] It contains four levels: f(x 1i , x 2i , x 3i , x 4i ) = [x 1i , x 2i , x 3i , x 4i ,

[0083] It contains module, comprehensive, and global: f(x 1i , x 2i , x 3i , x 4i ) = [x 2i , x 3i , x 4i ,

[0084] Containing comprehensive, global: f(x 1i , x 2i , x 3i , x 4i ) = [x 3i , x 4i ,

[0085] Containing global: f(x 1i , x 2i , x 3i , x 4i ) = [x 4i and other combinations

[0086] Fine-tune the model on the dataset pair by combining multi-level code descriptions to ensure that the model can not only master the specific hardware implementation details but also understand the high-level system architecture design principles.

[0087] Step 6: Verify the correctness of the large language model for hardware design;

[0088] To evaluate the functional correctness of the model, use the Pass@k metric. By determining whether any of the selected k samples pass the unit test related to the problem, evaluate whether the model has successfully solved the given problem. Specifically, it can be defined as:

[0089]

[0090] where n ≥ k represents the total number of samples generated for each task, and c represents the number of samples that pass the test.

[0091] This process not only enhances the model's adaptability to specific domains but also significantly improves the security and reliability of its output results, providing strong support for the development of hardware design. Through this series of technological innovations, the present invention overcomes the limitations in the prior art and significantly improves the accuracy and reliability of the code generation task in the hardware design process.

[0092] Specifically, when designing complex circuits and chips, such as developing high-performance computing (HPC) processors or application-specific integrated circuits (ASICs), adopting the dedicated large language model-assisted design method of the present invention can achieve efficient and accurate automated generation of hardware code.

[0093] This method enables the development team to focus on high-level design challenges, such as innovation and technological breakthroughs in architecture optimization, without having to worry about low-level manual coding tasks or interface consistency issues. As a result, the error rate caused by human negligence or misunderstanding of design specifications is significantly reduced, and at the same time, the efficiency of the entire design cycle is significantly optimized. This innovation not only accelerates the product development process but also enhances the product's market competitiveness, fully demonstrating the excellent value of the present invention in practical application scenarios.

[0094] Embodiment 2

[0095] This embodiment provides a dedicated large model-assisted design system for hardware design, including:

[0096] A dataset acquisition module, which is used to acquire the original code dataset;

[0097] A data preprocessing module, which is used to preprocess the original code dataset and construct a hardware description language code database that meets the hardware design requirements;

[0098] A multi-level description generation module, which is used to generate a multi-level code description pair dataset based on the hardware language code database that meets the hardware design requirements and the constructed multi-level description mechanism; among them, the construction process of the multi-level description mechanism includes:

[0099] Generate a description for each line of code, and use all the lines of code included in each hardware module and the corresponding line-by-line descriptions as the input of the large language model to generate an overall description of each module;

[0100] Use the code of all modules included in the integrated module composed of each hardware module and the corresponding module descriptions as the input of the large language model to generate an integrated description;

[0101] Use the overall code and the integrated description as the input of the large language model to generate a global description;

[0102] An assisted design module, which is used to fine-tune the large language model based on the multi-level code description pair dataset to generate a dedicated large language model for hardware design.

[0103] Embodiment 3

[0104] This embodiment provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the steps in the dedicated large model-assisted design method for hardware design as described above.

[0105] Embodiment 4

[0106] This embodiment provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps in the above-mentioned dedicated large model-assisted design method for hardware design.

[0107] Embodiment 5

[0108] This embodiment provides a program product, which is a computer program product and includes a computer program. When the computer program is executed by a processor, it implements the steps in the above-mentioned dedicated large model-assisted design method for hardware design.

[0109] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0110] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the specified functions in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0111] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the specified functions in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0112] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide for implementing the specified functions in Figure 1steps of one process or multiple processes and / or blocks Figure 1 steps of the functions specified in one block or multiple blocks.

[0113] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), or the like.

[0114] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A dedicated large model-assisted design method for hardware design, characterized in that: The steps include: Get the original code dataset; Preprocess the original code data set to construct a hardware description language code database that meets the hardware design requirements; A multi-level code description pair data set is generated based on a hardware language code database that meets hardware design requirements and a constructed multi-level description mechanism; wherein the construction process of the multi-level description mechanism includes: Generate a description for each line of code, take all the lines of code and the corresponding line-by-line descriptions contained in each hardware module as the input of the large language model, and generate the overall description of each module; The codes of all modules included in the comprehensive module composed of various hardware modules and the descriptions of the corresponding modules are used as inputs of the large language model to generate a comprehensive description; The overall code and comprehensive description are used as input to the large language model to generate a global description; Based on the multi-level code description dataset, the large language model is fine-tuned to generate a dedicated large language model for hardware design.

2. The dedicated large-scale model-assisted design method for hardware design as claimed in claim 1, characterized in that: The preprocessing of the original code data set includes syntax verification, length verification and content verification of the code, and then removing comments, removing leading and trailing lines from the verified code, and further screening and segmenting the code fragments.

3. The dedicated large-scale model-assisted design method for hardware design as claimed in claim 1, characterized in that: The method further includes filtering the data set after generating the multi-level code description pair data set, eliminating defective or redundant code samples, and obtaining a filtered multi-level code description pair data set.

4. The dedicated large-scale model-assisted design method for hardware design as claimed in claim 1, characterized in that: All lines of code between the start and end declarations of each hardware module are considered as one module, or based on a set number of lines of code.

5. The dedicated large-scale model-assisted design method for hardware design as claimed in claim 1, characterized in that: The overall description of each module includes the input, output, working principle and structural relationship with other parts of each module; The comprehensive description includes the interaction mode, data flow path and control signals between each submodule; The global description includes the architectural design and overall goals of the entire hardware system.

6. The dedicated large-scale model-assisted design method for hardware design as claimed in claim 1, characterized in that: When fine-tuning the large language model based on the multi-level code description, the loss function constructed is: Among them, x 1i ,x 2i ,x 3i ,x 4i are the input description sequences of sample i at the row-by-row, module-by-module, integrated, and global levels, N is the total number of samples, and y i is the corresponding target code sequence, θ represents the parameters of the model, P(y i| f(x 1i ,x 2i ,x 3i ,x 4i ), θ) is the given input f(x 1i ,x 2i ,x 3i ,x 4i ) and parameter θ under the condition of output y i The probability of f(x 1i ,x 2i ,x 3i ,x 4i ) represents the concatenation of multiple levels of input descriptions.

7. A dedicated large-scale model-assisted design system for hardware design, characterized in that: include: A data set acquisition module, which is used to acquire the original code data set; A data preprocessing module is used to preprocess the original code data set to construct a hardware description language code database that meets the hardware design requirements; A multi-level description generation module is used to generate a multi-level code description pair data set based on a hardware language code database that meets the hardware design requirements and a constructed multi-level description mechanism; wherein the construction process of the multi-level description mechanism includes: Generate a description for each line of code, take all the lines of code and the corresponding line-by-line descriptions contained in each hardware module as the input of the large language model, and generate the overall description of each module; The codes of all modules included in the comprehensive module composed of various hardware modules and the descriptions of the corresponding modules are used as inputs of the large language model to generate a comprehensive description; The overall code and comprehensive description are used as input to the large language model to generate a global description; The auxiliary design module is used to fine-tune the large language model based on the multi-level code description and the data set to generate a dedicated large language model for hardware design.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the dedicated large model-assisted design method for hardware design as described in any one of claims 1 to 6 are implemented.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps in the dedicated large model-assisted design method for hardware design as described in any one of claims 1-6 are implemented.

10. A program product, the program product being a computer program product, comprising a computer program, characterized in that: When the computer program is executed by a processor, the steps of the dedicated large model-assisted design method for hardware design as described in any one of claims 1 to 6 are implemented.

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