Front-end circuit for RFID transponder

Abstract

According to a first aspect of the present disclosure, there is provided a front-end circuit for an RFID transponder, the front-end circuit comprising: a rectifier configured to rectify an input voltage received from an antenna; a voltage limiter operably coupled to the rectifier, the voltage limiter configured to limit an output voltage of the rectifier; and a level detector operably coupled to the voltage limiter, the level detector configured to compare a level of an output signal of the voltage limiter with a predefined reference level. According to a second aspect of the present disclosure, a corresponding method of operating a front-end circuit is conceived.

Description

Technical Field

[0001] The present disclosure relates to a front - end circuit for a radio - frequency identification (RFID) transponder. Further, the present disclosure relates to a corresponding method of operating a front - end circuit for an RFID transponder. Background Art

[0002] RFID transponders can support a feature for intentionally reducing the maximum operating range in response to an RFID reader command, for example, to protect privacy. To implement this feature, the RFID transponder should determine whether the received power level exceeds a predefined power threshold. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a front - end circuit for an RFID transponder, the front - end circuit comprising: a rectifier configured to rectify an input voltage received from an antenna; a voltage limiter operatively coupled to the rectifier, the voltage limiter being configured to limit the output voltage of the rectifier; a level detector operatively coupled to the voltage limiter, the level detector being configured to compare the level of the output signal of the voltage limiter with a predefined reference level.

[0004] In one or more embodiments, the level detector is further configured to generate an output signal, wherein the output signal indicates the result of comparing the level of the output signal of the voltage limiter with the predefined reference level.

[0005] In one or more embodiments, the output signal of the level detector and / or the voltage limiter is configured to be enabled by a digital control circuit included in the RFID transponder.

[0006] In one or more embodiments, the output signal of the level detector and / or the voltage limiter is configured to be enabled during startup of an integrated circuit included in the RFID transponder.

[0007] In one or more embodiments, the output signal of the level detector and / or the voltage limiter is configured to be enabled in response to a command received from an external reader device.

[0008] In one or more embodiments, the output signal of the level detector and / or the voltage limiter is permanently enabled.

[0009] In one or more embodiments, the output signal of the level detector and / or the voltage limiter is periodically enabled.

[0010] In one or more embodiments, the output signal of the voltage limiter varies with the current dissipated by the voltage limiter.

[0011] In one or more embodiments, the output signal of the voltage limiter is a current or a voltage.

[0012] In one or more embodiments, the rectifier, voltage limiter, and level detector have configurable circuit parameters.

[0013] In one or more embodiments, an RFID transponder includes a front-end circuit of the type described and an integrated circuit operatively coupled to the output of the voltage limiter.

[0014] In one or more embodiments, the integrated circuit is configured to avoid responding to commands received from an external reader when the level of the output signal of the voltage limiter is below the predefined reference level.

[0015] According to a second aspect of the present disclosure, a method of operating a front-end circuit for an RFID transponder is contemplated. The front-end circuit includes a rectifier, a voltage limiter, and a level detector, and the method includes rectifying an input voltage received from an antenna by the rectifier; limiting the output voltage of the rectifier by the voltage limiter; and comparing the level of the output signal of the voltage limiter with a predefined reference level by the level detector.

[0016] In one or more embodiments, the level detector generates an output signal, where the output signal indicates the result of comparing the level of the output signal of the voltage limiter with the predefined reference level.

[0017] In one or more embodiments, the output signal of the voltage limiter varies with the current dissipated by the voltage limiter. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Embodiments will be described in more detail with reference to the accompanying drawings.

[0019] Figure 1 A graph showing the relationship between the minimum received power of an RFID transponder and the operating frequency is shown.

[0020] Figure 2 An illustrative embodiment of a front-end circuit for an RFID transponder is shown.

[0021] Figure 3 An illustrative embodiment of a method of operating a front-end circuit is shown.

[0022] Figure 4Shows another illustrative embodiment of a front-end circuit for an RFID transponder.

[0023] Figure 5 Shows an illustrative embodiment of a part of a front-end circuit for an RFID transponder.

[0024] Figure 6 Shows another illustrative embodiment of a part of a front-end circuit for an RFID transponder. Detailed Description

[0025] As mentioned above, an RFID transponder, which can also be referred to as an RFID tag, can support a feature for intentionally reducing the maximum operating range in response to an RFID reader command, for example, to protect privacy. For example, the optional untraceable command specified in the technical standard "EPC TM Radio Frequency Identification Protocol Generation 2 UHF RFID Standard" version 2.1 published in July 2018 allows the reader to configure the tag in a mode with a reduced operating range.

[0026] The reduction of the tag operating range can prevent unwanted tracking of the tag over long distances to protect privacy, while still maintaining the option to read tag data or change the tag configuration at close range. This can facilitate, for example, handling product returns in a retail application scenario. As shown in equation (1), considering the communication from the reader to the tag, the operating range R of the tag in the forward link depends on the transponder sensitivity P min .

[0027] (Equation 1)

[0028] The sensitivity corresponds to the minimum required power received by the transponder antenna to execute and respond to a reader command. For example, a typical reader command requests the tag to read data from non-volatile memory and transmit the data back to the reader. However, the transponder can also intentionally reduce the operating range by increasing the effective sensitivity power level P min . This can be achieved by detecting whether the received power level exceeds a specific power threshold.

[0029] Figure 1 Shows a graph 100 displaying the relationship between the minimum received power of an RFID transponder and the operating frequency. Specifically, Figure 1 shows an example of the sensitivity characteristics versus frequency of an RFID transponder for a normal read command response and a command response with a reduced range. The sensitivity level increases by a level ΔP of approximately 22 dBm min . Considering the equivalent isotropic radiated power maximum (EIRP) transmitter of a 4W reader, this corresponds to a reduction in the operating range from approximately 16m to approximately 1.3m.

[0030] Accordingly, an RFID tag integrated circuit (IC) may implement features that allow the tag to be configured in a mode with a reduced operating range. To implement such a mode, the tag IC should be able to detect whether the received power level exceeds a defined power threshold. However, the process of checking the received power level should be performed in a fast manner so as not to negatively impact the startup time of the tag IC. Additionally, the execution of the power check process should not cause a change in the RF power absorbed by the tag IC, thereby minimizing electromagnetic interference.

[0031] Discussed now is a front-end circuit for an RFID transponder and a corresponding method of operating the front-end circuit, which helps to implement the reduced operating range mode of the RFID transponder while reducing the negative impact on its performance.

[0032] Figure 2 An illustrative embodiment of a front-end circuit 200 for an RFID transponder is shown. The front-end circuit 200 includes a rectifier 202, a voltage limiter 204 operatively coupled to the rectifier 202, and a level detector 206 operatively coupled to the voltage limiter 204. The rectifier 202 is configured to rectify an input voltage received from an antenna. It should be noted that the antenna is external to the front-end circuit 200. Specifically, the antenna may form part of an RFID transponder into which the front-end circuit 200 may be integrated. Additionally, the voltage limiter 204 is configured to limit the output voltage of the rectifier 202. Further, the level detector 206 is configured to compare the level of the output signal of the voltage limiter 204 with a predefined reference level. The front-end circuit 200 helps to implement the reduced operating range mode of the RFID transponder into which it is integrated while alleviating the negative impact on the performance of the transponder. Specifically, the front-end circuit 200 helps to implement a power check for the RFID transponder, which utilizes a typical rectifier and voltage limiter circuit of the RFID transponder in combination with an additional level detector, thereby enabling a circuit implementation with a low layout area overhead and current consumption. Additionally, the internal power consumption and the absorbed RF power of the transponder IC remain largely unchanged during the activation and operation of the front-end circuit 200. Accordingly, the execution of the power check does not require a stable time overhead with respect to the internal supply voltage and does not cause electromagnetic interference due to a change in the absorbed power level.

[0033] In a particular implementation of the front-end circuit 200, the rectifier 202 rectifies and converts the RF power received by the transponder antenna to provide a DC voltage at the output VRECT. The voltage limiter 204 connected to the rectifier output supplies the supply voltage for the core circuit of the chip at its output VDD. In some transponder IC implementations, the voltage level at VDD can be substantially equal to the voltage at VRECT. The voltage limiter 204 limits the maximum voltage level of VRECT by dissipating the rectifier output current that exceeds the current consumption of the transponder core circuit to prevent damage to circuit components due to overvoltage. The front-end circuit 200 uses an additional output signal SENSE of the DC limiter. The level of SENSE varies with the current dissipated by the voltage limiter 204. For example, the level of SENSE can be proportional or inversely proportional to the current dissipated by the voltage limiter 204. The signal SENSE can be a voltage or current signal.

[0034] According to the present disclosure, the level detector 206 compares the level of the signal SENSE with a reference level at the input REF. In a practical implementation, the level detector output OUT indicates to the digital control circuit of the tag IC whether the signal SENSE has exceeded the reference level at REF. This helps to trigger the digital control circuit to limit the operating range of the tag, for example, by avoiding responding to commands received from an external reader when the level of the output signal SENSE of the voltage limiter is below a predefined reference level REF.

[0035] It should be noted that the voltage level at VRECT is substantially defined by the voltage limiter 204 at elevated levels of received power. In this case, assuming that the core current consumption is relatively negligible or mostly constant, the DC power consumption at the rectifier output VRECT is proportional to the dissipated current of the voltage limiter 204. Depending on the power conversion efficiency of the rectifier 202, the absorbed RF power at the input of the rectifier 202 is proportional to the DC power consumption at VRECT. In addition, the absorbed input RF power of the rectifier 202 is proportional to the received antenna power defined by the impedance match between the antenna and the tag IC. Therefore, the level of SENSE and the threshold defined by REF are proportional to the power received at the antenna.

[0036] In one or more embodiments, the output signal of the level detector and / or the voltage limiter is configured to be enabled by a digital control circuit included in the RFID transponder. In this way, power checking can be easily enabled and disabled, for example depending on the application of the use case of the RFID transponder. In one or more embodiments, the output signal of the level detector and / or the voltage limiter is configured to be enabled during startup of the integrated circuit included in the RFID transponder. In this way, power checking can be easily activated such that power checking is operational when the RFID transponder is in use. Further, in one or more embodiments, the output signal of the level detector and / or the voltage limiter is configured to be enabled in response to a command received from an external reader device. In this way, power checking can be activated only when necessary such that the power checking itself does not consume too much energy.

[0037] In one or more embodiments, the output signal of the level detector and / or the voltage limiter is permanently enabled. In this way, the level of the received power is permanently monitored. In one or more embodiments, the output signal of the level detector and / or the voltage limiter is periodically enabled. In this way, power checking can be periodically activated while the power checking itself does not consume too much energy.

[0038] Activation of the output signal of the level detector and / or the voltage limiter can be conditioned on the setting of configuration bits stored in the non-volatile memory included in the RFID transponder. The configuration bits of the non-volatile memory of the RFID transponder for otherwise enabling, disabling, or changing the behavior of the level detector and / or the voltage limiter can be changed in response to a command sent by an external reader device.

[0039] A digital memory cell can be used to temporarily store the state of the output signal OUT of the level detector 206 for later processing by the digital control circuit included in the RFID transponder. The digital control circuit of the RFID transponder can read the state of the signal OUT or the state of the signal OUT stored in the digital memory cell when receiving a command from an external reader to decide whether to reply to the reader command. In this way, if the RFID transponder replies to the reader command only when the level of the signal SENSE has exceeded a reference level REF (as indicated by the output signal OUT of the level detector 206), the effective operating range of the RFID transponder can be reduced.

[0040] Figure 3Illustrative embodiments of a method 300 for operating a front-end circuit are shown. Method 300 includes the following steps. At 302, a rectifier of the front-end circuit rectifies an input voltage received from an antenna. At 304, a voltage limiter of the front-end circuit limits the output voltage of the rectifier. Additionally, at 306, a level detector of the front-end circuit compares the level of the output signal of the voltage limiter with a predefined reference level. As explained for the corresponding front-end circuit as shown in reference Figure 2 As shown in the corresponding front-end circuit as shown in reference

[0041] Figure 4 Another illustrative embodiment of a front-end circuit 400 for an RFID transponder is shown. In addition to Figure 2 the rectifier 412, voltage limiter 414, and level detector 416 of the front-end circuit as shown in reference Figure 4 the front-end circuit 400 as shown in reference

[0042] also includes an ESD protection block 402, an RF limiter 404, an antenna tuning block 406, a modulator 408, and a demodulator 410. Specifically, an example of how the power check enabled by the rectifier 412, voltage limiter 414, and level detector 416 can be implemented in a non-limiting example of a typical front-end circuit 400 for an RFID transponder is shown.

[0043] Figure 5 An illustrative embodiment of a portion 500 of a front-end circuit for an RFID transponder is shown. Specifically, Figure 55 shows a non-limiting example of an implementation of a voltage limiter 502 and a level detector 504 of the type set forth above. The voltage limiter 502 includes a shunt transistor M1 to dissipate excess current from the supply voltage rail VRECT. 1 The gate of M is controlled by an amplifier in a closed loop configuration. When VRECT exceeds the reference voltage VREF1 supplied to the amplifier, M 1 The voltage at the gate increases, and M 1 The drain current and thus the input current at the terminal VRECT rises. Therefore, due to the increase in the input current at VRECT and the voltage drop generated at the finite output resistance of the rectifier (not shown), the voltage at VRECT approaches a constant value. The second transistor M 2 The gate is connected to M 1 The gate terminal. 2 The resulting drain current is related to M 1 The drain current is proportional to M 2 The drain current causes R 1 The voltage drop at SENSE is observed at the output SENSE. Therefore, the observable voltage at SENSE is inversely proportional to the current dissipated by the voltage limiter.

[0044] The level detector 504 includes a voltage comparator that compares the voltage at the input SENSE with a reference voltage VREF2 relative to the voltage level at VRECT, denoted as V(VRECT). The output signal OUT indicates whether the voltage at SENSE has dropped below a voltage equal to V(VRECT)-VREF2 corresponding to a particular level of dissipated current of the voltage limiter. In this example, the power detection threshold of the power check circuit is determined by the reference voltage VREF2, the resistor R 1 The value of M 1 and M 2 The power detection threshold is defined by the ratio of the transistor sizes of the reference voltage VREF1, the voltage level of VRECT defined by the reference voltage VREF1, the power conversion efficiency of the rectifier, and the impedance matching between the transponder antenna and the transponder IC. A practical transponder IC implementation may provide means for configuring these circuit parameters to adjust the power detection threshold. For example, a practical implementation of the present invention may include a switch to switch the resistor R 1 or transistor M 2 to adjust the power detection threshold.

[0045] Figure 6 Another illustrative embodiment of a portion 600 of a front-end circuit for an RFID transponder is shown. Specifically, Figure 6Shows another non - limiting example of an embodiment of a voltage limiter 602 and a level detector 604 of the type described above. It should be noted that the operation of the voltage limiter 602 is similar to Figure 5 the voltage limiter shown in 2 . The gate of transistor M Figure 5 is connected to the gate of transistor M 1 in the same way as the circuit of 1 . Thus, depending on the ratio of the transistor sizes of M 2 and M 1 , the output current at the SENSE terminal is proportional to the current dissipated via transistor M

[0046] The level detector 604 compares the current level at the input SENSE with a reference current IREF1. The signal SENSE is connected to the input of a current mirror composed of PMOS transistors M 3 and M 4 . The output of the current mirror, more specifically the drain of transistor M 4 , is connected to the node CMP. In addition, CMP is connected to the output of an NMOS current mirror including transistors M 5 and M 6 . The input of the NMOS current mirror is connected to the reference current IREF1. If the magnitude of the output current of the PMOS current mirror exceeds the magnitude of the output current of the NMOS current mirror, the voltage at CMP rises. The voltage at CMP is amplified by a voltage amplifier to a digital signal level at the output OUT. In this example, the power detection threshold of the power check circuit is defined by: the ratio of the transistor sizes of M 1 and M 2 , the voltage level of VRECT defined by the reference voltage VREF1, the power conversion efficiency of the rectifier, the impedance matching between the transponder antenna and the transponder IC, the PMOS and NMOS current mirror transistor ratios, and the level of the reference current IREF1. The actual transponder IC can provide means for configuring these circuit parameters to adjust the power detection threshold.

[0047] It should be noted that the reference voltage VREF1, VREF2, the reference current IREF1, or a combination thereof, as shown in the schematic diagrams of Figure 5 and Figure 6 , can be implemented in a way that achieves the desired temperature behavior to compensate the power detection threshold with respect to the temperature drift of other circuit components or sub - circuits of the rectifier, for example.

[0048] In addition, it should be noted that the above embodiments have been described with reference to different subject matters. Specifically, some embodiments may have been described with reference to method - type claims, while other embodiments may have been described with reference to apparatus - type claims. However, those skilled in the art will understand from the above that, unless otherwise stated, any combination of features related to different subject matters, in particular the combination of features of method - type claims and features of apparatus - type claims, in addition to any combination of features belonging to one type of subject matter, is also considered to be disclosed together with this document.

[0049] In addition, it should be noted that the drawings are schematic. In different diagrams, like or identical elements are denoted by the same reference numerals. Further, it should be noted that in order to provide a concise description of the illustrative embodiments, implementation details that are part of the routine practices of those skilled in the art may not have been described. It should be understood that in the development of any such implementation, as in any engineering or design project, numerous implementation - specific decisions must be made to achieve the developer's specific goals, such as compliance with system - related and business - related constraints, which may vary between different implementations. In addition, it should be understood that such development work may be complex and time - consuming, but is merely a routine task for those skilled in the art in design, manufacturing, and production.

[0050] Finally, it should be noted that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. "Comprising" does not exclude the presence of elements or steps other than those listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The measures recited in the claims can be implemented by means of hardware including several different elements and / or by means of a suitably programmed processor. In an apparatus claim listing several components, several of these components can be implemented by the same item in the hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0051] List of reference numerals

[0052] 100 Minimum received power vs. frequency

[0053] 200 Front - end circuit

[0054] 202 Rectifier

[0055] 204 Voltage limiter

[0056] 206 Level detector

[0057] 300 Method of operating a front - end circuit

[0058] 302 The rectifier of the front-end circuit rectifies the input voltage received from the antenna.

[0059] 304 The output voltage of the rectifier is limited by the voltage limiter of the front-end circuit.

[0060] 306 The level detector of the front-end circuit compares the level of the output signal of the voltage limiter with a predefined reference level.

[0061] 400 Front-end circuit

[0062] 402 ESD protection

[0063] 404 RF limiter

[0064] 406 Antenna tuning

[0065] 408 Modulator

[0066] 410 Demodulator

[0067] 412 Rectifier

[0068] 414 Voltage limiter

[0069] 416 Level detector

[0070] 500 A part of the front-end circuit

[0071] 502 Voltage limiter

[0072] 504 Level detector

[0073] 600 A part of the front-end circuit

[0074] 602 Voltage limiter

[0075] 604 Level detector.

Claims

1. A front-end circuit for a radio frequency identification (RFID) transponder, characterized in that: The front-end circuit comprises: a rectifier configured to rectify an input voltage received from the antenna; a voltage limiter operably coupled to the rectifier, the voltage limiter configured to limit an output voltage of the rectifier; A level detector is operatively coupled to the voltage limiter, the level detector being configured to compare a level of an output signal of the voltage limiter with a predefined reference level.

2. The front-end circuit according to claim 1, characterized in that: The level detector is further configured to generate an output signal, wherein the output signal is indicative of a result of comparing the level of the output signal of the voltage limiter with the predefined reference level.

3. The front-end circuit according to claim 1 or 2, characterized in that: The output signal of the level detector and / or the voltage limiter is configured to be enabled by a digital control circuit comprised in the RFID transponder.

4. The front-end circuit according to claim 3, characterized in that: The output signal of the level detector and / or the voltage limiter is configured to be enabled during startup of an integrated circuit included in the RFID transponder.

5. The front-end circuit according to claim 3, characterized in that: The output signals of the level detector and / or the voltage limiter are configured to be enabled in response to a command received from an external reader device.

6. The front-end circuit according to claim 1 or 2, characterized in that: The output signal of the level detector and / or the voltage limiter is permanently enabled.

7. The front-end circuit according to claim 1 or 2, characterized in that: The output signal of the level detector and / or the voltage limiter is periodically enabled.

8. A front-end circuit according to any preceding claim, characterised in that The output signal of the voltage limiter is a function of current dissipated by the voltage limiter.

9. An RFID transponder, characterized in that: The RFID transponder comprises a front end circuit according to any preceding claim and an integrated circuit operatively coupled to an output of the voltage limiter.

10. A method of operating a front-end circuit for a radio frequency identification (RFID) transponder, characterized in that: The front end circuit includes a rectifier, a voltage limiter and a level detector, and the method includes: The rectifier rectifies the input voltage received from the antenna; The output voltage of the rectifier is limited by the voltage limiter; The level of the output signal of the voltage limiter is compared with a predefined reference level by the level detector.

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