Interconnection architecture and simulation system of graphic processing chip

Abstract

The invention discloses an interconnection architecture of a graphic processing chip and a simulation system. The interconnection architecture comprises the graphic processing chip and an all-optical switching chip, and the graphic processing chips are interconnected through the all-optical switching chip. According to the interconnection architecture of the graphic processing chips disclosed by the invention, networking is carried out only by utilizing the optical switching chips, so that the time delays among the graphic processing chips are consistent, and the power consumption required by the distributed all-optical switching chips is very low, so that the power consumption required by the whole architecture is relatively low.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an interconnection architecture and a simulation system of a graphics processing chip. Background Art

[0002] With the rapid development of hardware and chip technology, artificial intelligence technology for machine learning has also made great progress. The current big data model based on image processing chips is bringing new changes to all walks of life. Traditional thinking and innovation models will be replaced by new artificial intelligence technologies. In order to simulate the brain's computing units for data learning and re-innovation, image processing chips need to interconnect a large number of chips for data exchange and collaborative computing.

[0003] The current mainstream interconnection solution is mainly a leaf-spine network topology with two layers of devices: the first layer uses chip packaging technology to integrate two or four graphics processing chips on a carrier board, and the chips are interconnected through carrier board routing. At the same time, two or four graphics processing chips on the carrier board integrate high-speed serial-parallel repeaters to realize the interconnection of more chips on the second layer; the second layer aggregates more high-speed serial-parallel repeaters on the graphics processing chip carrier board to a small-capacity electrical switching chip for networking and interconnection, in which cables or optoelectronic modules are used to interconnect the high-speed serial-parallel repeaters between the carrier board and the electrical switching chip for bidirectional communication.

[0004] This architecture of the prior art has the following problems: First, the interconnection between the graphics processing chips in the same computing node cannot guarantee the same latency, because each layer of electrical exchange convergence and distribution upward will bring additional latency, and the data packet reaches the destination after experiencing different layers of serial-to-parallel conversion, optoelectronic conversion and switching routing. Therefore, the latency between two or four graphics processing chips in the first layer is the shortest, the latency between the chips interconnected through the second layer is the second, and the latency between the chips interconnected through the third layer is the longest; second, with the exponential use of more small-capacity and large-capacity electrical exchange chips, the power configuration required for the entire computing node also increases exponentially, which brings the problem that the power configuration of the standard data center rack does not meet the requirements, and new technologies are also needed for chip heat dissipation, which requires very large changes to the standard data center rack. Summary of the invention

[0005] The present invention provides an interconnection architecture and a simulation system of a graphics processing chip to solve the problems of delay and high power consumption in the existing architecture.

[0006] According to one aspect of the present invention, there is provided an interconnection architecture of a graphics processing chip, comprising:

[0007] An interconnection architecture of a graphics processing chip, characterized by comprising a graphics processing chip and an all-optical switching chip;

[0008] The graphics processing chips are interconnected through the all-optical switching chip.

[0009] Optionally, the number of the all-optical switching chips is a first quantity, the number of the graphics processing chips is a second quantity, each all-optical switching chip includes a second quantity of input ports and a second quantity of output ports, each graphics processing chip includes a first quantity of receiving ports and a first quantity of transmitting ports, and the first quantity is equal to the second quantity minus one;

[0010] For each graphics processing chip, each transmitting port of the graphics processing chip is respectively connected to an input port of each all-optical switching chip, and each receiving port of the graphics processing chip is respectively connected to an output port of each all-optical switching chip.

[0011] Optionally, the graphics processing chip includes a single-fiber bidirectional optical-electric converter, the number of the all-optical switching chips is a third quantity, the number of the graphics processing chips is a fourth quantity, and the signal transmission between the graphics processing chip and the all-optical switching chip is bidirectional;

[0012] When the fourth quantity is an even number, the third quantity is one-half of the fourth quantity;

[0013] When the fourth quantity is an odd number, the third quantity is one-half of the fourth quantity minus one.

[0014] Optionally, the optical-electric converter includes an optical-electric conversion chip, and the optical-electric conversion chip includes a modulator and a reflector;

[0015] In the signal transmission direction, the electrical signal generated by the graphics processing chip is modulated to the optical-electric conversion chip, and the optical-electric conversion chip converts the electrical signal into an optical signal and reflects it to the transmission optical fiber;

[0016] In the signal reception direction, the optical-electric conversion chip receives the optical signal and converts it into an electrical signal, and the graphics processing chip receives the electrical signal sent by the optical-electric conversion chip.

[0017] Optionally, the interconnection architecture of the graphics processing chip further includes a central processing chip;

[0018] The central processing chip is used for scheduling and managing the graphics processing chip and the all-optical switching chip.

[0019] Optionally, the central processing chip is specifically used for:

[0020] Initialize and configure the ports of the all-optical switching chip through an existing protocol.

[0021] According to another aspect of the present invention, a simulation system for a graphics processing chip is established based on the interconnection architecture of the graphics processing chip according to any embodiment of the present invention and using programming simulation technology.

[0022] Optionally, the system can be used to evaluate the functions of the interconnection architecture of the graphics processing chip.

[0023] The interconnection architecture of the graphics processing chip disclosed in the present invention only uses optical switching chips for networking, so that the time delay between each graphics processing chip is consistent, and the power consumption required by the distributed all-optical switching chips is very low. Therefore, the overall architecture requires low power consumption.

[0024] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Brief Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0026] Figure 1 It is a diagram of the interconnection architecture of a graphics processing chip provided according to an embodiment of the present invention;

[0027] Figure 2 It is a topology diagram of an interconnection method of a graphics processing chip provided according to an embodiment of the present invention;

[0028] Figure 3 It is another topology diagram of an interconnection method of a graphics processing chip provided according to an embodiment of the present invention;

[0029] Figure 4 It is another topology diagram of an interconnection method of a graphics processing chip provided according to an embodiment of the present invention;

[0030] Figure 5 It is another topology diagram of an interconnection method of a graphics processing chip provided according to an embodiment of the present invention;

[0031] Figure 6 It is another topology diagram of an interconnection method of a graphics processing chip provided according to an embodiment of the present invention;

[0032] Figure 7It is a topology diagram of another interconnection method of a graphics processing chip provided according to an embodiment of the present invention;

[0033] Figure 8 It is a topology diagram of another interconnection method of a graphics processing chip provided according to an embodiment of the present invention;

[0034] Figure 9 It is an interconnection architecture diagram of another graphics processing chip provided according to an embodiment of the present invention;

[0035] Figure 10 It is a schematic structural diagram of an optoelectronic conversion chip provided according to an embodiment of the present invention;

[0036] Figure 11 It is an interconnection architecture diagram of another graphics processing chip provided according to an embodiment of the present invention;

[0037] Figure 12 It is a schematic structural diagram of a simulation system of a graphics processing chip provided according to an embodiment of the present invention. Detailed implementation manners

[0038] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0040] The embodiment of the present invention provides an interconnection architecture of a graphics processing chip, which includes a graphics processing chip and an all-optical switching chip, and the graphics processing chips are interconnected through the all-optical switching chip.

[0041] Specifically, an image processing chip is an integrated circuit chip dedicated to processing image data, with advantages such as fast processing speed, low energy consumption, and high performance. It is widely used in fields such as computer vision, artificial intelligence, and medical imaging, capable of achieving high-speed processing and analysis of images, and supporting the calculation of various complex algorithms. With the rapid development of hardware and chip technologies, the artificial intelligence technology for machine learning has also made great progress. Currently, the big data model based on image processing chips is bringing about a new revolution in all industries. The traditional thinking mode and innovation mode will be replaced by the new artificial intelligence technology. In order to simulate the brain's computing units for data learning and re-innovation, the image processing chip needs to perform data exchange and collaborative computing with a large number of interconnected chips. According to the interconnection architecture of the graphics processing chip provided by the embodiments of the present invention, the graphics processing chips are interconnected through all-optical switching chips, that is, an all-optical switching chip is used for networking to achieve the interconnection of graphics processing chips. Among them, an all-optical switching chip is a chip that performs information exchange based on optical signals. Its core lies in using optical signals for data transmission and processing without the need for optoelectronic conversion. The core technology of the all-optical switching chip is the optical switch and optical amplifier based on optical signals, and its basic principle is to achieve fast information exchange by controlling the optical path of optical signals. In terms of architecture, the all-optical switching chip usually adopts silicon-based optoelectronic technology, and realizes high-speed optical signal processing by integrating key devices such as optical waveguides, optical switches, and optical amplifiers. The all-optical switching chip has significant advantages in technology, which can significantly reduce energy consumption and improve transmission rate and system reliability.

[0042] In an embodiment of the present invention, the number of all-optical switching chips is the first quantity, the number of graphics processing chips is the second quantity. Each all-optical switching chip includes the second quantity of input ports and the second quantity of output ports. Each graphics processing chip includes the first quantity of receiving ports and the first quantity of transmitting ports, and the first quantity is equal to the second quantity minus one; for each graphics processing chip, the respective transmitting ports of the graphics processing chip are respectively connected to the input ports of the respective all-optical switching chips, and the respective receiving ports of the graphics processing chip are respectively connected to the output ports of the respective all-optical switching chips.

[0043] Figure 1It is an interconnection architecture diagram of a graphics processing chip provided by an embodiment of the present invention. In the figure, taking the interconnection of 8 graphics processing chips using 7 all-optical switching chips as an example, as shown in the figure, the figure includes 7 all-optical switching chips (denoted as sw0, sw1, sw2, sw3, sw4, sw5, sw6 respectively) and 8 graphics processing chips (denoted as GPU0, GPU1, GPU2, GPU3, GPU4, GPU5, GPU6, GPU7 respectively). Each all-optical switching chip includes 8 input ports and 8 output ports, and each graphics processing chip includes 7 receiving ports and 7 transmitting ports. The transmitting port Tx0 of the graphics processing chip GPU0 is connected to the input port 0 of the all-optical switching chip sw0. After being transmitted by the all-optical switching chip sw0, the output port 0 of the all-optical switching chip sw0 is connected to the receiving port Rx0 of the graphics processing chip GPU0; the transmitting port Tx1 of the graphics processing chip GPU0 is connected to the input port 0 of the all-optical switching chip sw1. After being transmitted by the all-optical switching chip sw1, the output port 0 of the all-optical switching chip sw1 is connected to the receiving port Rx1 of the graphics processing chip GPU0; and so on.

[0044] Figures 2-8 It is a topology diagram of 7 interconnection methods of graphics processing chips provided by an embodiment of the present invention. In each interconnection method, 0-7 represent 8 graphics processing chips, and the arrow direction represents the data flow direction. According to Figure 1 the interconnection architecture of the graphics processing chips shown, Figures 2-8 the 7 interconnection methods of the graphics processing chips shown can be realized. Among them, Figure 1 the 7 all-optical switching chips sw0 - sw6 in Figures 2-8 correspond to the interconnection methods in

[0045] In the interconnection architecture of the graphics processing chips provided by the embodiment of the present invention, only one layer of optical switching chips is used for networking, so that the delay between each graphics processing chip is consistent, and there is no need for additional optoelectronic conversion in the switching layer. Moreover, the power consumption required by the distributed all-optical switching chips is very low, and a small-current voltage source can ensure that the optical switching chips are configured in different topological structures. Therefore, the power consumption required by the interconnection architecture of the graphics processing chips provided by the embodiment of the present invention is relatively low.

[0046] In an embodiment of the present invention, the graphics processing chip includes a single-fiber bidirectional optoelectronic converter. The number of all-optical switching chips is the third quantity, and the number of graphics processing chips is the fourth quantity. The signal transmission between the graphics processing chip and the all-optical switching chip is bidirectional; when the fourth quantity is an even number, the third quantity is half of the fourth quantity; when the fourth quantity is an odd number, the third quantity is half of the fourth quantity minus one.

[0047] Specifically, a single-fiber bidirectional optical-electric converter can be set in the graphics processing chip. The graphics processing chips are networked and interconnected by using the single-fiber bidirectional optical-electric converter in combination with an all-optical switching chip. In this way, the number of all-optical switching chips required in the interconnection architecture of the graphics processing chips can be reduced. For example, if the number of graphics processing chips is 8, the number of all-optical switching chips required in the interconnection architecture of the graphics processing chips is 4; if the number of graphics processing chips is 7, the number of all-optical switching chips required in the interconnection architecture of the graphics processing chips is 3.

[0048] Figure 9 FIG. 4 is another interconnection architecture diagram of a graphics processing chip provided by an embodiment of the present invention. Taking the interconnection of 8 graphics processing chips by using 4 all-optical switching chips as an example, as shown in the figure, the figure includes 4 all-optical switching chips (sw0, sw1, sw2, sw3), and 8 graphics processing chips (GPU0, GPU1, GPU2, GPU3, GPU4, GPU5, GPU6, GPU7). Each graphics processing chip includes 7 receiving / transmitting ports. Due to the setting of the optical-electric converter, each receiving / transmitting port can both receive signals and transmit signals. The signal transmission between the graphics processing chip and the all-optical switching chip is bidirectional. Figure 9 The interconnection architecture of the graphics processing chip shown can also achieve Figures 2-8 the 7 interconnection modes of the graphics processing chips shown, where Figure 9 SW0 in FIG. 5 transmits corresponding to Figure 2 interconnection mode 1 in FIG. 6, and transmits from right to left corresponding to Figure 8 interconnection mode 7 in FIG. 7. And so on, SW1 corresponds to interconnection modes 2 and 6, SW2 corresponds to interconnection modes 3 and 5, and SW3 corresponds to interconnection mode 4.

[0049] According to the interconnection architecture of the graphics processing chip provided by the embodiment of the present invention, the graphics processing chips can achieve data interconnection and interoperability on the same path, and can effectively reduce the number of all-optical switching chips, thereby further reducing the system power consumption and cost.

[0050] Further, the optical-electric converter includes an optical-electric conversion chip, and the optical-electric conversion chip includes a modulator and a reflector; in the signal transmission direction, the electrical signal generated by the graphics processing chip is modulated to the optical-electric conversion chip, and the optical-electric conversion chip converts the electrical signal into an optical signal and reflects it to the transmission optical fiber; in the signal reception direction, the optical-electric conversion chip receives the optical signal and converts it into an electrical signal, and the graphics processing chip receives the electrical signal sent by the optical-electric conversion chip.

[0051] Specifically, an optoelectronic conversion chip is an integrated circuit chip that can convert light energy into electrical energy. The function of the modulator is to convert the characteristic information of an electrical signal into that of an optical signal, realizing the conversion from an electrical signal to an optical signal. The reflector is mainly used for the reflection and focusing of light. It can reflect light back at a specific angle or focus light on a specific area. In the embodiment of the present invention, a directly driven, parallel, single-fiber bidirectional optoelectronic conversion chip can be used for the interconnection of graphics processing chips. The signal interface generated by the graphics processing chip is directly modulated onto the optoelectronic conversion chip, and at the same time, the transceiver-in-one and single-fiber bidirectional functions are realized by using the reflector integrated in the optoelectronic conversion chip. Among them, the optoelectronic conversion chip and the reflector can be jointly realized through a silicon photonics integrated MZ modulator and an optical waveguide grating structure.

[0052] Figure 10 FIG. 4 is a schematic structural diagram of an optoelectronic conversion chip provided by an embodiment of the present invention. As shown in the figure, the optoelectronic conversion chip includes multiple signal channels. Each signal channel corresponds to a port of the graphics processing chip. Each signal channel includes a modulator, a reflector, and a corresponding receiver, and can realize the conversion between optical and electrical signals.

[0053] In the interconnection architecture of the graphics processing chip provided by the embodiment of the present invention, an optoelectronic converter can be used to eliminate the serial-to-parallel converter in the traditional architecture, thereby reducing the overall interconnection power consumption.

[0054] In an embodiment of the present invention, the interconnection architecture of the graphics processing chip further includes a central processing chip; the central processing chip is used for scheduling and managing the graphics processing chip and the all-optical switching chip.

[0055] Further, the central processing chip is specifically used for: performing port initialization configuration on the all-optical switching chip through an existing protocol.

[0056] Specifically, the central processing chip is the core component of a computer system, responsible for interpreting and executing most of the instructions issued by other hardware and software of the computer. Through the central processing chip, centralized unified management, scheduling, operation, and maintenance of the all-optical switching chip and the graphics processing chip in the interconnection architecture of the graphics processing chip can be performed. Through the PCIe or SPI interface in the central processing chip, the existing protocol can be used to perform initialization port configuration on the all-optical switching chip, so that all all-optical chips can be configured into a state that meets each interconnection method at the same time.

[0057] Figure 11 FIG. 20 is another interconnection architecture diagram of a graphics processing chip provided by an embodiment of the present invention. In the figure, taking the interconnection of 8 graphics processing chips by using 4 all-optical switching chips as an example, as shown in the figure, this architecture includes two central processing chips, and can realize the scheduling and management of 4 all-optical switching chips and 8 graphics processing chips.

[0058] With the central processing chip, the interconnection architecture of the graphics processing chip provided by the embodiments of the present invention can adapt to the unified interface of the current graphics processing chip to control and schedule the all-optical switching chip.

[0059] In an embodiment of the present invention, a simulation system for a graphics processing chip is further provided. The system is established according to the interconnection architecture of the graphics processing chip described in any of the above embodiments and by using programming simulation technology.

[0060] Furthermore, the system can be used to evaluate the function of the interconnection architecture of the graphics processing chip.

[0061] Specifically, in the interconnection architecture of the graphics processing chip provided by the present invention, an all-optical switching chip is combined with a directly-driven optoelectronic conversion module to realize the interconnection of the graphics processing chips. This has some essential changes compared with the data center interconnection architecture in the prior art. The most core change lies in the processing of the electrical signal transmission performance and the optical signal transmission performance.

[0062] In the data center architecture in the prior art, the processing of electrical signals and optical signals is completely decoupled, maximizing the performance of each responsible for its own, with a very complete boundary definition. To achieve this decoupling, some digital signal processing has to be reused at different nodes. As the bandwidth continues to increase, the required digital signal processing algorithms become more and more complex, resulting in an increase in more power consumption. In order to pursue the maximum reduction of power consumption, the entire end-to-end link needs to integrate the processing of optical signals and electrical signals, and use as little digital signal processing technology as possible to achieve the unified processing of optoelectronic signals. Such integration will bring about the blurring of the boundary, resulting in the need to establish a complete optoelectronic fusion model for the evaluation of transmission performance.

[0063] Figure 12 It is a schematic structural diagram of a simulation system for a graphics processing chip provided by the embodiments of the present invention. As shown in the figure, the system includes a signal generator, a digital signal processing unit, a link electrical model, a driver chip model, a laser model, an optical modulation chip model, an optical fiber model, an overall optical path loss model, an optoelectronic receiver model, a cross-group conversion model, a digital signal processing unit, and an error code analyzer.

[0064] The system can evaluate the end-to-end transmission performance by combining digital signal processing algorithms with the models of optical and electrical chips, and evaluate the main functions of the interconnection architecture of the graphics processing chip through code programming simulation technology. The main role of the evaluation is to provide technical guidance for various chip designs before the actual product, such as determining how much bandwidth is required for the silicon optical modulator; if the bandwidth is not satisfied, how much data processing function needs to be adjusted to meet the requirements of the receiver error code, etc. The system can evaluate the interconnection architecture of the graphics processing chip as follows:

[0065] Evaluate the influence of the frequency response, insertion loss, return loss, and crosstalk of the electrical link on the transmission performance;

[0066] Evaluate the influence of the performance indicators of the laser on the transmission performance;

[0067] Evaluate the influence of the frequency response of the optical modulator on the link performance;

[0068] Evaluate the influence of fiber dispersion and polarization mode dispersion on the transmission performance;

[0069] Evaluate the influence of the bandwidth and noise of model chips such as CTLE, driver, and cross-group amplifier on the transmission performance;

[0070] Utilize the modeling of the digital signal processing unit FFE / DFE to evaluate the use of the optimized signal processing nodes for different links.

[0071] Using the simulation system of the graphics processing chip provided by the embodiments of the present invention, theoretical guidance and early feasibility analysis can be carried out on the interconnection architecture of the graphics processing chip, and through simulation analysis, the performance of the optical chip can be optimized to achieve the interconnection architecture design with the lowest power consumption, and the digital signal processing unit can be optimized to achieve the interconnection architecture design with the lowest power consumption.

Claims

1. An interconnection architecture of a graphics processing chip, characterized in that: Including graphics processing chips and all-optical switching chips; The graphics processing chips are interconnected through the all-optical switching chip.

2. The architecture according to claim 1, characterized in that The number of the all-optical switching chips is a first number, the number of the graphics processing chips is a second number, each of the all-optical switching chips includes a second number of input ports and a second number of output ports, each of the graphics processing chips includes a first number of receiving ports and a first number of transmitting ports, and the first number is equal to the second number minus one; For each of the graphics processing chips, each transmitting port of the graphics processing chip is respectively connected to an input port of each of the all-optical switching chips, and each receiving port of the graphics processing chip is respectively connected to an output port of each of the all-optical switching chips.

3. The method according to claim 1, characterized in that The graphics processing chip includes a single-fiber bidirectional photoelectric converter, the number of the all-optical switching chips is the third number, the number of the graphics processing chips is the fourth number, and the signal transmission between the graphics processing chip and the all-optical switching chip is bidirectional; When the fourth number is an even number, the third number is half of the fourth number; When the fourth number is an odd number, the third number is half of the fourth number minus one.

4. The method according to claim 3, characterized in that The photoelectric converter includes a photoelectric conversion chip, and the photoelectric conversion chip includes a modulator and a reflector; In the signal transmission direction, the electrical signal generated by the graphics processing chip is modulated to the photoelectric conversion chip, and the photoelectric conversion chip converts the electrical signal into an optical signal and reflects it to the transmission optical fiber; In the signal receiving direction, the photoelectric conversion chip receives the optical signal and converts it into an electrical signal, and the graphics processing chip receives the electrical signal sent by the photoelectric conversion chip.

5. The method according to claim 1, characterized in that The interconnection architecture of the graphics processing chip also includes a central processing chip; The central processing chip is used to schedule and manage the graphics processing chip and the all-optical switching chip.

6. The method according to claim 5, characterized in that The central processing chip is specifically used for: The port initialization configuration of the all-optical switching chip is performed through an existing protocol.

7. A simulation system for a graphics processing chip, characterized in that: The system is established according to the interconnection architecture of the graphics processing chip according to claims 1-6 and using programming simulation technology.

8. The system according to claim 7, characterized in that The system can be used to perform functional evaluation on the interconnection architecture of the graphics processing chip.

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