Ultrasonic mode control circuit for limiting lower limit of light load switching frequency

Abstract

The invention belongs to the technical field of power management, and particularly relates to an ultrasonic mode control circuit for limiting the lower limit of light load switching frequency. According to the invention, an ultrasonic mode control circuit is designed, and the ultrasonic mode control circuit is nested in the switching converter as an independent circuit and can monitor the switching period. When the switching period is close to the audio frequency range, the DCM state is forcibly quitted, and the flip point of the ZCD is adjusted through the loop to enable the inductive current to flow backward, so that the circuit balance is realized. According to the invention, the problem of noise interference of the current switching power supply converter in an extremely light load state is solved from the source. As the system load is gradually reduced, the circuit switching frequency is gradually reduced so as to improve the conversion efficiency. When the switching frequency is reduced to a designed lower limit threshold, the frequency is stable and does not continue to be reduced. The system has the advantages of a current mainstream control mode for improving light load efficiency, and solves the problem of noise during extremely light load.

Description

Technical Field

[0001] The present invention belongs to the technical field of power management, and particularly relates to an ultrasonic mode control circuit for limiting the lower limit of the switching frequency under light load. Background Art

[0002] Switching power converters such as buck, boost, etc. occupy an increasingly important position in power management chips due to their high conversion efficiency, wide application range, and small volume. The efficiency of a linear voltage regulator LDO is the ratio of the output voltage to the input voltage, resulting in a very low conversion efficiency when the difference between the input and output voltages is large. Ideally, a switching power converter can achieve lossless conversion at any voltage. Although the on-resistance of the power transistor and switching losses will reduce the conversion efficiency of the converter to a certain extent, a high efficiency can still be achieved. Therefore, switching power converters are widely used at present.

[0003] In recent years, with the development of the Internet of Things and wearable devices, people have paid more and more attention to improving the standby time of electronic devices. Therefore, reducing the light-load power consumption has become a development trend of power management chips. In addition to reducing the static power consumption of the chip itself, it is also necessary to reduce the dynamic losses under light load. If the continuous conduction mode (CCM) is still maintained under light load, the switching losses will significantly affect the light-load efficiency. Currently, a commonly used method to improve the light-load efficiency is to reduce the switching frequency under light load. For example, constant on-time (COT) control is adopted. Through zero-crossing detection (ZCD), when the inductor current crosses zero, the converter enters the discontinuous conduction mode (DCM). The smaller the load current, the lower the switching frequency, so the proportion of switching losses is smaller, and a relatively high efficiency can be maintained under light load. This will cause the switching frequency of the chip to be as low as the kHz or even Hz level under extremely light load or no load conditions. This frequency range will bring unwanted noise. Of course, a complex electromagnetic shielding cover can be designed to filter out this noise, but this will result in corresponding sacrifices in cost, weight, and volume. Summary of the Invention

[0004] Aiming at the contradiction between the current mainstream control modes in terms of light-load efficiency and electromagnetic interference (EMI) in the audio range, the present invention proposes an ultrasonic mode control circuit for limiting the lower limit of the switching frequency under light load, so as to avoid noise interference that occurs when the circuit operates at low frequencies under light load from the source.

[0005] The technical solution of the present invention is as follows:

[0006] An ultrasonic mode control circuit for limiting the lower limit of the light load switching frequency, which is used in a switching power supply converter. Define the output voltage of the switching power supply converter as Vout and the feedback voltage as VFB. There is a zero-crossing detection circuit in the switching power supply converter, and the switching power supply converter enters the discontinuous conduction mode (DCM) after receiving the zero-crossing signal; the error amplifier is used to compare the feedback voltage V FB and the reference voltage V REF to obtain the error signal EA OUT ; characterized in that the ultrasonic mode control circuit outputs a first control signal V OUT and a second control signal V COMP according to the error signal EA C , where the first control signal V COMP is used to control the zero-crossing detection timing of the switching power supply converter, and the second control signal V C is used to control the time for the switching power supply converter to exit the DCM, so that under light load conditions, the DCM time of the control circuit is forced to avoid the frequency from entering the audible noise range.

[0007] Further, the ultrasonic mode control circuit includes a current sampling circuit with a zero-crossing detection function. The current sampling circuit includes a power PMOS transistor, a first PMOS transistor, a second MOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first MOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first resistor, a second resistor, and a comparator; the ultrasonic mode control circuit also includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a first bias current source, a second bias current source, a third bias current source, a fourth bias current source, a fifth bias current source, a first capacitor, a second capacitor, a third capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a Schmitt trigger;

[0008] In the described current sampling circuit, the source of the power PMOS transistor is connected to the connection point of the P power transistor and the N power transistor in the switching power supply converter. The gate of the power PMOS transistor is connected to the same driving signal as the gate of the P power transistor in the switching power supply converter. The drain of the power PMOS transistor is connected to the source of the first PMOS transistor. The source of the second PMOS transistor is connected to Vout. The gates of the first PMOS transistor and the second PMOS transistor are connected to the first enable signal, and the first enable signal is at a low level only when the P power transistor in the switching power supply converter is conducting. The sources of the third PMOS transistor and the fourth PMOS transistor are connected to Vout. The gate and drain of the third PMOS transistor are interconnected and connected to the drain of the first PMOS transistor, the drain of the first NMOS transistor, and the negative input terminal of the comparator. The gate and drain of the fourth PMOS transistor are interconnected and connected to the drain of the second PMOS transistor, the drain of the second NMOS transistor, and the positive input terminal of the comparator. The output terminal of the comparator outputs the first control signal V COMP ; The gates of the first NMOS transistor and the second NMOS transistor are connected to the second enable signal, and the second enable signal is a high-level signal. The drain of the third NMOS transistor is connected to the source of the first NMOS transistor. The drain of the fourth NMOS transistor is connected to the source of the second NMOS transistor. The gates of the third NMOS transistor and the fourth NMOS transistor are connected to the error signal EA OUT ; The drain of the fifth NMOS transistor is connected to the source of the third NMOS transistor. The drain of the sixth NMOS transistor is connected to the source of the fourth NMOS transistor. The gates of the fifth NMOS transistor and the sixth NMOS transistor are connected to the error signal EA OUT ; The source of the fifth NMOS transistor is grounded through the first resistor, and the source of the sixth NMOS transistor is grounded through the second resistor;

[0009] The eighth PMOS transistor, the first bias current source, the second bias current source, the twelfth NMOS transistor, the eleventh NMOS transistor, the seventh resistor, the eighth resistor, and the first capacitor form a lower limit clamping loop. Among them, the source of the eighth PMOS transistor is connected to the power supply, and its gate and drain are interconnected. The drain of the twelfth NMOS transistor is connected to the drain of the eighth PMOS transistor and the input terminal of the second bias current source. The output terminal of the second bias current source is grounded, and the source of the twelfth NMOS transistor is connected to the error signal EA OUT , the gate of the twelfth NMOS transistor is connected to the output terminal of the first bias current source, the drain of the eleventh NMOS transistor, and one end of the eighth resistor. The input terminal of the first bias current source is connected to the power supply. The gate of the eleventh NMOS transistor is connected to the error signal EA OUT , its source is grounded through the seventh resistor, and the other end of the eighth resistor is grounded through the first capacitor;

[0010] The seventh PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the third bias current source, the fourth bias current source, the fifth bias current source, the second capacitor, the third resistor, the fourth resistor, and the Schmitt trigger form a timing circuit; wherein, the source of the ninth PMOS transistor is connected to the power supply, and its gate is connected to the drain of the eighth PMOS transistor; the source of the tenth PMOS transistor is connected to the drain of the ninth PMOS transistor; the gate of the tenth PMOS transistor is connected to the bias voltage (VB), and its drain is connected to the drain and gate of the thirteenth NMOS transistor and the gate of the fourteenth NMOS transistor; the source of the thirteenth NMOS transistor is grounded; the drain of the fortieth NMOS transistor is connected to the output terminal of the third bias current source, the source of the fifteenth NMOS transistor, and the gate of the sixteenth NMOS transistor, and the source of the fourteenth NMOS transistor is grounded; the input terminal of the third bias current source is connected to the power supply; the source of the eleventh PMOS transistor is connected to the power supply, and its gate and drain are interconnected; the drain of the fifteenth NMOS transistor is connected to the drain of the eleventh PMOS transistor, and the gate of the fifteenth NMOS transistor is connected to the output terminal of the fifth bias current source, the drain of the seventh NMOS transistor, and one end of the second capacitor; the input terminal of the fifth current source is connected to the power supply; the drain of the sixteenth NMOS transistor is connected to the power supply, and its source is connected to the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, and the input terminal of the fourth bias current source; the source of the seventh NMOS transistor is grounded through the third resistor, and the source of the eighth NMOS transistor is grounded through the fourth resistor; the other end of the second capacitor is grounded, and the output terminal of the fourth bias current source is grounded; the source of the seventh PMOS transistor is connected to the power supply, and its gate is connected to the third enable signal, and the third enable signal is only at a high level in DCM; the input terminal of the Schmitt trigger is connected to the drain of the seventh PMOS transistor and the drain of the eighth NMOS transistor, and the output terminal of the Schmitt trigger outputs the second control signal V C ;

[0011] The fifth PMOS transistor, the sixth PMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the fifth resistor, the sixth resistor, and the third capacitor form a current amplification circuit; wherein, one end of the third capacitor is connected to the drain of the seventh PMOS transistor, and the other end is grounded; the source of the fifth PMOS transistor is connected to the power supply, and its gate is connected to the drain of the eleventh PMOS transistor; the source of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the sixth PMOS transistor is connected to the bias voltage, and the drain of the sixth PMOS transistor is connected to the drain and gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor; the source of the ninth NMOS transistor is grounded through the fifth resistor; the source of the tenth NMOS transistor is grounded through the sixth resistor; the drain of the tenth NMOS transistor is connected to the source of the second NMOS transistor and the drain of the fourth NMOS transistor.

[0012] Further, the drain current of the eighth PMOS transistor is the clamping current I clamp , expressed as:

[0013] I clamp = g m,EA (V FB - V REF )

[0014] where g m,EA is the transconductance of the error amplifier;

[0015] The clamping current I clamp is mirror - copied to the drain current of the fourteenth NMOS transistor, and the current of the third bias current source is greater than that of the second bias current source, so that the gate signal of the sixteenth NMOS transistor is at a high level when there is no clamping current; setting the seventh NMOS transistor and the eighth NMOS transistor to be the same, and the third resistor and the fourth resistor to be the same, the timing time is obtained as:

[0016]

[0017] where V DD is the power supply voltage, I bias5 is the current of the fifth bias current source, and t represents the longest duration of DCM;

[0018] Setting the currents of the third bias current source and the fourth bias current source to be the same, so that the current in the fifth PMOS transistor is the clamping current I clamp , after passing through the current amplification circuit, the amplified current I change is output by the tenth NMOS transistor to the current sampling circuit. After I change is injected into the current sampling circuit, the zero - crossing point during light load is adjusted to a negative value, thereby realizing the inductor current reverse injection.

[0019] The beneficial effect of the present invention is that it solves the noise interference problem in the extremely light - load state of the current switching - mode power supply converter from the source. As the system load gradually changes from heavy to light, the circuit switching frequency will gradually decrease to improve the conversion efficiency. When the switching frequency decreases to the designed lower threshold, the frequency is stable and will not continue to decrease. It not only has the advantages of the current mainstream light - load efficiency improvement control mode but also solves the noise problem in the extremely light - load state. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram of a traditional circuit structure.

[0021] Figure 2 is a schematic diagram of the circuit structure of the present invention.

[0022] Figure 3 is a schematic diagram of the circuit structure of Embodiment 1.

[0023] Figure 4 It is a schematic diagram of the circuit structure in Embodiment 2. Specific Embodiment

[0024] The present invention will be described in detail below with reference to the accompanying drawings.

[0025] The traditional frequency reduction scheme is a good method to improve the light load efficiency. However, since it allows the switching frequency to drop freely, when the switching frequency is low enough to be within the audible range of human hearing, it will cause noise interference, which is not conducive to the application scenarios of current portable devices. The present invention designs an ultrasonic mode control circuit. As an independent circuit, it is nested in the switching converter and can monitor the switching period. When the switching period approaches the audio range, it forcibly exits the DCM state and adjusts the flip point of the ZCD through the loop to reverse the inductor current, thereby achieving circuit balance.

[0026] As Figure 1 shown, this figure shows a specific application schematic diagram of the ultrasonic mode control circuit proposed by the present invention when used in a Boost converter. The designed ultrasonic mode control circuit requires the output EA of the error amplifier (EA) OUT as the input signal and outputs the V COMP signal to control the ZCD timing of the Boost converter, and the V C signal to control the time to exit the DCM. When the system is extremely lightly loaded, if the circuit is forced to maintain a fixed DCM time to avoid the frequency entering the audible noise range, according to the law of conservation of energy, the output voltage V OUT will continuously accumulate energy, causing V FB to be higher than V REF . By setting the lower limit clamping loop of EA OUT , the clamping current can reflect the deviation value between V FB and V REF . By constructing a negative feedback loop with this signal to automatically adjust the flip point of the ZCD, the control of the lower limit of the light load frequency can be achieved.

[0027] Figure 2 Namely, it is the specific circuit diagram of the ultrasonic mode control circuit designed by the present invention. The rightmost part is the lower limit clamping loop, and the clamping current I clamp is:

[0028] I clamp = g m,EA (V FB - V REF )

[0029] where g m,EAis the transconductance of the error amplifier EA. The clamping current is copied to MN14 through a series of mirrors. Setting the Ibias3 current greater than the Ibias2 current can ensure that V1 is at a high level without the clamping current. When there is a certain clamping current, the negative feedback loop shown by the red line is established, and C2 is used to compensate the loop. Setting MN7 and MN8 equal and R3 and R4 equal can achieve a current of Ibias5 in MN8. The control signal Ctrol of MP7 is high only in the DCM stage, that is, V2 is reset to VDD in the non-DCM stage, and the current discharges the capacitor C3 in the DCM stage. When V2 is lower than the low-level threshold of the Schmitt trigger, V C flips high to exit the DCM. Therefore, the timing time can be obtained as:

[0030]

[0031] So the longest DCM time is the set time t above. By reasonably setting the sizes of Ibias5 and C3, it can be ensured that the switching frequency does not enter the noise range. When the load gradually becomes heavier, the clamping current starts to decrease, the voltage of V3 will rise and make the current flowing through MN8 greater than Ibias5, so that the loop can automatically adjust the DCM time. This circuit only sets the upper limit of the DCM time. When the load is heavy enough, V3 will be high enough to quickly pull V2 to a low potential, so there is no DCM time.

[0032] Setting Ibias3 equal to Ibias4 can make the current flowing through MP5 also be I clamp which is proportionally amplified to generate I change and input into the current sampling circuit. The current sampling circuit samples the current in the power transistor M P i.e., the inductor current, according to a certain ratio. When V COMP flips high, it means that the inductor current crosses zero, and I change can change its flip point.

[0033] Figure 3 is the current sampling circuit proposed by the present invention for detecting the zero-crossing of the inductor current, and this figure details how I change adjusts the flip point of the zero-crossing of the inductor current. Among them, ENH is usually at a high level, but ENL is at a low level only when the P power transistor is conducting. MP3 and MP4 are used to set the initial values of V+ and V- to speed up the sampling speed. Compared with the current mainstream closed-loop current sampling scheme, the sampling speed is limited by the loop bandwidth, and high-speed current sampling requires high power consumption. Therefore, we designed such an open-loop current sampling structure to achieve fast sampling and use a differential method to suppress circuit noise. The voltages of V+ and V- can be obtained as:

[0034]

[0035] And we can obtain the relationship between the inductor current and the SW and Vout voltages:

[0036] SW-V OUT = I L R on,MP

[0037] By setting MPS, MP1, and MP2 to be exactly the same and the MOS transistors and resistors at corresponding positions on the two branches to be exactly the same, and by equating V+ and V-, the flip point can be obtained:

[0038]

[0039] MPS and MP are transistors of the same type. The current sampling ratio of the circuit can be set by only adjusting the aspect ratios of the two and the resistance value of R1.

[0040] Through the lower limit clamping loop, the lower limit value of the EA_OUT voltage can be set near the threshold voltage of the NMOS transistor. In this case, the following can be obtained:

[0041]

[0042] Therefore, this circuit can be used for ZCD detection. Considering I change And recalculate the result when V+ is equal to V-:

[0043] I L R on,MP = -I change R on,MPS

[0044] Therefore, injecting a current I change can adjust the zero-crossing point to a negative value under light load, that is, realize inductor current reverse injection. The circuit proposed by the present invention can automatically adjust the zero-crossing point to achieve stable operation of the circuit by designing a closed-loop system.

[0045] Figure 4 is the typical waveform of the proposed ultrasonic mode control circuit. At the same time, loop small-signal analysis will be carried out with the aid of this figure. Under extremely light load, I valley is approximately equal to I peak , so t2 is less than or equal to t1. From the perspective of energy conservation, the integral of the inductor current at t1 and t2 multiplied by the input voltage should be equal to the integral of the load current at T SW multiplied by the output voltage. I valley will automatically adjust between 0-I peak according to the load condition. Since it is a closed-loop control, it is necessary to abstractly model the power stage and compensate the loop. The following results are obtained from the loop analysis:

[0046]

[0047] where \(R_L\) and \(C_L\) are the load circuit and load capacitance, and \(k\) is the amplification factor from \(I\) clamp to \(I\) change . Thus, we can obtain:

[0048]

[0049] The internal resistance of the controlled source itself is ignored in the above small-signal analysis, but it does not affect the design. In actual design, an appropriate loop bandwidth can be designed according to the characteristics of one's own circuit, and the maximum bandwidth should be ensured to be below 1 / 5 of the switching frequency to ensure the stable operation of the negative feedback loop.

Claims

1. An ultrasonic mode control circuit for limiting the lower limit of light-load switching frequency, used for a switching power converter, wherein the output voltage of the switching power converter is defined as Vout, the feedback voltage is defined as VFB, the switching power converter has a zero-crossing detection circuit, and the switching power converter enters a discontinuous conduction mode (DCM) after receiving a zero-crossing signal; the feedback voltage V is detected by an error amplifier. FB and reference voltage V REF Compare and get the error signal EA OUT ; It is characterized in that, The ultrasonic mode control circuit is based on the error signal EA OUT Output the first control signal V COMP and the second control signal V C , where the first control signal V COMP The second control signal V is used to control the zero-crossing detection timing of the switching power converter. C It is used to control the time when the switching power converter exits DCM, so that under light load conditions, the DCM time of the control circuit is forced to avoid the frequency entering the noise range.

2. The ultrasonic mode control circuit for limiting the lower limit of light load switching frequency according to claim 1, characterized in that: The ultrasonic mode control circuit includes a current sampling circuit with a zero-crossing detection function, and the current sampling circuit includes a power PMOS tube, a first PMOS tube, a second MOS tube, a third PMOS tube, a fourth PMOS tube, a first MOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first resistor, a second resistor, and a comparator; the ultrasonic mode control circuit also includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a first bias current source, a second bias current source, a third bias current source, a fourth bias current source, a fifth bias current source, a first capacitor, a second capacitor, a third capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a Schmitt trigger; In the current sampling circuit, the source of the power PMOS tube is connected to the connection point of the P power tube and the N power tube in the switching power converter, the gate of the power PMOS tube and the gate of the P power tube in the switching power converter are connected to the same driving signal, and the drain of the power PMOS tube is connected to the source of the first PMOS tube; the source of the second PMOS tube is connected to Vout, the gate of the first PMOS tube and the gate of the second PMOS tube are connected to the first enable signal, and the first enable signal is at a low level only when the P power tube in the switching power converter is turned on; the source of the third PMOS tube and the source of the fourth PMOS tube are connected to Vout, the gate and drain of the third PMOS tube are interconnected, and are connected to the drain of the first PMOS tube, the drain of the first NMOS tube, and the negative input terminal of the comparator; the gate and drain of the fourth PMOS tube are interconnected, and are connected to the drain of the second PMOS tube, the drain of the second NMOS tube, and the positive input terminal of the comparator; the output terminal of the comparator outputs the first control signal V COMP The gate of the first NMOS tube and the gate of the second NMOS tube are connected to the second enable signal, and the second enable signal is a high level signal; the drain of the third NMOS tube is connected to the source of the first NMOS tube, the drain of the fourth NMOS tube is connected to the source of the second NMOS tube, and the gate of the third NMOS tube and the gate of the fourth NMOS tube are connected to the error signal EA OUT The drain of the fifth NMOS tube is connected to the source of the third NMOS tube, the drain of the sixth NMOS tube is connected to the source of the fourth NMOS tube, and the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are connected to the error signal EA OUT The source of the fifth NMOS tube is grounded after passing through the first resistor, and the source of the sixth NMOS tube is grounded after passing through the second resistor; The eighth PMOS tube, the first bias current source, the second bias current source, the twelfth NMOS tube, the eleventh NMOS tube, the seventh resistor, the eighth resistor, and the first capacitor form a lower limit clamping loop; wherein the source of the eighth PMOS tube is connected to the power supply, and the gate and drain thereof are interconnected; the drain of the twelfth NMOS tube is connected to the drain of the eighth PMOS tube and the input end of the second bias current source; the output end of the second bias current source is grounded, and the source of the twelfth NMOS tube is connected to the error signal EA OUT The gate of the twelfth NMOS tube is connected to the output end of the first bias current source, the drain of the eleventh NMOS tube, and one end of the eighth resistor; the input end of the first bias current source is connected to the power supply; the gate of the eleventh NMOS tube is connected to the error signal EA OUT , its source is grounded after passing through the seventh resistor, and the other end of the eighth resistor is grounded after passing through the first capacitor; The seventh PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube, the seventh NMOS tube, the eighth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth NMOS tube, the third bias current source, the fourth bias current source, the fifth bias current source, the second capacitor, the third resistor, the fourth resistor, and the Schmitt trigger constitute a timing circuit; wherein, the source of the ninth PMOS tube is connected to the power supply, and the gate thereof is connected to the drain of the eighth PMOS tube; the source of the tenth PMOS tube is connected to the drain of the ninth PMOS tube; the gate of the tenth PMOS tube is connected to the bias voltage, and the drain thereof is connected to the drain and gate of the thirteenth NMOS tube and the gate of the fourteenth NMOS tube; the source of the thirteenth NMOS tube is grounded; the drain of the fortieth NMOS tube is connected to the output end of the third bias current source, the source of the fifteenth NMOS tube, the gate of the sixteenth NMOS tube, and the source of the fourteenth NMOS tube is grounded; the The input end is connected to the power supply; the source of the eleventh PMOS tube is connected to the power supply, and the gate and drain thereof are interconnected; the drain of the fifteenth NMOS tube is connected to the drain of the eleventh PMOS tube, and the gate of the fifteenth NMOS tube is connected to the output end of the fifth bias current source, the drain of the seventh NMOS tube, and one end of the second capacitor; the input end of the fifth current source is connected to the power supply; the drain of the sixteenth NMOS tube is connected to the power supply, and the source thereof is connected to the gate of the seventh NMOS tube, the gate of the eighth NMOS tube, and the input end of the fourth bias current source; the source of the seventh NMOS tube is grounded after passing through the third resistor, and the source of the eighth NMOS tube is grounded after passing through the fourth resistor; the other end of the second capacitor is grounded, and the output end of the fourth bias current source is grounded; the source of the seventh PMOS tube is connected to the power supply, and the gate thereof is connected to the third enable signal, and the third enable signal is high level only in DCM; the input end of the Schmitt trigger is connected to the drain of the seventh PMOS tube and the drain of the eighth NMOS tube, and the output end of the Schmitt trigger outputs the second control signal V C ; The fifth PMOS tube, the sixth PMOS tube, the ninth NMOS tube, the tenth NMOS tube, the fifth resistor, the sixth resistor, and the third capacitor constitute a current amplification circuit; wherein one end of the third capacitor is connected to the drain of the seventh PMOS tube, and the other end is grounded; the source of the fifth PMOS tube is connected to the power supply, and the gate thereof is connected to the drain of the eleventh PMOS tube; the source of the sixth PMOS tube is connected to the drain of the fifth PMOS tube, the gate of the sixth PMOS tube is connected to the bias voltage, and the drain of the sixth PMOS tube is connected to the drain and gate of the ninth NMOS tube and the gate of the tenth NMOS tube; the source of the ninth NMOS tube is grounded after passing through the fifth resistor; the source of the tenth NMOS tube is grounded after passing through the sixth resistor; the drain of the tenth NMOS tube is connected to the source of the second NMOS tube and the drain of the fourth NMOS tube.

3. The ultrasonic mode control circuit for limiting the lower limit of light load switching frequency according to claim 2, characterized in that: The drain current of the eighth PMOS tube is the clamping current I clamp , expressed as: I clamp =g m,EA (V FB -V REF ) Among them, g m,EA is the transconductance of the error amplifier; Clamping current I clamp The drain current of the fourteenth NMOS tube is mirrored, and the current of the third bias current source is greater than the current of the second bias current source, so that the gate signal of the sixteenth NMOS tube is at a high level when there is no clamping current; the seventh NMOS tube is set to be the same as the eighth NMOS tube, and the third resistor is the same as the fourth resistor, then the timing time is: Where V DD is the supply voltage, I bias5 is the current of the fifth bias current source, t represents the maximum duration of DCM; The currents of the third bias current source and the fourth bias current source are set to be the same, so that the current in the fifth PMOS tube is the clamping current I clamp After passing through the current amplifier circuit, the tenth NMOS tube outputs the amplified current I change To the current sampling circuit, at I change After being injected into the current sampling circuit, the zero-crossing point is adjusted to a negative value when the load is light, thereby realizing the reverse injection of the inductor current.

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