Preparation method of FD-SOI substrate structure through hydrogen, boron and nitrogen ion implantation process

Abstract

The invention discloses a preparation method of an FD-SOI substrate structure through a hydrogen, boron and nitrogen ion implantation process, and belongs to the technical field of semiconductor design and manufacturing. The preparation method comprises the following steps: preparing a first wafer and a second wafer; performing thermal oxidation treatment on the surface of the first wafer; performing hydrogen ion implantation and boron and nitrogen ion implantation processes on the first wafer to enable the first wafer to form a hydrogen implantation layer below the insulating oxide layer and form a boron and nitrogen implantation layer between the hydrogen implantation layer and the insulating oxide layer; combining the surface of the insulating oxide layer of the first wafer with a second wafer through a bonding process; stripping the first wafer, and recrystallizing the top silicon film through thermal annealing treatment; and etching the top-layer silicon film to be below the boron-nitrogen injection layer through wet etching treatment, so that the top-layer silicon film reaches the required thickness. According to the invention, the required ultrathin film structure can be obtained in a more controllable manner, and the single crystal property of the top silicon film is ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor design and manufacturing, and particularly relates to a preparation method of an FD-SOI substrate structure by hydrogen, boron, and nitrogen ion implantation processes. Background Art

[0002] For transistors fabricated using FD-SOI (Fully Depleted Silicon on Insulator) technology, the silicon thin film defines the source-drain junction depth and depletion region, which can improve short-channel effects such as DIBL (Drain Induced Barrier Lowering), further improve the subthreshold characteristics of the device, and reduce the static power consumption of the circuit. Compared with traditional Bulk Silicon technology, FD-SOI can provide better transistor electrostatic characteristics, and the buried oxide can reduce the parasitic capacitance between the source and the drain. In addition, this technology can effectively limit the electron flow between the source and the drain, significantly reducing the leakage current performance of the device. Therefore, the FD-SOI technology is highly competitive and has become a solution for advanced chips. However, to obtain transistors with smaller feature sizes, in the FD-SOI substrate structure, an ultra-thin top silicon thin film needs to be formed. The existing FD-SOI technology uses chemical mechanical polishing to form this film layer structure, which has problems such as difficulty in controlling the layer thickness, and there is likely to be a large (e.g., more than 10%) thickness difference at the wafer edge, and surface scratches will also occur. The top silicon thin film of the existing FD-SOI substrate structure is relatively thick, so the above defects do not significantly affect the performance; while for an ultra-thin top silicon thin film such as at the nanoscale, the above defects will significantly affect the performance. In addition, during the process, it is also necessary to pay attention not to introduce impurities to ensure the single-crystallinity of the top silicon thin film. Summary of the Invention

[0003] Based on the technical problems existing in the prior art, the present invention provides a preparation method of an FD-SOI substrate structure by hydrogen, boron, and nitrogen ion implantation processes, which solves the problems in the prior art such as difficult control of the thickness of the top silicon ultra-thin film of the FD-SOI substrate structure and more defects, and realizes the ability to more controllably obtain the required ultra-thin film structure and ensure the single-crystallinity of the top silicon thin film.

[0004] According to the technical solution of the present invention, the present invention provides a preparation method of an FD-SOI substrate structure by hydrogen, boron, and nitrogen ion implantation processes, which is characterized by including the following steps carried out in sequence:

[0005] Step S1: Prepare a first wafer and a second wafer, both of which are bare die of wafer substrates;

[0006] Step S2: Perform a thermal oxidation process on the surface of the first wafer to form an insulating oxide layer on the surface of the first wafer;

[0007] Step S3: Perform a hydrogen ion implantation and boron and nitrogen ion implantation process on the first wafer to form a hydrogen implantation layer under the insulating oxide layer of the first wafer, and a boron nitride implantation layer between the hydrogen implantation layer and the insulating oxide layer;

[0008] Step S4: After cleaning the surfaces of the first wafer and the second wafer, bond the surface of the insulating oxide layer of the first wafer to the second wafer through a bonding process;

[0009] Step S5: Peel off the first wafer along the hydrogen implantation layer, and the remaining part of the first wafer outside the insulating oxide layer forms a top silicon thin film on the second wafer. Then, perform a thermal annealing process to recrystallize the top silicon thin film;

[0010] Step S6: Etch the top silicon thin film to below the boron nitride implantation layer through a wet etching process to make the top silicon thin film reach the required thickness.

[0011] In some embodiments, the insulating oxide layer is a silicon dioxide layer.

[0012] In some embodiments, in Step S3, the hydrogen ion implantation dose is higher than the boron ion implantation dose, and the hydrogen ion implantation dose is higher than the nitrogen ion implantation dose.

[0013] In some embodiments, in Step S3, the boron ion implantation dose is lower than the nitrogen ion implantation dose.

[0014] In some embodiments, in Step S3, the hydrogen ion implantation energy is 50 keV to 200 keV, and the hydrogen ion implantation dose is 1×10^16 atoms / cm² to 1×10^18 atoms / cm²;

[0015] And / or, the boron ion implantation energy is 50 eV to 30 keV, the boron ion implantation dose is 1×10^13 atoms / cm² to 1×10^16 atoms / cm², the nitrogen ion implantation energy is 1 keV to 50 keV, and the nitrogen ion implantation dose is 1×10^14 atoms / cm² to 1×10^16 atoms / cm².

[0016] In some embodiments, in Step S3, the temperature condition for hydrogen ion implantation is ≤60 °C;

[0017] And / or, the temperature condition for boron and nitrogen ion implantation is ≤0 °C.

[0018] In some embodiments, in step S4, the bonding process is a low-temperature bonding process, and the bonding process temperature is ≤200°C.

[0019] In some embodiments, in step S5, the thermal annealing treatment is a high-temperature thermal annealing treatment, and the temperature of the thermal annealing treatment is ≥500°C.

[0020] In some embodiments, after step S6, the top silicon thin film reaches the required ultra-thin thickness, and the ultra-thin thickness is ≤20 nm.

[0021] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0022] In the preparation method of the FD-SOI substrate structure of the present invention by hydrogen, boron, and nitrogen ion implantation processes, a combination of ion implantation and wet etching processes is adopted; by implanting hydrogen ions, a relatively flat weakening layer is formed at a certain depth position on the substrate surface to facilitate subsequent peeling; then boron ions and nitrogen ions are implanted to form a relatively flat barrier layer at another relatively shallow depth position. On the one hand, as an ion diffusion barrier layer, the large characteristics of boron ions and nitrogen ions are used to block the diffusion of hydrogen ions to the substrate surface. On the other hand, it is also a wet etching barrier layer. When performing the wet etching process later, when etching to the wet etching barrier layer, the etching rate will slow down significantly. The appearance of this phenomenon indicates that the etching has reached this layer position, and at this time, stopping the etching can retain the required thin film thickness. In this way, it is possible to effectively control the top silicon thin film to reach the required ultra-thin thickness; in particular, due to the electrical relationship between boron ions and nitrogen ions, after ion implantation, a BN structure similar to a compound will be formed in the boron-nitrogen implantation layer, and this structure is relatively stable, so the diffusion of boron and nitrogen can be avoided; in this way, the monocrystallinity of the remaining part of the required wafer (i.e., the finally obtained top silicon thin film) is ensured; and the wet etching process makes the film uniformity consistent, and the thickness difference can be less than 2%, and the surface is defect-free; the FD-SOI substrate structure prepared by the method of the present invention has a relatively flat surface and few defects on the surface and inside the structure; the method of the present invention is particularly suitable for the situation where the top silicon thin film of the advanced process requires an ultra-thin thickness at the nanometer level, and can form the required high-quality nanometer-scale ultra-thin film, which has great significance for the application of FD-SOI technology in semiconductor devices with smaller feature sizes. Description of the Drawings

[0023] Figure 1 is a flowchart of the method provided by the present invention.

[0024] Figures 2 to 8 is a schematic structural diagram of the process of gradually obtaining the FD-SOI substrate structure by using the method of the present invention.

[0025] Explanation of the reference numerals in the drawings:

[0026] A, the first wafer; B, the second wafer; 1, insulating oxide layer; 2, hydrogen implantation layer; 3, boron nitride implantation layer; 4, top silicon thin film; 5, substrate. Detailed implementation manners

[0027] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0028] In addition, it should be noted that for the sake of description, only parts related to the relevant invention are shown in the drawings. Without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0029] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or the interdependent relationship.

[0030] It should be noted that the modifications of "one" and "multiple" mentioned in the present invention are illustrative rather than restrictive. Those skilled in the art should understand that unless clearly specified otherwise in the context, it should be understood as "one or more".

[0031] The present invention provides a preparation method of an FD-SOI substrate structure by hydrogen, boron, and nitrogen ion implantation processes, in other words, a preparation method of an FD-SOI substrate structure including hydrogen, boron, and nitrogen ion implantation processes, belonging to the field of semiconductor design and manufacturing. The typical preparation method includes: (1) preparing two bare wafer substrates A and B; (2) performing thermal oxidation treatment on the surface of wafer A; (3) performing hydrogen ion implantation, boron ion and nitrogen ion implantation processes on wafer A; (4) first cleaning the surfaces of wafer A and wafer B, and then performing low-temperature bonding; (5) peeling off wafer A to form a top silicon thin film, and then performing recrystallization on the top silicon thin film by high-temperature thermal annealing treatment; (6) using wet etching treatment to etch the top silicon to an ultra-thin film. Without changing the FD-SOI substrate structure, the present invention improves the preparation method of FD-SOI, solves the problems in the prior art such as the difficult control of the thickness of the top silicon ultra-thin film of the FD-SOI substrate structure and more defects, and realizes the ability to more controllably obtain the required ultra-thin film structure and ensure the single crystal property of the top silicon thin film.

[0032] Please refer to Figures 1 to 8, A preparation method of an FD-SOI substrate structure of the present invention by hydrogen, boron, and nitrogen ion implantation processes includes the following steps carried out in sequence.

[0033] Step S1, Prepare the first wafer A and the second wafer B, both of which are bare wafer substrates. This step S1 corresponds to Figure 2 the initial state shown.

[0034] Step S2, Perform thermal oxidation treatment on the surface of the first wafer A to form a high-quality insulating oxide layer 1 on the surface of the first wafer A. In the embodiment, the insulating oxide layer 1 is a silicon dioxide layer. The state after this step S2 is as Figure 3 shown.

[0035] Step S3, Perform hydrogen ion implantation and boron and nitrogen ion implantation processes on the first wafer A. In this way, through two ion implantation processes, a hydrogen implantation layer 2 is formed under the insulating oxide layer 1 on the first wafer A, and a boron nitride implantation layer 3 is formed between the hydrogen implantation layer 2 and the insulating oxide layer 1. In a typical embodiment, the two ion implantation processes in step S3 are to first implant high-dose hydrogen ions (at room temperature), and then implant low-dose boron ions and nitrogen ions (at low temperature), where the boron ions and nitrogen ions are mixed together and implanted simultaneously through one ion implantation. The state of hydrogen ion implantation in this step S3 is as Figure 4 shown, and the state of low-temperature boron and nitrogen ion implantation is as Figure 5 shown.

[0036] Step S4, After cleaning the surfaces of the first wafer A and the second wafer B, bond the surface of the insulating oxide layer 1 of the first wafer A to the second wafer B through a bonding process. In the embodiment, when performing the bonding process, the first wafer A is flipped and placed upside down on the upper surface of the second wafer B. Preferably, the bonding process is a low-temperature bonding process, and the bonding process temperature is, for example, ≤200°C. The state after this step S4 is as Figure 6 shown.

[0037] Step S5, Peel off the first wafer A along the hydrogen implantation layer 2 (that is, based on the exact position of the weakened layer region formed in the previous steps). The remaining part of the first wafer A outside the insulating oxide layer 1 forms a top silicon thin film 4 on the second wafer B, and then perform recrystallization on the top silicon thin film 4 through a thermal annealing process. Preferably, the thermal annealing process is a high-temperature thermal annealing process, and the temperature of the thermal annealing process is, for example, ≥500°C. The state of the peeling process in this step S5 is as Figure 7 shown.

[0038] Step S6: Etch the top silicon thin film 4 by wet etching to below the boron-nitrogen implantation layer 3 so that the top silicon thin film 4 reaches the required thickness. Among them, the boron-nitrogen implantation layer 3 formed by wet etching and the previous process can accurately control the thickness of the top silicon thin film 4. Preferably, after step S6, the top silicon thin film 4 reaches the required ultra-thin thickness, and the ultra-thin thickness is ≤20 nm. The state after this step S6 is as Figure 8 shown, that is, an FD-SOI substrate structure is obtained. The FD-SOI substrate structure is a substrate 5 (formed by the second wafer B), an insulating oxide layer 1, and a top silicon thin film 4 stacked in sequence.

[0039] The key concept and principle of the present invention are as follows.

[0040] In step S3, hydrogen ions are implanted first. Since hydrogen ions are relatively small, they are driven into a deeper position in the substrate to form a structure similar to bubbles, which is a weakened layer of the substrate structure, that is, the hydrogen implantation layer 2. Since this layer is a weak link in the substrate, peeling can be carried out along this layer in step S5 to initially obtain the top layer structure of FD-SOI. Among them, the hydrogen ion implantation is preferably a high dose. Compared with low-dose implantation, high-dose implantation can make the hydrogen implantation layer 2 flatter, that is, the surface generated after peeling is smoother.

[0041] After implanting hydrogen ions, boron and nitrogen ions are implanted to form a barrier layer, that is, the boron-nitrogen implantation layer 3. The hydrogen implanted in the previous steps will diffuse, and the boron-nitrogen implantation layer 3 is formed above the hydrogen implantation layer 2. Since boron and nitrogen ions are relatively large, they can block the diffusion of hydrogen. At the same time, negatively charged nitrogen ions can combine with positively charged boron ions to form a relatively stable BN structure, thereby avoiding the diffusion of boron because the influence of boron on performance is more obvious. In this way, it is ensured that the upper part of the boron-nitrogen implantation layer 3 (that is, the finally obtained top silicon thin film 4) does not contain hydrogen, boron, and does not contain or basically does not contain nitrogen, avoiding affecting the device performance.

[0042] When wet etching is carried out in step S6, the etching rate above the boron-nitrogen implantation layer 3 (that is, the etching rate for the silicon substrate) will be very fast. When etching to the boron-nitrogen implantation layer 3, the etching rate will decrease significantly. If the boron-nitrogen implantation layer 3 is completely etched away and the underlying substrate is continued to be etched, the etching rate will become fast again. Therefore, it is possible to know that the substrate has been etched to the position of the boron-nitrogen implantation layer 3 through the etching rate (which will be directly reflected in the corresponding etching equipment or can be obtained in real time through data processing). Thus, it is convenient to stop etching through manual control or system automatic control so that the top silicon thin film 4 retains the required ultra-thin thickness.

[0043] As a supplementary explanation, the depths of the hydrogen implantation layer 2 and the boron-nitrogen implantation layer 3 are based on the implantation energy. For the same type of ions, the greater the implantation energy, the deeper the ions penetrate below the substrate surface. When the implantation energy of the implanted ions is the same, a layer structure with a specific depth will be formed. The implantation depths of the hydrogen implantation layer 2 and the boron-nitrogen implantation layer 3 and the corresponding implantation energies are designed to achieve the desired effects. In particular, for the implantation of boron and nitrogen ions, the position of the boron-nitrogen implantation layer 3 is directly related to the thickness of the finally obtained top silicon thin film 4.

[0044] Preferably, in step S3, the hydrogen ion implantation dose is higher than the boron ion implantation dose, and the hydrogen ion implantation dose is higher than the nitrogen ion implantation dose, so as to make the weakening layer effect better and avoid adverse effects caused by excessive boron and nitrogen doping. Further, the hydrogen ion implantation energy is 50 keV to 200 keV, and the hydrogen ion implantation dose is 1×10^16 atoms / cm² to 1×10^18 atoms / cm²; and / or, the boron ion implantation energy is 50 eV to 30 keV, the boron ion implantation dose is 1×10^13 atoms / cm² to 1×10^16 atoms / cm², the nitrogen ion implantation energy is 1 keV to 50 keV, and the nitrogen ion implantation dose is 1×10^14 atoms / cm² to 1×10^16 atoms / cm².

[0045] It is worth mentioning that preferably, in step S3, the boron ion implantation dose is lower than the nitrogen ion implantation dose. More specifically, on the basis of 1:1, the amount of nitrogen is slightly higher than that of boron. Boron ions and nitrogen ions are combined in a ratio of approximately 1:1. In the actual process, since boron has a greater impact on the performance, a slightly excessive amount of nitrogen is required to ensure that all boron is stabilized. Of course, the amount of nitrogen ions cannot be too much, as too much may affect the stress and change the film characteristics, etc.

[0046] Preferably, the temperature condition for hydrogen ion implantation is ≤60°C; and / or, the temperature condition for boron and nitrogen ion implantation is ≤0°C. The boron and nitrogen ion implantation adopts a low-temperature ion implantation process, which can avoid the ion diffusion during ion implantation, control the ions to be uniformly implanted into a certain position in the substrate, with precise position and narrow distribution range, that is, a boron-nitrogen implantation layer 3 with precise position and flatness is formed; similarly, the hydrogen ion implantation temperature should not be too high; furthermore, in the case of low-temperature implantation, a lower dose implantation can be selected to further avoid lattice damage and reduce defects.

[0047] In summary, in the preparation method of the FD-SOI substrate structure of the present invention by hydrogen, boron, and nitrogen ion implantation processes, a combination of ion implantation and wet etching processes is adopted; by implanting hydrogen ions, a relatively flat weakening layer is formed at a certain depth position on the substrate surface to facilitate subsequent peeling; then boron ions and nitrogen ions are implanted to form a relatively flat barrier layer at another relatively shallow depth position. On the one hand, as an ion diffusion barrier layer, the large characteristics of boron ions and nitrogen ions are used to block the diffusion of hydrogen ions to the substrate surface. On the other hand, it is also a wet etching barrier layer. During the subsequent wet etching process, when the wet etching reaches the wet etching barrier layer, the etching rate will slow down significantly. The appearance of this phenomenon indicates that the etching has reached this layer position, and at this time, the etching can be stopped to retain the required thin film thickness. In this way, it is possible to effectively control the top silicon thin film to reach the required ultra-thin thickness; in particular, due to the electrical relationship between boron ions and nitrogen ions, after ion implantation, a BN structure similar to a compound will be formed in the boron-nitrogen implantation layer, and this structure is relatively stable, so the diffusion of boron and nitrogen can be avoided; in this way, the monocrystallinity of the remaining part of the required wafer (i.e., the finally obtained top silicon thin film) is ensured; and the wet etching process makes the film uniformity consistent, and the thickness difference can be lower than 2%, and there are no defects on the surface; the FD-SOI substrate structure prepared by the method of the present invention has a relatively flat surface and few defects on the surface and inside the structure; the method of the present invention is particularly suitable for the case where the advanced process requires the top silicon thin film to reach the ultra-thin thickness of the nanometer level, and can form the required high-quality nanometer-level ultra-thin film, which is of great significance for the application of FD-SOI technology in semiconductor devices with smaller feature sizes.

[0048] Moreover, for the transistors fabricated by FD-SOI technology, the silicon thin film defines the source-drain junction depth and depletion region, which can improve short-channel effects such as DIBL (Drain Induced Barrier Lowering), further improve the subthreshold characteristics of the device, and reduce the static power consumption of the circuit. In addition, FD-SOI transistors do not require channel doping, which can avoid effects such as RDF (Random Dopants Fluctuation) and the reduction of carrier mobility, and maintain a stable threshold voltage (Vth). Different from the 3D transistor structure adopted by the FinFET process, FD-SOI is a planar process technology, which can effectively reduce the process difficulty; compared with the traditional Bulk Silicon technology, FD-SOI can provide better transistor electrostatic characteristics, and the buried oxide layer can reduce the parasitic capacitance between the source and the drain; in addition, this technology can effectively limit the electron flow between the source and the drain, significantly reducing the leakage current performance of the device. In addition to through the gate, FD-SOI can also control the transistor behavior through the bottom substrate of the device to achieve the back bias control function.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a FD-SOI substrate structure by hydrogen, boron and nitrogen ion implantation process, characterized in that: The method comprises the following steps in sequence: Step S1, preparing a first wafer (A) and a second wafer (B), wherein the first wafer (A) and the second wafer (B) are both wafer substrate bare chips; Step S2, performing thermal oxidation treatment on the surface of the first wafer (A) to form an insulating oxide layer (1) on the surface of the first wafer (A); Step S3, performing a hydrogen ion implantation and a boron and nitrogen ion implantation process on the first wafer (A), so that a hydrogen implantation layer (2) is formed below the insulating oxide layer (1) of the first wafer (A), and a boron and nitrogen implantation layer (3) is formed between the hydrogen implantation layer (2) and the insulating oxide layer (1); Step S4, after cleaning the surfaces of the first wafer (A) and the second wafer (B), the surface of the insulating oxide layer (1) of the first wafer (A) is bonded to the second wafer (B) through a bonding process; Step S5, peeling off the first wafer (A) along the hydrogen implantation layer (2), forming a top silicon film (4) on the second wafer (B) at the portion of the remaining first wafer (A) outside the insulating oxide layer (1), and then performing a thermal annealing treatment to recrystallize the top silicon film (4); Step S6, etching the top silicon film (4) to below the boron nitrogen implantation layer (3) by wet etching, so that the top silicon film (4) reaches a desired thickness.

2. The method for preparing the FD-SOI substrate structure by hydrogen, boron and nitrogen ion implantation process according to claim 1, characterized in that: The insulating oxide layer (1) is a silicon dioxide layer.

3. The method for preparing the FD-SOI substrate structure by hydrogen, boron and nitrogen ion implantation process according to claim 1, characterized in that: In step S3, the hydrogen ion implantation dose is higher than the boron ion implantation dose, and the hydrogen ion implantation dose is higher than the nitrogen ion implantation dose.

4. The method for preparing the FD-SOI substrate structure by hydrogen, boron and nitrogen ion implantation process according to claim 1, characterized in that: In step S3, the boron ion implantation dose is lower than the nitrogen ion implantation dose.

5. The method for preparing the FD-SOI substrate structure by hydrogen, boron and nitrogen ion implantation process according to claim 1, characterized in that: In step S3, the hydrogen ion implantation energy is 50keV to 200keV, and the hydrogen ion implantation dose is 1×1016atoms / cm2 to 1×1018atoms / cm2; And / or, the boron ion implantation energy is 50 eV to 30 keV, the boron ion implantation dose is 1×1013 atoms / cm2 to 1×1016 atoms / cm2, the nitrogen ion implantation energy is 1 keV to 50 keV, and the nitrogen ion implantation dose is 1×1014 atoms / cm2 to 1×1016 atoms / cm2.

6. The method for preparing the FD-SOI substrate structure by hydrogen, boron and nitrogen ion implantation according to claim 1, wherein in step S3, the temperature condition of hydrogen ion implantation is ≤ 60°C; And / or, the temperature condition for implantation of boron and nitrogen ions is ≤ 0°C.

7. The method for preparing the FD-SOI substrate structure by hydrogen, boron and nitrogen ion implantation process according to claim 1, characterized in that: In step S4, the bonding process is a low-temperature bonding process, and the bonding process temperature is ≤200°C.

8. The method for preparing the FD-SOI substrate structure by hydrogen, boron and nitrogen ion implantation process according to claim 1, characterized in that: In step S5, the thermal annealing treatment is a high temperature thermal annealing treatment, and the temperature of the thermal annealing treatment is ≥500°C.

9. The method for preparing the FD-SOI substrate structure by hydrogen, boron and nitrogen ion implantation process according to claim 1, characterized in that: After step S6, the top silicon film (4) reaches the required ultra-thin thickness, which is ≤20 nm.

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