Manufacturing method of split gate semiconductor device

Abstract

The invention provides a manufacturing method of a separation gate semiconductor device, which comprises the following steps of: providing a wafer with a back sealing layer, and the back sealing layer comprises an inner polycrystalline silicon layer, a middle oxide layer and an outer polycrystalline silicon layer which are superposed in sequence; forming a groove from the front surface of the wafer; forming a sacrificial oxide layer on the inner wall of the groove, and removing the sacrificial oxide layer by wet etching; a trench gate structure is formed in the trench, the trench gate structure comprises a shield gate oxide layer, shield gate polycrystalline silicon, a gate oxide layer and gate polycrystalline silicon which are formed in sequence, a first oxide layer, a first polycrystalline silicon layer, a second oxide layer and a second polycrystalline silicon layer are accumulated on the back face of the wafer in sequence, and the first oxide layer is combined on the surface of the outer polycrystalline silicon layer. According to the invention, the back sealing layer with a sandwich structure of polycrystalline silicon, an oxide layer and polycrystalline silicon is adopted, the oxide layer on the back surface is retained due to the blocking of the polycrystalline silicon on the outer layer in the subsequent wet etching process, the warping degree of the wafer in the technological process is integrally improved, and various risks caused by warping in the measurement / technological process are reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology and relates to a manufacturing method of a split-gate semiconductor device. Background Art

[0002] The rapid development of integrated circuits has put forward higher requirements for the performance of power MOSFETs. Lower switching losses and higher working efficiency have become the development trend of power devices. The split-gate power MOSFET device structure developed based on trench MOSFET devices uses a shielding gate to shield the capacitive coupling between the control gate and the epitaxial layer, so as to achieve the purpose of reducing the gate-drain parasitic capacitance Cgd. At the same time, the shielding gate, as an in-body field plate, can assist in depleting the carriers in the drift region, significantly improving the doping concentration of the device drift region and reducing the specific on-resistance.

[0003] In addition, with the rapid development of integrated circuits, the requirements for lattice defects and heavy metal impurities in silicon materials have become increasingly strict. For this reason, on the one hand, the quality of silicon single crystal and silicon wafer processing needs to be improved, and on the other hand, defect engineering, that is, controlling and utilizing defects, is required. The extrinsic gettering technology has been widely used in the field of silicon wafer manufacturing, and polysilicon gettering is one of them.

[0004] In the current manufacturing of split-gate MOS transistors, the wafer back-sealing layer usually adopts the form of polysilicon + low-temperature oxide layer (LTO). Among them, polysilicon is used to adsorb impurities, and LTO is used to prevent the out-diffusion of dopants (such as phosphorus). This back-sealing form is susceptible to the high-temperature stress of polysilicon / oxide in the trench in some process sections of deep trench devices, resulting in difficulties in the robotic arm grasping the wafer due to excessive wafer warpage in the process / measurement machine.

[0005] Therefore, how to improve the wafer warpage to enhance the process throughput has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0006] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a manufacturing method of a split-gate semiconductor device, which is used to solve the problems such as easy fragmentation due to excessive wafer warpage in the manufacturing process of existing split-gate semiconductor devices.

[0008] To achieve the above and other related objectives, the present invention provides a method for manufacturing a separated gate semiconductor device, comprising the following steps:

[0009] Provide a wafer with a back-sealing layer, the back-sealing layer comprising an inner polysilicon layer, a middle oxide layer, and an outer polysilicon layer sequentially stacked from the back surface of the wafer;

[0010] Form a trench from the front surface of the wafer, the trench opening from the front surface of the wafer and extending towards the back surface of the wafer;

[0011] Form a sacrificial oxide layer on the inner wall of the trench and remove the sacrificial oxide layer by wet etching;

[0012] Form a trench gate structure in the trench, the trench gate structure comprising a shielding gate oxide layer, a shielding gate polysilicon, a gate oxide layer, and a gate polysilicon formed successively. The shielding gate oxide layer is located between the outer wall of the shielding gate polysilicon and the inner wall of the trench, and the gate oxide layer is located between the outer wall of the gate polysilicon and the inner wall of the trench. Among them, during the successive formation of the shielding gate oxide layer, the shielding gate polysilicon, the gate oxide layer, and the gate polysilicon, a first oxide layer, a first polysilicon layer, a second oxide layer, and a second polysilicon layer are successively accumulated on the back surface of the wafer. Among them, the first oxide layer is combined with the surface of the outer polysilicon layer.

[0013] Optionally, the middle oxide layer comprises a low-temperature oxide layer, and the formation temperature of the low-temperature oxide layer is less than 500 °C.

[0014] Optionally, the material of the sacrificial oxide layer comprises silicon oxide, the material of the middle oxide layer comprises silicon oxide, and the etching solution used for the wet etching comprises hydrofluoric acid.

[0015] Optionally, the method for forming the inner polysilicon layer comprises an epitaxial method, the method for forming the middle silicon oxide layer comprises an epitaxial method, and the method for forming the outer polysilicon layer comprises an epitaxial method.

[0016] Optionally, forming the gate polysilicon comprises the following steps:

[0017] Deposit a polysilicon material layer, the polysilicon material layer filling into the trench and covering the wafer;

[0018] Planarize the polysilicon material layer;

[0019] Etch back the gate material layer to a preset thickness to obtain the gate polysilicon.

[0020] Optionally, after forming the gate polysilicon, the following steps are further included:

[0021] Body region ion implantation and annealing;

[0022] Source region ion implantation and annealing.

[0023] Optionally, the method further includes the following steps:

[0024] Form an interlayer dielectric layer on the front side of the wafer;

[0025] Form contact holes in the interlayer dielectric layer;

[0026] Form conductive plugs in the contact holes;

[0027] Form a metal electrode layer on the interlayer dielectric layer.

[0028] Optionally, the method further includes a back thinning step, in which the second polysilicon layer, the second oxide layer, the first polysilicon layer, the first oxide layer and the outer polysilicon layer are removed in the back thinning step.

[0029] Optionally, forming a trench from the front side of the wafer includes the following steps:

[0030] Form a hard mask layer on the front side of the wafer;

[0031] Pattern the hard mask layer to obtain an etching window;

[0032] Etch the wafer based on the etching window to obtain the trench.

[0033] Optionally, the wafer includes a P-type doped silicon wafer or an N-type doped silicon wafer.

[0034] As described above, the manufacturing method of the split gate semiconductor device of the present invention changes the back encapsulation form of the wafer, adds a layer of polysilicon on the basis of the original two-layer structure, that is, adopts a sandwich structure back encapsulation layer of polysilicon + oxide layer + polysilicon. In the subsequent wet etching process, the back oxide layer is retained due to the blocking of the polysilicon. The stress of the back oxide layer is compressive stress, forcing the whole wafer to deform upward, buffering the influence of the polysilicon in the trench bending downward due to thermal expansion at high temperature, and in the subsequent steps, the back oxide layer will not be removed either. The overall warpage of the wafer in the process flow is improved by 18%, reducing the risks of stacking, broken pieces, scratches, peeling, defocus shift, etc. caused by warping during measurement / process, and can indirectly improve the uniformity of the critical dimension (CT photo CD) of the subsequent contact hole lithography. In addition, the change of the back encapsulation structure in the present invention will not affect the device, and at the same time, the redundant polysilicon structure will be removed in the subsequent back grinding process, and the electrical parameters such as on-resistance perform normally. Description of the Drawings

[0035] Figure 1 It shows a process flow chart of the manufacturing method of the isolated gate semiconductor device of the present invention.

[0036] Figure 2 It shows a schematic diagram of the film layer structure of a wafer with a back seal layer provided by the manufacturing method of the isolated gate semiconductor device of the present invention.

[0037] Figure 3 It shows a schematic diagram of the structure obtained after forming a trench from the front side of the wafer in the manufacturing method of the isolated gate semiconductor device of the present invention.

[0038] Figure 4 It shows a schematic diagram of the structure obtained after forming a sacrificial oxide layer on the inner wall of the trench in the manufacturing method of the isolated gate semiconductor device of the present invention.

[0039] Figure 5 It shows a schematic diagram of the structure obtained after removing the sacrificial oxide layer by wet etching in the manufacturing method of the isolated gate semiconductor device of the present invention.

[0040] Figure 6 It shows a schematic diagram of the structure obtained after forming a trench gate structure in the trench in the manufacturing method of the isolated gate semiconductor device of the present invention.

[0041] Figure 7 It shows a schematic diagram of the back film layer structure of the wafer after forming the trench gate structure in the manufacturing method of the isolated gate semiconductor device of the present invention

[0042] Figure 8 It shows a schematic diagram of the back seal layer of the wafer in a control example.

[0043] Figure 9 It shows a schematic diagram of the back film layer structure of the wafer after forming the trench gate structure in the control example.

[0044] Figure 10 It shows a contour map of the wafer with the polysilicon + LTO double - layer back - seal structure of the control example after gate polysilicon back - etching.

[0045] Figure 11 It shows a contour map of the wafer with the polysilicon + LTO + polysilicon triple - layer back - seal structure of the present invention after gate polysilicon back - etching.

[0046] Figure 12 It shows the change in the Y - direction bow of the two wafers at each process flow node.

[0047] Figure 13 It shows the change in the X - direction bow of the two wafers at each process flow node.

[0048] Description of Component Labels

[0049] Steps S1 to S4

[0050] 1 Wafer

[0051] 201 Inner polysilicon layer

[0052] 202 Middle oxide layer

[0053] 203 Outer polysilicon layer

[0054] 3 Trench

[0055] 4 Sacrificial oxide layer

[0056] 5 Masking gate oxide layer

[0057] 6 Masking gate polysilicon

[0058] 7 Gate oxide layer

[0059] 8 Gate polysilicon

[0060] 9 First oxide layer

[0061] 10 First polysilicon layer

[0062] 11 Second oxide layer

[0063] 12 Second polysilicon layer

[0064] 201’ Polysilicon layer

[0065] 202’ Low-temperature oxide layer

[0066] 9’ First oxide layer

[0067] 10’ First polysilicon layer

[0068] 11’ Second oxide layer

[0069] 12’ Second polysilicon layer Detailed Implementation Manner

[0070] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0071] Please refer to Figures 1 to 13It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0072] The present invention provides a method for manufacturing a split-gate semiconductor device. Please refer to Figure 1 , which shows a process flow chart of the method, including the following steps:

[0073] S1: Provide a wafer with a back-sealing layer, where the back-sealing layer includes an inner polysilicon layer, a middle oxide layer, and an outer polysilicon layer sequentially stacked from the back surface of the wafer.

[0074] S2: Form a trench from the front surface of the wafer. The trench opens from the front surface of the wafer and extends towards the back surface of the wafer.

[0075] S3: Form a sacrificial oxide layer on the inner wall of the trench, and remove the sacrificial oxide layer by wet etching.

[0076] S4: Form a trench gate structure in the trench. The trench gate structure includes a shielding gate oxide layer, a shielding gate polysilicon, a gate oxide layer, and a gate polysilicon formed successively. The shielding gate oxide layer is located between the outer wall of the shielding gate polysilicon and the inner wall of the trench, and the gate oxide layer is located between the outer wall of the gate polysilicon and the inner wall of the trench. Among them, during the successive formation of the shielding gate oxide layer, the shielding gate polysilicon, the gate oxide layer, and the gate polysilicon, a first oxide layer, a first polysilicon layer, a second oxide layer, and a second polysilicon layer are successively accumulated on the back surface of the wafer. Among them, the first oxide layer is combined with the surface of the outer polysilicon layer.

[0077] The implementation manners of the above steps will be described in detail below with reference to the structure diagrams.

[0078] First, please refer to Figure 2 , and execute the step S1: Provide a wafer 1 with a back-sealing layer 2. The back-sealing layer 2 includes an inner polysilicon layer 201, a middle oxide layer 202, and an outer polysilicon layer 203 sequentially stacked from the back surface of the wafer 1.

[0079] As an example, the wafer 1 can be a P-type doped silicon wafer or an N-type doped silicon wafer. The P-type doping ions include, but are not limited to, boron (B), and the N-type doping ions include, but are not limited to, phosphorus (P) and arsenic (As). The specific doping concentration of the wafer 1 can be set according to actual needs and is not specifically limited in the present invention.

[0080] Specifically, the inner polysilicon layer 201 is used to adsorb impurities. As an example, it can be formed on the back side of the wafer 1 by epitaxial growth. For example, in some embodiments, silane (SiH4) can be used as the silicon source, and hydrogen or other inert gases can be introduced as the carrier gas to epitaxially grow the inner polysilicon layer 201 on the back side of the wafer 1.

[0081] Specifically, the middle oxide layer 202 is used to prevent the outward diffusion of dopants. In some embodiments, the middle oxide layer 202 includes a low-temperature oxide layer (Low Temperature Oxide, abbreviated as LTO), that is, silicon dioxide deposited at low temperature, and its formation temperature is less than 500 °C. For example, silane (SiH4) and oxygen can be used as the source gases to epitaxially grow the low-temperature oxide layer on the back side of the inner polysilicon layer 201.

[0082] Specifically, the outer polysilicon layer 203 is used to protect the middle oxide layer 202 from being removed by the etching solution during the subsequent wet etching process, so as to utilize the middle oxide layer 202 to counteract the downward deformation of the wafer and improve the warpage of the wafer.

[0083] As an example, the outer polysilicon layer 203 can be formed by substantially the same method as that for forming the inner polysilicon layer 201.

[0084] Specifically, the specific thickness of the inner polysilicon layer 201 and the specific thickness of the middle oxide layer 202 can be adjusted according to the actual fabricated device and the warpage degree of the wafer during the process, and no specific limitation is made in the present invention. The thickness of the outer polysilicon layer 203 should at least ensure that it is not completely oxidized during the subsequent oxidation process of forming the sacrificial oxide layer and loses its function of protecting the middle oxide layer 202.

[0085] Please refer to Figure 3 again, and perform step S2: form a trench 3 from the front side of the wafer 1. The trench 3 opens from the front side of the wafer 1 and extends in the direction of the back side of the wafer 1.

[0086] As an example, forming the trench 3 from the front side of the wafer 1 includes the following steps:

[0087] (1) Form a hard mask layer (such as a silicon oxide layer and / or a silicon nitride layer) on the front side of the wafer 1;

[0088] (2) Pattern the hard mask layer by semiconductor processes such as photolithography and etching to obtain an etching window;

[0089] (3) Etch the wafer 1 based on the etching window to obtain the trench 3.

[0090] Specifically, the trench 3 is used to form a trench gate structure. The specific depth and opening width of the trench 3 can be set according to the electrical requirements of the actual device, and no specific limitation is made in the present invention.

[0091] Please refer to Figure 4 and Figure 5 , perform the step S3: form a sacrificial oxide layer 4 on the inner wall of the trench 3 (as shown in Figure 4 ), and use wet etching to remove the sacrificial oxide layer 4 (as shown in Figure 5 ).

[0092] Specifically, the main function of the sacrificial oxide layer 4 is to eliminate the lattice damage generated by etching on the inner wall of the trench 3 and remove surface impurities.

[0093] As an example, the material of the sacrificial oxide layer 4 includes silicon oxide, the material of the middle oxide layer 202 includes silicon oxide, and the etching solution used for the wet etching includes hydrofluoric acid.

[0094] Specifically, during the wet etching process, the middle oxide layer 202 is not corroded by the etching solution due to the blocking of the outer polysilicon layer 203, and thus remains on the back side of the wafer.

[0095] Please refer to Figure 6 , perform the step S4: form a trench gate structure in the trench 3. The trench gate structure includes a shielding gate oxide layer 5, a shielding gate polysilicon 6, a gate oxide layer 7, and a gate polysilicon 8 formed in sequence. The shielding gate oxide layer 5 is located between the outer wall of the shielding gate polysilicon 6 and the inner wall of the trench 3, and the gate oxide layer 7 is located between the outer wall of the gate polysilicon 8 and the inner wall of the trench 3.

[0096] As an example, the split-gate semiconductor device can be of the up-down type or the left-right type. Among them, Figure 6 taking the up-down type as an example for illustration, the gate polysilicon 8 is located above the shielding gate polysilicon 5.

[0097] As an example, please refer to Figure 7 , which shows a schematic diagram of the back film layer structure of the wafer 1 after forming the trench gate structure. Among them, during the process of forming the shielding gate oxide layer 5, the shielding gate polysilicon 6, the gate oxide layer 7, and the gate polysilicon 8 in sequence, a first oxide layer 9, a first polysilicon layer 10, a second oxide layer 11, and a second polysilicon layer 12 are successively accumulated on the back side of the wafer 1. Among them, the first oxide layer 9 is combined with the surface of the outer polysilicon 203.

[0098] As an example, forming the gate polysilicon 8 includes the following steps:

[0099] (1) Deposit a polysilicon material layer, and the polysilicon material layer is filled into the trench and covers the wafer;

[0100] (2) Planarize the polysilicon material layer by chemical mechanical polishing (CMP) or other suitable methods;

[0101] (3) Etch back the gate material layer to a preset thickness to obtain the gate polysilicon 8.

[0102] As an example, after forming the gate polysilicon 8, the following steps are further included:

[0103] (1) Perform body region ion implantation on the upper surface layer of the wafer on both sides of the trench 3, and anneal;

[0104] (2) Perform source region ion implantation on the upper surface layer of the body region, and anneal.

[0105] As an example, a metal interconnection layer is further formed, including the following steps:

[0106] (1) Form an interlayer dielectric layer on the front surface of the wafer;

[0107] (2) Form contact holes in the interlayer dielectric layer;

[0108] (3) Form conductive plugs in the contact holes;

[0109] (4) Form a metal electrode layer on the interlayer dielectric layer.

[0110] As an example, a back thinning step is further included, wherein the second polysilicon layer 12, the second oxide layer 11, the first polysilicon layer 10, the first oxide layer 9, and the outer polysilicon layer 203 are removed in the back thinning step. Since the outer polysilicon layer 203 in the polysilicon + LTO + polysilicon three-layer back seal structure will be removed in the back grinding process, that is to say, the change of the back seal structure in the present invention will not affect the device, and the electrical parameters such as the on-resistance in the final device are normal.

[0111] It should be noted that in the above-described manufacturing process, only some of the main process steps of the isolated-gate semiconductor device are emphasized, and some steps are omitted. For example, in one embodiment, the manufacturing process of the isolated-gate semiconductor device includes the following process flow nodes: Bare Wafer (a bare chip with a back-end layer) → HM DEP (hard mask deposition) → HM DEP ANN (annealing after hard mask deposition) → TR SI AEI (inspection after trench etching) → SAC OXIDATION (sacrificial oxide layer) → SAC OX RM (removal of the sacrificial oxide layer) → TR OX (shield gate oxide layer) → TR POLY DEP (shield gate polysilicon deposition) → TR POLY CMP (chemical mechanical polishing of the shield gate polysilicon) → TR OX CMP (chemical mechanical polishing of the shield gate oxide layer) → IP AEI (inspection after lithography) → GATE OX (gate oxide layer) → GATE POLY DEP (gate polysilicon deposition) → GATE POLY CMP (chemical mechanical polishing of the gate polysilicon) → GC RECESS ETCH (etching back of the gate polysilicon) → GC OX (repair oxide layer) → PBODY IMP ANN (P-type body region ion implantation and annealing) → XN IMP ANNEAL (source region ion implantation and annealing) → BARR DEP (barrier layer deposition) → BPSG DEP (phosphosilicate glass deposition) → BPSG flow (phosphosilicate glass reflow) → CT Si AEI (inspection after contact hole etching) → CT IMP ANN (contact hole ion implantation and annealing) → TISPUTTER (titanium sputtering) → TI ANN (titanium annealing) → W DEP (tungsten deposition) → W EB (etching back of tungsten) → M1 SPUTTER (first layer metal sputtering) → TV SiN DEP (deposition of silicon nitride passivation layer) → TV ALLOY (alloying).

[0112] As an example, please refer to Figure 8 and Figure 9 , where Figure 8 shows a schematic diagram of the back-end layer of the wafer in a comparative example. In this comparative example, the back-end layer of the wafer has a two-layer structure, which is, from the inside to the outside, a polysilicon layer 201' and a low-temperature oxide layer 202' in sequence. Figure 9 shows a schematic diagram of the back-side film layer structure of the wafer after forming the trench gate structure in this comparative example, which includes, from the inside to the outside, a polysilicon layer 201', a first oxide layer 9', a first polysilicon layer 10', a second oxide layer 11' and a second polysilicon layer 12' in sequence, lacking the low-temperature oxide layer 202'. This is because the low-temperature oxide layer 202' is etched away by the etching solution during the wet etching process of removing the sacrificial oxide layer. In the present invention, as described above Figure 7As shown, after forming the trench gate structure, the back film layer of the wafer 1 sequentially includes the inner polysilicon layer 201, the middle oxide layer 202, the outer polysilicon layer 203, the first oxide layer 9, the first polysilicon layer 10, the second oxide layer 11, and the second polysilicon layer 12. Among them, the middle oxide layer 202 remains in the back seal layer, and the first oxide layer 9 is combined with the surface of the outer polysilicon 203.

[0113] As an example, please refer to Figure 10 and Figure 11 , Figure 12 and Figure 13 , where Figure 10 shows the contour map of the wafer with the polysilicon + LTO double-layer back seal structure of the control example after gate polysilicon etch-back. Figure 11 shows the contour map of the wafer with the polysilicon + LTO + polysilicon triple-layer back seal structure of the present invention after gate polysilicon etch-back. It can be seen that the wafer with the polysilicon + LTO + polysilicon triple-layer back seal structure of the present invention has better flatness after gate polysilicon etch-back.

[0114] As an example, please refer to Figure 12 and Figure 13 , where Figure 12 shows the change in the Y-direction bow of the two wafers at each process flow node. Figure 13 shows the change in the X-direction bow of the two wafers at each process flow node. It can be seen that after the TROX (shield gate oxide layer) node and later, the wafer has a relatively high X-direction bow, and after the GATEOX (gate oxide layer) node and later, the wafer has a relatively high Y-direction bow. This is because the formation temperature of the oxide layer is relatively high. For example, the formation temperature of the gate oxide layer is higher than 1000 °C, which will cause relatively large stress, making the wafer warp downward. Among them, at the GC RECESS ETCH (gate polysilicon etch-back) node, the Y-direction bow of the wafer reaches the highest value. Compared with the polysilicon + LTO double-layer back seal structure of the control example, the present invention adopts the polysilicon + LTO + polysilicon triple-layer back seal structure, which can reduce the degree of downward warping of the wafer, stretch the whole wafer upward by 18%, thereby reducing the risks of stacking, broken pieces, scratches, peeling, defocus shift, etc. caused by warping during the measurement / process, and can indirectly improve the uniformity of the critical dimension of the subsequent contact hole lithography (CT photo CD).

[0115] It should be noted that, as Figure 12 and Figure 13As shown, although the present invention uses a three-layer back-end encapsulation structure of polysilicon + LTO + polysilicon, which reduces the wafer warpage of some process nodes (such as gate polysilicon etch-back) while increasing the wafer warpage of some other process nodes (such as removal of the sacrificial oxide layer), the increased wafer warpage of these other process nodes is still within the safe range. And by reducing the wafer warpage of the gate oxide layer node and later, especially at the GC RECESS ETCH (gate polysilicon etch-back) node, the present invention can significantly reduce various risks caused by excessive wafer warpage and improve the process throughput.

[0116] In summary, the manufacturing method of the isolated-gate semiconductor device of the present invention changes the form of wafer back-end encapsulation. On the basis of the original two-layer structure, a layer of polysilicon is added, that is, a sandwich-structured back-end encapsulation layer of polysilicon + oxide layer + polysilicon is adopted. During the subsequent wet etching process, the back oxide layer is retained due to the blocking of polysilicon. The stress of the back oxide layer is compressive stress, forcing the whole wafer to deform upward, buffering the influence of the polysilicon in the trench bending downward due to thermal expansion at high temperature. And in the subsequent steps, the back oxide layer will not be removed either. The overall improvement of the wafer warpage in the process flow reaches 18%, reducing risks such as stacking, broken, scratch, peeling, defocus shift, etc. caused by warpage during measurement / process, and can indirectly improve the uniformity of the critical dimension of the subsequent contact hole lithography (CT photo CD). In addition, the change of the back-end encapsulation structure in the present invention will not affect the device, and at the same time, the redundant polysilicon structure will be removed during the subsequent back grinding process, and the electrical parameters such as on-resistance perform normally. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0117] The above embodiments merely illustrate the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A manufacturing method of a split-gate semiconductor device, characterized in that, Including the following steps: Providing a wafer with a back encapsulation layer, the back encapsulation layer including an inner polysilicon layer, a middle oxide layer, and an outer polysilicon layer stacked in sequence from the back surface of the wafer; Forming a trench from the front surface of the wafer, the trench opening from the front surface of the wafer and extending in the direction of the back surface of the wafer; Forming a sacrificial oxide layer on the inner wall of the trench and removing the sacrificial oxide layer by wet etching; Forming a trench gate structure in the trench, the trench gate structure including a shielding gate oxide layer, a shielding gate polysilicon, a gate oxide layer, and a gate polysilicon formed successively, the shielding gate oxide layer being located between the outer wall of the shielding gate polysilicon and the inner wall of the trench, the gate oxide layer being located between the outer wall of the gate polysilicon and the inner wall of the trench, wherein, during the successive formation of the shielding gate oxide layer, the shielding gate polysilicon, the gate oxide layer, and the gate polysilicon, a first oxide layer, a first polysilicon layer, a second oxide layer, and a second polysilicon layer are successively accumulated on the back surface of the wafer, wherein the first oxide layer is combined with the surface of the outer polysilicon layer.

2. The manufacturing method of the split-gate semiconductor device according to claim 1, characterized in that: The middle oxide layer includes a low-temperature oxide layer, and the formation temperature of the low-temperature oxide layer is less than 500 °C.

3. The manufacturing method of the split-gate semiconductor device according to claim 1, characterized in that: The material of the sacrificial oxide layer includes silicon oxide, the material of the middle oxide layer includes silicon oxide, and the etching solution used for the wet etching includes hydrofluoric acid.

4. The manufacturing method of the split-gate semiconductor device according to claim 1, characterized in that: The method for forming the inner polysilicon layer includes an epitaxial method, the method for forming the middle silicon oxide layer includes an epitaxial method, and the method for forming the outer polysilicon layer includes an epitaxial method.

5. The manufacturing method of the split-gate semiconductor device according to claim 1, characterized in that, Forming the gate polysilicon includes the following steps: Depositing a polysilicon material layer, the polysilicon material layer filling into the trench and covering above the wafer; Planarizing the polysilicon material layer; Etching back the gate material layer to a preset thickness to obtain the gate polysilicon.

6. The manufacturing method of the split-gate semiconductor device according to claim 1, characterized in that, After forming the gate polysilicon, the following steps are further included: Body region ion implantation and annealing; Source region ion implantation and annealing.

7. The manufacturing method of the split-gate semiconductor device according to claim 1, characterized in that, The following steps are further included: Forming an interlayer dielectric layer on the front surface of the wafer; Forming contact holes in the interlayer dielectric layer; Forming conductive plugs in the contact holes; Forming a metal electrode layer on the interlayer dielectric layer.

8. The manufacturing method of the split-gate semiconductor device according to claim 1, characterized in that: A back thinning step is further included, and the second polysilicon layer, the second oxide layer, the first polysilicon layer, the first oxide layer, and the outer polysilicon layer are removed in the back thinning step.

9. The manufacturing method of the split-gate semiconductor device according to claim 1, characterized in that, Forming a trench from the front surface of the wafer includes the following steps: Forming a hard mask layer on the front surface of the wafer; Patterning the hard mask layer to obtain an etching window; Etching the wafer based on the etching window to obtain the trench.

10. The manufacturing method of the split-gate semiconductor device according to claim 1, characterized in that: The wafer includes a P-type doped silicon wafer or an N-type doped silicon wafer.

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