Short-channel metal oxide semiconductor field effect transistor (MOSFET) device with low starting voltage and manufacturing method thereof

Abstract

The invention discloses a short-channel metal-oxide-semiconductor field effect transistor (MOSFET) device with low turn-on voltage and a manufacturing method thereof. The manufacturing method comprises the following steps: sequentially growing an epitaxial layer and a first oxide layer on a silicon wafer; body region injection and source region injection are carried out on the upper portion of the epitaxial layer; etching to form a gate trench; growing a gate oxide layer on the groove wall of the gate groove; grid polycrystalline silicon is formed in the grid groove; and the subsequent manufacturing process is completed. According to the invention, the body region injection and the source region injection are carried out firstly, and then the etching is carried out to form the gate trench, so that the situation that the source region injection at the position close to the gate trench is too deep when the source region injection is carried out after a sunken region is formed by over-etching of polycrystalline silicon in the gate trench, so that a conductive channel is shorter, and channel electric leakage is caused can be avoided; and mass production of short-channel MOSFET devices with low turn-on voltage becomes possible.

Description

Technical Field

[0001] The present invention belongs to the field of trench MOSFETs, and particularly relates to a short-channel MOSFET device with a low turn-on voltage and a manufacturing method thereof. Background Art

[0002] When designing a MOSFET device with a low turn-on voltage, a process using a thin gate oxide (i.e., a thin gate oxide layer) is required. Refer to Figure 1 , due to process limitations, the grinding process is not suitable for removing polysilicon in the thin gate oxide process, and a dry etching process needs to be used. To ensure complete removal of the polysilicon outside the gate trench, there will be a certain over-etching, resulting in a certain depression in the polysilicon within the gate trench, forming a depression region.

[0003] Meanwhile, based on the requirement of lower on-resistance, and the resistance of the conductive channel of the low-voltage MOSFET accounts for more than 30% of the on-resistance, optimizing the channel has great benefits. Therefore, the on-resistance is optimized by reducing the length of the conductive channel. In the traditional MOSFET manufacturing process, the implantation of the active region is carried out after the polysilicon etching. Due to a certain depression depth during the polysilicon etching, some ions will be implanted from the polysilicon depression region within the gate trench into the active region during the active region implantation, resulting in over-deep implantation of the source region at the position close to the gate trench, thus requiring a longer conductive channel. Refer to Figure 2 , if the source region is not over-deeply implanted, the length of the conductive channel should be L1. However, due to over-deep implantation of the source region at the position close to the gate trench, the length of the conductive channel becomes L2, thereby reducing the length of the conductive channel. At this time, due to the reduction of the conductive channel length, channel leakage is likely to occur. The above problems cannot be well solved by the etching process, resulting in the inability of MOSFET low turn-on / short-channel products to enter mass production. Summary of the Invention

[0004] Aiming at the deficiencies of the above-mentioned prior art, the technical problem to be solved by the present invention is: to provide a short-channel MOSFET device with a low turn-on voltage and a manufacturing method thereof.

[0005] To solve the above technical problem, the present invention provides the following technical solutions:

[0006] A manufacturing method of a short-channel MOSFET device with a low turn-on voltage includes the following steps:

[0007] S100: Take a silicon wafer, and sequentially grow an epitaxial layer and a first oxide layer on the silicon wafer;

[0008] S200: Perform body region implantation and source region implantation on the upper part of the epitaxial layer;

[0009] S300: Etch to form a gate trench;

[0010] S400. Grow a gate oxide layer on the sidewalls of the gate trench;

[0011] S500. Form a gate polysilicon in the gate trench;

[0012] S600. Complete the subsequent manufacturing processes.

[0013] Furthermore, after the source region implantation, reduce the temperature and time of the high-temperature processes in the subsequent processes.

[0014] Furthermore, determine the minimum designed thickness of the gate oxide layer according to the gate breakdown voltage requirement of the device, and in the step S400, make the thickness of the gate oxide layer at the source region corresponding part of the gate trench and the thickness of the gate oxide layer at the body region corresponding part of the gate trench both greater than or equal to the minimum designed thickness of the gate oxide layer.

[0015] Furthermore, the steps of performing body region implantation and source region implantation on the upper part of the epitaxial layer include the following sub-steps:

[0016] S210. Perform body region implantation on the upper part of the epitaxial layer and push the well to activate;

[0017] S220. Perform source region implantation on the upper part of the body region.

[0018] Furthermore, the step of etching to form the gate trench includes the following sub-steps:

[0019] S310. Grow a hard mask as the first mask layer;

[0020] S320. Etch out the gate trench region on the first mask layer through a photolithography process;

[0021] S330. Etch downward in the gate trench region through an etching process to form a gate trench;

[0022] S340. Remove the first oxide layer and the first mask layer.

[0023] Furthermore, the step of growing a gate oxide layer on the sidewalls of the gate trench includes the following sub-steps:

[0024] S410. Grow an oxide layer on the sidewalls of the gate trench to form a sacrificial oxide layer;

[0025] S420. Etch and remove the sacrificial oxide layer;

[0026] S430. Grow an oxide layer again on the sidewalls of the gate trench to form a gate oxide layer.

[0027] Further, when forming the sacrificial oxide layer and the gate oxide layer, the temperature for growing the oxide layer is 800°C to 900°C, and a catalyst is added to shorten the time required for growing the oxide layer.

[0028] Further, the step of forming gate polysilicon in the gate trench includes the following sub-steps:

[0029] S510: Deposit polysilicon to fill the gate trench;

[0030] S520: Use dry etching to remove the polysilicon outside the gate trench.

[0031] Further, the subsequent manufacturing process includes the following sub-steps:

[0032] S610: Deposit a dielectric layer;

[0033] S620: Etch the contact hole area through a photolithography process;

[0034] S630: Complete the etching of the contact hole through an etching process;

[0035] S640: Fill the contact hole to form a tungsten plug;

[0036] S650: Deposit a surface metal layer.

[0037] A short-channel MOSFET device with a low turn-on voltage is formed by using the manufacturing method of the short-channel MOSFET device with a low turn-on voltage described in any one of the above.

[0038] In the present invention, by first performing body region implantation and source region implantation, and then etching to form a gate trench, the influence of the recessed region formed by polysilicon etching on the conductive channel length is solved, and the situation of leakage of the conductive channel caused by over-deep source region implantation near the position of the gate trench is avoided. By process improvement, the temperature and time of the high-temperature process are reduced, and the premature implantation process of the body region and the source region is avoided, which causes further diffusion of the ions implanted in the body region and the source region during the subsequent high-temperature process. By respectively checking the thickness of the gate oxide layer corresponding to the source region of the gate trench and the thickness of the gate oxide layer corresponding to the body region of the gate trench, the situation that the premature implantation process of the body region and the source region causes inconsistent thickness of the oxide layer in the regions corresponding to the body region and the source region when forming the gate oxide layer, resulting in the thickness of the thinnest part of the gate oxide layer being lower than the minimum design thickness of the gate oxide layer is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation of the present application. In the drawings:

[0040] Figure 1 Schematic diagram of a structure where over-etching causes a recessed area to form in the gate trench.

[0041] Figure 2 Schematic diagram of a structure where the presence of the recessed area causes the source region implantation to be too deep near the gate trench.

[0042] Figure 3 Flowchart of an embodiment of the low-threshold-voltage short-channel MOSFET device and its manufacturing method according to the present invention.

[0043] Figure 4 Schematic diagram of the structure after growing the epitaxial layer and the first oxide layer.

[0044] Figure 5 Schematic diagram of the structure after performing body region implantation and driving the well to activate.

[0045] Figure 6 Schematic diagram of the structure after performing source region implantation.

[0046] Figure 7 Schematic diagram of the structure after etching out the gate trench region.

[0047] Figure 8 Schematic diagram of the structure after etching to form the gate trench and removing the first oxide layer and the first mask layer.

[0048] Figure 9 Schematic diagram of the structure after forming the sacrificial oxide layer.

[0049] Figure 10 Schematic diagram of the structure after removing the sacrificial oxide layer.

[0050] Figure 11 Schematic diagram of the structure after forming the gate oxide layer.

[0051] Figure 12 Schematic diagram of the structure after depositing polysilicon.

[0052] Figure 13 Schematic diagram of the structure after etching away the polysilicon outside the gate trench.

[0053] Figure 14 Schematic diagram of the structure after depositing the dielectric layer.

[0054] Figure 15 Schematic diagram of the structure after etching out the contact hole region.

[0055] Figure 16 Schematic diagram of the structure after etching out the contact hole.

[0056] Figure 17 Schematic diagram of the structure after depositing the surface metal layer.

[0057] The reference numerals in the drawings are as follows:

[0058] Silicon wafer - 100; epitaxial layer - 200; body region - 210; source region - 220; gate trench - 230; recessed area - 231; sacrificial oxide layer - 240; gate oxide layer - 250; first oxide layer - 300; first mask layer - 400; gate trench region - 410; polysilicon - 500; dielectric layer - 600; second mask layer - 700; contact hole region - 710; contact hole - 800; tungsten plug - 810; surface metal layer - 900. Detailed implementation manners

[0059] The following uses specific specific examples to illustrate the implementation manners of the present invention. The drawings provided in the following embodiments only schematically illustrate the basic concept of the present invention. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0060] Please refer to Figure 3 , Figure 3 , which is a flowchart of an embodiment of the manufacturing method of a low-threshold-voltage short-channel MOSFET device of the present invention. The manufacturing method of the low-threshold-voltage short-channel MOSFET device in this embodiment includes the following steps:

[0061] S100. Please refer to Figure 4 , take a silicon wafer 100, first grow an epitaxial layer 200 on the silicon wafer 100, and then grow a first oxide layer 300 on the epitaxial layer 200.

[0062] S200. Perform body region 210 implantation and source region 220 implantation on the upper part of the epitaxial layer 200. This step may specifically include the following sub-steps:

[0063] S210. Please refer to Figure 5 , perform body region 210 implantation on the upper part of the epitaxial layer 200, and then perform well push activation.

[0064] S220. Please refer to Figure 6 , perform source region 220 implantation on the upper part of the body region 210. Since the implantation of the body region 210 and the source region 220 is completed in advance in this embodiment, after the source region 220 implantation, it is necessary to reduce the temperature and time of the high-temperature process in the subsequent process; for example: the process temperature and process time when forming the sacrificial oxide layer 240 and the gate oxide layer 250.

[0065] S300. Etch to form the gate trench 230. This step may specifically include the following sub-steps:

[0066] S310. Please refer to Figure 7 , grow a hard mask as the first mask layer 400 to facilitate the subsequent lithography process.

[0067] S320. Please continue to refer to Figure 7 , and etch a gate trench region 410 on the first mask layer 400 through a photolithography process to facilitate the subsequent formation of the gate trench 230.

[0068] S330. Please refer to Figure 8 , and etch downward in the gate trench region 410 through an etching process to form a gate trench 230 that penetrates the body region 210 and the source region 220.

[0069] S340. Please continue to refer to Figure 8 , after the etching of the gate trench 230 is completed, remove the first oxide layer 300 and the first mask layer 400 on the first oxide layer 300.

[0070] S400. Grow a gate oxide layer 250 on the sidewalls of the gate trench 230. This step may specifically include the following sub-steps:

[0071] S410. Please refer to Figure 9 , grow an oxide layer on the sidewalls of the gate trench 230 to form a sacrificial oxide layer 240. Since a relatively high temperature (generally above 1000 °C) is required when forming the sacrificial oxide layer 240, and the body region 210 and the source region 220 have been implanted in advance in this application, in order to avoid the ions implanted in the body region 210 and the source region 220 from continuing to diffuse at high temperature, the process temperature for forming the sacrificial oxide layer 240 is reduced in this embodiment, and the sacrificial oxide layer 240 is grown at a temperature in the range of 800 °C to 900 °C. At the same time, in order to avoid increasing the process time after reducing the temperature, a catalyst that can accelerate the growth rate of the oxide layer is also used in this step, so as not to increase the process time or even reduce the process time under the condition of reducing the process temperature, and reduce the diffusion of the ions implanted in the body region 210 and the source region 220.

[0072] S420. Please refer to Figure 10 , etch and remove the sacrificial oxide layer 240. By removing the sacrificial oxide layer 240, the damage on the silicon surface can be removed.

[0073] S430. Please refer to Figure 11 , grow an oxide layer on the sidewalls of the gate trench 230 again to form a gate oxide layer 250. Similarly, this step also grows the gate oxide layer 250 at a temperature in the range of 800 °C to 900 °C, and a catalyst that can accelerate the growth rate of the oxide layer is also used.

[0074] In addition, since the implanted ions in the source region 220 and the body region 210 are different, the growth rate of the oxide layer in the gate trench 230 corresponding to the source region 220 is different from that of the oxide layer in the gate trench 230 corresponding to the body region 210. Therefore, after determining the minimum design thickness of the gate oxide layer 250 according to the gate breakdown voltage requirement of the device, it is necessary to separately check the thickness of the gate oxide layer 250 in the gate trench 230 corresponding to the source region 220 and the thickness of the gate oxide layer 250 in the gate trench 230 corresponding to the body region 210, so that the thickness of the gate oxide layer 250 in the gate trench 230 corresponding to the source region 220 and the thickness of the gate oxide layer 250 in the gate trench 230 corresponding to the body region 210 are both greater than or equal to the minimum design thickness of the gate oxide layer 250.

[0075] S500. Form a gate polysilicon 500 in the gate trench 230. This step may specifically include the following sub-steps:

[0076] S510. Refer to Figure 12 , deposit polysilicon 500 to fill the gate trench 230; of course, at this time, a layer of polysilicon 500 will also be formed on the platforms on both sides of the gate trench 230.

[0077] S520. Refer to Figure 13 , use dry etching to remove the polysilicon 500 outside the gate trench 230, that is, remove the polysilicon 500 on the platforms on both sides of the gate trench 230. Of course, in order to ensure that the polysilicon 500 outside the gate trench 230 is completely removed, there will be a certain amount of over-etching in this step, so that the surface of the polysilicon 500 in the gate trench 230 is lower than the surface of the platforms on both sides after etching, forming a recessed area 231; since the body region 210 and the source region 220 have been implanted and formed before this embodiment, the recessed area 231 in this embodiment will not cause the source region 220 to be implanted too deeply.

[0078] S600. Complete the subsequent manufacturing process. The subsequent manufacturing process generally includes the following sub-steps:

[0079] S610. Refer to Figure 14 , deposit a dielectric layer 600.

[0080] S620. Refer to Figure 15 , form a second mask layer 700 on the dielectric layer 600, and etch a contact hole region 710 on the second mask layer 700 through a photolithography process to facilitate the subsequent etching to form a contact hole 800.

[0081] S630. Refer to Figure 16 , complete the etching of the contact hole 800 through an etching process.

[0082] S640. Refer toFigure 17 , the contact hole 800 is filled to form a tungsten plug 810.

[0083] S650. Please continue to refer to Figure 17 , the surface metal layer 900 is deposited to connect the surface metal layer 900 to the tungsten plug 810.

[0084] In this embodiment, by first performing the body region 210 implantation and the source region 220 implantation, and then etching to form the gate trench 230, it is possible to avoid the formation of a recessed region 231 due to over-etching of the polysilicon 500 in the gate trench 230. During the source region 220 implantation, some ions are implanted into the source region 220 from the recessed region 231 in the gate trench 230, resulting in an over-deep implantation of the source region 220 near the position of the gate trench 230, thereby making the conductive channel shorter and causing channel leakage. In addition, in order to prevent the implantation processes of the body region 210 and the source region 220 from causing the ions implanted in the body region 210 and the source region 220 to further diffuse during subsequent high-temperature process steps, this embodiment also reduces the temperature and time of the high-temperature process through process improvements. For the situation where the implantation processes of the body region 210 and the source region 220 lead to inconsistent oxide layer thicknesses in the regions corresponding to the body region 210 and the source region 220 when forming the gate oxide layer 250, this embodiment also checks the thickness of the gate oxide layer 250 corresponding to the source region 220 in the gate trench 230 and the thickness of the gate oxide layer 250 corresponding to the body region 210 in the gate trench 230, respectively, to ensure that the thickness of the thinnest part of the gate oxide layer 250 is not lower than the minimum design thickness of the gate oxide layer 250 determined according to the gate breakdown voltage requirements of the device.

[0085] The present invention also discloses a short-channel MOSFET device with a low turn-on voltage. The short-channel MOSFET device with a low turn-on voltage is fabricated by using the fabrication method of the short-channel MOSFET device with a low turn-on voltage in any of the above embodiments. The short-channel MOSFET device with a low turn-on voltage fabricated by the above method avoids the situation of over-deep implantation of the source region 220 near the position of the gate trench 230, thereby avoiding the channel leakage situation after optimizing the on-resistance by reducing the conductive channel length.

[0086] The above embodiments only represent the preferred implementation modes of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A method for manufacturing a short-channel MOSFET device with a low turn-on voltage, characterized in that: The following steps are involved: S100, taking a silicon wafer, and sequentially growing an epitaxial layer and a first oxide layer on the silicon wafer; S200, performing body region implantation and source region implantation on the upper part of the epitaxial layer; S300, etching to form a gate trench; S400, growing a gate oxide layer on the wall of the gate trench; S500, forming gate polysilicon in the gate trench; S600, completing subsequent production processes.

2. The method for manufacturing a short channel MOSFET device with a low turn-on voltage as claimed in claim 1, characterized in that: After the source region is implanted, the temperature and time of the high-temperature process in the subsequent process are reduced.

3. The method for manufacturing a short channel MOSFET device with a low turn-on voltage as claimed in claim 1, characterized in that: The minimum design thickness of the gate oxide layer is determined according to the gate withstand voltage requirement of the device, and in the step S400, the thickness of the gate oxide layer at the source region corresponding to the gate trench and the thickness of the gate oxide layer at the body region corresponding to the gate trench are both greater than or equal to the minimum design thickness of the gate oxide layer.

4. The method for manufacturing a short channel MOSFET device with a low turn-on voltage according to any one of claims 1 to 3, characterized in that: The step of performing body region implantation and source region implantation on the upper part of the epitaxial layer comprises the following sub-steps: S210, performing body region implantation on the upper part of the epitaxial layer and pushing the well to activate; S220, performing source region implantation on the upper portion of the body region.

5. The method for manufacturing a short channel MOSFET device with a low turn-on voltage as claimed in claim 4, characterized in that: The step of etching to form a gate trench includes the following sub-steps: S310, growing a hard mask layer as a first mask layer; S320, etching a gate trench region on the first mask layer by a photolithography process; S330, etching downward in the gate trench region to form a gate trench through an etching process; S340 , removing the first oxide layer and the first mask layer.

6. The method for manufacturing a short channel MOSFET device with a low turn-on voltage as claimed in claim 5, characterized in that: The step of growing a gate oxide layer on the wall of the gate trench comprises the following sub-steps: S410, growing an oxide layer on the wall of the gate trench to form a sacrificial oxide layer; S420, etching to remove the sacrificial oxide layer; S430, growing another oxide layer on the wall of the gate trench to form a gate oxide layer.

7. The method for manufacturing a short channel MOSFET device with a low turn-on voltage as claimed in claim 6, characterized in that: When forming the sacrificial oxide layer and the gate oxide layer, the temperature for growing the oxide layer is 800° C. to 900° C., and the time required for growing the oxide layer is shortened by adding a catalyst.

8. The method for manufacturing a short channel MOSFET device with a low turn-on voltage as claimed in claim 6, characterized in that: The step of forming gate polysilicon in the gate trench comprises the following sub-steps: S510, depositing polysilicon so that the polysilicon fills the gate trench; S520, removing the polysilicon outside the gate trench by dry etching.

9. The method for manufacturing a short channel MOSFET device with a low turn-on voltage as claimed in claim 1, characterized in that: The subsequent production process includes the following sub-steps: S610, depositing a dielectric layer; S620, etching a contact hole region by a photolithography process; S630, completing etching of the contact hole through an etching process; S640, filling the contact hole to form a tungsten plug; S650, depositing a surface metal layer.

10. A short channel MOSFET device with low turn-on voltage, characterized in that: The device is manufactured by the method for manufacturing a short channel MOSFET device with a low turn-on voltage as claimed in any one of claims 1 to 9.

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