Three-dimensional inductor and method of manufacturing same

Abstract

A three-dimensional inductor and a method of manufacturing the same are disclosed. The three-dimensional inductor includes a substrate, a plurality of first horizontal wirings over an upper surface of the substrate, a plurality of second horizontal wirings over a back surface of the substrate, and a plurality of vertical wirings, the plurality of vertical wirings connect the plurality of first horizontal wirings to the plurality of second horizontal wirings to form a spiral body.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0185157, filed on December 18, 2023, and Korean Patent Application No. 10-2024-0028152, filed on February 27, 2024, with the Korean Intellectual Property Office, the disclosures of each of which are hereby incorporated by reference in their entirety. Technical Field

[0002] Various exemplary embodiments of the inventive concept relate to inductors, and more particularly, to integrated circuit type three-dimensional (3D) inductors, methods of manufacturing 3D inductors, and / or methods of using 3D inductors in radio frequency (RF) circuits, etc. Background Art

[0003] Inductors, together with resistors and capacitors, are essential passive devices in electrical and electronic engineering, especially in the field of communication.

[0004] While analog integrated circuits typically use resistors and capacitors, RF circuits used in communication devices additionally require inductors. Devices using resistors and capacitors have a reduced voltage gain in the high-frequency range. However, inductors can operate at higher frequencies while resonating with capacitors, and since a negligible voltage drop occurs in the inductors, the inductors can operate while providing an appropriate voltage gain.

[0005] As wireless communication evolves and the amount of information to be transmitted increases, higher frequencies are used, and higher performance devices are desired and / or required. On the other hand, in order to achieve miniaturization and integration suitable for use in portable communication devices such as mobile phones, there is a great need for design solutions for large-sized inductors.

[0006] To meet the needs of miniaturization and integration of communication devices, multiple passive devices are integrated on-chip, and thus, the number of devices can be reduced compared to off-chip implementation. For this, it is desired and / or required to include a relatively large inductor on-chip while maintaining desired device performance including low resistance and / or high inductance, etc. Summary of the Invention

[0007] Various exemplary embodiments of the inventive concept provide high-performance and / or high-efficiency inductors that can be applied to compact integrated circuit devices. According to one or more exemplary embodiments of the inventive concept, high-performance and / or high-quality inductors are provided.

[0008] Various example embodiments of the inventive concept also provide high-efficiency and / or high-performance inductors applied on-chip. To provide good and / or excellent high-frequency performance, inductors with a large number of turns, a large thickness of the wire, and / or a large size are provided. As a result, inductors with high inductance, low resistance, and / or low capacitance can be provided.

[0009] According to one or more example embodiments of the inventive concept, a three-dimensional (3D) inductor is provided, the three-dimensional (3D) inductor including a substrate and at least one spiral body, the at least one spiral body including: a plurality of first horizontal wirings on an upper surface of the substrate; a plurality of second horizontal wirings on a back surface of the substrate; and a plurality of vertical wirings connecting the plurality of first horizontal wirings and the plurality of second horizontal wirings.

[0010] According to one or more example embodiments of the inventive concept, a method of manufacturing a three-dimensional (3D) inductor is provided, the method including: forming at least one spiral body on a substrate, the step of forming at least one spiral body including forming a plurality of first horizontal wirings on a first surface of the substrate, forming a plurality of second horizontal wirings on a second surface of the substrate, and connecting the plurality of first horizontal wirings to the plurality of second horizontal wirings using a plurality of vertical wirings passing through the substrate.

[0011] According to one or more example embodiments of the inventive concept, a three-dimensional (3D) inductor is provided, the three-dimensional (3D) inductor including: a plurality of substrates including a first substrate and a second substrate stacked on each other, the first substrate being at the uppermost position of the plurality of substrates and the second substrate being at the lowermost position of the plurality of substrates, a back surface of the first substrate being adjacent to a back surface of the second substrate; and at least one spiral body, the at least one spiral body including: two terminals; a plurality of first horizontal wirings on a front surface of the first substrate; a plurality of second horizontal wirings on a front surface of the second substrate; and a plurality of vertical wirings extending in a vertical direction, the plurality of vertical wirings connecting the plurality of first horizontal wirings and the plurality of second horizontal wirings.

[0012] According to one or more example embodiments of the inventive concept, there is provided a multi-chip package including: a plurality of substrates including a first substrate and a second substrate stacked on each other, the first substrate being at the uppermost position of the plurality of substrates and the second substrate being at the lowermost position of the plurality of substrates, a rear surface of the first substrate being adjacent to a rear surface of the second substrate; a three-dimensional (3D) inductor including at least one spiral including two terminals, a plurality of first horizontal wirings, a plurality of second horizontal wirings, and a plurality of vertical wirings, the plurality of first horizontal wirings being on a front surface of the first substrate, the plurality of second horizontal wirings being on a front surface of the second substrate, and the plurality of vertical wirings being connected to the first horizontal wirings and the second horizontal wirings and extending in a vertical direction; and a mother board on which the plurality of substrates and the 3D inductor are mounted.

[0013] According to one or more example embodiments of the inventive concept, there is provided a dual three-dimensional (3D) inductor including: a substrate; a first 3D inductor including at least one first spiral including two first terminals, a plurality of first horizontal wirings, a plurality of second horizontal wirings, and a plurality of first vertical wirings, the plurality of first horizontal wirings being on an upper surface of the substrate, the plurality of second horizontal wirings being on a back surface of the substrate, and the plurality of vertical wirings being connected to the first horizontal wirings and the second horizontal wirings; and a second 3D inductor including at least one second spiral including two second terminals, a plurality of third horizontal wirings, a plurality of fourth horizontal wirings, and a plurality of second vertical wirings, the plurality of third horizontal wirings being on the upper surface of the substrate, the plurality of fourth horizontal wirings being on the back surface of the substrate, and the plurality of second vertical wirings being connected to the plurality of third horizontal wirings and the plurality of fourth horizontal wirings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various example embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0015] Figure 1A and Figure 1B respectively show a perspective view and a top view of a planar spiral inductor.

[0016] Figure 2 shows a schematic perspective view of a planar spiral inductor.

[0017] Figures 3A to 3C respectively show a perspective view, a front view, and a side view of a vertical inductor according to at least one example embodiment.

[0018] Figure 4 shows a schematic perspective view of a three-dimensional (3D) inductor according to at least one example embodiment.

[0019] Figures 5A to 5C is a schematic diagram of a vertical inductor according to some example embodiments when viewed from above.

[0020] Figure 6A and Figure 6B illustrate a horizontal wiring, a vertical wiring, and a connection portion therebetween according to some example embodiments.

[0021] Figure 7A illustrates a chip including a 3D inductor according to at least one example embodiment.

[0022] Figure 7B illustrates a chip including a 3D inductor according to at least one example embodiment.

[0023] Figure 8A illustrates a package including a chip including a 3D inductor according to at least one example embodiment.

[0024] Figure 8B illustrates a vertical inductor and a package including the vertical inductor according to at least one example embodiment.

[0025] Figure 9 illustrates a flowchart of operations for manufacturing a 3D inductor according to at least one example embodiment.

[0026] Figure 10 illustrates an operation of forming an opening in a substrate as part of an operation for manufacturing a 3D inductor according to at least one example embodiment.

[0027] Figures 11A to 11C is a schematic diagram of a dual 3D inductor according to some example embodiments when viewed from above.

[0028] Figure 12A and Figure 12B is a schematic diagram of a 3D inductor having three terminals according to some example embodiments when viewed from above.

[0029] Figure 13 illustrates a circuit diagram of a voltage controlled oscillator (VCO) including a vertical inductor according to at least one example embodiment of the inventive concept. Detailed Description

[0030] Hereinafter, various example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0031] First, Figure 1A and Figure 1BA perspective view and a top view of a planar coil inductor are respectively shown. As an inductor in an on-chip that is compatible with a semiconductor manufacturing process, a planar spiral inductor can be used, but the exemplary embodiments are not limited thereto.

[0032] Referring Figure 1A , the planar spiral inductor includes an inductor body 900 and has a first terminal E1 and a second terminal E2. The first terminal E1 is connected to the inner end of the spiral (e.g., the coil), and the second terminal E2 is connected to the outer end of the spiral. The planar spiral inductor is above a substrate (not shown), and an interlayer insulating film 200 may be located between the substrate and the planar spiral inductor. Optionally, a metal pattern 920 may be formed around and / or adjacent to the planar spiral inductor to reduce and / or prevent interference from the outside (e.g., an external source, etc.).

[0033] In the inductor body 900 of the planar spiral inductor, a spiral (e.g., a coil) is formed by repeatedly turning a conductive metal wire at the same level (e.g., the same vertical level (or called the perpendicular level) and / or height level, etc.). When spirals (e.g., coils) having the same shape are repeatedly formed, the area of the spiral changes. In other words, the area formed (e.g., enclosed, etc.) by the inner spiral is smaller than the area formed by the outer spiral.

[0034] Figure 2 is a schematic diagram of a planar spiral inductor, and the inductance L of the planar spiral inductor can be calculated using the following formula 1.

[0035] [Formula 1]

[0036] In the above formula 1, N is the number of repetitions of the spiral, R is the radius, and W is the thickness of the spiral (i.e., the distance between the outermost spiral and the innermost spiral).

[0037] Examining formula 1, as the value of W increases (i.e., as the dispersion of the spiral size increases), the inductance L can decrease. Therefore, in order to design a high-performance inductor, it is necessary to increase R to increase the overall size of the planar inductor, and / or it is necessary to increase the number of repetitions N of the spiral. However, these changes can increase the design burden of the inductor.

[0038] In addition, a planar spiral inductor can be fabricated using semiconductor processes. During the wiring process in the semiconductor chip post-processing stage, a conductive metal can be patterned at the same level (e.g., vertical level and / or height level, etc.) to form a repeatedly turning spiral (e.g., increasing the count and / or number of spirals included in the inductor, etc.).

[0039] However, as Figure 1B can be seen, since the planar area of the substrate onto which the planar spiral inductor is projected (e.g., the planar spiral inductor is on and / or above the substrate, etc.) increases, the value of the parasitic capacitance C with respect to the substrate can increase. Even if an interlayer insulating film is provided between the substrate and the planar spiral inductor, limitations due to the capacitance with respect to the substrate (e.g., parasitic capacitance) can occur. Therefore, when increasing the physical size of the planar spiral inductor and / or the number of repetitions of the spiral to fabricate a high-performance inductor, the design complexity can increase.

[0040] Next, the planar spiral inductor must be equipped with an extension line for connecting the inner end of the spiral to the first terminal E1, and this extension line should pass above (see Figure 1A ) or below (see Figure 1B ) at least a part of the inductor body 900 of the planar spiral inductor. This hinders the symmetry of the entire inductor and results in an increase in the parasitic capacitance due to the extension line. Therefore, the design complexity can increase.

[0041] A spiral inductor having a size of several hundred μm × several hundred μm may be desired and / or required to ensure an inductance of several nH, or may be desired and / or required for high-performance RF circuits. However, the planar spiral inductor has limitations in increasing its size and / or physical area, and there is a high risk and / or an increasing risk of generating capacitance with respect to the substrate. In addition, it is complex and difficult to design the planar spiral inductor to be stacked with other devices. As described above, when the inductor is placed on a plane, the inductor design becomes complex and the wiring length increases, which can increase circuit delay and / or power consumption, etc.

[0042] Figures 3A to 3C A three-dimensional (3D) inductor 300 according to at least one example embodiment is shown.

[0043] Among the drawings, Figure 3Ais a perspective view of a 3D inductor 300 according to at least one exemplary embodiment, and the 3D inductor 300 may have a length extending in the X direction, a width in the Y direction, and a height in the Z direction. The 3D inductor 300 may have a first terminal 302 and a second terminal 304 at either end of the 3D inductor 300, but is not limited thereto. Herein, the 3D inductor may also be referred to as a vertical inductor, but is not limited thereto.

[0044] Referring to Figure 3A , for example, the shape of the vertical inductor 300 may form a quadrilateral projection plane through its width and height, and these quadrilateral projection planes may all be the same repeatedly, but the exemplary embodiments are not limited thereto, and for example, the vertical inductor 300 may have different shapes, sizes, and / or the number of spirals, etc. If the width and height of the vertical inductor 300 are expanded, the quadrilateral projection plane may be expanded. If the number (N) of spirals of the vertical inductor 300 increases, the length of the vertical inductor 300 may increase.

[0045] In some exemplary embodiments, the first terminal 302 and the second terminal 304 are respectively connected to opposite ends of the spiral, so that an extension line entering the interior of the spiral is not required. Therefore, even if the vertical inductor is designed to have many spirals, the design of the vertical inductor will not become more complex and will not affect the magnetic field distribution.

[0046] Figure 3B is a view of the vertical inductor 300 according to at least one exemplary embodiment when viewed in the Y direction. Referring to Figure 3B , a substrate 100 may be provided, and the vertical inductor 300 may include: a plurality of first horizontal wirings 340, a plurality of second horizontal wirings 360, and a plurality of vertical wirings (or vertical wirings) 320, etc. The plurality of first horizontal wirings 340 are above (and / or on) the upper surface of the substrate 100, and the plurality of second horizontal wirings 360 are on the back surface (or rear surface) of the substrate 100, but are not limited thereto. In some exemplary embodiments, the first terminal 302 may be connected to one of the plurality of first horizontal wirings 340, and the second terminal 304 may be connected to another of the plurality of first horizontal wirings 340. The plurality of vertical wirings 320 may connect the plurality of first horizontal wirings 340 to the plurality of second horizontal wirings 360. Therefore, the plurality of first horizontal wirings 340, the plurality of second horizontal wirings 360, and the plurality of vertical wirings 320 may form a single wire.

[0047] In some example embodiments, multiple first horizontal wirings 340 are at the same level, and the first horizontal wirings 340 may be at least partially parallel to each other (e.g., a portion of one of the first horizontal wirings 340 is parallel to a portion of another one of the first horizontal wirings 340), but is not limited thereto. Referring to Figure 3A , multiple first horizontal wirings 340 may include portions parallel to the Y direction and portions "extending in the X direction and respectively connected to multiple vertical wirings 320", but is not limited thereto. In this case, multiple second horizontal wirings 360 may be at the same level and parallel to each other.

[0048] In some example embodiments, multiple second horizontal wirings 360 are at the same level, and the second horizontal wirings 360 may be at least partially parallel to each other (e.g., a portion of one of the second horizontal wirings 360 is parallel to a portion of another one of the second horizontal wirings 360), but the example embodiments are not limited thereto. Different from Figure 3A shown, the second horizontal wirings 360 may include portions parallel to the Y direction and portions extending in the X direction and respectively connected to the vertical wirings 320, etc. In this case, multiple first horizontal wirings 340 may be at the same level and parallel to each other.

[0049] In some example embodiments, multiple first horizontal wirings 340 may be spaced apart from each other at a specific and / or desired interval, and / or multiple second horizontal wirings 360 may also be spaced apart from each other at a specific and / or desired interval.

[0050] In some example embodiments, multiple vertical wirings 320 may be divided into Figure 3A vertical wirings shown in the front (e.g., relatively arranged in the -Y direction) as shown in Figure 3A and vertical wirings shown in the rear (e.g., relatively arranged in the +Y direction) as shown in

[0051] (and may be referred to as the "front group" here), and Figure 3B The multiple vertical wirings 320 may extend perpendicular to the substrate 100 as shown in Figure 3B , and may vertically pass through the interlayer insulating film 200 (and / or interlayer insulating layer) and the substrate 100 as shown in

[0052] In addition, multiple vertical wirings 320 may have the same height (e.g., length in the longitudinal direction) and may be parallel to each other, but are not limited thereto. In some example embodiments, the vertical wirings 320 in the front group among the multiple vertical wirings 320 may be spaced apart from each other at a specific and / or desired interval, and / or the vertical wirings 320 in the rear group may also be spaced apart from each other at a specific and / or desired interval.

[0053] Figure 3C is a side view of the vertical inductor 300 according to at least one example embodiment when observed in the X direction. When observed in the X direction, the first horizontal wiring 340, the second horizontal wiring 360, and the two vertical wirings 320 form a quadrilateral area, but the example embodiments are not limited thereto, and for example, the first horizontal wiring 340, the second horizontal wiring 360, and the two vertical wirings 320 may form different shapes, etc. This area may correspond to Figure 3B the height in Figure 3C and the product of the width in

[0054] According to at least one example embodiment, different from the height that is subject to many semiconductor process limitations, the width and length may have very high degrees of freedom, increasing degrees of freedom, and / or relatively few process limitations, etc. For example, the width and / or length may be used from several micrometers to several nanometers. However, in order to increase and / or optimize the inductance value, the length of the vertical inductor 300 may be increased while maintaining the ratio of the width to the height at about 1:1 to about 5:1, but the example embodiments are not limited thereto.

[0055] In addition, as Figure 3BAs shown, as the number of turns (and / or repeated turns, etc.) of the coil increases, the length of the vertical inductor 300 increases. However, even if the number of turns of the coil of the vertical inductor 300 increases and the length of the vertical inductor 300 increases, the area of the vertical inductor 300 that is horizontal to the substrate 100 does not increase significantly. Therefore, the parasitic capacitance with respect to the substrate 100 is small. Considering the design aspects in at least one exemplary embodiment, since there is a relatively large degree of freedom in selecting the length of the vertical inductor, there is almost no limitation on increasing the number of repeated turns. In addition, in some exemplary embodiments, when the spacing between adjacent wirings is appropriately reduced, even if the number of turns is increased, the length of the vertical inductor can be appropriately adjusted. In some exemplary embodiments, the number of turns N of the coil can be 3 or more, and the number of turns N of the coil can be from about 3 to about 20 in order to increase and / or optimize the inductance value, but the exemplary embodiments are not limited thereto, and for example, there can be more or fewer turns, etc.

[0056] The value of the inductance L of a vertical inductor having a circular projection plane as shown in Figure 4 can be obtained by Equation 2 below.

[0057] [Equation 2]

[0058] In Equation 2, N is the number of repetitions of the coil, R is the radius, and H is the height perpendicular to the projection plane of the coil and can correspond to the length of the vertical inductor 300 in Figure 3A . Different from horizontal inductors, the parameters of vertical inductors (such as the number of repetitions N, width, height, and / or length) have almost no limitations in terms of scalability.

[0059] Specifically, the projection plane can be increased by increasing the width and / or height of the vertical inductor, the number of repetitions N of the coil can be set to a large number, and / or the spacing between the coils can be adjusted by increasing the number of repetitions N of the coil during design and / or manufacturing. As described above, vertical inductors can have greater parameter freedom than horizontal spiral inductors, and thus can provide higher inductance, lower parasitic capacitance, smaller physical size, lower manufacturing cost, etc.

[0060] Therefore, various types of vertical inductors can be provided in terms of inductor design and parameter selection.

[0061] For example, in some exemplary embodiments, the first horizontal wiring and the second horizontal wiring may not be parallel to each other, etc. In other exemplary embodiments, the first horizontal wiring and the second horizontal wiring may be parallel to each other, etc.

[0062] Figures 5A to 5CFIG. is a schematic diagram of vertical inductors 500a to 500c according to some example embodiments when viewed from above the substrate.

[0063] First, referring to Figure 5A , the vertical inductor 500a may include a vertical wiring 520, a first horizontal wiring 540, a second horizontal wiring 560, etc., and may also include a first terminal 502 and a second terminal 504, but is not limited thereto.

[0064] In Figure 5A the vertical inductor 500a shown, the first horizontal wirings 540 may be parallel to each other, and the second horizontal wirings 560 may be parallel to each other, but the example embodiments are not limited thereto. In some example embodiments, the first horizontal wiring 540 and the second horizontal wiring 560 may not be parallel to each other, etc. The first horizontal wiring 540 may be arranged perpendicular to the longitudinal direction (e.g., the length direction or the X direction) of the vertical inductor 500a, but is not limited thereto.

[0065] In Figure 5A , the first horizontal wiring 540 is arranged perpendicular to the longitudinal direction of the vertical inductor 500a, and the second horizontal wiring 560 is arranged at an angle with respect to the longitudinal direction of the vertical inductor 500a. However, in some example embodiments, the second horizontal wiring 560 may be perpendicular to the longitudinal direction of the vertical inductor 500a, and the first horizontal wiring 540 may be arranged at an angle with respect to the longitudinal direction of the vertical inductor 500a, etc.

[0066] Figure 5B FIG. shows a vertical inductor 500b according to at least one example embodiment. As Figure 5B shown, the vertical inductor 500b may include a first horizontal wiring 540, a second horizontal wiring 560, and a vertical wiring 520, and may also include a first terminal 502 and a second terminal 504, but the example embodiments are not limited thereto. Referring to Figure 5B , the first horizontal wirings 540 are parallel to each other and the second horizontal wirings 560 are parallel to each other, but are not limited thereto. For example, the first horizontal wiring 540 and the second horizontal wiring 560 may not be parallel to each other. In addition, according to some example embodiments, both the first horizontal wiring 540 and the second horizontal wiring 560 may not be arranged perpendicular to the longitudinal direction of the vertical inductor 500b.

[0067] Figure 5C FIG. shows a vertical inductor 500c according to at least one example embodiment. As Figure 5C shown, the vertical inductor 500c may include a first horizontal wiring 540, a second horizontal wiring 560, and a vertical wiring 520, and may also include a first terminal 502 and a second terminal 504, but is not limited thereto. Referring to Figure 5C, each of the first horizontal wirings 540 may include a first portion 540a and a second portion 540b. The first portion 540a is parallel to the longitudinal direction of the vertical inductor 500c, and the second portion 540b is perpendicular to the longitudinal direction of the vertical inductor 500c, but is not limited thereto. The second portions 540b of the first horizontal wirings 540 may be parallel to each other, but is not limited thereto. Each of the second horizontal wirings 560 may include a first portion 560a and a second portion 560b. The first portion 560a is parallel to the longitudinal direction of the vertical inductor 500c, and the second portion 560b is perpendicular to the longitudinal direction of the vertical inductor 500c, but is not limited thereto. The second portions 560b of the second horizontal wirings 560 may be parallel to each other, but is not limited thereto.

[0068] As Figure 5C shown, the second portion 540b of the first horizontal wiring 540 may be parallel to the second portion 560b of the second horizontal wiring 560, but the exemplary embodiments are not limited thereto. In addition, all of the second portions 540b of the first horizontal wirings 540 and the second portions 560b of the second horizontal wirings 560 may be arranged perpendicular to the longitudinal direction of the vertical inductor 500c, but is not limited thereto.

[0069] Returning to Figures 3A to 3C , in some exemplary embodiments, the vertical inductor may be formed as a single body, but is not limited thereto. For example, the vertical inductor may be formed by connecting the first horizontal wiring, the second horizontal wiring, and the vertical wiring to each other, etc.

[0070] Referring to Figure 6A , the first horizontal wiring 340 and the second horizontal wiring 360 may extend parallel to each other with a constant width, but is not limited thereto. The vertical wiring 320 may be connected to the first horizontal wiring 340 and the second horizontal wiring 360. It may be advantageous to form the vertical wiring 320 as a thick and / or wide wiring to reduce the resistance of the vertical inductor. Since the resistance of the vertical inductor is reduced, the quality factor (Q factor) is improved. Therefore, a high-performance inductor can be provided.

[0071] To reduce the resistance of the inductor, the first horizontal wiring 340, the second horizontal wiring 360, and the vertical wiring 320 may be well matched. As Figure 6B shown, the first horizontal wiring 340 may include a connection portion 342 and a wiring portion 343. In addition, the second horizontal wiring 360 may include a connection portion 362 and a wiring portion 363. The vertical wiring 320 may be connected to both the connection portion 342 of the first horizontal wiring 340 and the connection portion 362 of the second horizontal wiring 360. To increase the area of the connection portion, the shape of the wiring portion may be different from the shape of the connection portion, but is not limited thereto. As Figure 6BAs shown, the widths of connection portions 342 and 362 may be greater than the widths of wiring portions 343 and 363, but are not limited thereto.

[0072] In some example embodiments, as Figure 5C shown, a first portion 540a of the first horizontal wiring 540, a second portion 540b of the first horizontal wiring 540, a first portion 560a of the second horizontal wiring 560, and a second portion 560b of the second horizontal wiring 560 may each include a connection portion having a width greater than that of the wiring portion, and the vertical wiring 520 may be connected to these connection portions, but the example embodiments are not limited thereto.

[0073] In some example embodiments, the projection planes formed by the spirals may be the same and / or substantially the same (e.g., within + / - 10%, etc.). The projection plane may have a quadrilateral shape, but the example embodiments are not limited thereto. In addition, the horizontal wiring and / or vertical wiring included in the vertical inductor may be arranged at a desired and / or specific interval. As shown above, if the distance between the wiring and the projection plane formed by the repeated inductor spirals remains constant, the magnetic fields generated by the wiring may properly overlap each other. Therefore, the inductance can be increased.

[0074] Therefore, in the vertical inductor according to at least one example embodiment, a plurality of vertical wirings may have the same height and may be parallel to each other, a plurality of first horizontal wirings may be at the same level and at least partially parallel to each other (e.g., a part of one of the first horizontal wirings 340 is parallel to a part of another one of the first horizontal wirings 340), and / or a plurality of second horizontal wirings may be at the same level and at least partially parallel to each other, etc.

[0075] In some example embodiments, the first horizontal wiring provided above (and / or on) the upper surface of the substrate may include ultra-thick metal (UTM), but the example embodiments are not limited thereto. The UTM may be provided in the top metal layer of the chip, and the UTM has a thickness of, for example, 3 μm or more, and thus the resistance can be reduced, but is not limited thereto. Specifically, the thickness of the UTM may be about 2 μm to about 5 μm, but is not limited thereto. The first horizontal wiring includes a conductive material and may include, but is not limited to, copper, silver, platinum, nickel, gold, tungsten, aluminum, and / or their alloys, etc. Specifically, the first horizontal wiring may include copper having a low resistance. Therefore, a desired Q factor can be ensured.

[0076] Generating a larger inductance to, for example, provide a larger projection area may be advantageous. In some example embodiments, in order to increase the height of the spiral, a vertical wiring having a through-silicon via (TSV, or silicon through hole) passing through the substrate may be used. For example, referring toFigure 3B , multiple vertical wirings 320 can be respectively connected to multiple first horizontal wirings 340, vertically extend through the substrate 100, and be respectively connected to multiple second horizontal wirings 360 on the lower surface of the substrate 100, etc. The TSV can be formed as a single body. For this purpose, an opening can be formed starting from the upper part of the interlayer insulating film 200 through the substrate 100, and at least one conductive material can fill the opening. Optionally, the opening can also be formed starting from the lower part of the substrate 100 through the interlayer insulating film 200. In some exemplary embodiments, a combined vertical wiring can be provided, in which a first vertical wiring segment formed through the interlayer insulating film 200 and a second vertical wiring segment formed through the substrate 100 are combined with each other, but the exemplary embodiments are not limited thereto.

[0077] The TSV includes a conductive material (such as, W, Sn, Cu, Ag, Pt, Au, and / or their alloys), but the exemplary embodiments are not limited thereto.

[0078] The TSV must be insulated from the substrate, and the insulation between the substrate and the TSV can be achieved in various ways. For example, an insulating layer can be formed between the substrate and the TSV to isolate the substrate from the TSV, but the exemplary embodiments are not limited thereto. The insulating layer can include an insulating film formed on the side surface of the opening that has passed through the substrate. The insulating film can include but is not limited to a silicon oxide film, a silicon nitride film, and / or their composite films, etc. In addition to these films, various insulating films (such as, metal oxide films and nitride films) can be used. Furthermore, insulation can be created by forming voids.

[0079] In another method of insulating the substrate from the TSV, as Figure 7A shown, an insulating layer can be formed in the peripheral region (or area) 105 where the TSV is formed. In another method, as Figure 7B shown, at least one region (i.e., an insulating isolation region) including an insulating material can be integrally formed in the region 106 of the substrate 130 where a vertical inductor is formed. Subsequently, a vertical wiring can be set by (for example, in at least one insulating isolation region) forming an opening and filling the opening with a conductive material, etc., such that, for example, the vertical wiring can pass through at least one insulating isolation region.

[0080] As Figure 7B shown, when an insulating isolation region is formed in a part of the substrate 130 and then an opening is formed, the opening can be formed under the same or similar etching conditions. Therefore, the process conditions can be easily set. In addition, since the opening extends to the back surface of the substrate 130, even if the opening is very deep, the vertical wiring has a high aspect ratio. Therefore, a vertical wiring with a relatively consistent thickness can be formed.

[0081] The cross-section of the vertical wiring includes, but is not limited to, circular, elliptical, quadrilateral, and / or polygonal shapes. In terms of resistance, it is advantageous to increase the thickness and / or diameter of the vertical wiring, and for example, considering the process and design, the thickness and / or diameter of the vertical wiring can be approximately 2 μm to approximately 5 μm, but the exemplary embodiments are not limited thereto.

[0082] In some exemplary embodiments, as Figure 7A shown, at least a part of the substrate 130 may be left at the center of the vertical inductor, or at least a part of the substrate 130 may be replaced with a conductive material, but the exemplary embodiments are not limited thereto. In this case, the value of the inductance can be adjusted.

[0083] In some exemplary embodiments, the height of the vertical inductor can be approximately 20 μm to approximately 200 μm, but is not limited thereto.

[0084] In some exemplary embodiments, the front surface and / or the back surface of the substrate may be pre-removed before forming at least one vertical wiring vertically passing through the substrate. The height of the substrate is not limited, but considering the aspect ratio of the vertical wiring, the height (or thickness) of the substrate can be approximately 50 μm or less, but is not limited thereto.

[0085] In some exemplary embodiments, the second horizontal wiring may include at least one wiring provided on the lower surface of the substrate, and specifically, may include a redistribution layer and / or a backside metal (BSM) layer. It is advantageous to increase the thickness of the second horizontal wiring to reduce the resistance, and for example, in terms of chip design and process, the thickness of the second horizontal wiring can be approximately 2 μm to approximately 5 μm, but the exemplary embodiments are not limited thereto.

[0086] To effectively transmit power to the chip, a backside power delivery network (BS-PDN) is formed on the back surface of the substrate, but the exemplary embodiments are not limited thereto. The wiring layer formed in this case may be referred to as a BSM layer. The second horizontal wiring may be formed in the BSM layer, but is not limited thereto.

[0087] In some exemplary embodiments, a chip (or chiplet) package may be provided, in which a chip including a vertical inductor according to at least one exemplary embodiment of the inventive concept, another RF chip (or chiplet), another logic chip (or chiplet), and / or another memory chip (or chiplet) are mounted together.

[0088] Referring to Figure 8AAs an example, a chip (or die) 620 is provided, which is different from the chip (or die) 610 including the vertical inductor 300 according to at least one example embodiment. The package can be formed by mounting at least two chips (or dies) 610 and 620 at specified positions on a motherboard 630, but the example embodiment is not limited thereto. The motherboard 630 can have conductive layer patterns 631 and 632 on its upper surface, and the conductive layer patterns 631 and 632 can include connection points for the chips 610 and 620 to be mounted, but it is not limited thereto. The motherboard 630 can have a plurality of balls 633 on its top or bottom, but it is not limited thereto. In addition, in some example embodiments, an interposer can be provided between the motherboard 630 and the chips (or dies) 610 and 620 to mount the chips 610 and 620, etc. on the motherboard 630.

[0089] In addition, the package can have a 3D stacked structure (such as a 3D3D integrated circuit (IC) / die) in logical processing, but the example embodiment is not limited thereto. When using a stacked chip structure, the height of the vertical inductor can be further increased by using the stacked chip structure.

[0090] Figure 8B A vertical inductor and a package (e.g., a semiconductor package) including the vertical inductor are shown. A chip structure 400 in which a plurality of chips (e.g., three chips, etc.), each having a semiconductor substrate, are stacked on one another can be mounted on the motherboard 630, but the example embodiment is not limited thereto.

[0091] Continuing to refer to Figure 8B , the chip structure 400 can have a structure in which a first chip 401 at the topmost position (and can be referred to as the "topmost chip" here), a second chip 402 immediately below the topmost chip 401 (and can be referred to as the "intermediate chip" here), and a third chip 403 below the intermediate chip (and can be referred to as the "bottommost chip" or "bottom chip" here) are stacked, but the example embodiment is not limited thereto, and for example, there can be a greater or smaller number of chips, etc.

[0092] The topmost chip 401 can include a first substrate 101, a first horizontal wiring 440, and a first vertical wiring segment V1, etc. The first horizontal wiring 440 is above (and / or on) the upper surface of the first substrate 101, and the first vertical wiring segment V1 is connected to the first horizontal wiring 440 and passes through the first substrate 101.

[0093] The intermediate chip 402 may include a second substrate 102, and the second substrate 102 may be adjacent to the first substrate 101 of the uppermost chip 401. The intermediate chip 402 may include a second vertical wiring segment V2, etc., and the second vertical wiring segment V2 passes through the second substrate 102.

[0094] The lowermost chip 403 may include a third substrate 103, and the third substrate 103 may be adjacent to the intermediate chip 402. The lowermost chip 403 may include a third vertical wiring segment V3, etc., and the third vertical wiring segment V3 passes through the third substrate 103. In addition, the lowermost chip 403 may include a second horizontal wiring 450, etc., and the second horizontal wiring 450 is above (and / or on) the upper surface of the third substrate 103.

[0095] The first vertical wiring segment V1 of the uppermost chip 401 may be connected to the second vertical wiring segment V2 of the intermediate chip 402 via at least one conductive connection element 480, etc. The second vertical wiring segment V2 of the intermediate chip 402 may be connected to the third vertical wiring segment V3 of the lowermost chip 403 via at least one conductive connection element 490. For example, the conductive connection elements 480 and 490 may include micro-bumps and / or hybrid copper bonding (HCB), etc., but are not limited thereto. An underfill 270 and / or a molding material may be disposed between the chips to reduce and / or prevent physical damage and / or provide electrical protection for the stacked chips. In addition, passivation films 250 and 260 may be formed on the tops of the chips to reduce and / or prevent physical damage and / or provide electrical protection, etc., but the example embodiments are not limited thereto. In one example embodiment, each of the first vertical wiring segment V1 to the third vertical wiring segment V3 may include a TSV such that the TSV passes through the first substrate 101 to the third substrate 103. As described above, the projection area height of the vertical inductor is increased by connecting the vertical wiring segments of the stacked chips to each other. Therefore, an inductor with a better Q factor and / or inductance can be provided.

[0096] In some example embodiments, the number N of turns of the helix of the vertical inductor in the stacked chip structure may be from about 3 to about 20, and the height of the vertical inductor may be from about 40 μm to about 800 μm, but the example embodiments are not limited thereto, and the number of turns and / or the height of the inductor may be greater than or less than the values specified herein. As an example, the height of each of the substrates may be 50 μm or less, and the thickness of each of the vertical wirings may be from about 2 μm to about 5 μm, but is not limited thereto.

[0097] As described above, in some example embodiments, the vertical inductor may include a first substrate 101 at the uppermost position (and may be referred to herein as the "uppermost substrate") and a third substrate 103 at the lowermost position (and may be referred to herein as the "lowermost substrate"). The vertical inductor may include a plurality of stacked substrates such that the upper surface of the uppermost substrate 101 and the upper surface of each of the other substrates (e.g., the lowermost substrate 103) are arranged opposite to each other, or such that the lower surface of the uppermost substrate 101 and the lower surface of each of the other substrates (e.g., the lowermost substrate 103) are arranged adjacent to each other. The vertical inductor may further include: a first horizontal wiring 440, a second horizontal wiring 450, and / or a vertical wiring 420, etc. The first horizontal wiring 440 is formed above the uppermost substrate 101 among the plurality of stacked substrates (and / or on the uppermost substrate 101 among the plurality of stacked substrates), the second horizontal wiring 450 is formed above the lowermost substrate 103 among the plurality of stacked substrates (and / or on the lowermost substrate 103 among the plurality of stacked substrates), and the vertical wiring 420 extends in the vertical direction and connects the first horizontal wiring 440 to the second horizontal wiring 450. A plurality of vertical wirings 420, a plurality of first horizontal wirings 440, and / or a plurality of second horizontal wirings 450 may form a helix (e.g., a coil, etc.), and the helix may be provided as a vertical inductor having two terminals, included in a vertical inductor having two terminals, and / or attached as a vertical inductor having two terminals.

[0098] As described above with reference to the drawings, even in Figure 8B the stacked vertical inductor shown in, the second horizontal wiring 450 may use the uppermost wire (e.g., UTM), but the example embodiments are not limited thereto.

[0099] In some example embodiments, the two terminals for connecting the vertical inductor to the outside (e.g., connecting to an external device, etc.) may extend from the uppermost chip or from the lowermost chip. In some example embodiments, the two terminals may be respectively connected to two different horizontal wirings among the plurality of first horizontal wirings 440 or the plurality of second horizontal wirings 450. Therefore, various modifications can be provided in terms of the freedom of design (e.g., IC design, etc.).

[0100] In some example embodiments, the direction in which the substrates are stacked may vary. For example, the substrates may be stacked such that all of its front surfaces face upward, but are not limited thereto. In addition, an interposer may be optionally provided between the stacked chips and the motherboard 630, and additional logic chips and / or memory chips may be mounted on the motherboard 630, etc.

[0101] Next, a method of manufacturing a vertical inductor will be described according to at least one example embodiment. Figure 9is a flowchart showing operations for manufacturing a vertical inductor, but the exemplary embodiments are not limited thereto.

[0102] Referring Figure 9 , a substrate may be provided (S100). The substrate may include a base, and passive elements (such as resistors, capacitors, inductors, and / or other elements (such as p-type transistors and / or n-type transistors, etc.)) are formed on the base, but are not limited thereto. The substrate may include a single-material semiconductor substrate and / or a compound semiconductor substrate (such as GaN, etc.). The single-material semiconductor substrate may include an n-type substrate doped with n-type impurities or a p-type substrate doped with p-type impurities. For example, the material forming the single-material semiconductor substrate may include silicon, germanium, carbon, etc.

[0103] The substrate may include at least one semiconductor region and at least one insulator region, etc. The substrate may represent a semiconductor wafer (e.g., a silicon semiconductor wafer), or may represent a segment cut into multiple IC chips, etc. In addition, the substrate may be in a state before multiple semiconductor processes are performed, or the substrate may be in a state in which elements have been formed thereon through semiconductor processes.

[0104] Next, a plurality of vertical wirings may be formed on the substrate (S200). The vertical wirings may vertically connect a first horizontal wiring to a second horizontal wiring and thus extend in height. For example, the vertical wirings may pass through the substrate and / or an interlayer insulating film formed on the substrate, etc.

[0105] As a method of forming vertical wirings passing through the substrate and the interlayer insulating film, there are examples of methods of forming integrated vertical wirings and connected vertical wirings.

[0106] According to at least one integrated vertical wiring formation method, an in-situ dry etching method may be used to form (and / or simultaneously form) an opening having a large aspect ratio toward the upper surface of the substrate on which the interlayer insulating film has been formed. Subsequently, the vertical wiring may be formed (and / or simultaneously formed) by filling the opening with a conductive material. In at least one integrated vertical wiring formation method, less misalignment occurs and the resistance is reduced, and thus, an excellent Q factor can be obtained.

[0107] According to at least one connected vertical wiring formation method, TSVs passing through the substrate are separately formed. Then, vertical wiring segments (and / or vias, contacts, etc.) passing through the interlayer insulating film may be formed so as to be well aligned with the TSVs. In at least one connected vertical wiring formation method, the process can be simplified, and good alignment can reduce resistance generation.

[0108] In some example embodiments, to form at least one vertical wiring, at least one first opening is formed through a substrate and at least one first opening is filled with a sacrificial film (such as, SiO2, Si / SiO2, etc.). Then, at least one second opening is formed through an interlayer insulating film so as to align the second opening with the first opening, and the sacrificial film is removed. Subsequently, the vertical wiring can be formed by filling (and / or simultaneously filling) the first opening and the second opening with a conductive material. However, the example embodiments are not limited to the above-described method of forming the vertical wiring.

[0109] To electrically insulate the vertical wiring from the substrate, at least one insulating film can be applied thereto. Figure 10 An operation of forming an opening in a substrate, which is part of an operation of manufacturing a vertical inductor according to at least one example embodiment, is shown, but the example embodiments are not limited thereto.

[0110] Referring to Figure 10 , Figure 9 Forming a plurality of vertical wirings (S200) on a substrate in [reference] may include: forming an opening through the substrate (S220), forming an insulating film / insulating portion that electrically separates each of the openings from the substrate (S240), and filling the opening with a conductive material (S250).

[0111] Forming an insulating film (S240) between the opening and the substrate may include: forming an insulating film on at least one side surface of the opening. The insulating film may include but is not limited to: a silicon oxide film, a silicon nitride film, a metal nitride film, a metal oxide film, and / or a composite film thereof, but is not limited thereto.

[0112] In at least one example embodiment described with reference to Figure 7A After forming an insulating portion in region 105 of substrate 130, an opening may be formed through region 105 to form a vertical wiring.

[0113] In some example embodiments, removing a part of the substrate (S230) may be additionally performed before or after forming an opening in the substrate to reduce the thickness of the substrate. As a part of the substrate, the substrate may be removed (e.g., polished, ground, etched, etc.) from its back surface to a desired and / or specific thickness. The method of removing the substrate may include chemical mechanical polishing (CMP) and / or dry / wet etching. If the substrate is partially removed (S230), the thickness of the substrate is reduced. Accordingly, a process of penetrating the substrate can be easily performed, and a TSV having a high aspect ratio can be formed.

[0114] Returning to reference Figure 9 ,a plurality of first horizontal wirings (S300) can be formed above the substrate.

[0115] The first horizontal wiring can use a wiring layer above the substrate, but a thick wiring layer can be beneficial for reducing the resistance of the vertical inductor. Additionally, in order to generate a larger inductance, the first horizontal wiring disposed above the upper surface of the substrate can include UTM, but is not limited thereto. The first horizontal wiring includes a conductive material and can include, but is not limited to, copper, silver, platinum, nickel, gold, tungsten, aluminum, and / or their alloys, etc. For example, the first horizontal wiring can include copper with low resistance.

[0116] Next, a plurality of second horizontal wirings (S400) can be formed under the substrate. The second horizontal wiring can include at least one wiring disposed on the lower surface of the substrate and can include, for example, a redistribution layer and / or BSM, etc. In order to reduce the resistance of the vertical inductor, it can be beneficial for the second horizontal wiring to be thicker. According to the sequence of the semiconductor process, the step (S400) of forming the second horizontal wiring can be performed in a pre-treatment operation or can be performed in a post-treatment operation.

[0117] In addition, in the above operation (S200), the method of forming a plurality of vertical wirings includes forming the vertical wirings from the upper surface of the substrate, but is not limited thereto. However, in some example embodiments, a plurality of vertical wirings can be formed from the back surface of the substrate, etc.

[0118] After forming the TSV that penetrates the substrate from the back surface of the substrate, the first horizontal wiring can be formed, and then the second horizontal wiring can be formed, but the example embodiments are not limited thereto. As described above, according to at least one example embodiment of the inventive concept, it should be understood that the method of forming a vertical inductor includes Figure 9 the operations S100 to S400 shown in, but is not limited thereto, and for example, the order of the operations can be changed, one or more operations can be omitted, added, and / or combined, etc. Additionally, herein, the expression "the vertical wiring connects the horizontal wirings to each other" should not be construed as indicating or implying a processing order, but should be understood to indicate that the vertical wiring structurally connects the horizontal wirings to each other.

[0119] Various devices and / or integrated circuits, etc. including the vertical inductor disclosed herein can be provided. For example, devices and circuits such as an LC filter including a plurality of single vertical inductors of various sizes can be provided. Additionally or alternatively, in devices and circuits where low noise and / or high-speed signal processing are desired and / or required, differential signals can be used as input signals. Devices and / or circuits using such a pair of differential signals as input can be provided as devices and / or circuits including dual vertical inductors.

[0120] According to at least one exemplary embodiment of the inventive concept, a dual vertical inductor may include a substrate, a first vertical inductor, and a second vertical inductor, but is not limited thereto. The first vertical inductor may include a plurality of first horizontal wirings on an upper surface of the substrate, a plurality of second horizontal wirings on a back surface of the substrate, and a plurality of first vertical wirings, but is not limited thereto. The plurality of first vertical wirings may connect the plurality of first horizontal wirings to the plurality of second horizontal wirings to form a first helix, and the first helix may correspond to a first vertical inductor having two terminals, etc. The second vertical inductor may include a plurality of third horizontal wirings on an upper surface of the substrate, a plurality of fourth horizontal wirings on a back surface of the substrate, and a plurality of second vertical wirings, but is not limited thereto. The plurality of second vertical wirings may connect the plurality of third horizontal wirings to the plurality of fourth horizontal wirings to form a second helix, and the second helix may correspond to a second vertical inductor having two terminals, etc. Structural features and / or manufacturing methods for the first vertical inductor and the second vertical inductor may be the same as or similar to those of the single vertical inductor described above with reference to the drawings, but are not limited thereto. Accordingly, descriptions of the same or similar parts are omitted.

[0121] The first vertical inductor and the second vertical inductor in the dual vertical inductor may be spatially combined and / or magnetically combined with each other, but are not limited thereto. For example, as Figures 11A to 11C shown, when viewed from above the upper surface of the substrate, the first vertical inductor and the second vertical inductor may be parallel to each other, but are not limited thereto. In another example, as Figure 12A and Figure 12B shown, when viewed from above the upper surface of the substrate, the first vertical inductor and the second vertical inductor may be symmetric to each other, but are not limited thereto.

[0122] Referring to Figures 11A to 11C , the first vertical inductor 902 and the second vertical inductor 904 may be provided, but the exemplary embodiment is not limited thereto, and for example, a greater number of vertical inductors may be provided. The plurality of first horizontal wirings 942 of the first vertical inductor 902 may be parallel to the plurality of third horizontal wirings 944 of the second vertical inductor 904, but are not limited thereto. The plurality of second horizontal wirings 962 of the first vertical inductor 902 may be parallel to the plurality of fourth horizontal wirings 964 of the second vertical inductor 904, but are not limited thereto. The plurality of first vertical wirings 922 of the first vertical inductor 902 may be parallel to the plurality of second vertical wirings 924 of the second vertical inductor 904, but are not limited thereto. Accordingly, the first vertical inductor 902 and the second vertical inductor 904 may be parallel to each other in space, and a first inductance formed by the first vertical inductor 902 and a second inductance formed by the second vertical inductor 904 may create an increased inductance. In addition, as Figures 11A to 11CAs shown, inductors are spatially arranged differently to provide a phase difference in the inductance values provided by the inductors.

[0123] Next, referring to Figure 12A and Figure 12B , when viewed from above the upper surface of the substrate, the first vertical inductor and the second vertical inductor in the dual vertical inductor may be symmetric to each other, but are not limited thereto. Figure 12A Shows the first vertical inductor 801a on the left and the second vertical inductor 802a on the right when viewed from above the substrate. The first vertical inductor 801a on the left may include a plurality of first horizontal wirings 840, a plurality of second horizontal wirings 860, and a plurality of first vertical wirings 820, and the plurality of first vertical wirings 820 connect the plurality of first horizontal wirings 840 to the plurality of second horizontal wirings 860. The second vertical inductor 802a on the right may include a plurality of third horizontal wirings 842, a plurality of fourth horizontal wirings 862, and a plurality of second vertical wirings 822, and the plurality of second vertical wirings 822 connect the plurality of third horizontal wirings 842 to the plurality of fourth horizontal wirings 862.

[0124] The first vertical inductor 801a and the second vertical inductor 802a may respectively include a first terminal E1 and a second terminal E2, but are not limited thereto.

[0125] As Figure 12A and Figure 12B shown, in some example embodiments, the first vertical inductor 801a and the second vertical inductor 802a may share a terminal and form a three-terminal dual vertical inductor having a first terminal E1, a second terminal E2, and a common terminal E3, but the example embodiments are not limited thereto.

[0126] In some example embodiments, Figure 12A and Figure 12B the dual vertical inductor shown may be used in an RF circuit that "uses a differential signal as an input and / or uses a differential signal as an output", but is not limited thereto. For example, a constant voltage may be applied to the common terminal E3, and a differential signal may be applied to and / or generated from the first terminal E1 and / or the second terminal E2. In addition, since the dual vertical inductor provides a high ratio of inductance L to resistance, the dual vertical inductor may have an excellent Q factor and may thus be used as an inductance providing element for high-performance and / or high-efficiency RF circuits, etc.

[0127] Next, as an example of an RF communication circuit including a vertical inductor, a voltage-controlled oscillator (VCO) can be provided. The VCO or VCO circuit is an important building block in a communication system. The VCO circuit can include an LC block and can generate a signal oscillating at a resonant frequency. The LC block includes an inductor and a capacitor, and the resonant frequency can be adjusted according to and / or based on a desired frequency. To adjust the resonant frequency, the inductor and / or the capacitor can be variably adjusted to match the reactance magnitude of the inductance and / or the reactance magnitude of the capacitance. In addition, the resistance loss can be compensated by installing an amplifier or the like in the LC circuit.

[0128] Figure 13 is a circuit diagram of a VCO including a vertical inductor according to at least one example embodiment. Unless otherwise specified, Figure 13 the transistors shown in are n-type (or n-channel) transistors, but the example embodiments are not limited thereto.

[0129] Referring to Figure 13 , the VCO circuit can include the dual vertical inductor IND described above with reference to the accompanying drawings, but is not limited thereto. More specifically, the dual vertical inductor IND can include a first vertical inductor L1 and a second vertical inductor L2. The power supply voltage Vdd can be applied to a common node a, and a first capacitor C1 and a second capacitor C2 can be connected to the remaining nodes b and c respectively, but the example embodiments are not limited thereto. For example, the dual vertical inductor IND can use the symmetric dual vertical inductor described above with reference to Figure 12A and Figure 12B described, but is not limited thereto.

[0130] Node b can be connected to the drain of the first capacitor C1 and the first transistor T1, and node c can be connected to the drain of the second capacitor C2 and the second transistor T2, etc. In addition, node b can be connected to the gate of the second transistor T2, node c can be connected to the gate of the first transistor T1, and the voltages of node b and node c can control the outputs of the opposite transistors mutually.

[0131] The first capacitor C1 and / or the second capacitor C2 can include a variable capacitor (for example, the first capacitor C1 and / or the second capacitor C2 can be a variable capacitor, etc.). One end of the first capacitor C1 can be connected to node b, and one end of the second capacitor C2 can be connected to node c. In addition, the first capacitor C1 and the second capacitor C2 can be connected in series between node b and node c.

[0132] The drain of the first transistor T1 can be connected to the first vertical inductor L1 and the first capacitor C1, and the drain of the second transistor T2 can be connected to the second vertical inductor L2 and the second capacitor C2. The sources of the first transistor T1 and the second transistor T2 are connected to node f to form a common source.

[0133] In addition, in order to supply a stable current, a current source CS that provides a constant current may be provided, and a current mirror connected to the current source CS may be provided, but the exemplary embodiments are not limited thereto. For example, a node e corresponding to the gate of a third transistor T3 connected to the current source CS may be connected to a terminal d corresponding to the drain of the third transistor T3. The drain of a fourth transistor T4 having a source connected to the ground GND may be connected to the node f. Next, the gate of the fourth transistor T4 may be connected to the node e (i.e., the gate of the third transistor T3). As disclosed herein, various types of RF circuits including vertical inductors may be provided.

[0134] Although various exemplary embodiments of the inventive concept have been specifically shown and described above, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended inventive concept.

Claims

1. A three-dimensional inductor, comprising: substrate; as well as At least one spirochete, the at least one spirochete comprising: a plurality of first horizontal wirings on the upper surface of the substrate; a plurality of second horizontal wirings on the back surface of the substrate; and Multiple vertical wiring lines, The plurality of vertical wirings are connected to the plurality of first horizontal wirings and the plurality of second horizontal wirings.

2. The three-dimensional inductor according to claim 1, wherein: The plurality of first horizontal wirings are at the same vertical level; and The plurality of first horizontal wirings are at least partially parallel to each other.

3. The three-dimensional inductor according to claim 1, wherein: The plurality of second horizontal wirings are at the same vertical level; and The plurality of second horizontal wirings are at least partially parallel to each other.

4. The three-dimensional inductor according to claim 1, wherein: The plurality of vertical wirings have the same length and are parallel to each other.

5. The three-dimensional inductor according to claim 1, wherein: The plurality of first horizontal wirings include ultra-thick metal.

6. The three-dimensional inductor according to claim 1, wherein: Each of the plurality of first horizontal wirings and each of the plurality of second horizontal wirings includes a connection portion connected to one of the plurality of vertical wirings and a wiring portion connected to the connection portion; and The connection portion has a width greater than a width of the wiring portion.

7. The three-dimensional inductor according to claim 1, wherein: The plurality of second horizontal wirings include a backside metal.

8. The three-dimensional inductor according to any one of claims 1 to 7, wherein: Each of the plurality of vertical wirings includes a through-silicon via; and Each of the plurality of through-silicon vias passes through the substrate.

9. The three-dimensional inductor according to any one of claims 1 to 7, wherein: The substrate also includes: at least one insulating isolation region; and The plurality of vertical wirings pass through the at least one insulating isolation region.

10. A three-dimensional inductor, comprising: a plurality of substrates, including a first substrate and a second substrate stacked on each other, the first substrate being at an uppermost position of the plurality of substrates, and the second substrate being at a lowermost position of the plurality of substrates, a rear surface of the first substrate being adjacent to a rear surface of the second substrate; as well as At least one spirochete, the at least one spirochete comprising: Two terminals; a plurality of first horizontal wirings on the front surface of the first substrate; a plurality of second horizontal wirings on the front surface of the second substrate; and A plurality of vertical wirings extend in a vertical direction, and the plurality of vertical wirings are connected to the plurality of first horizontal wirings and the plurality of second horizontal wirings.

11. The three-dimensional inductor according to claim 10, wherein: The plurality of first horizontal wirings are at the same vertical level; The plurality of first horizontal wirings are at least partially parallel to each other; The plurality of second horizontal wirings are at the same vertical level; The plurality of second horizontal wirings are at least partially parallel to each other; and The plurality of vertical wirings have the same length.

12. The three-dimensional inductor according to claim 10, wherein: The two terminals are respectively connected to two different first horizontal wirings among the plurality of first horizontal wirings.

13. The three-dimensional inductor according to claim 10, wherein: The two terminals are respectively connected to two different second horizontal wirings among the plurality of second horizontal wirings.

14. The three-dimensional inductor according to any one of claims 10 to 13, wherein: Each of the plurality of vertical wirings includes a plurality of vertical wiring segments extending in a vertical direction.

15. The three-dimensional inductor according to claim 14, wherein: Each of the plurality of vertical wiring segments includes a through-silicon via that passes through the first substrate.

16. The three-dimensional inductor according to claim 14, further comprising: At least one micro bump connects two of the plurality of vertical wiring segments to each other.

17. The three-dimensional inductor according to claim 14, wherein: The plurality of vertical wiring segments are connected to each other by hybrid copper bonding.

18. The three-dimensional inductor according to claim 14, wherein: The plurality of first horizontal wirings and the plurality of second horizontal wirings include ultra-thick metal.

19. A multi-chip package, comprising: a plurality of substrates, including a first substrate and a second substrate stacked on each other, the first substrate being at an uppermost position of the plurality of substrates, and the second substrate being at a lowermost position of the plurality of substrates, a rear surface of the first substrate being adjacent to a rear surface of the second substrate; A three-dimensional inductor comprising at least one spiral body, the at least one spiral body comprising two terminals, a plurality of first horizontal wirings, a plurality of second horizontal wirings, and a plurality of vertical wirings, the plurality of first horizontal wirings being on a front surface of a first substrate, the plurality of second horizontal wirings being on a front surface of a second substrate, and the plurality of vertical wirings being connected to the plurality of first horizontal wirings and the plurality of second horizontal wirings, the plurality of vertical wirings extending in a vertical direction; as well as A motherboard is provided on which the plurality of substrates and the three-dimensional inductor are mounted.

20. The multi-chip package of claim 19, further comprising: At least one interposer is bonded to the plurality of substrates.

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