Preparation method of MOS device

Abstract

The invention provides a preparation method of a metal oxide semiconductor (MOS) device, which comprises the following steps of: firstly, providing a substrate, forming a gate oxide layer on one side of the substrate, then injecting deuterium plasma or fluorine plasma between the substrate and the gate oxide layer by adopting a decoupling plasma injection method, and finally, carrying out annealing treatment. The deuterium plasma or the fluorine plasma is bonded with silicon between the substrate and the gate oxide layer to generate a silicon-deuterium bond or a silicon-fluorine bond with higher bond energy; according to the decoupling plasma injection method, the injection depth and the injection amount of the deuterium plasma or the fluorine plasma can be well controlled, annealing treatment is performed after the deuterium plasma or the fluorine plasma is injected, and deuterium or fluorine can replace hydrogen to form a silicon-deuterium bond or a silicon-fluorine bond with the silicon between the substrate and the gate oxide layer, and the bond energy of the silicon-deuterium bond or the silicon-fluorine bond is larger than that of a silicon-hydrogen bond. And silicon-hydrogen bond fracture and hydrogen diffusion at the interface of the gate oxide layer and the substrate are improved, so that the negative bias temperature instability effect of the MOS device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more particularly to a method for manufacturing a MOS device. Background Art

[0002] With the increasing integration of semiconductor integrated circuit devices, the requirements for transistor performance are also increasing day by day. In addition, the requirements for transistor reliability are also increasing accordingly.

[0003] Complementary Metal Oxide Semiconductor (CMOS) devices include Negative channel Metal Oxide Semiconductor (NMOS) devices and positive channel Metal Oxide Semiconductor (PMOS) devices. The reliability problems of MOS devices mainly stem from various failure mechanisms of the gate oxide layer. Among them, the negative bias temperature instability (NBTI) effect has a particularly significant impact on the reliability of PMOS devices.

[0004] Currently, the physical size of MOS devices is continuously decreasing, but the operating voltage does not decrease with the reduction of the physical size dimension, resulting in an increase in the electric field stress of MOS devices, thereby exacerbating the negative bias temperature instability effect. The negative bias temperature instability effect is generally considered to be caused by the breaking of silicon-hydrogen bonds and hydrogen diffusion at the interface between the gate oxide layer and the silicon substrate. That is, when a MOS device is operating, the generated non-equilibrium carriers will collide with the silicon-hydrogen bonds, causing the silicon-hydrogen bonds to break, thereby generating the negative bias temperature instability effect. In the prior art solutions, fluorine is introduced at the interface between the gate oxide layer and the silicon substrate, so that fluorine replaces hydrogen to form a silicon-fluorine bond with higher bond energy with silicon at the interface, thereby repairing the charge at the interface between the gate oxide layer and the silicon substrate, reducing the trap charges at the interface between the gate oxide layer and the silicon substrate, and achieving the improvement of the negative bias temperature instability. Among them, fluorine can be injected by ion implantation when the source / drain region is lightly doped. However, in the existing process of ion implanting fluorine, fluorine is implanted in the source / drain region and then diffuses to the interface in the form of thermal diffusion. Since thermal diffusion is multi-directional, it is difficult to control the dose of fluorine at the interface. Therefore, the current process of implanting fluorine has limited improvement effect on the negative bias temperature instability characteristics, especially in deep sub-micron processes, the improvement effect on the negative bias temperature instability is not obvious.

[0005] Based on this, the present invention provides a method for manufacturing a MOS device to solve the above problems. Summary of the Invention

[0006] In view of this, to solve the above problems, the present invention provides a method for manufacturing a MOS device, and the technical solution is as follows:

[0007] A method for manufacturing a MOS device, comprising:

[0008] Providing a substrate;

[0009] Forming a gate oxide layer on one side of the substrate;

[0010] Injecting deuterium plasma or fluorine plasma between the substrate and the gate oxide layer by using a decoupled plasma injection method;

[0011] Performing an annealing treatment; wherein, the deuterium plasma or the fluorine plasma is used to bond with the silicon between the substrate and the gate oxide layer.

[0012] Optionally, in the above method for manufacturing a MOS device, the providing a substrate includes:

[0013] Providing a substrate having a well region, a first isolation trench, and a second isolation trench; the well region is located between the first isolation trench and the second isolation trench.

[0014] Optionally, in the above method for manufacturing a MOS device, the injecting deuterium plasma or fluorine plasma between the substrate and the gate oxide layer by using a decoupled plasma injection method includes:

[0015] Introducing deuterium gas or fluorine gas into a decoupled plasma device;

[0016] Performing a plasma treatment on the deuterium gas or the fluorine gas to form the deuterium plasma or the fluorine plasma;

[0017] Injecting the deuterium plasma or the fluorine plasma between the substrate and the gate oxide layer.

[0018] Optionally, in the above method for manufacturing a MOS device, the power range during the injection of deuterium plasma or fluorine plasma between the substrate and the gate oxide layer is 500W - 1500W.

[0019] Optionally, in the above method for manufacturing a MOS device, the temperature range during the annealing treatment is 600°C - 1000°C.

[0020] Optionally, in the method for manufacturing the MOS device described above, the pressure range during the annealing process is 5 torr - 50 torr.

[0021] Optionally, in the method for manufacturing the MOS device described above, a mixed gas of oxygen and nitrogen is introduced during the annealing process.

[0022] Optionally, in the method for manufacturing the MOS device described above, providing the substrate having a well region, a first isolation trench, and a second isolation trench includes:

[0023] Providing a silicon substrate;

[0024] On one side of the silicon substrate, a first groove and a second groove are formed on one side of the substrate by an etching process;

[0025] The bottom surface and side walls of the first groove and the second groove are oxidized by an in-situ growth method to form a first silicon oxide layer;

[0026] A second silicon oxide layer is deposited in the first groove and the second groove by a chemical vapor deposition method;

[0027] An annealing process is performed to form the first isolation trench and the second isolation trench.

[0028] Optionally, in the method for manufacturing the MOS device described above, providing the substrate having a well region, a first isolation trench, and a second isolation trench further includes:

[0029] A well region is formed between the first isolation trench and the second isolation trench by an ion implantation method.

[0030] Optionally, in the method for manufacturing the MOS device described above, forming a gate oxide layer on one side of the substrate includes:

[0031] A gate oxide layer is formed on one side of the substrate by an in-situ growth method, or an atomic layer deposition method, or a thermal oxidation method, wherein the gate oxide layer exposes the first isolation trench and the second isolation trench.

[0032] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0033] The present invention provides a method for manufacturing a MOS device. First, a substrate is provided, and a gate oxide layer is formed on one side of the substrate. Then, a decoupled plasma injection method is used to inject deuterium plasma or fluorine plasma between the substrate and the gate oxide layer. Finally, an annealing treatment is performed to bond the deuterium plasma or fluorine plasma with the silicon between the substrate and the gate oxide layer, generating a silicon-deuterium bond or a silicon-fluorine bond with a greater bond energy. The decoupled plasma injection method can well control the injection depth and injection amount of the deuterium plasma or fluorine plasma, thereby well controlling the injection concentration of the deuterium plasma or fluorine plasma. After injecting the deuterium plasma or fluorine plasma and performing the annealing treatment, deuterium or fluorine can replace hydrogen to form a silicon-deuterium bond or a silicon-fluorine bond with a greater bond energy than the silicon-hydrogen bond with the silicon between the substrate and the gate oxide layer, improving the breakage of the silicon-hydrogen bond and hydrogen diffusion at the interface between the gate oxide layer and the substrate, thereby improving the negative bias temperature instability effect of the MOS device and enhancing the device lifetime. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0035] Figure 1 It is a partial flowchart of a method for manufacturing a MOS device provided for an embodiment of the present invention;

[0036] Figure 2 It is a partial structural diagram of a MOS device provided for an embodiment of the present invention;

[0037] Figure 3 It is a partial flowchart of another method for manufacturing a MOS device provided for an embodiment of the present invention;

[0038] Figure 4 It is a partial structural diagram of another MOS device provided for an embodiment of the present invention;

[0039] Figure 5 It is a partial structural diagram of yet another MOS device provided for an embodiment of the present invention;

[0040] Figure 6 It is a partial structural diagram of yet another MOS device provided for an embodiment of the present invention;

[0041] Figure 7 It is a partial structural diagram of yet another MOS device provided for an embodiment of the present invention;

[0042] Figure 8Another partial structural schematic diagram of a MOS device provided for the implementation of the present invention;

[0043] Figure 9 Another partial process schematic diagram of a manufacturing method of a MOS device provided for the implementation of the present invention;

[0044] Figure 10 Another partial structural schematic diagram of a MOS device provided for the implementation of the present invention. Detailed implementation manners

[0045] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] Based on the content in the background technology, in the current MOS device manufacturing process, in order to increase the dielectric constant of the gate and reduce the gate leakage current, nitrogen oxides need to be formed in the gate oxide layer. Among them, injecting nitrogen into the gate oxide layer using decoupled plasma can well control the injection depth of nitrogen, achieve a relatively high injection concentration, and the injection amount is easy to adjust. In addition, the decoupled plasma also has the advantages of low ion energy and avoiding damage to the gate oxide layer.

[0047] Based on this, the present invention provides a manufacturing method of a MOS device. First, a substrate is provided, and a gate oxide layer is formed on one side of the substrate. Then, the method of injecting decoupled plasma is used to inject deuterium plasma or fluorine plasma between the substrate and the gate oxide layer. Finally, an annealing treatment is performed to bond the deuterium plasma or fluorine plasma with the silicon between the substrate and the gate oxide layer, generating a silicon-deuterium bond or a silicon-fluorine bond with a greater bond energy; the method of injecting decoupled plasma can well control the injection depth and injection amount of the deuterium plasma or fluorine plasma, thereby well controlling the injection concentration of the deuterium plasma or fluorine plasma. After injecting the deuterium plasma or fluorine plasma and performing the annealing treatment, deuterium or fluorine can replace hydrogen to form a silicon-deuterium bond or a silicon-fluorine bond with a greater bond energy than the silicon-hydrogen bond with the silicon between the substrate and the gate oxide layer, improving the breakage of the silicon-hydrogen bond and hydrogen diffusion at the interface between the gate oxide layer and the substrate, thereby improving the negative bias temperature instability effect of the MOS device and enhancing the device life.

[0048] Moreover, the method of decoupled plasma can avoid damage to the gate oxide layer, so that the injected deuterium plasma or fluorine plasma can well replace the hydrogen in the silicon-hydrogen bond between the gate oxide layer and the substrate, generating a silicon-deuterium bond or a silicon-fluorine bond with a greater bond energy.

[0049] To make the above objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] Reference Figure 1 , Figure 1 is a partial process schematic diagram of a method for manufacturing a MOS device provided in an embodiment of the present invention; reference Figure 2 , Figure 2 is a partial structural schematic diagram of a MOS device provided in an embodiment of the present invention; the method for manufacturing the MOS device includes:

[0051] S101: Provide a substrate 01.

[0052] Optionally, in another embodiment of the present invention, the providing a substrate 01 includes:

[0053] Provide a substrate 01 having a well region 02, a first isolation trench 03, and a second isolation trench 03; the well region 02 is located between the first isolation trench 03 and the second isolation trench 03.

[0054] Optionally, reference Figure 3 , Figure 3 is a partial process schematic diagram of another method for manufacturing a MOS device provided in an embodiment of the present invention; reference Figure 4 , Figure 4 is a partial structural schematic diagram of another MOS device provided in an embodiment of the present invention; reference Figure 5 , Figure 5 is a partial structural schematic diagram of yet another MOS device provided in an embodiment of the present invention; reference Figure 6 , Figure 6 is a partial structural schematic diagram of yet another MOS device provided in an embodiment of the present invention; reference Figure 7 , Figure 7 is a partial structural schematic diagram of yet another MOS device provided in an embodiment of the present invention; in another embodiment of the present invention, the providing a substrate 01 having a well region 02, a first isolation trench 03, and a second isolation trench 03 includes:

[0055] S201: Provide a silicon substrate 011.

[0056] S202: On one side of the silicon substrate 011, use an etching process to form a first groove 012 and a second groove 013 on one side of the substrate.

[0057] S203: Use an in-situ growth method to oxidize the bottom surface and side walls of the first groove 012 and the second groove 013 to form a first silicon oxide layer 014.

[0058] S204: Deposit a second silicon oxide layer in the first groove 012 and the second groove 013 by chemical vapor deposition.

[0059] S205: Perform annealing treatment to form the first isolation trench 03 and the second isolation trench 03.

[0060] Specifically, as Figure 4 shown, first provide a silicon substrate 011. As Figure 5 shown, use an etching process on the silicon substrate 011 to etch out the first groove 012 and the second groove 013. It should be noted that no specific limitation is imposed on the etching process. For example, dry etching can be used for etching, and wet cleaning will also be used after dry etching to remove some polymer impurities generated during the dry etching process. It should be noted that the first groove 012 and the second groove 013 are spaced apart and located on the same side of the silicon substrate 011.

[0061] As Figure 6 shown, after etching out the first groove 012 and the second groove 013, use an in-situ growth method to oxidize the bottom surface and side walls of the first groove 012 and the second groove 013. That is to say, oxidize the silicon substrate 011 near the bottom surface and side walls to generate a first silicon oxide layer 014. As Figure 7 shown, continue to deposit silicon oxide in the first groove 012 and the second groove 013 by chemical vapor deposition to form a second silicon oxide layer. Use annealing treatment to compact the deposited second silicon oxide layer to obtain the first isolation trench 03 and the second isolation trench 04. It should be noted that the second silicon oxide layer formed in the first groove 012 is the first isolation trench 03, and the second silicon oxide layer formed in the second groove 013 is the second isolation trench 04, and the silicon oxide in the first isolation trench 03 and the second isolation trench 04 will be slightly higher than the silicon substrate 011. It should also be noted that both the first isolation trench 03 and the second isolation trench 04 can be shallow trench isolation (STI for short).

[0062] Optionally, refer to Figure 8 , Figure 8 which is a partial structural schematic diagram of another MOS device provided by an embodiment of the present invention; in another embodiment of the present invention, the provided substrate 01 having a well region 02, a first isolation trench 03, and a second isolation trench 03 further includes:

[0063] A well region 02 is formed between the first isolation trench 03 and the second isolation trench 04 by ion implantation.

[0064] Specifically, the well region 02 is doped by ion implantation. When doping, the well region 02 can be P-type doped or N-type doped to ensure the fabrication of MOS devices. When the well region 02 is P-type doped, the fabricated MOS device is a PMOS device; when the well region 02 is N-type doped, the fabricated MOS device is an NMOS device. No specific limitation is made.

[0065] S102: Form a gate oxide layer 05 on one side of the substrate 01.

[0066] In this step, after forming the substrate 01 as shown in Figure 8 ; continue to form a gate oxide layer 05 on the side of the substrate 01 where the first isolation trench 03 and the second isolation trench 04 are provided.

[0067] Optionally, in another embodiment of the present invention, forming the gate oxide layer 05 on one side of the substrate 01 includes:

[0068] Forming the gate oxide layer 05 on one side of the substrate 01 by using an in-situ growth method, or an atomic layer deposition method, or a thermal oxidation method; wherein, the gate oxide layer 05 exposes the first isolation trench 03 and the second isolation trench 04.

[0069] It should be noted that no specific limitation is made on the growth method of the gate oxide layer 05, including but not limited to methods such as in-situ growth method, or atomic layer deposition method, or thermal oxidation method. For example, using the method of in-situ steam generation (In-Situ Steam Generation, abbreviated as ISSG), or the method of ALD atomic layer deposition, or the method of dry oxygen oxidation RTO, etc. Usually, the ISSG method is more applied in production and manufacturing.

[0070] Based on the MOS device with the above structure, the non-equilibrium carriers generated during device operation will collide with the silicon-hydrogen bonds formed at the interface between the substrate 01 and the gate oxide layer 05, causing the silicon-hydrogen bonds to break or hydrogen diffusion to occur, thereby generating the negative bias temperature instability effect. Based on this, the present invention adopts a new method to form bonds with a higher bond energy than the silicon-hydrogen bonds, which will be described below.

[0071] S103: Inject deuterium plasma or fluorine plasma between the substrate 01 and the gate oxide layer 05 by using a decoupled plasma implantation method.

[0072] Optionally, refer to Figure 9 , Figure 9 which is a partial process schematic diagram of another method for fabricating a MOS device provided by an embodiment of the present invention; refer to Figure 10 , Figure 10Partial structural schematic diagram of another MOS device provided for the implementation of the present invention; in another embodiment of the present invention, the method of injecting deuterium plasma or fluorine plasma by decoupled plasma implantation into the space between the substrate 01 and the gate oxide layer 05 includes:

[0073] S301: Introduce deuterium gas or fluorine gas into the decoupled plasma equipment.

[0074] S302: Perform plasma treatment on the deuterium gas or the fluorine gas to form the deuterium plasma or the fluorine plasma.

[0075] S303: Inject the deuterium plasma or the fluorine plasma into the space between the substrate 01 and the gate oxide layer 05.

[0076] Specifically, the deuterium plasma or the fluorine plasma is derived from deuterium gas or fluorine gas. To incorporate deuterium or fluorine into silicon oxide, it is basically impossible for individual gas molecules at room temperature. This requires plasma treatment of the gas molecules. Deuterium gas or fluorine gas is introduced into the decoupled plasma equipment, and the radio frequency generator in the decoupled plasma equipment will perform plasma treatment on the deuterium gas or the fluorine gas to form deuterium plasma or fluorine plasma. As Figure 10 shown, the deuterium plasma or the fluorine plasma can be injected in the direction from the gate oxide layer 05 towards the substrate 01.

[0077] Optionally, in another embodiment of the present invention, the power range during the injection of deuterium plasma or fluorine plasma between the substrate 01 and the gate oxide layer 05 is 500W - 1500W.

[0078] It should be noted that the power range used during the injection of deuterium plasma or fluorine plasma is 500W - 1500W, including the endpoint values. For example, the power range used during the injection of deuterium plasma or fluorine plasma can be 800W or 900W, etc., without specific limitations, and can be adjusted considering other factors during injection.

[0079] It should also be noted that the method of decoupling plasma incorporates deuterium plasma or fluorine plasma under the condition of no photoresist. The incorporated deuterium plasma or fluorine plasma acts on the entire wafer. However, the position where the incorporated deuterium plasma or fluorine plasma takes effect is the gate oxide layer 05, because deuterium plasma or fluorine plasma cannot be injected at the first isolation trench 03 and the second isolation trench 04 during injection, or even if deuterium plasma or fluorine plasma is injected, it will not affect the performance of the device. It should be noted that the thickness or depth of introducing deuterium plasma or fluorine plasma on the surface of the gate oxide layer 05 is approximately between the gate oxide layer 05 and the substrate 01, and it can be near the interface between the gate oxide layer 05 and the substrate 01. That is to say, it can also be within the gate oxide layer 05, and no specific limitation is made.

[0080] S104: Perform annealing treatment.

[0081] Wherein, the deuterium plasma or the fluorine plasma is used to bond with the silicon between the substrate 01 and the gate oxide layer 05.

[0082] Optionally, in another embodiment of the present invention, the temperature range during the annealing treatment is 600°C - 1000°C.

[0083] Optionally, in another embodiment of the present invention, the pressure range during the annealing treatment is 5 torr - 50 torr.

[0084] Optionally, in another embodiment of the present invention, a mixed gas of oxygen and nitrogen is introduced during the annealing treatment.

[0085] Specifically, after the injection of deuterium plasma or fluorine plasma, the deuterium plasma or fluorine plasma cannot directly bond with the silicon in the silicon oxide and needs to be heat-treated, that is, annealed. The temperature range during the annealing process is 600°C - 1000°C, including the end values. For example, the temperature during the annealing process can be 700°C or 800°C, etc.; the pressure range during the annealing treatment is 5 torr - 50 torr, including the end values. For example, the pressure during the annealing treatment can be 6 torr or 20 torr, etc.; a mixed gas of oxygen and nitrogen is introduced during the annealing treatment. It should be noted that the flow rates of oxygen and nitrogen can be 0.1 slm for O2 and 5 slm for N2, etc. It should be noted that the parameters during annealing are related to factors such as the thickness, film quality, deuterium doping concentration, depth of the gate oxide layer 05, and are also related to the requirements for device performance, so no specific limitation is made.

[0086] During annealing, deuterium plasma or fluorine plasma undergoes thermal diffusion and reaches the interface between the gate oxide layer 05 and the substrate 01. At this time, the deuterium plasma replaces the hydrogen in the silicon-hydrogen bond at the interface between the gate oxide layer 05 and the substrate 01 to form a silicon-deuterium bond. The bond energy of the silicon-deuterium bond is greater than that of the silicon-hydrogen bond. Therefore, during device operation, the breakage of the silicon-deuterium bond or hydrogen diffusion is not likely to occur, thus reducing the occurrence of the negative bias temperature instability effect. Similarly, the fluorine plasma replaces the hydrogen in the silicon-hydrogen bond at the interface between the gate oxide layer 05 and the substrate 01 to form a silicon-fluorine bond. The bond energy of the silicon-fluorine bond is greater than that of the silicon-hydrogen bond. Therefore, during device operation, the breakage of the silicon-fluorine bond or hydrogen diffusion is not likely to occur, thus reducing the occurrence of the negative bias temperature instability effect.

[0087] After annealing, the subsequent structure of the MOS device is continued to be constructed. The construction of the subsequent structure is the same as that in the prior art, so it will not be elaborated here.

[0088] It should be noted that the annealing can also be carried out after growing the subsequent structure. For example, after injecting deuterium plasma or fluorine plasma, hafnium dioxide is deposited on the side of the gate oxide layer 05 away from the substrate 01 and gate nitridation is carried out during the growth of the subsequent structure. At this time, annealing is also required, and this annealing can also be directly used to complete the bonding of deuterium plasma or fluorine plasma with silicon at the interface between the gate oxide layer 05 and the substrate 01. That is to say, one annealing process can be omitted, thus saving the process flow and thermal budget of MOS device fabrication.

[0089] The present invention adopts the method of decoupled plasma injection to introduce deuterium plasma or fluorine plasma between the substrate 01 and the gate oxide layer 05. Through annealing, the deuterium plasma or fluorine plasma diffuses to the interface between the substrate 01 and the gate oxide layer 05, so that deuterium or fluorine replaces the silicon-hydrogen bond at the interface between the substrate 01 and the gate oxide layer 05, generating a silicon-deuterium bond or a silicon-fluorine bond with a greater bond energy, and improving the problem of negative bias temperature instability of the MOS device caused by the breakage of the silicon-hydrogen bond and hydrogen diffusion at the interface between the gate oxide layer 05 and the substrate 01.

[0090] It should be noted that the present invention has a better improvement effect on the problem of negative bias temperature instability of PMOS devices.

[0091] The preparation method of a MOS device provided by the present invention has been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. At the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation of the present invention.

[0092] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0093] It should also be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements also includes the elements inherent to these processes, methods, articles or devices, or further includes elements inherent to these processes, methods, articles or devices. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0094] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a MOS device, characterized in that, Comprising: Providing a substrate; Forming a gate oxide layer on one side of the substrate; Injecting deuterium plasma or fluorine plasma between the substrate and the gate oxide layer by means of decoupled plasma implantation; Performing annealing treatment; wherein, the deuterium plasma or the fluorine plasma is used to bond with silicon between the substrate and the gate oxide layer.

2. The manufacturing method of the MOS device according to claim 1, characterized in that, The providing a substrate comprises: Providing the substrate having a well region, a first isolation trench and a second isolation trench; the well region is located between the first isolation trench and the second isolation trench.

3. The manufacturing method of the MOS device according to claim 2, characterized in that, The injecting deuterium plasma or fluorine plasma between the substrate and the gate oxide layer by means of decoupled plasma implantation comprises: Introducing deuterium gas or fluorine gas into a decoupled plasma device; Performing plasma treatment on the deuterium gas or the fluorine gas to form the deuterium plasma or the fluorine plasma; Injecting the deuterium plasma or the fluorine plasma between the substrate and the gate oxide layer.

4. The manufacturing method of the MOS device according to claim 1, characterized in that, The power range during the process of injecting deuterium plasma or fluorine plasma between the substrate and the gate oxide layer is 500W - 1500W.

5. The manufacturing method of the MOS device according to claim 1, characterized in that, The temperature range during the annealing treatment process is 600°C - 1000°C.

6. The manufacturing method of the MOS device according to claim 1, characterized in that, The pressure range during the annealing treatment process is 5 torr - 50 torr.

7. The manufacturing method of the MOS device according to claim 1, wherein A mixed gas of oxygen and nitrogen is introduced during the annealing treatment process.

8. The manufacturing method of the MOS device according to claim 2, characterized in that, The providing the substrate having a well region, a first isolation trench and a second isolation trench comprises: Providing a silicon substrate; On one side of the silicon substrate, forming a first groove and a second groove on one side of the substrate by means of an etching process; Performing oxidation treatment on the bottom surface and side walls of the first groove and the second groove by means of in-situ growth to form a first silicon oxide layer; Depositing a second silicon oxide layer in the first groove and the second groove by means of chemical vapor deposition; Performing annealing treatment to form the first isolation trench and the second isolation trench.

9. The manufacturing method of the MOS device according to claim 2, characterized in that, The providing the substrate having a well region, a first isolation trench and a second isolation trench further comprises: Forming a well region between the first isolation trench and the second isolation trench by means of ion implantation.

10. The manufacturing method of the MOS device according to claim 2, characterized in that, The forming a gate oxide layer on one side of the substrate comprises: Forming a gate oxide layer on one side of the substrate by means of in-situ growth method, or atomic layer deposition method, or thermal oxidation method, wherein the gate oxide layer exposes the first isolation trench and the second isolation trench.

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