Calculation chip, calculation method, calculation device, storage medium and program product

Abstract

The embodiment of the invention discloses a computing chip, a computing method, a computing device, a storage medium and a program product. The computing chip comprises a computing core, the computing core comprises an arithmetic logic unit, the arithmetic logic unit comprises a first storage unit and a computing unit, and data circulation exists between the computing unit and the first storage unit in the fusion computing process. According to the technical scheme, the fusion calculation efficiency can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of data processing, and in particular, to a computing chip, a computing method, a computing device, a storage medium, and a program product. Background Art

[0002] In high-performance computing scenarios, the hardware architecture design of computing chips is crucial for achieving high-performance computing. Currently, relevant personnel often use computing chips for the fusion calculation of multiple data.

[0003] In the process of implementing the present invention, the inventors found the following technical problems in the prior art: the fusion calculation efficiency is relatively low (that is, the fusion calculation performance is not good), which needs to be solved urgently. Summary of the Invention

[0004] Embodiments of the present invention provide a computing chip, a computing method, a computing device, a storage medium, and a program product, which solve the problem of relatively low fusion calculation efficiency.

[0005] According to one aspect of the present invention, there is provided a computing chip, which may include a computing core. Among them, the computing core includes an arithmetic logic unit, and the arithmetic logic unit includes a first storage unit and a computing unit that has data flow with the first storage unit during the fusion calculation process.

[0006] According to another aspect of the present invention, there is provided a computing method, which is applied to a computing chip. The computing chip includes a computing core, the computing core includes an arithmetic logic unit, and the arithmetic logic unit includes a first storage unit and at least one computing unit. The computing method may include:

[0007] For the first data and the second data to be calculated and the first calculation flow instruction corresponding to the first data and the second data, through the first computing unit corresponding to the first calculation flow instruction in all the computing units, in response to the first calculation flow instruction, calculate the first data and the second data, so as to store the obtained intermediate calculation result into the first storage unit;

[0008] For the third data to be calculated with the first data and the second data and the second calculation flow instruction corresponding to the third data, through the second computing unit corresponding to the second calculation flow instruction in all the computing units, in response to the second calculation flow instruction, calculate the third data and the intermediate calculation result obtained from the first storage unit to obtain the target calculation result.

[0009] According to another aspect of the present invention, there is provided a computing device, which is configured in a computing chip. The computing chip includes a computing core, the computing core includes an arithmetic logic unit, and the arithmetic logic unit includes a first storage unit and at least one computing unit. The computing device may include:

[0010] A first calculation module, configured to calculate first data and second data for first data and second data to be calculated and a first calculation stream instruction corresponding to the first data and the second data, through a first calculation unit corresponding to the first calculation stream instruction among all calculation units, and in response to the first calculation stream instruction, and store the obtained intermediate calculation result into a first storage unit;

[0011] A second calculation module, configured to calculate third data to be calculated with the first data and the second data and a second calculation stream instruction corresponding to the third data, through a second calculation unit corresponding to the second calculation stream instruction among all calculation units, and in response to the second calculation stream instruction, calculate the third data and the intermediate calculation result obtained from the first storage unit to obtain a target calculation result.

[0012] According to another aspect of the present invention, there is provided a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to implement the calculation method provided by any embodiment of the present invention when executed by a processor.

[0013] According to another aspect of the present invention, there is provided a computer program product, on which a computer program is stored, and the computer program implements the calculation method provided by any embodiment of the present invention when executed by a processor.

[0014] The calculation chip described in the embodiments of the present invention includes a calculation core, wherein the calculation core includes an arithmetic logic unit, and the arithmetic logic unit includes a first storage unit and a calculation unit having data transfer with the first storage unit during the fusion calculation process. The above technical solution relies on the first storage unit in the arithmetic logic unit to implement the fusion calculation within the arithmetic logic unit, improving the fusion calculation efficiency.

[0015] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 is a structural block diagram of a calculation chip provided by an embodiment of the present invention;

[0018] Figure 2It is a structural block diagram of another computing chip provided according to an embodiment of the present invention;

[0019] Figure 3 It is an example diagram of the hardware architecture of another computing chip provided according to an embodiment of the present invention;

[0020] Figure 4 It is an example diagram of parallel computing of another computing chip provided according to an embodiment of the present invention;

[0021] Figure 5 It is a flowchart of a computing method provided according to an embodiment of the present invention;

[0022] Figure 6a It is a schematic diagram of the TensorCore computing process in a computing method provided according to an embodiment of the present invention;

[0023] Figure 6b It is a schematic diagram of the VerctorCore computing process in a computing method provided according to an embodiment of the present invention;

[0024] Figure 6c It is a schematic diagram of the TensorCore+VerctorCore fusion computing process in a computing method provided according to an embodiment of the present invention;

[0025] Figure 6d It is a schematic diagram of the VerctorCore+VerctorCore fusion computing process in a computing method provided according to an embodiment of the present invention;

[0026] Figure 7 It is a structural block diagram of a computing device provided according to an embodiment of the present invention. Detailed implementation manners

[0027] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The same is true for "target", "original", etc., which will not be elaborated here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0029] Figure 1 is a structural block diagram of a computing chip provided by an embodiment of the present invention. This embodiment is applicable to the case of fusion computing, especially applicable to the case where fusion computing is completed inside an arithmetic logic unit.

[0030] See Figure 1 , the computing chip described in the embodiment of the present invention includes: a computing core 1, where the computing core 1 includes an arithmetic logic unit 10, and the arithmetic logic unit 10 includes a first storage unit 101 and a computing unit 102 that has data flow with the first storage unit 101 during the fusion computing process.

[0031] Among them, the computing core 1 can be understood as the core for data computing. In the embodiment of the present invention, optionally, the number of the computing cores 1 can be one or more, especially multiple, to achieve parallel computing and improve computing performance. Additionally, optionally, the computing core 1 can also be referred to as a PCore.

[0032] For each computing core 1, the computing core 1 may include an arithmetic logic unit (ALU) 10. Among them, the ALU 10 can be understood as a unit for performing arithmetic and logical operations. In the embodiment of the present invention, optionally, the number of the ALU 10 can be one or more, especially multiple, to achieve parallel computing and improve computing performance.

[0033] For each ALU 10, the ALU 10 may include a first storage unit 101 and a computing unit 102 that has data flow with the first storage unit 101 during the fusion computing process. It should be noted that the data flowing here can be at least one of the original data to be calculated, the intermediate calculation result and the target calculation result obtained after calculating the original data, etc., especially the intermediate calculation result, so as to achieve fusion computing within the ALU 10 and improve the fusion computing performance.

[0034] Among them, the first storage unit 101 can be understood as a unit for data storage, and the data stored therein can be exactly the same or partially the same as the above-mentioned transferred data, and no specific limitation is made here.

[0035] The computing unit 102 can be understood as a unit for data computing. In the embodiments of the present invention, optionally, the number of the computing units 102 can be one or more, especially multiple, to achieve parallel computing and improve computing performance. In the case where there are multiple computing units 102, the multiple computing units 102 can be exactly the same, partially the same or completely different computing units. Exemplarily, at least some of the multiple computing units 102 can be applicable to computing one-dimensional data, and the one-dimensional data can be directed data (i.e., one-dimensional vector) or undirected data (i.e., one-dimensional scalar). On this basis, optionally, the computing unit 102 can be implemented by a vector computing core (VerctorCore). Of course, it can also be implemented by other cores, and no specific limitation is made here. Additionally, exemplarily, at least some of the multiple computing units 102 can be applicable to computing two-dimensional data and / or multi-dimensional data, that is, applicable to matrix computing, thereby ensuring matrix computing performance. On this basis, optionally, the computing unit 102 can be implemented by a tensor computing core (TensorCore). Of course, it can also be implemented by other cores, and no specific limitation is made here.

[0036] It should be noted that during the process of fusing and computing multiple data, it is necessary to first use a certain computing unit 102 to compute two of the multiple data to obtain an intermediate computing result, and then use a certain computing unit 102 to compute the intermediate computing result and another data among the multiple data except the two data. The two computing units 102 applied here can be the same or different, and no specific limitation is made here.

[0037] In the related solution, since the first storage unit 101 is not provided in the ALU 10, the intermediate computing result computed by a certain computing unit 102 needs to be transferred to a storage unit outside the ALU 10 for storage. Then, when using a certain computing unit 102 for computing again, the intermediate computing result needs to be transferred back into the ALU 10 for computing, which will lead to an overly long data transfer chain and thus affect the fusion computing efficiency.

[0038] Correspondingly, in the embodiments of the present invention, relying on the first storage unit 101 provided in the ALU 10, the intermediate computing result only needs to be transferred between the first storage unit 101 and the computing unit 102, without being transferred outside the ALU 10. That is, within the ALU 10, communication between the computing units 102 can be achieved to implement fusion computing, which makes the data transfer chain shorter and thus improves the fusion computing efficiency.

[0039] The computing chip described in the embodiments of the present invention includes a computing core. Among them, the computing core includes an arithmetic logic unit, and the arithmetic logic unit includes a first storage unit and a computing unit that has data flow with the first storage unit during the fusion computing process. The above technical solution relies on the first storage unit in the arithmetic logic unit to implement fusion computing within the arithmetic logic unit, improving the efficiency of fusion computing.

[0040] An optional technical solution is that the computing core may further include a second storage unit and a second control unit. Among them, the second control unit is used to perform data flow between the first storage unit and the second storage unit. The above technical solution realizes the effect of transferring the original data to be calculated into the ALU for calculation and transferring the finally obtained target calculation result out of the ALU after calculation.

[0041] Figure 2 It is a structural block diagram of another computing chip provided by the embodiments of the present invention. This embodiment is optimized based on the above technical solutions. In this embodiment, optionally, the number of computing units is at least two, and the arithmetic logic unit further includes a first control unit corresponding to each computing unit respectively. Among them, the first control unit is used to perform data flow between the corresponding computing unit and the first storage unit to achieve fusion computing. Among them, the explanations of the same or corresponding terms as those in the above embodiments will not be elaborated here.

[0042] Specifically, referring to Figure 2 , the computing chip described in this embodiment includes a computing core 2. Among them, the computing core 2 includes an arithmetic logic unit 20. The arithmetic logic unit 20 may include a first storage unit 201, at least two computing units 202 (two are taken as an example in the figure), and a first control unit 203 corresponding to each computing unit 202 respectively. Among them, the first control unit 203 is used to perform data flow between the corresponding computing unit 202 and the first storage unit 201 during the fusion computing process to achieve fusion computing.

[0043] Among them, for each computing unit 202, a first control unit 203 corresponding one-to-one to the computing unit 202 can be set within the arithmetic logic unit 20 (i.e., ALU20). The first control unit 203 can be used to perform data flow between the computing unit 202 and the first storage unit 201 during the fusion computing process to achieve fusion computing. For example, the original data or intermediate calculation result to be calculated can be transferred from the first storage unit 201 to the computing unit 202, and the calculated intermediate calculation result or target calculation result can be transferred from the computing unit 202 to the first storage unit 201 to achieve fusion computing.

[0044] It should be noted that if only one first control unit 203 is provided in the ALU 20, it means that data transfer can only occur between the first storage unit 201 and one computing unit 202 during the same time segment. Correspondingly, in the embodiments of the present invention, since each computing unit 202 is respectively provided with a corresponding first control unit 203, data transfer between the first storage unit 201 and each computing unit 202 can be performed in parallel during the same time segment, so that the data calculation processes of each computing unit 202 can be executed in parallel.

[0045] In the technical solution of the embodiments of the present invention, by respectively providing a corresponding first control unit for each computing unit within the arithmetic logic unit, parallel execution of the data calculation processes of each computing unit is achieved, thereby further improving the fusion calculation efficiency.

[0046] An alternative technical solution is that the computing core further includes a second storage unit and a second control unit, where the second control unit is used to perform data transfer between the first storage unit and the second storage unit.

[0047] Among them, a second storage unit and a second control unit are provided within the computing core. The second storage unit can be understood as a storage unit located outside the ALU within the computing core; the second control unit can be used to perform data transfer between the first storage unit and the second storage unit. For example, it can transfer the original data to be calculated from the second storage unit to the first storage unit, and transfer the calculated target calculation result from the first storage unit to the second storage unit, so as to implement the calculation process.

[0048] In the above technical solution, based on the first control unit, by providing a second control unit within the computing core, parallel execution of the data transfer process between the first storage unit and the second storage unit and the data calculation process of the computing unit is achieved, thereby further improving the fusion calculation efficiency.

[0049] On this basis, optionally, the computing chip may further include a third storage unit, where there is data transfer between the second storage unit and the third storage unit.

[0050] Among them, a third storage unit is provided within the computing chip and outside the computing core. The third storage unit can directly perform data transfer with the first storage unit, and there is no other storage unit between them. This means that there are only two levels of storage units within the computing core. Fewer levels of storage units can shorten the data transfer link and reduce communication latency, thereby further improving the fusion calculation efficiency.

[0051] On this basis, optionally, the computing chip further includes a third control unit, where the third control unit is used to perform data transfer between the second storage unit and the third storage unit.

[0052] Among them, a third control unit is arranged within the computing chip and outside the computing core. The third control unit is used to perform data transfer between the second storage unit and the third storage unit. For example, the original data to be calculated can be transferred from the third storage unit to the second storage unit, and the calculated target calculation result can be transferred from the second storage unit to the third storage unit, so as to implement the calculation process.

[0053] In the above technical solution, on the basis of the second control unit, by setting the third control unit, the parallel execution of the data transfer process between the first storage unit and the second storage unit and the data transfer process between the second storage unit and the third storage unit is realized, thereby further improving the fusion calculation efficiency.

[0054] Another option is that the bandwidth of the second storage unit is less than that of the first storage unit and greater than that of the third storage unit; and / or, the storage capacity of the second storage unit is less than that of the third storage unit and greater than that of the first storage unit.

[0055] Among them, since the first storage unit communicates with the computing unit, in order to ensure the computing efficiency, it can have a larger bandwidth; and / or, since it only needs to store data related to the computing unit, it can have a smaller storage capacity. The same applies to the second storage unit and the third storage unit, which will not be elaborated here.

[0056] On this basis, combined with the application scenarios that the embodiments of the present invention may involve, optionally, the third storage unit may be a Global Memory (GM), the second storage unit may be a First Level Cache (L1 Cache), and the first storage unit may be a Middle Level Cache (L2 Cache). Of course, each storage unit can also be implemented in other ways, which are not specifically limited here.

[0057] To better understand the hardware architecture of the computing chip described above as a whole, the following will give an exemplary description in combination with an example of the hardware architecture of a computing chip. Exemplarily, see Figure 3 :

[0058] a. One computing chip includes a Global Memory, 48 PCores (only 2 are shown in the figure), and third control units (TS1) corresponding to each PCore respectively;

[0059] b. One PCore includes an L1 Cache, four ALUs, and second control units (TS2) respectively corresponding to each ALU;

[0060] c. One ALU includes an L2 Cache, one TensorCore, one VectorCore, a first control unit (TS3) corresponding to the TensorCore, and a first control unit (TS4) corresponding to the VectorCore.

[0061] Specifically, for the computing units, they may include TensorCore and VertorCore. Among them, TensorCore can be used for calculations such as matrix multiplication and matrix addition; VerctorCore is used for calculations such as addition, subtraction, multiplication, division, derivative calculation, remainder calculation, and square root extraction of vectors and scalars. In this example, optionally, these computing units can be implemented based on the model.

[0062] For the storage units, they may include L1 Cache, L2 Cache, and GlobalMemory. Among them, L1 Cache and L2 Cache can also be collectively referred to as local memory (LocalMemory). These storage units can be used to store the original data to be calculated, the intermediate calculation results and target calculation results calculated, and model parameters, etc. The model parameters can be understood as calculation flow instructions for indicating what kind of calculations the computing units should perform. In this example, in terms of bandwidth size, L2 Cache > L1 Cache > GlobalMemory; in terms of storage capacity, GlobalMemory > L1 Cache > L2 Cache.

[0063] For the control units, including TS1, TS2, TS3, and TS4, they are mainly used to control the data flow instructions and calculation flow instructions during the calculation process of the computing chip, and control the transfer of various data required during the calculation process between the storage units and the computing units through instruction transfer. Specifically,

[0064] TS1 can be understood as a data flow instruction control unit, and the data flow instruction can include instructions for data transfer (i.e., transfer) from GlobalMemory to L1Cache or from L1 Cache to ClobalMemory;

[0065] TS2 can be understood as a data flow instruction control unit, and the data flow instruction can include instructions for data transfer from L1 Cache to L2Cache or from L2 Cache to L1 Cache;

[0066] TS3 can be understood as the TensorCore computing stream instruction control unit, which can control the TensorCore computing stream instructions (i.e., matrix computing stream instructions) to perform calculations on the TensorCore;

[0067] TS4 can be understood as the VerctorCore computing stream instruction control unit, which can control the VerctorCore computing stream instructions (i.e., vector / scalar computing stream instructions) to perform calculations on the VerctorCore.

[0068] In addition, to cooperate with the control work of the control unit, corresponding control queues can be created for each control unit in advance, that is, each control unit maintains a control queue, and the instructions in the control queue are executed sequentially, and the instructions in different control queues can be executed in parallel. Exemplarily,

[0069] The TS1 control unit corresponds to the control queue TS1_Queue, and TS1_Queue has InQue and DeQue methods. Among them, InQue is responsible for passing the data stream instructions from GlobalMemory to L1 Cache, or the data stream instructions from L1 Cache to GlobalMemory, into TS1_Queue; DeQue is responsible for TS1 to execute the data stream instructions to achieve data transfer from GlobalMemory to L1 Cache, or from L1 Cache to GlobalMemory.

[0070] The TS2 control unit corresponds to the control queue TS2_Queue, and TS2_Queue has InQue and DeQue methods. Among them, InQue is responsible for passing the data stream instructions from L1 Cache to L2 Cache, or the data stream instructions from L2 Cache to L1 Cache, into TS2_Queue; DeQue is responsible for executing the data stream instructions in TS2 to achieve data transfer from L1 Cache to L2 Cache, or from L2 Cache to L1 Cache.

[0071] The TS3 control unit corresponds to the control queue TS3_Queue, and TS3_Queue has InQue and DeQue methods. Among them, InQue is responsible for passing the matrix computing stream instructions into TS3_Queue; DeQue is responsible for executing the matrix computing stream instructions in the TensorCore and transmitting the obtained calculation results to the L2 Cache.

[0072] The TS4 control unit corresponds to a control queue TS4_Queue, and TS4_Queue has InQue and DeQue methods. Among them, InQue is responsible for passing vector / scalar computation flow instructions into the queue; DeQue is responsible for executing the vector / scalar computation flow instructions in the VerctorCore and transmitting the computation results to the L2 Cache.

[0073] Exemplarily, the parallel computing described above can be understood as that each control unit can execute in parallel, and the core idea of parallel computing can include at least one of the following: 1. Computation flow instructions and data flow instructions can be executed in parallel; 2. Computation flow instructions can be executed in parallel. For example, the TS3 executing TensorCore computation flow instructions can be executed in parallel with the TS4 executing VerctorCore computation flow instructions; 3. Data flow instructions can be executed in parallel. For example, the TS1 performing data transfer between the GlobalMemory and the L1 Cache can be executed in parallel with the TS2 performing data transfer between the L1 Cache and the L2 Cache. Therefore, through the parallel execution of the control units, it is possible to achieve the parallel execution of each instruction in TS1, TS2, TS3, and TS4 in the same time segment, thereby realizing the parallel execution of computing tasks. Here, taking Figure 4 as an example, within the same time segment time-4, the instructions in TS1, TS2, TS3, and TS4 are executed in parallel, thereby improving the computing efficiency.

[0074] Figure 5 is a flowchart of a computing method provided in an embodiment of the present invention. This embodiment is applicable to the case of fused computing, especially applicable to the case of completing fused computing inside the ALU. This method can be executed by the computing device provided in the embodiment of the present invention. The device can be implemented in software and / or hardware, and the device can be integrated on a computing chip. The computing chip includes a computing core, and the computing core includes an arithmetic logic unit, and the arithmetic logic unit includes a first storage unit and at least one computing unit.

[0075] See Figure 5 , the method of the embodiment of the present invention specifically includes the following steps:

[0076] S310. For the first data and the second data to be computed and the first computation flow instruction corresponding to the first data and the second data, through the first computing unit corresponding to the first computation flow instruction in all computing units, in response to the first computation flow instruction, compute the first data and the second data to store the obtained intermediate computation result in the first storage unit.

[0077] Among them, in the embodiments of the present invention, it is necessary to perform fusion calculations on the first data, the second data, and the third data, and the first data, the second data, and the third data are the original data described above. On this basis, first calculate the first data and the second data through this step to obtain an intermediate calculation result; then, calculate the intermediate calculation result and the third data through the following steps to obtain a target calculation result.

[0078] Specifically, the first calculation stream instruction can be understood as an instruction indicating a certain calculation operation on the first data and the second data. For the first calculation unit responsible for executing this calculation operation among all calculation units, through this first calculation unit, in response to the first calculation stream instruction, calculate the first data and the second data based on this calculation operation to obtain an intermediate calculation result. Further, store the intermediate calculation result in the first storage unit. It should be noted that this storage process can be performed by this first calculation unit or a unit other than this first calculation unit, which can be set according to actual needs and is not specifically limited here.

[0079] S320. For the third data to be calculated with the first data and the second data and the corresponding second calculation stream instruction of the third data, through the second calculation unit corresponding to the second calculation stream instruction among all calculation units, in response to the second calculation stream instruction, calculate the third data and the intermediate calculation result obtained from the first storage unit to obtain a target calculation result.

[0080] Among them, the second calculation stream instruction can be understood as an instruction indicating a certain calculation operation on the third data, and further can be understood as an instruction indicating a certain calculation operation on the third data and the intermediate calculation result obtained above. For the second calculation unit responsible for executing this calculation operation among all calculation units, through this second calculation unit, in response to the second calculation stream instruction, calculate the third data and the intermediate calculation result based on this calculation operation to obtain the final target calculation result. It should be noted that the second calculation unit in this step and the first calculation unit in the above step may be the same or different calculation units, which is related to the actual situation and is not specifically limited here.

[0081] The calculation method described in the embodiments of the present invention is applied to a computing chip. The computing chip includes a computing core, the computing core includes an arithmetic logic unit, and the arithmetic logic unit includes a first storage unit and at least one computing unit. On this basis, for the first data and the second data to be calculated and the first computing stream instruction corresponding to the first data and the second data, through the first computing unit corresponding to the first computing stream instruction among all the computing units, in response to the first computing stream instruction, the first data and the second data are calculated, and then the obtained intermediate calculation result is stored in the first storage unit; further, for the third data to be calculated with the first data and the second data and the second computing stream instruction corresponding to the third data, the second computing unit corresponding to the second computing stream instruction among all the computing units can be used to calculate the third data and the intermediate calculation result obtained from the first storage unit in response to the second computing stream instruction to obtain the target calculation result. In the above technical solution, relying on the first storage unit provided in the arithmetic logic unit, the transfer process of the intermediate calculation result can be completed within the arithmetic logic unit, that is, the fused calculation can be realized within the arithmetic logic unit, thereby improving the fused calculation efficiency.

[0082] An optional technical solution is that the number of computing units is at least two, and the arithmetic logic unit further includes a first control unit corresponding to each computing unit. Then, through the first computing unit corresponding to the first computing stream instruction among all the computing units, in response to the first computing stream instruction, the first data and the second data are calculated to store the obtained intermediate calculation result in the first storage unit, including:

[0083] For the first computing unit corresponding to the first computing stream instruction among all the computing units, using the first control unit corresponding to the first computing unit, the first computing stream instruction is transferred to the first computing unit, so that the first computing unit calculates the first data and the second data in response to the first computing stream instruction, and using the first control unit corresponding to the first computing unit, the intermediate calculation result calculated by the first computing unit is stored in the first storage unit.

[0084] In the above technical solution, by using the first control unit corresponding to the first computing unit, the first computing stream instruction is transferred into the first computing unit for data calculation, and then the intermediate calculation result is transferred to the first storage unit by using the first control unit, thereby realizing the control effect of data calculation and the transfer of the intermediate calculation result.

[0085] On this basis, optionally, using the first control unit corresponding to the first computing unit to transfer the first computing stream instruction to the first computing unit includes:

[0086] For a first control unit corresponding to a first computing unit and a control queue created in advance for the first control unit, write a first computing stream instruction into the control queue, so that the first control unit reads the first computing stream instruction from the control queue and transfers the first computing stream instruction to the first computing unit.

[0087] Among them, in practical applications, the first control unit usually needs to process multiple first computing stream instructions. Therefore, in order to ensure the sequential execution of each first computing stream instruction, a control queue can be created in advance for the first control unit. In this way, the first control unit can sequentially take out each first computing stream instruction from the control queue and transfer them to the first computing unit in sequence for response.

[0088] The above technical solution realizes the sequential execution of each first computing stream instruction by establishing a control queue, and thus realizes the sequential execution of each computing task.

[0089] Another alternative technical solution is that the number of computing units is at least two, and the arithmetic logic unit further includes a first control unit corresponding to each computing unit respectively. Then, through the second computing unit corresponding to the second computing stream instruction among all the computing units, in response to the second computing stream instruction, calculate the third data and the intermediate calculation result obtained from the first storage unit to obtain the target calculation result, including:

[0090] For the second computing unit corresponding to the second computing stream instruction among all the computing units, use the first control unit corresponding to the second computing unit to obtain the intermediate calculation result from the first storage unit, and transfer the intermediate calculation result and the second computing stream instruction to the second computing unit, so that the second computing unit calculates the third data and the intermediate calculation result in response to the second computing stream instruction to obtain the target calculation result.

[0091] The above technical solution realizes the control effect of data calculation and intermediate calculation result transfer by using the second control unit corresponding to the second computing unit to transfer the second computing stream instruction and the intermediate calculation result obtained from the first storage unit into the second computing unit for data calculation.

[0092] Yet another alternative technical solution is that the computing core further includes a second storage unit and a second control unit, and the above computing method further includes:

[0093] Use the second control unit to obtain the first data and the second data from the second storage unit in response to the data stream instruction, and transfer the first data and the second data to the first storage unit, so that the first computing unit performs data calculation based on the first data and the second data stored in the first storage unit.

[0094] In the above technical solution, through the second control unit, the transfer control of the first data and the second data to be calculated from the second storage unit outside the ALU to the first storage unit inside the ALU is realized.

[0095] On this basis, in order to better understand the overall computing process in the above computing chip, four examples of the TensorCore computing process, the VerctorCore computing process, the TensorCore+VerctorCore computing process, and the VerctorCore+VerctorCore computing process are given below for exemplary illustration.

[0096] Exemplarily, for the TensorCore computing process, see Figure 6a . TensorCore can be used for matrix multiplication calculation. For example, for matrix A with dimension (M, K) and matrix B with dimension (K, N), the following matrix multiplication calculation process can be used to obtain matrix Y with dimension (M, N):

[0097] 1. Resource initialization: TS1_Queue, TS2_Queue, and TS3_Queue are pre-created; the Central Processing Unit (CPU) outside the computing chip copies A and B from the system memory to the GlobalMemory in the computing chip for data calculation in the computing chip;

[0098] 2. Data transfer GlobalMemory -> L1 Cache: The data stream instruction (from GlobalMemory to L1 Cache) is InQueued to TS1_Queue. TS1 deQueues the data stream instruction (from GlobalMemory to L1 Cache) from TS1_Queue and executes this instruction by TS1 to transfer A and B from GlobalMemory to L1 Cache;

[0099] 3. Data transfer L1 Cache -> L2 Cache: The data stream instruction (from L1 Cache to L2 Cache) can be InQueued to TS2_Queue. TS2 deQueues the data stream instruction (from L1 Cache to L2 Cache) from TS2_Queue and executes this instruction by TS2 to transfer A and B from L1 Cache to L2 Cache;

[0100] 4. TensorCore Calculation (A multiplied by B): Enqueue the (TensorCore) calculation stream instruction InQue to the TS3_Queue. TS3 dequeues the (TensorCore) calculation stream instruction from the TS3_Queue, and then TS3 manages the execution of this instruction on the TensorCore to achieve matrix multiplication calculation, and then transports the calculated Y to the L2 Cache;

[0101] 5. Data Transfer L2 Cache -> L1 Cache: The data stream instruction from (L2 Cache to L1 Cache) can be EnQueued to the TS2_Queue. TS2 dequeues the data stream instruction from (L2 Cache to L1 Cache) from the TS2_Queue, and TS2 executes this instruction to achieve the transfer of Y from the L2 Cache to the L1 Cache;

[0102] 6. Data Transfer L1 Cache -> GlobalMemory: Enqueue the data stream instruction from (L1 Cache to GlobalMemory) to the TS1_Queue. TS1 dequeues the data stream instruction from (L1 Cache to GlobalMemory) from the TS1_Queue, and TS1 executes this instruction to achieve the transfer of Y from the L1 Cache to GlobalMemory;

[0103] 7. Resource Release: Release all kinds of data stored in the L1 Cache and L2 Cache.

[0104] Exemplarily, for the VerctorCore calculation process, refer to Figure 6b ... TensorCore is used for vector / scalar calculation, such as: vector A and vector B calculation, vector A and scalar B calculation, or scalar A and scalar B calculation, etc., to obtain vector Y or scalar Y. Taking vector calculation as an example, the specific calculation process is as follows:

[0105] 1. Resource Initialization: Pre-create TS1_Queue, TS2_Queue, and TS4_Queue; the CPU outside the computing chip copies A and B from the system memory to the GlobalMemory of the computing chip for data calculation in the computing chip;

[0106] 2. Data transfer from GlobalMemory to L1 Cache: The data stream instructions from (GlobalMemory to L1 Cache) can be InQueued to the TS1_Queue. TS1 DeQueues the data stream instructions from (GlobalMemory to L1 Cache) from the TS1_Queue and executes these instructions, realizing the transfer of A and B from GlobalMemory to L1 Cache;

[0107] 3. Data transfer from L1 Cache to L2 Cache: The data stream instructions from (L1 Cache to L2 Cache) can be InQueued to the TS2_Queue. TS2 DeQueues the data stream instructions from (L1 Cache to L2 Cache) from the TS2_Queue and executes these instructions, realizing the transfer of A and B from L1 Cache to L2 Cache;

[0108] 4. VerctorCore calculation (vector A and vector B calculation): The calculation stream instructions from (VerctorCore) can be InQueued to the TS4_Queue. TS4 DeQueues the calculation stream instructions from (VerctorCore) from the TS4_Queue, and then TS4 manages the execution of these instructions on VerctorCore to realize vector calculation. Then the calculated Y is transferred to L2 Cache;

[0109] 5. Data transfer from L2 Cache to L1 Cache: The data stream instructions from (L2 Cache to L1 Cache) can be InQueued to the TS2_Queue. TS2 DeQueues the data stream instructions from (L2 Cache to L1 Cache) from the TS2_Queue and executes these instructions, realizing the transfer of Y from L2 Cache to L1 Cache;

[0110] 6. Data transfer from L1 Cache to GlobalMemory: The data stream instructions from (L1 Cache to GlobalMemory) are InQueued to the TS1_Queue. TS1 DeQueues the data stream instructions from (L1 Cache to GlobalMemory) from the TS1_Queue and executes these instructions, realizing the transfer of Y from L1 Cache to GlobalMemory;

[0111] 7. Resource release: Release various data stored in L1 Cache and L2 Cache.

[0112] Exemplarily, for the TensorCore + VerctorCore computing process, refer to Figure 6c . First, perform matrix multiplication of matrix A with dimension (M, K) and matrix B with dimension (K, N) to obtain an intermediate calculation result X with dimension (M, N). Then, perform an addition calculation of X and vector C with dimension (1, N) to obtain the target calculation result Y. The specific calculation process is as follows:

[0113] 1. Resource initialization: Pre-create TS1_Queue, TS2_Queue, TS3_Queue, and TS4_Queue; the CPU outside the computing chip copies A, B, and C from the system memory to the GlobalMemory in the computing chip for data calculation in the computing chip;

[0114] 2. Data transfer GlobalMemory -> L1 Cache: InQue the data stream instruction (from GlobalMemory to L1 Cache) to TS1_Queue. TS1 DeQue the data stream instruction (from GlobalMemory to L1 Cache) from TS1_Queue and executes this instruction by TS1 to implement the transfer of A, B, and C from GlobalMemory to L1 Cache;

[0115] 3. Data transfer L1 Cache -> L2 Cache: The data stream instruction (from L1 Cache to L2 Cache) can be InQue to TS2_Queue. TS2 DeQue the data stream instruction (from L1 Cache to L2 Cache) from TS2_Queue and executes this instruction by TS2 to implement the transfer of A, B, and C from L1 Cache to L2 Cache;

[0116] 4. TensorCore calculation (A multiplied by B): InQue the (TensorCore) calculation stream instruction to TS3_Queue. TS3 DeQue the (TensorCore) calculation stream instruction from TS3_Queue, and then TS3 manages the execution of this instruction on the TensorCore to implement the matrix multiplication calculation of A and B, and transfers the calculated X to L2 Cache;

[0117] 5. VerctorCore Calculation (X plus C): Enqueue the (VerctorCore) computational stream instruction InQue to TS4_Queue. TS4 dequeues the (VerctorCore) computational stream instruction from TS4_Queue and manages the execution of this instruction on VerctorCore to achieve vector calculation, and transports the calculated Y to the L2 Cache.

[0118] 6. Data Transfer L2 Cache -> L1 Cache: The data stream instruction from (L2 Cache to L1 Cache) can be enqueued to TS2_Queue. TS2 dequeues the data stream instruction from (L2 Cache to L1 Cache) from TS2_Queue and executes this instruction to achieve the transfer of Y from L2 Cache to L1 Cache.

[0119] 7. Data Transfer L1 Cache -> GlobalMemory: Enqueue the data stream instruction from (L1 Cache to GlobalMemory) to TS1_Queue. TS1 dequeues the data stream instruction from (L1 Cache to GlobalMemory) from TS1_Queue and executes this instruction to achieve the transfer of Y from L1 Cache to GlobalMemory.

[0120] 8. Resource Release: Release all kinds of data stored in L1 Cache and L2 Cache.

[0121] The above example realizes the fused calculation of TensorCore + VerctorCore.

[0122] Exemplarily, for the VerctorCore + VerctorCore calculation process, see Figure 6d , first calculate the vector A and the scalar C to obtain the intermediate calculation result X, and then add it to the vector B to obtain the target calculation result Y. The specific calculation process is as follows:

[0123] 1. Resource Initialization: Pre-create TS1_Queue, TS2_Queue, TS3_Queue, and TS4_Queue; the CPU outside the computing chip copies A, B, and C from the system memory to the GlobalMemory of the computing chip for data calculation in the computing chip.

[0124] 2. Data transfer from Global Memory to L1 Cache: Enqueue the data stream instructions (from Global Memory to L1 Cache) into TS1_Queue. TS1 dequeues the data stream instructions (from Global Memory to L1 Cache) from TS1_Queue and executes these instructions to transfer A, B, and C from Global Memory to L1 Cache.

[0125] 3. Data transfer from L1 Cache to L2 Cache: Enqueue the data stream instructions (from L1 Cache to L2 Cache) into TS2_Queue. TS2 dequeues the data stream instructions (from L1 Cache to L2 Cache) from TS2_Queue and executes these instructions to transfer A, B, and C from L1 Cache to L2 Cache.

[0126] 4. VerctorCore calculation (A and C calculation): Enqueue the calculation stream instructions (for VerctorCore) into TS4_Queue. TS4 dequeues the calculation stream instructions (for VerctorCore) from TS4_Queue and manages the execution of these instructions on VerctorCore to perform the calculation of A and C, and transfer the calculated X to L2 Cache.

[0127] 5. VerctorCore calculation (X and B calculation): Enqueue the calculation stream instructions (for VerctorCore) into TS4_Queue. TS4 dequeues the calculation stream instructions (for VerctorCore) from TS4_Queue and manages the execution of these instructions on VerctorCore to perform the calculation of X and B, and transfer the calculated Y to L2 Cache.

[0128] 6. Data transfer from L2 Cache to L1 Cache: Enqueue the data stream instructions (from L2 Cache to L1 Cache) into TS2_Queue. TS2 dequeues the data stream instructions (from L2 Cache to L1 Cache) from TS2_Queue and executes these instructions to transfer Y from L2 Cache to L1 Cache.

[0129] 7. Data transfer from L1 Cache to Global Memory: The data stream instruction from (L1 Cache to Global Memory) is enqueued into TS1_Queue. TS1 dequeues the data stream instruction from (L1 Cache to Global Memory) from TS1_Queue and executes this instruction, realizing the transfer of Y from L1 Cache to Global Memory.

[0130] 8. Resource release: Release all kinds of data stored in L1 Cache and L2 Cache.

[0131] The above example realizes the fusion calculation of VerctorCore + VerctorCore.

[0132] Figure 7 The structural block diagram of the computing device provided by the embodiment of the present invention is used to execute the computing method provided by any of the above embodiments. The device and the computing methods of the above embodiments belong to the same inventive concept. For the details not described in detail in the embodiment of the computing device, reference can be made to the embodiment of the above computing method. Refer to Figure 7 , the device is configured on a computing chip. The computing chip includes a computing core, and the computing core includes an arithmetic logic unit. The arithmetic logic unit includes a first storage unit and at least one computing unit. Specifically, the device may include: a first computing module 410 and a second computing module 420.

[0133] Among them, the first computing module 410 is used to calculate the first data and the second data and the first computing stream instruction corresponding to the first data and the second data through the first computing unit corresponding to the first computing stream instruction in all computing units, and in response to the first computing stream instruction, calculate the first data and the second data to store the obtained intermediate calculation result in the first storage unit;

[0134] The second computing module 420 can be used to calculate the third data to be calculated with the first data and the second data and the second computing stream instruction corresponding to the third data through the second computing unit corresponding to the second computing stream instruction in all computing units, and in response to the second computing stream instruction, calculate the third data and the intermediate calculation result obtained from the first storage unit to obtain the target calculation result.

[0135] Optionally, the number of computing units is at least two, and the arithmetic logic unit further includes a first control unit corresponding to each computing unit respectively; the first computing module 410 may include:

[0136] The first computing unit is configured to, for the first computing unit corresponding to the first computing stream instruction among all the computing units, use the first control unit corresponding to the first computing unit to transfer the first computing stream instruction to the first computing unit, so that the first computing unit calculates the first data and the second data in response to the first computing stream instruction, and uses the first control unit corresponding to the first computing unit to store the intermediate computing result calculated by the first computing unit into the first storage unit;

[0137] And / or, the second computing module 410 may include:

[0138] The second computing unit is configured to, for the second computing unit corresponding to the second computing stream instruction among all the computing units, use the first control unit corresponding to the second computing unit to obtain the intermediate computing result from the first storage unit, and transfer the intermediate computing result and the second computing stream instruction to the second computing unit, so that the second computing unit calculates the third data and the intermediate computing result in response to the second computing stream instruction to obtain the target computing result.

[0139] On this basis, optionally, the first computing unit may include:

[0140] The first computing stream instruction transfer subunit is configured to, for the first control unit corresponding to the first computing unit and the control queue created in advance for the first control unit, write the first computing stream instruction into the control queue, so that the first control unit reads the first computing stream instruction from the control queue and transfers the first computing stream instruction to the first computing unit.

[0141] Optionally, the computing core further includes a second storage unit and a second control unit, and the above computing device may further include:

[0142] The data transfer module is configured to, in response to the data stream instruction, use the second control unit to obtain the first data and the second data from the second storage unit, and transfer the first data and the second data to the first storage unit, so that the first computing unit performs data calculation based on the first data and the second data stored in the first storage unit.

[0143] The computing device provided by the embodiment of the present invention is configured in a computing chip, the computing chip includes a computing core, the computing core includes an arithmetic logic unit, the arithmetic logic unit includes a first storage unit and at least one computing unit. On this basis, through a first computing module, for a first data and a second data to be computed and a first computing stream instruction corresponding to the first data and the second data, the first computing unit corresponding to the first computing stream instruction among all the computing units is used to compute the first data and the second data in response to the first computing stream instruction, and then the obtained intermediate computing result is stored in the first storage unit; then, through a second computing module, for a third data to be computed with the first data and the second data and a second computing stream instruction corresponding to the third data, the second computing unit corresponding to the second computing stream instruction among all the computing units can be used to compute the third data and the intermediate computing result obtained from the first storage unit in response to the second computing stream instruction to obtain a target computing result. The above device, relying on the first storage unit provided in the arithmetic logic unit, can complete the transfer process of the intermediate computing result inside the arithmetic logic unit, that is, the fused computing can be realized inside the arithmetic logic unit, thereby improving the fused computing efficiency.

[0144] The computing device provided by the embodiment of the present invention can execute the computing method provided by any embodiment of the present invention, and has a functional module and beneficial effect corresponding to the execution of the method.

[0145] It should be noted that in the above embodiment of the computing device, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific names of the functional units are only for the convenience of mutual distinction and do not limit the protection scope of the present invention.

[0146] In some embodiments, the computing method can be implemented as a computer program, which is tangibly included in a computer-readable storage medium. In some embodiments, part or all of the computer program can be loaded and / or installed on the computing chip, so as to execute one or more steps of the computing method described above.

[0147] The various embodiments of the systems and techniques described above in this specification can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from, and transmits data and instructions to, a storage system, at least one input device, and at least one output device.

[0148] The computer programs for implementing the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The computer programs can be executed entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

[0149] In the context of the present invention, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0150] To provide interaction with a user, the systems and techniques described herein can be implemented on a computing chip that has: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computing chip. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0151] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), blockchain network, and the Internet.

[0152] A computing system can include a client and a server. The client and the server are generally far from each other and usually interact through a communication network. The client-server relationship is created by computer programs that run on the respective computers and have a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system and solves the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services.

[0153] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0154] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A computing chip, characterized in that: It includes a computing core, wherein the computing core includes an arithmetic logic unit, and the arithmetic logic unit includes a first storage unit and a computing unit with which data flows during a fusion computing process.

2. The computing chip according to claim 1, characterized in that: The number of the computing units is at least two, and the arithmetic logic unit also includes a first control unit corresponding to each of the computing units, wherein the first control unit is used to perform data flow between the corresponding computing unit and the first storage unit to achieve fusion calculation.

3. The computing chip according to claim 1 or 2, characterized in that: The computing core also includes a second storage unit and a second control unit, wherein the second control unit is used for transferring data between the first storage unit and the second storage unit.

4. The computing chip according to claim 3, characterized in that: The computing chip further includes a third storage unit, wherein data flows between the second storage unit and the third storage unit.

5. The computing chip according to claim 4, characterized in that: The computing chip further includes a third control unit, wherein the third control unit is used for transferring data between the second storage unit and the third storage unit.

6. The computing chip according to claim 4, characterized in that: The bandwidth of the second storage unit is smaller than that of the first storage unit and larger than that of the third storage unit; and / or the storage capacity of the second storage unit is smaller than that of the third storage unit and larger than that of the first storage unit.

7. The computing chip according to claim 2, characterized in that: At least one of all the computing units performs calculations on at least two-dimensional data.

8. A calculation method, characterized in that: Applied to a computing chip, the computing chip includes a computing core, the computing core includes an arithmetic logic unit, the arithmetic logic unit includes a first storage unit and at least one computing unit, the method includes: For first data and second data to be calculated and a first calculation flow instruction corresponding to the first data and the second data, a first calculation unit corresponding to the first calculation flow instruction among all the calculation units is used to calculate the first data and the second data in response to the first calculation flow instruction, so as to store the obtained intermediate calculation result in the first storage unit; For the third data to be calculated with the first data and the second data and the second calculation flow instruction corresponding to the third data, the second calculation unit corresponding to the second calculation flow instruction among all the calculation units calculates the third data and the intermediate calculation result obtained from the first storage unit in response to the second calculation flow instruction to obtain the target calculation result.

9. The calculation method according to claim 8, characterized in that: The number of the computing units is at least two, and the arithmetic logic unit further includes a first control unit corresponding to each of the computing units; The step of calculating the first data and the second data by a first computing unit corresponding to the first computing flow instruction among all the computing units in response to the first computing flow instruction, so as to store the obtained intermediate computing result in the first storage unit, comprises: For a first computing unit corresponding to the first computing flow instruction among all the computing units, using the first control unit corresponding to the first computing unit, transferring the first computing flow instruction to the first computing unit, so that the first computing unit calculates the first data and the second data in response to the first computing flow instruction, and using the first control unit corresponding to the first computing unit, storing the intermediate calculation result calculated by the first computing unit in the first storage unit; and / or, The step of calculating the third data and the intermediate calculation result obtained from the first storage unit in response to the second calculation flow instruction by the second calculation unit corresponding to the second calculation flow instruction among all the calculation units to obtain the target calculation result includes: For the second computing unit corresponding to the second computing flow instruction among all the computing units, the first control unit corresponding to the second computing unit is used to obtain the intermediate computing result from the first storage unit, and the intermediate computing result and the second computing flow instruction are transferred to the second computing unit, so that the second computing unit responds to the second computing flow instruction, calculates the third data and the intermediate computing result, and obtains the target computing result.

10. The calculation method according to claim 9, characterized in that: The using the first control unit corresponding to the first computing unit to transfer the first computing flow instruction flow to the first computing unit includes: For the first control unit corresponding to the first computing unit and the control queue created in advance for the first control unit, the first computing flow instruction is written into the control queue, so that the first control unit reads the first computing flow instruction from the control queue and transfers the first computing flow instruction to the first computing unit.

11. The calculation method according to claim 8, characterized in that: The computing core further includes a second storage unit and a second control unit, and the method further includes: Using the second control unit, in response to the data flow instruction, the first data and the second data are obtained from the second storage unit, and the first data and the second data are transferred to the first storage unit, so that the first computing unit performs data calculation based on the first data and the second data stored in the first storage unit.

12. A computing device, characterized in that: The device is configured on a computing chip, the computing chip includes a computing core, the computing core includes an arithmetic logic unit, the arithmetic logic unit includes a first storage unit and at least one computing unit, and the device includes: a first computing module, configured to compute the first data and the second data to be computed and a first computing flow instruction corresponding to the first data and the second data, by using a first computing unit corresponding to the first computing flow instruction among all the computing units, in response to the first computing flow instruction, the first data and the second data, so as to store the obtained intermediate computing result in the first storage unit; A second computing module is used to calculate the third data to be calculated with the first data and the second data and a second computing flow instruction corresponding to the third data, through the second computing units corresponding to the second computing flow instruction in all the computing units, in response to the second computing flow instruction, calculate the third data and the intermediate computing result obtained from the first storage unit to obtain a target computing result.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the computing method as described in any one of claims 8 to 11 when executed.

14. A computer program product, characterized in that The computer program product comprises a computer program which, when executed by a processor, implements the computing method according to any one of claims 8 to 11.

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