Package substrate and / or board with shared power distribution network

Abstract

An apparatus includes: a substrate; a first integration device coupled to the first surface of the substrate; a second integration device coupled to the first surface of the substrate; a first passive device coupled to the second surface of the substrate; and a second passive device coupled to the second surface of the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects. The plurality of interconnects includes power interconnects. The power interconnect is configured to be electrically coupled to a power source. The first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnect through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects is configured to operate as inductors, wherein the first plurality of interconnects includes via interconnects.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit and priority of U.S. Non - Provisional Application Serial No. 17 / 988,642, filed on November 16, 2022, with the United States Patent and Trademark Office, the entire content of which is incorporated herein by reference as if set forth in full below and for all applicable purposes. Technical Field

[0003] Various features relate to boards, packages, and substrates. Background Art

[0004] Packages can include substrates and integrated devices. These components are coupled together to provide a package that can perform various functions. The performance of the package and its components can depend on how power can be provided to the package and / or its components through a board. There has been a continuing need to provide packages with improved performance. Summary of the Invention

[0005] Various features relate to boards, packages, and substrates.

[0006] One example provides a device that includes: a substrate; a first integrated device coupled to a first surface of the substrate; a second integrated device coupled to the first surface of the substrate; a first passive device coupled to the substrate; and a second passive device coupled to the substrate. The substrate includes at least one dielectric layer; and a plurality of interconnects formed on at least a plurality of metal layers of the substrate. The plurality of metal layers includes a first metal layer and a second metal layer. The plurality of interconnects includes power interconnects. The power interconnects are configured to be electrically coupled to a power source. The first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnects through a first plurality of interconnects from the plurality of interconnects. At least one interconnect from the first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to a power source. The first plurality of interconnects includes a first interconnect located on the first metal layer, a second interconnect located on the second metal layer, and a via interconnect coupling the first interconnect and the second interconnect.

[0007] An example provides a device that includes: a board substrate; a first integrated device coupled to a first surface of the board substrate; a second integrated device coupled to the first surface of the board substrate; a first passive device coupled to a second surface of the board substrate; and a second passive device coupled to the second surface of the board substrate. The board substrate includes at least one dielectric layer; and a plurality of interconnects formed on at least a plurality of metal layers of the board substrate. The plurality of metal layers includes a first metal layer and a second metal layer. The plurality of interconnects includes power interconnects. The power interconnects are configured to be electrically coupled to a power supply. The first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnects through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to a power supply, where the first plurality of interconnects includes a first interconnect located on the first metal layer, a second interconnect located on the second metal layer, and a via interconnect coupled to the first interconnect and the second interconnect.

[0008] An example provides a device that includes: a package substrate; a first integrated device coupled to a first surface of the package substrate; a second integrated device coupled to the first surface of the package substrate; a first passive device coupled to a second surface of the package substrate; and a second passive device coupled to the second surface of the package substrate. The package substrate includes at least one dielectric layer; and a plurality of interconnects formed on at least a plurality of metal layers of the package substrate. The plurality of metal layers includes a first metal layer and a second metal layer. The plurality of interconnects includes power interconnects. The power interconnects are configured to be electrically coupled to a power supply. The first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnects through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to a power supply, where the first plurality of interconnects includes a first interconnect located on the first metal layer, a second interconnect located on the second metal layer, and a via interconnect coupled to the first interconnect and the second interconnect. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various features, natures, and advantages will become apparent when the following detailed description is understood in conjunction with the accompanying drawings, in which like reference characters correspond throughout.

[0010] Figure 1 A cross-sectional view of an integrated device coupled to a board substrate is illustrated.

[0011] Figure 2 Illustrates a cross-sectional view of an integrated device coupled to a board substrate.

[0012] Figure 3 Illustrates a cross-sectional view of an exemplary package including a package substrate and an integrated device.

[0013] Figure 4 Illustrates a cross-sectional view of an exemplary package including a package substrate and an integrated device.

[0014] Figure 5 Illustrates a cross-sectional view of an exemplary package including a package substrate and an integrated device.

[0015] Figure 6 Illustrates an exemplary circuit path in a substrate.

[0016] Figure 7 Illustrates an exemplary circuit path in a substrate.

[0017] Figure 8 Illustrates an exemplary circuit path in a substrate.

[0018] Figure 9 Illustrates an exemplary circuit path in a substrate.

[0019] Figure 10 Illustrates an exemplary circuit diagram of a board substrate and / or package having a shared power distribution network, the package including a package substrate and an integrated device.

[0020] Figure 11 Illustrates an exemplary circuit path in a substrate.

[0021] Figure 12 Illustrates a cross-sectional view of an exemplary package coupled to a board substrate, wherein the package includes a package substrate and an integrated device.

[0022] Figures 13A to 13C Illustrates an exemplary process for manufacturing a substrate having interconnects.

[0023] Figures 14A to 14C Illustrates an exemplary process for manufacturing a substrate having interconnects.

[0024] Figures 15A to 15B Illustrates an exemplary process for manufacturing a package including a package substrate and an integrated device.

[0025] Figure 16 Illustrates an exemplary flowchart of a method for manufacturing a package including a package substrate and an integrated device.

[0026] Figure 17A cross-sectional view of an exemplary package including a package substrate and an integrated device is illustrated.

[0027] Figure 18 A cross-sectional view of an integrated device coupled to a board substrate is illustrated.

[0028] Figure 19 A cross-sectional view of an exemplary package including a package substrate and an integrated device is illustrated.

[0029] Figure 20 Various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein are illustrated. DETAILED DESCRIPTION

[0030] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, one of ordinary skill in the art will understand that these aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring these aspects with unnecessary details. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure these aspects of the present disclosure.

[0031] The present disclosure describes a device that includes: a substrate; a first integrated device coupled to a first surface of the substrate; a second integrated device coupled to the first surface of the substrate; a first passive device coupled to a second surface of the substrate; and a second passive device coupled to the second surface of the substrate. The substrate includes at least one dielectric layer; and a plurality of interconnects formed on at least a plurality of metal layers of the substrate. The plurality of metal layers includes a first metal layer and a second metal layer. The plurality of interconnects includes power interconnects. The power interconnects are configured to be electrically coupled to a power supply. The first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnects through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to a power supply, where the first plurality of interconnects includes a first interconnect located on the first metal layer, a second interconnect located on the second metal layer, and a via interconnect coupling the first interconnect and the second interconnect. The substrate can be a board substrate. The substrate can be a package substrate. The plurality of interconnects is configured to provide a shared power distribution network for the first integrated device and the second integrated device. The plurality of interconnects is arranged and / or configured in such a way that improved noise isolation is provided between the first integrated device and / or the second integrated device. Providing improved noise isolation between integrated devices can contribute to improving the overall performance of the package and / or the integrated device.

[0032] Exemplary boards and packages including integrated devices and substrates

[0033] Figure 1 A cross-sectional view of configuration 100 is illustrated, which includes a board substrate 102 (e.g., a board, a printed circuit board), integrated device 103, integrated device 105, passive device 107, and passive device 109. Integrated device 103 may be a first integrated device. Integrated device 105 may be a second integrated device. Integrated device 105 may be an integrated device package (e.g., a flip chip) including a package substrate, a semiconductor die, and an encapsulation layer. Passive device 107 may be a first passive device. Passive device 109 may be a second passive device. Passive device 107 and / or passive device 109 may each include a capacitor (e.g., a decoupling capacitor). Board substrate 102 may be configured to provide a shared power distribution network. Integrated device 103, integrated device 105, passive device 107, and passive device 109 are configured to be coupled to the shared power distribution network.

[0034] Board substrate 102 includes at least one dielectric layer 120 (e.g., a board dielectric layer) and a plurality of interconnects 122 (e.g., board interconnects). Board substrate 102 also includes a solder mask layer 140 and a solder mask layer 142. Board substrate 102 includes four (4) metal layers, where the interconnects are located on and between the metal layers. However, as will be further described below, the board substrate may include a different number of metal layers (e.g., more than four metal layers). Board substrate 102 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The second surface of board substrate 102 may be opposite to the first surface of board substrate 102, and vice versa. Integrated device 103 is coupled to the first surface of substrate 102 through a plurality of solder interconnects 130. In some embodiments, integrated device 103 is coupled to the first surface of board substrate 102 through a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 130. Integrated device 105 is coupled to the first surface of board substrate 102 through a plurality of solder interconnects 150. In some embodiments, integrated device 105 is coupled to the first surface of board substrate 102 through a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 150.

[0035] Passive device 107 is coupled to the second surface of board substrate 102 through a plurality of solder interconnects 170. Passive device 109 is coupled to the second surface of board substrate 102 through a plurality of solder interconnects 190. Integrated device 103, integrated device 105, passive device 107, and passive device 109 may each be configured to be electrically coupled to one or more of the interconnects from the plurality of interconnects 122.

[0036] Configuration 100 can be configured to be electrically coupled to a power distribution network. The power distribution network can be configured to be electrically coupled to a power management integrated circuit (PMIC) (e.g., a power management integrated device). The power distribution network can be a power distribution network shared for integrated device 103 and integrated device 105. For example, power for both integrated device 103 and integrated device 105 can be provided by and / or through a power management integrated circuit (PMIC). The power management integrated circuit (PMIC) can be coupled to board substrate 102.

[0037] Passive device 107 is configured to be electrically coupled to integrated device 103 through a first plurality of interconnects of a plurality of interconnects 122 from board substrate 102. For example, circuit path 132 between at least passive device 107 and integrated device 103 includes a first plurality of interconnects of a plurality of interconnects 122 from board substrate 102. Circuit path 132 can represent at least a portion of a circuit path of power between a power management integrated circuit (PMIC) (not shown), passive device 107, and integrated device 103. For example, power from the power management integrated circuit (PMIC) can travel through interconnects on a metal layer (e.g., the second metal layer), travel downward through at least one via interconnect toward another metal layer (e.g., the third metal layer), travel along another metal layer (e.g., the third metal layer), travel upward through at least one via interconnect toward a metal layer (e.g., the second metal layer), travel along the metal layer (e.g., the second metal layer), travel downward through at least one via interconnect toward another metal layer (e.g., the third metal layer), travel along another metal layer (e.g., the third metal layer), travel downward through at least one via interconnect toward the bottom metal layer (e.g., the fourth metal layer), travel through a solder interconnect from a plurality of solder interconnects 170 and toward a terminal of passive device 107, and travel upward from another metal layer (e.g., the third metal layer) through at least one via interconnect toward a metal layer (e.g., the second metal layer), travel upward through at least one via interconnect toward the top metal layer (e.g., the first metal layer) and toward integrated device 103 through at least one solder interconnect from a plurality of solder interconnects 130. In some specific implementations, the other terminal of passive device 107 can be configured to be electrically coupled to an interconnect configured to provide ground from a plurality of interconnects 122. Note that only a portion of circuit path 132 is shown. Circuit path 132 can be coupled to the power management integrated circuit (PMIC) through various possible interconnects. Figure 1Illustrated is that the circuit path 132 can extend up and down several times through a number of metal layers and via interconnects between the metal layers to generate additional inductance to help isolate the power supplied to two different integrated devices in a shared power distribution network. The additional inductance in the circuit can be positioned along the circuit path between the passive device 107 and the passive device 109. The additional inductance in the circuit can be positioned along the circuit path between the integrated device 103 and the integrated device 105. The additional inductance in the circuit can be positioned along the circuit path between the passive device 107, the passive device 109, the integrated device 103, and the integrated device 105.

[0038] Note that (i) the first metal layer of a board substrate (e.g., 102, 202) as used in this disclosure can mean any metal layer among the metal layers of the board substrate (e.g., 102, 202), (ii) the second metal layer of a board substrate (e.g., 102, 202) as used in this disclosure can mean any metal layer among the metal layers of the board substrate (e.g., 102, 202), (iii) the third metal layer of a board substrate (e.g., 102, 202) as used in this disclosure can mean any metal layer among the metal layers of the board substrate (e.g., 102, 202), and (iv) the fourth metal layer of a board substrate (e.g., 102, 202) as used in this disclosure can mean any metal layer among the metal layers of the board substrate (e.g., 102, 202).

[0039] The passive device 109 is configured to be electrically coupled to the integrated device 105 through a second plurality of interconnects of the plurality of interconnects 122 from the board substrate 102. For example, the circuit path 152 between at least the passive device 109 and the integrated device 105 includes a second plurality of interconnects of the plurality of interconnects 122 from the board substrate 102. The circuit path 152 may represent at least a portion of the circuit path of power between a power management integrated circuit (PMIC) (not shown), the passive device 109, and the integrated device 105. For example, power from the power management integrated circuit (PMIC) may travel through interconnects on a metal layer (e.g., the second metal layer), travel downward through at least one via interconnect toward another metal layer (e.g., the third metal layer), travel downward through at least one via interconnect toward the bottom metal layer (e.g., the fourth metal layer), travel through a solder interconnect from the plurality of solder interconnects 190 and toward a terminal of the passive device 109, and travel from the bottom metal layer (e.g., the fourth metal layer) through at least one via interconnect toward another metal layer (e.g., the third metal layer), travel upward through at least one via interconnect toward the metal layer (e.g., the second metal layer), travel upward through at least one via interconnect toward the top metal layer (e.g., the first metal layer), and travel through at least one solder interconnect from the plurality of solder interconnects 150 toward the integrated device 105. In some embodiments, the other terminal of the passive device 109 may be configured to be electrically coupled to an interconnect of the plurality of interconnects 122 configured to provide a ground. Note that only a portion of the circuit path 152 is shown. The circuit path 152 may be coupled to the power management integrated circuit (PMIC) through various possible interconnects. Figure 1 Illustrated is that the circuit path 152 may extend up and down several times through several metal layers and through via interconnects between the metal layers to create additional inductance to help isolate the power provided to two different integrated devices in a shared power distribution network. The circuit path 132 and the circuit path 152 may be configured to be electrically coupled to each other. In some embodiments, the circuit path 132 and the circuit path 152 may be considered part of the same circuit path. In some embodiments, the second plurality of interconnects from the plurality of interconnects 122 may be considered part of the first plurality of interconnects from the plurality of interconnects 122, and vice versa.

[0040] The passive devices 107 and 109 may share a power distribution network. For example, both the passive device 107 and the passive device 109 may be directly or indirectly coupled to at least one same interconnect configured to provide power (e.g., an interconnect on the second metal layer). In some embodiments, the interconnect on the second metal layer may include power interconnects (e.g., wide trace interconnects, planar interconnects, rail interconnects) that are part of circuit paths 132 and 152. Thus, the circuit paths 132 and 152 may be configured to be electrically coupled to each other. Power may travel from the board substrate 102 through the power management integrated circuit (PMIC) and the interconnects, where the power is split to the passive device 107, the passive device 109, the integrated device 103, and the integrated device 105. For example, power may be provided to the passive device 107 and the integrated device 103, and power may be provided to the passive device 109 and the integrated device 105.

[0041] The circuit path 132 and / or the circuit path 152 may include a plurality of interconnects from the plurality of interconnects 122, which are configured to form at least one inductor defined by at least one interconnect on one metal layer, another interconnect on another metal layer, and at least one via interconnect. The inductor is integrated in the board substrate 102 and is configured to be coupled to a power source. The inductor may include one or more complex windings (from the interconnects) up and down two or more metal layers of the board substrate 102. The inductor defined by at least one via interconnect (e.g., an additional via interconnect) may be positioned along the circuit path between the passive device 107 and the passive device 109. The inductor defined by at least one via interconnect (e.g., an additional via interconnect) may be positioned along the circuit path between the integrated device 103 and the integrated device 105. Thus, the additional windings (e.g., vertical windings and / or horizontal windings) of the interconnects that are part of the circuit path between the passive device 107 and the passive device 109 and part of the circuit path between the integrated device 103 and the integrated device 105 help increase the inductance, which helps reduce noise transfer between the integrated devices. The additional windings (e.g., vertical windings and / or horizontal windings) of the interconnects may be positioned along a common path (e.g., a common circuit path) between the passive device 107, the passive device 109, the integrated device 103, and the integrated device 105. In Figure 5 more detailed examples of the common path are further described and illustrated.

[0042] Figure 2 An exemplary cross-sectional view of a configuration 200 including a board substrate 202, an integrated device 103, an integrated device 105, a passive device 107, and a passive device 109 is illustrated. The integrated device 103, the integrated device 105, the passive device 107, and the passive device 109 may be the same as Figure 1coupled to the board substrate 202 in a manner similar to the board substrate 102. The board substrate 202 may be similar to the board substrate 102. However, the board substrate 202 includes a different number of metal layers, and the interconnects are located on and between the metal layers.

[0043] The board substrate 202 includes at least one dielectric layer 120 (e.g., a board dielectric layer) and a plurality of interconnects 122. The board substrate 102 includes at least six (6) metal layers. The board substrate 202 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The second surface of the board substrate 202 may be opposite to the first surface of the board substrate 202. The integrated device 103 is coupled to the first surface of the board substrate 202 by a plurality of solder interconnects 130. In some specific embodiments, the integrated device 103 is coupled to the first surface of the board substrate 202 by a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 130. The integrated device 105 is coupled to the first surface of the board substrate 202 by a plurality of solder interconnects 150. In some specific embodiments, the integrated device 105 is coupled to the first surface of the board substrate 202 by a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 150.

[0044] The passive device 107 is coupled to the second surface of the board substrate 202 by a plurality of solder interconnects 170. The passive device 109 is coupled to the second surface of the board substrate 202 by a plurality of solder interconnects 190. The integrated device 103, the integrated device 105, the passive device 107, and the passive device 109 may each be configured to be electrically coupled to one or more of the interconnects from the plurality of interconnects 122.

[0045] The configuration 200 may be configured to be electrically coupled to a power distribution network. The power distribution network may be configured to be electrically coupled to a power management integrated circuit (PMIC) (e.g., a power management integrated device). The power distribution network may be a power distribution network shared for the integrated device 103 and the integrated device 105.

[0046] The passive device 107 is configured to be electrically coupled to the integrated device 103 through a first plurality of interconnects of the plurality of interconnects 122 from the board substrate 202. For example, the circuit path 232 between at least the passive device 107 and the integrated device 103 includes a first plurality of interconnects of the plurality of interconnects 122 from the board substrate 202. The circuit path 232 may represent at least a portion of the circuit path of power between a power management integrated circuit (PMIC) (not shown), the passive device 107, and the integrated device 103. For example, power from the power management integrated circuit (PMIC) may travel through interconnects on a metal layer (e.g., the 3rd metal layer), travel downward through at least one via interconnect toward another metal layer (e.g., the 4th metal layer), travel downward through at least one via interconnect toward another metal layer (the 5th metal layer), travel along another metal layer (the 5th metal layer), travel downward through at least one via interconnect toward the bottom metal layer (e.g., the 6th metal layer), travel through a solder interconnect from the plurality of solder interconnects 170 and toward a terminal of the passive device 107, and travel upward from another metal layer (e.g., the 5th metal layer) through at least one via interconnect toward another metal layer (e.g., the 4th metal layer), travel upward through at least one via interconnect toward a metal layer (e.g., the 3rd metal layer), travel upward through at least one via interconnect toward another metal layer (the 2nd metal layer), travel upward through at least one via interconnect toward the top metal layer (e.g., the 1st metal layer), and travel through at least one solder interconnect from the plurality of solder interconnects 130 toward the integrated device 103. In some embodiments, the other terminal of the passive device 107 may be configured to be electrically coupled to an interconnect of the plurality of interconnects 122 configured to provide a ground. Note that only a portion of the circuit path 232 is shown. The circuit path 232 may be coupled to the power management integrated circuit (PMIC) through various possible interconnects.

[0047] Note that (i) the first metal layer of the board substrate (e.g., 102, 202) as used in this disclosure may refer to any metal layer among the metal layers of the board substrate (e.g., 102, 202), (ii) the second metal layer of the board substrate (e.g., 102, 202) as used in this disclosure may refer to any metal layer among the metal layers of the board substrate (e.g., 102, 202), (iii) the third metal layer of the board substrate (e.g., 102, 202) as used in this disclosure may refer to any metal layer among the metal layers of the board substrate (e.g., 102, 202), (iv) the fourth metal layer of the board substrate (e.g., 102, 202) as used in this disclosure may refer to any metal layer among the metal layers of the board substrate (e.g., 102, 202), (v) the fifth metal layer of the board substrate (e.g., 202) as used in this disclosure may refer to any metal layer among the metal layers of the board substrate (e.g., 202), (vi) the sixth metal layer of the board substrate (e.g., 202) as used in this disclosure may refer to any metal layer among the metal layers of the board substrate (e.g., 202), and so on.

[0048] The passive device 109 is configured to be electrically coupled to the integrated device 105 through a second plurality of interconnects of the plurality of interconnects 122 from the board substrate 202. For example, the circuit path 252 between at least the passive device 109 and the integrated device 105 includes a second plurality of interconnects of the plurality of interconnects 122 from the board substrate 202. The circuit path 252 may represent at least a portion of the circuit path of power between a power management integrated circuit (PMIC) (not shown), the passive device 109, and the integrated device 105. For example, power from the power management integrated circuit (PMIC) may travel through interconnects on a metal layer (e.g., the 3rd metal layer), travel downward through at least one via interconnect toward another metal layer (e.g., the 4th metal layer), travel downward through at least one via interconnect toward another metal layer (e.g., the 5th metal layer), travel downward through at least one via interconnect toward the bottom metal layer (e.g., the 6th metal layer), travel along the interconnects of the bottom metal layer (e.g., the 6th metal layer), travel through a solder interconnect of the plurality of solder interconnects 190 and toward a terminal of the passive device 109, and travel upward from the bottom metal layer (e.g., the 6th metal layer) through at least one via interconnect toward another metal layer (e.g., the 5th metal layer), travel upward through at least one via interconnect toward another metal layer (e.g., the 4th metal layer), travel upward through at least one via interconnect toward another metal layer (e.g., the 3rd metal layer), travel upward through at least one via interconnect toward another metal layer (e.g., the 2nd metal layer), travel upward through at least one via interconnect toward the top metal layer (e.g., the 1st metal layer), and travel toward the integrated device 105 through at least one solder interconnect of the plurality of solder interconnects 150. In some specific embodiments, the other terminal of the passive device 109 may be configured to be electrically coupled to an interconnect of the plurality of interconnects 122 configured to provide ground. Note that only a portion of the circuit path 252 is shown. The circuit path 252 may be coupled to the power management integrated circuit (PMIC) through various possible interconnects.

[0049] The passive devices 107 and 109 may share a power distribution network. For example, both the passive device 107 and the passive device 109 may be directly or indirectly coupled to the same set of interconnects (e.g., the interconnects on the third metal layer) configured to provide power. In some embodiments, the interconnects on the third metal layer may include power interconnects (e.g., wide power interconnects, wide trace interconnects, planar interconnects, rail interconnects) that are part of circuit paths 232 and 252. The circuit path 232 may be configured to couple to the circuit path 252. The circuit paths 232 and 252 may be considered part of the same circuit path. In some embodiments, a second plurality of interconnects from the plurality of interconnects 122 may be considered part of a first plurality of interconnects from the plurality of interconnects 122, and vice versa.

[0050] The circuit path 232 and / or the circuit path 252 may include a plurality of interconnects from the plurality of interconnects 122, the plurality of interconnects being configured as at least one inductor defined by at least one interconnect on one metal layer, another interconnect on another metal layer, and at least one via interconnect. The inductor is integrated in the board substrate 202 and is configured to couple to a power supply. The inductor may include one or more multiple windings (from interconnects) up and down two or more metal layers of the board substrate 202.

[0051] Figure 1 and Figure 2 The illustrated circuit paths for power are not limited to any particular metal layer of a board substrate (e.g., a board, a printed circuit board). Thus, any metal layer may be used for the circuit paths. Figure 1 and Figure 2 Illustrated is that instead of taking the most direct path to the integrated devices 103 and / or 105, power may first be directed closer to and / or nearer to the passive devices (e.g., 107, 109) (and thus vertically away from the integrated devices 103 and / or 105), and then directed towards the integrated devices 103 and / or 105. For example, one circuit path may be lengthened in the board substrate by extending the circuit path up and down through several metal layers, which creates additional inductance that helps isolate the power between different integrated devices in the shared power distribution network. As will be further described at least in Figure 10 below, this design and / or method of routing power may help improve power delivery, and provide improved isolation between the power to different integrated devices (e.g., by adding inductance through the interconnects), and reduce noise transfer between the integrated devices.

[0052] In some embodiments, other types of substrates may implement the designs and / or configurations shown and described in the present disclosure. For example, the above designs may be implemented in a package substrate, instead of and / or in addition to a board substrate.

[0053] Figure 3 Illustrates a cross-sectional view of package 300, which includes substrate 302, integrated device 303, integrated device 305, passive devices 107, passive devices 109, and encapsulation layer 108. Integrated device 303 is coupled to the first surface of substrate 302 through a plurality of solder interconnects 330. Integrated device 305 is coupled to the first surface of substrate 302 through a plurality of solder interconnects 350. Passive device 107 is coupled to the second surface of substrate 302 through a plurality of solder interconnects 170. Passive device 109 is coupled to the second surface of substrate 302 through a plurality of solder interconnects 190. Encapsulation layer 108 can be coupled to substrate 302, integrated device 303, and integrated device 305. Encapsulation layer 108 is coupled to the first surface of board substrate 102. Encapsulation layer 108 can encapsulate integrated device 103 and integrated device 105. Encapsulation layer 108 can include a molding, a resin, and / or an epoxy resin. Encapsulation layer 108 can be a component for encapsulation. Encapsulation layer 108 can be provided by using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0054] Substrate 302 can be a package substrate. Substrate 302 can be a cored substrate. Substrate 302 includes core layer 320, at least one dielectric layer 324, at least one dielectric layer 326, and a plurality of interconnects 325. The plurality of interconnects 325 can be located in, on, and / or under at least one dielectric layer 324 and at least one dielectric layer 326. The plurality of interconnects 325 can include a plurality of core interconnects located in core layer 320. In some embodiments, an embedded trace substrate (ETS) can be used for package 300. A plurality of solder interconnects 110 are coupled to the plurality of interconnects 325 of substrate 302.

[0055] Package 300 can be configured to be electrically coupled to a power distribution network. The power distribution network can be configured to be electrically coupled to a power management integrated circuit (PMIC) (e.g., a power management integrated device). The power distribution network can be a power distribution network shared for integrated device 303 and integrated device 305. For example, power for both integrated device 303 and integrated device 305 can be provided by and / or through a power management integrated circuit (PMIC).

[0056] The passive device 107 is configured to be electrically coupled to the integrated device 303 through a first plurality of interconnects of the plurality of interconnects 325 from the substrate 302. For example, the circuit path 332 between at least the passive device 107 and the integrated device 303 includes a first plurality of interconnects of the plurality of interconnects 325 from the substrate 302. The circuit path 332 may represent at least a portion of the circuit path of power between a power management integrated circuit (PMIC) (not shown), the passive device 107, and the integrated device 303. For example, power from the power management integrated circuit (PMIC) may travel through a solder interconnect from the plurality of solder interconnects 110, through interconnects of several metal layers, through interconnects on a metal layer (e.g., the second metal layer), downward toward another metal layer (e.g., the third metal layer) through at least one core interconnect (e.g., a via core interconnect), travel along another metal layer (e.g., the third metal layer), downward toward the bottom metal layer (e.g., the fourth metal layer) through at least one via interconnect, travel through a solder interconnect from the plurality of solder interconnects 170 and toward a terminal of the passive device 107, and upward from another metal layer (e.g., the third metal layer) toward the metal layer (e.g., the second metal layer) through at least one via interconnect, upward toward the top metal layer (e.g., the first metal layer) through at least one via interconnect, and toward the integrated device 303 through at least one solder interconnect from the plurality of solder interconnects 130. In some embodiments, the other terminal of the passive device 107 may be configured to be electrically coupled to an interconnect from the plurality of interconnects 325 configured to provide ground. Note that only a portion of the circuit path 332 is shown. The circuit path 332 may be coupled to the power management integrated circuit (PMIC) through various possible interconnects. Power may pass through the package 300 through at least one solder interconnect from the plurality of solder interconnects 110.

[0057] The circuit path 332 and / or the circuit path 352 may include a plurality of interconnects from the plurality of interconnects 325 configured as an inductor defined by at least one interconnect on one metal layer, another interconnect on another metal layer, and at least one via interconnect. The inductor is integrated in the package substrate 302 and is configured to be coupled to a power source. The inductor may include one or more multiple windings (from interconnects) up and down two or more metal layers of the package substrate 302.

[0058] Note that (i) the first metal layer of a substrate (e.g., 302, 402) as used in this disclosure may refer to any metal layer among the metal layers of the substrate (e.g., 302, 402), (ii) the second metal layer of a substrate (e.g., 302, 402) as used in this disclosure may refer to any metal layer among the metal layers of the substrate (e.g., 302, 402), (iii) the third metal layer of a substrate (e.g., 302, 402) as used in this disclosure may refer to any metal layer among the metal layers of the substrate (e.g., 302, 402), (iv) the fourth metal layer of a substrate (e.g., 302, 402) as used in this disclosure may refer to any metal layer among the metal layers of the substrate (e.g., 302, 402), (v) the fifth metal layer of a substrate (e.g., 402) as used in this disclosure may refer to any metal layer among the metal layers of the substrate (e.g., 402), (vi) the sixth metal layer of a substrate (e.g., 402) as used in this disclosure may refer to any metal layer among the metal layers of the substrate (e.g., 402), and so on. Substrate 302 and / or substrate 402 may be a packaging substrate.

[0059] The passive device 109 is configured to be electrically coupled to the integrated device 305 through a second plurality of interconnects of the plurality of interconnects 325 from the substrate 302. For example, the circuit path 352 between at least the passive device 109 and the integrated device 305 includes a second plurality of interconnects of the plurality of interconnects 325 from the substrate 302. The circuit path 352 may represent at least a portion of the circuit path of power between a power management integrated circuit (PMIC) (not shown), the passive device 109, and the integrated device 305. For example, power from the power management integrated circuit (PMIC) may travel through interconnects on a metal layer (e.g., the second metal layer), travel downward through at least one core interconnect (e.g., a core via interconnect) toward another metal layer (e.g., the third metal layer), travel downward through at least one via interconnect toward the bottom metal layer (e.g., the fourth metal layer), travel along the bottom metal layer (e.g., the fourth metal layer), travel through a solder interconnect of the plurality of solder interconnects 190 and toward a terminal of the passive device 109, and travel upward from the bottom metal layer (e.g., the fourth metal layer) through at least one via interconnect toward a metal layer (e.g., the third metal layer), travel upward through at least one via interconnect toward a metal layer (e.g., the second metal layer), travel upward through at least one via interconnect toward the top metal layer (e.g., the first metal layer), and travel toward the integrated device 305 through at least one solder interconnect of the plurality of solder interconnects 150. In some embodiments, the other terminal of the passive device 109 may be configured to be electrically coupled to an interconnect of the plurality of interconnects 325 configured to provide a ground. Note that only a portion of the circuit path 352 is shown. The circuit path 352 may be coupled to the power management integrated circuit (PMIC) through various possible interconnects. The circuit path 332 may be configured to be electrically coupled to the circuit path 352. In some embodiments, the circuit path 332 and the circuit path 352 may be considered part of the same circuit path. In some embodiments, the second plurality of interconnects of the plurality of interconnects 325 may be considered part of the first plurality of interconnects of the plurality of interconnects 325, and vice versa.

[0060] Circuit path 332 and / or circuit path 352 may include a plurality of interconnects from a plurality of interconnects 325, the plurality of interconnects being configured as at least one inductor defined by at least one interconnect on one metal layer, another interconnect on another metal layer, and at least one via interconnect. The inductor is integrated in substrate 302 and is configured to be coupled to a power supply. The inductor may include one or more complex windings (from interconnects) up and down two or more metal layers of substrate 302. The inductor defined by at least one via interconnect (e.g., an additional via interconnect) may be positioned along a circuit path located between passive device 107 and passive device 109. The inductor defined by at least one via interconnect (e.g., an additional via interconnect) may be positioned along a circuit path located between integrated device 303 and integrated device 305. The inductor is located in a common path (e.g., a common circuit path) between integrated device 103, integrated device 105, passive device 107, and passive device 109. In Figure 5 More detailed examples of the common path are further described and illustrated. Thus, additional windings (e.g., vertical windings and / or horizontal windings) along the common path that are part of the circuit path between passive device 107 and passive device 109 and part of the circuit path between integrated device 303 and integrated device 305 of the interconnects contribute to increasing the inductance, which helps reduce noise transfer between integrated devices.

[0061] Figure 4 An exemplary cross-sectional view of package 400 is illustrated, which includes substrate 402, integrated device 303, integrated device 305, passive device 107, passive device 109, and encapsulation layer 108. Integrated device 303, integrated device 305, passive device 107, passive device 109, and encapsulation layer 108 may be coupled to substrate 302 in a manner similar to Figure 3 substrate 302. Integrated device 303 is coupled to a first surface of substrate 402 by a plurality of solder interconnects 330. Integrated device 305 is coupled to a first surface of substrate 402 by a plurality of solder interconnects 350.

[0062] Substrate 402 may be a package substrate. Substrate 402 may be a cored substrate. Substrate 402 includes core layer 420, at least one dielectric layer 424, at least one dielectric layer 426, and a plurality of interconnects 425. The plurality of interconnects 425 may be located in, on, and / or under at least one dielectric layer 424 and at least one dielectric layer 326. The plurality of interconnects 345 may include a plurality of core interconnects located in core layer 420. Substrate 402 is similar to substrate 302. However, substrate 402 includes more metal layers with interconnects positioned thereon.

[0063] Package 400 can be configured to be electrically coupled to a power distribution network. The power distribution network can be configured to be electrically coupled to a power management integrated circuit (PMIC) (e.g., a power management integrated device). The power distribution network can be a shared power distribution network for integrated device 303 and integrated device 305. For example, power for both integrated device 303 and integrated device 305 can be provided by and / or through a power management integrated circuit (PMIC).

[0064] Passive device 107 is configured to be electrically coupled to integrated device 303 via a first plurality of interconnects of a plurality of interconnects 425 from substrate 402. For example, circuit path 432 between at least passive device 107 and integrated device 303 includes a first plurality of interconnects of a plurality of interconnects 425 from substrate 402. Circuit path 432 can represent at least a portion of the circuit path of power between a power management integrated circuit (PMIC) (not shown), passive device 107, and integrated device 303. For example, power from a power management integrated circuit (PMIC) can travel through a solder interconnect of a plurality of solder interconnects 110, through interconnects on several metal layers, through interconnects on a metal layer (e.g., the 4th metal layer), travel downward toward another metal layer (e.g., the 5th metal layer) through at least one via interconnect, travel along another metal layer (e.g., the 5th metal layer), travel downward toward the bottom metal layer (e.g., the 6th metal layer) through at least one via interconnect, travel through a solder interconnect of a plurality of solder interconnects 170 and toward a terminal of passive device 107, and travel upward from another metal layer (e.g., the 5th metal layer) toward a metal layer (e.g., the 4th metal layer) through at least one via interconnect, travel upward toward a metal layer (e.g., the 3rd metal layer) through at least one core interconnect (e.g., a via core interconnect), travel upward toward a metal layer (e.g., the 2nd metal layer) through at least one via interconnect, travel upward toward the top metal layer (e.g., the 1st metal layer) through at least one via interconnect, and travel toward integrated device 303 through at least one solder interconnect of a plurality of solder interconnects 130. In some embodiments, the other terminal of passive device 107 can be configured to be electrically coupled to an interconnect of a plurality of interconnects 425 configured to provide ground. Note that only a portion of circuit path 432 is shown. Circuit path 432 can be coupled to a power management integrated circuit (PMIC) via various possible interconnects.

[0065] The passive device 109 is configured to be electrically coupled to the integrated device 305 through a second plurality of interconnects of the plurality of interconnects 425 from the substrate 402. For example, the circuit path 452 between at least the passive device 109 and the integrated device 305 includes a second plurality of interconnects of the plurality of interconnects 425 from the substrate 402. The circuit path 452 may represent at least a portion of the circuit path of power between a power management integrated circuit (PMIC) (not shown), the passive device 109, and the integrated device 305. For example, power from the power management integrated circuit (PMIC) may travel through interconnects on a metal layer (e.g., the 4th metal layer), travel downward toward another metal layer (e.g., the 5th metal layer) through at least one via interconnect, travel downward toward the bottom metal layer (e.g., the 6th metal layer) through at least one via interconnect, travel along the bottom metal layer (e.g., the 6th metal layer), travel through a solder interconnect of the plurality of solder interconnects 190 and toward a terminal of the passive device 109, and travel upward from the bottom metal layer (e.g., the 6th metal layer) through at least one via interconnect toward a metal layer (e.g., the 5th metal layer), travel upward toward a metal layer (e.g., the 4th metal layer) through at least one via interconnect, travel upward toward a metal layer (e.g., the 3rd metal layer) through at least one core interconnect (e.g., a via core interconnect), travel upward toward a metal layer (e.g., the 2nd metal layer) through at least one via interconnect, travel upward toward the top metal layer (e.g., the 1st metal layer) through at least one via interconnect and travel toward the integrated device 305 through at least one solder interconnect of the plurality of solder interconnects 150. In some embodiments, the other terminal of the passive device 109 may be configured to be electrically coupled to an interconnect of the plurality of interconnects 425 configured to provide ground. Note that only a portion of the circuit path 452 is shown. The circuit path 452 may be coupled to the power management integrated circuit (PMIC) through various possible interconnects. The circuit path 432 may be configured to be electrically coupled to the circuit path 452. The circuit path 432 and the circuit path 452 may be considered part of the same circuit path. In some embodiments, a second plurality of interconnects from the plurality of interconnects 122 may be considered part of a first plurality of interconnects from the plurality of interconnects 122, and vice versa.

[0066] Circuit path 432 and / or circuit path 452 may include a plurality of interconnects from the plurality of interconnects 425, which are configured to be at least one inductor defined by at least one interconnect on one metal layer, another interconnect on another metal layer, and at least one via interconnect. The inductor is integrated in the package substrate 402 and is configured to be coupled to a power supply. The inductor may include one or more windings (from interconnects) up and down two or more metal layers of the package substrate 402. The inductor defined by at least one via interconnect (e.g., additional via interconnect) may be positioned along the circuit path between the passive device 107 and the passive device 109. The inductor defined by at least one via interconnect (e.g., additional via interconnect) may be positioned along the circuit path between the integrated device 303 and the integrated device 305. The inductor is in the common path between the integrated device 303, the integrated device 305, the passive device 107, and the passive device 109 / along the common circuit path. Thus, additional windings (e.g., vertical windings and / or horizontal windings) along the common path that are part of the circuit path between the passive device 107 and the passive device 109 and part of the circuit path between the integrated device 303 and the integrated device 305 of the interconnects help increase the inductance, which helps reduce noise transfer between the integrated devices. In Figure 5 More detailed examples of the common path are further described and illustrated.

[0067] Figure 5 An exemplary cross-sectional view of the package 500 is illustrated, which includes a substrate 402, an integrated device 303, an integrated device 305, a passive device 107, a passive device 109, and an encapsulation layer 108. The integrated device 303, the integrated device 305, the passive device 107, the passive device 109, and the encapsulation layer 108 may be coupled to the substrate 402 in a manner similar to Figure 3 the package substrate 302. The integrated device 303 is coupled to the first surface of the substrate 402 through a plurality of solder interconnects 330. The integrated device 305 is coupled to the first surface of the substrate 402 through a plurality of solder interconnects 350.

[0068] Figure 5 Another configuration is illustrated of how the circuit path may be arranged between the integrated device and / or the passive device. In particular, the circuit path 532 may be configured to be electrically coupled to the passive device 107, the passive device 109, the integrated device 303, and the integrated device 305.

[0069] The passive device 107 is configured to be electrically coupled to the integrated device 303 through a first plurality of interconnects of the plurality of interconnects 425 from the substrate 402. For example, the circuit path 532 between at least the passive device 107 and the integrated device 303 includes a first plurality of interconnects of the plurality of interconnects 425 from the substrate 402. The circuit path 532 may represent at least a portion of the circuit path of power between a power management integrated circuit (PMIC) (not shown), the passive device 107, and the integrated device 303. For example, power from the power management integrated circuit (PMIC) may travel from a solder interconnect of the plurality of solder interconnects 110, travel through an interconnect on a bottom metal layer (e.g., the 6th metal layer), travel upward toward an interconnect on a metal layer (e.g., the 5th metal layer), travel through an interconnect on the metal layer (e.g., the 5th metal layer), travel downward toward the bottom metal layer (e.g., the 6th metal layer) through at least one via interconnect, travel through a solder interconnect of the plurality of solder interconnects 170 and toward a terminal of the passive device 107, and travel upward from an interconnect on a metal layer (e.g., the 5th metal layer) through at least one via interconnect toward a metal layer (e.g., the 4th metal layer), travel upward through at least one core interconnect (e.g., a via core interconnect) toward a metal layer (e.g., the 3rd metal layer), travel upward through at least one via interconnect toward a metal layer (e.g., the 2nd metal layer), travel upward through at least one via interconnect toward the top metal layer (e.g., the 1st metal layer) and through at least one solder interconnect of the plurality of solder interconnects 130 toward the integrated device 303. In some embodiments, the other terminal of the passive device 107 may be configured to be electrically coupled to an interconnect of the plurality of interconnects 425 configured to provide a ground. Note that only a portion of the circuit path 532 is shown. The circuit path 532 may be coupled to the power management integrated circuit (PMIC) through various possible interconnects.

[0070] The circuit path 532 can be configured to be electrically coupled to the passive device 109 and / or the integrated device 305. The passive device 109 is configured to be electrically coupled to the integrated device 305 through a second plurality of interconnects from the plurality of interconnects 425 of the substrate 402. For example, the circuit path 532 between at least the passive device 109 and the integrated device 305 includes a second plurality of interconnects from the plurality of interconnects 425 of the substrate 402. The circuit path 532 can represent at least a portion of the circuit path of power between a power management integrated circuit (PMIC) (not shown), the passive device 109, and the integrated device 305. For example, power from the power management integrated circuit (PMIC) can travel through interconnects on a metal layer (e.g., the 5th metal layer), travel downward toward the bottom metal layer (e.g., the 6th metal layer) through at least one via interconnect, travel through a solder interconnect from the plurality of solder interconnects 190 and toward a terminal of the passive device 109, and travel upward from the metal layer (e.g., the 5th metal layer) through at least one via interconnect toward the metal layer (e.g., the 4th metal layer), travel upward through at least one core interconnect (e.g., a via core interconnect) toward the metal layer (e.g., the 3rd metal layer), travel upward through at least one via interconnect toward the metal layer (e.g., the 2nd metal layer), travel upward through at least one via interconnect toward the top metal layer (e.g., the 1st metal layer), and travel through at least one solder interconnect from the plurality of solder interconnects 150 toward the integrated device 305. In some embodiments, the other terminal of the passive device 109 can be configured to be electrically coupled to an interconnect from the plurality of interconnects 425 configured to provide a ground. Note that only a portion of the circuit path 532 is shown. The circuit path 532 can be coupled to the power management integrated circuit (PMIC) through various possible interconnects. Figure 5 It is illustrated that the circuit path 532 can extend up and down several times through several metal layers and through via interconnects between the metal layers to generate additional inductance to help isolate the power provided to two different integrated devices in a shared power distribution network. In some embodiments, the circuit path 532 can extend up and down between two or more adjacent metal layers to generate additional inductance to help improve isolation.

[0071] Circuit path 532 may include a plurality of interconnects from a plurality of interconnects 425, the plurality of interconnects being configured as at least one inductor defined by at least one interconnect on one metal layer, another interconnect on another metal layer, and at least one via interconnect. The inductor is integrated in the package substrate 402 and is configured to be coupled to a power supply. The inductor may include one or more complex windings (from interconnects) up and down two or more metal layers of the package substrate 402. The inductor defined by at least one via interconnect (e.g., additional via interconnect) may be positioned along a circuit path located between passive device 107 and passive device 109. The inductor defined by at least one via interconnect (e.g., additional via interconnect) may be positioned along a circuit path located between integrated device 303 and integrated device 305. The inductor is positioned along a common path (e.g., common circuit path) located between integrated device 303 and integrated device 305 and between passive device 107 and passive device 109. Thus, additional windings (e.g., vertical windings and / or horizontal windings) of the interconnects that are part of the circuit path between passive device 107 and passive device 109 and part of the circuit path between integrated device 303 and integrated device 305 contribute to increasing the inductance, which helps reduce noise transfer between the integrated devices.

[0072] Figure 5 Examples are illustrated of what a common path or common circuit path may mean. Circuit path 532 includes point A, point B, point C, point D, point AC, and point BD. Point A may represent a pin and / or terminal of integrated device 303. Point B may represent a pin and / or terminal of integrated device 305. Point C may represent a pin and / or terminal of passive device 107. Point D may represent a pin and / or terminal of passive device 109. Note that point A, point B, point C, and / or point D may represent other components in circuit path 532. For example, point A may represent integrated device 303, point B may represent integrated device 305, point C may represent passive device 107 and / or point D may represent passive device 109.

[0073] Point AC is a point located on circuit path 532 and is between point A and point C. Point BD is a point located on circuit path 532 and is between point B and point D. In some specific implementations, the common path between point A, point B, point C, and point D can be the path between point AC and point BD. In some specific implementations, the additional inductance provided by circuit path 532 is between point AC and point BD. Thus, at least some of the interconnects (e.g., the third plurality of interconnects) that are part of circuit path 532 and between point AC and point BD can be configured as inductors to provide additional inductance, thereby helping to reduce noise transfer between integrated devices. The interconnects between point AC and point BD of circuit path 532 can be a subset of the interconnects from the interconnects that define circuit path 532. Point AC can represent one or more interconnects from circuit path 532. Point BD can represent one or more interconnects from circuit path 532.

[0074] Note that the concept and / or definition of a common path and / or a common circuit path can apply to a package substrate and / or a board substrate. Additionally, the concept and / or definition of a common path and / or a common circuit path can apply to any package and / or configuration shown and described in this disclosure. Further note that a circuit path, a common path, and / or a common circuit path are intended to be a conceptual representation of a path, and thus, a circuit path, a common path, and / or a common circuit path can have different shapes and / or configurations, and / or can extend in different directions in and / or around a substrate (e.g., a board substrate, a package substrate).

[0075] Figures 3 to 5 An example is shown of how at least one circuit path can be lengthened in a package substrate by extending the circuit path up and down through several metal layers and extending between the metal layers, which creates additional inductance that helps with isolation between the powers to different integrated devices in a shared power distribution network. As will be further described at least in Figure 10 what follows, this design and / or method of routing power can help improve power delivery and provide improved isolation between the powers to different integrated devices (e.g., by adding inductance through interconnects), and reduce noise transfer between integrated devices.

[0076] Figures 1 to 5 An example of a column of interconnects located in a substrate (e.g., a board substrate, a package substrate) is shown. The column of interconnects in the substrate can be used to electrically couple an integrated device to a passive device. The additional inductance generated by the windings described in this disclosure can be located along the circuit path between two columns of interconnects, each of which is electrically coupled to a corresponding integrated device and a corresponding passive device. Note that the use of columns of interconnects is not required. In some specific implementations, other types of vertical circuit paths can be used between an integrated device and a capacitor.

[0077] Figure 6 Conceptually illustrates an exemplary circuit path in a substrate. Figure 6 Conceptually illustrates a substrate 602 including at least four metal layers. For clarity purposes, only four metal layers are shown. However, the substrate 602 may include more than four metal layers. Each metal layer may include a plurality of interconnects. The substrate 602 may conceptually represent any of the substrates described in the present disclosure. The substrate 602 may represent a package substrate or a board substrate (e.g., a board, a printed circuit board).

[0078] Note that (i) the first metal layer of the substrate as used in the present disclosure may mean any of the metal layers in the substrate, (ii) the second metal layer of the substrate as used in the present disclosure may mean any of the metal layers in the substrate, (iii) the third metal layer of the substrate as used in the present disclosure may mean any of the metal layers in the substrate, and (iv) the fourth metal layer of the substrate as used in the present disclosure may mean any of the metal layers in the substrate.

[0079] The at least four metal layers include a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. In some embodiments, the first metal layer may represent the top metal layer of the substrate. In some embodiments, the fourth metal layer may represent the bottom metal layer of the substrate. The second metal layer and the third metal layer are located between the first metal layer and the fourth metal layer. The second metal layer is located between the first metal layer and the third metal layer. The third metal layer is located between the second metal layer and the fourth metal layer. In one example, when the substrate 602 includes seven metal layers, the first metal layer may be the M1 metal layer, the second metal layer may be the M2 metal layer or the M3 metal layer, the third metal layer may be the M5 metal layer or the M6 metal layer, and the fourth metal layer may be the M7 metal layer. Thus, the metal layers shown in the substrate 602 do not necessarily need to correspond to specific metal layers of the substrate. Instead, the metal layers shown in the substrate 602 may represent the positioning of the metal layers relative to other metal layers in the substrate. Thus, for example, in some embodiments, there may be at least one metal layer between the first metal layer and the second metal layer. Similarly, in some embodiments, there may be at least one metal layer between the second metal layer and the third metal layer. Additionally, in some embodiments, there may be at least one metal layer between the third metal layer and the fourth metal layer. When a circuit path extends from one metal layer to another metal layer, the circuit path may also extend between any metal layers between the two metal layers. For example, if the circuit path extends from the third metal layer to the second metal layer, the circuit path may also extend through any metal layer (e.g., any interconnect) located between the third metal layer and the second metal layer.

[0080] In Figure 6In [the context], power interconnects (e.g., wide trace interconnects, planar interconnects, rail interconnects) may be located in a second metal layer (e.g., M2 layer). The power interconnects may be configured to be electrically coupled to a power management integrated circuit (PMIC) 601. The power interconnects are a type of interconnect whose size, width, and / or shape are greater than those of pad interconnects and / or trace interconnects. The power interconnects may occupy a majority (e.g., 10% or more of the metal layer). The power interconnects may have a width that is at least 50% greater than the width of the trace interconnects. The power interconnects are configured to provide a circuit path for power to provide low impedance power. The power interconnects may be split into a number of smaller individual power trace interconnects. For example, the power interconnects may include wide power interconnects that may be split and become two or more power trace interconnects. The width of the power trace interconnects may be less than the width of the wide power interconnects. In some embodiments, the width of the power trace interconnects may be similar to, the same as, or greater than the width of the trace interconnects configured for input / output signals. In some embodiments, the power interconnects may include a number of power interconnects (e.g., a number of rails of power interconnects).

[0081] The circuit path 632 between the power management integrated circuit (PMIC) 601, the integrated device 103, and the passive device 107 includes a first plurality of interconnects that extend through the second metal layer, extend downward toward the third metal layer through via interconnects, extend along the third metal layer, extend downward toward the fourth metal layer through via interconnects and toward the passive device 107, extend upward from the third metal layer and through via interconnects toward the second metal layer, extend upward through via interconnects toward the first metal layer, and extend toward the integrated device 103. It should be noted that a portion of the circuit path 632 between the second metal layer and the first metal layer does not contact the power interconnects on the second metal layer.

[0082] The circuit path 652 between the power management integrated circuit (PMIC) 601, the integrated device 105, and the passive device 109 includes a second plurality of interconnects that extend through the second metal layer, extend downward toward the third metal layer through via interconnects, extend downward toward the fourth metal layer through via interconnects, extend along the fourth metal layer and toward the passive device 109, extend upward from the fourth metal layer and through via interconnects toward the third metal layer, extend upward through via interconnects toward the second metal layer, extend upward through via interconnects toward the first metal layer, and extend toward the integrated device 105. It should be noted that a portion of the circuit path 652 between the second metal layer and the first metal layer does not contact the power interconnects on the second metal layer.

[0083] Circuit path 632 and circuit path 652 can be configured to be coupled to each other through at least one power interconnect on the second metal layer. The power interconnect can be considered as part of circuit path 632 and / or circuit path 652. Circuit path 632 and circuit path 652 can be considered as part of the same circuit path.

[0084] Figure 7 Conceptually illustrates another example of a circuit path in substrate 602. In Figure 7 this case, the power interconnect can be located in the second metal layer (e.g., M2 layer). The power interconnect can be configured to be electrically coupled to a power management integrated circuit (PMIC) 601.

[0085] The circuit path 732 between the power management integrated circuit (PMIC) 601, integrated device 103, and passive device 107 includes a first plurality of interconnects that extend through the second metal layer, extend downward toward the third metal layer through via interconnects, extend along the third metal layer, extend downward toward the fourth metal layer through via interconnects and toward the passive device 107, extend upward from the third metal layer and through via interconnects toward the second metal layer, extend upward through via interconnects toward the first metal layer, and extend toward the integrated device 103. It should be noted that a portion of the circuit path 732 between the second metal layer and the first metal layer does not contact the power interconnect on the second metal layer.

[0086] The circuit path 752 between the power management integrated circuit (PMIC) 601, integrated device 105, and passive device 109 includes a second plurality of interconnects that extend through the second metal layer, extend downward toward the third metal layer through via interconnects, extend along the third metal layer, extend downward toward the fourth metal layer through via interconnects, extend along the fourth metal layer and toward the passive device 109, extend upward from the fourth metal layer and through via interconnects toward the third metal layer, extend upward through via interconnects toward the second metal layer, extend upward through via interconnects toward the first metal layer, and extend toward the integrated device 105. It should be noted that a portion of the circuit path 752 between the second metal layer and the first metal layer does not contact the power interconnect on the second metal layer.

[0087] Circuit path 732 and circuit path 752 can be configured to be coupled to each other through at least one power interconnect on the second metal layer. The power interconnect can be considered as part of circuit path 732 and / or circuit path 752. Circuit path 732 and circuit path 752 can be considered as part of the same circuit path.

[0088] Figure 8 Conceptually illustrates another example of a circuit path in substrate 602. In Figure 8In [the figure], the power interconnect may be located in a second metal layer (e.g., the M2 layer). The power interconnect may be configured to be electrically coupled to a power management integrated circuit (PMIC) 601.

[0089] The circuit path 832 between the power management integrated circuit (PMIC) 601, the integrated device 103, and the passive device 107 includes a first plurality of interconnects that extend through the second metal layer, extend downward toward the third metal layer through via interconnects, extend along the third metal layer, extend upward toward the second metal layer through via interconnects, extend along the second metal layer, extend downward toward the third metal layer through via interconnects, extend along the third metal layer, extend downward toward the fourth metal layer through via interconnects, extend along the fourth metal layer and extend toward the passive device 107, extend upward from the third metal layer and extend toward the second metal layer through via interconnects, extend upward toward the first metal layer through via interconnects, and extend toward the integrated device 103. It should be noted that a portion of the circuit path 832 between the second metal layer and the first metal layer does not contact the power interconnect on the second metal layer.

[0090] The circuit path 852 between the power management integrated circuit (PMIC) 601, the integrated device 105, and the passive device 109 includes a second plurality of interconnects that extend through the second metal layer, extend downward toward the third metal layer through via interconnects, extend downward toward the fourth metal layer through via interconnects, and extend toward the passive device 109, and extend upward from the second metal layer and extend toward the first metal layer through via interconnects, and extend toward the integrated device 105.

[0091] The circuit paths 832 and 852 may be configured to be coupled to each other through at least one interconnect (e.g., a power interconnect) on the second metal layer. The power interconnect may be considered as part of the circuit path 832 and / or the circuit path 852. The circuit paths 832 and 852 may be considered as part of the same circuit path.

[0092] In some specific embodiments, the power interconnect configured to be electrically coupled to the power management integrated circuit (PMIC) may be located on a metal layer different from at least Figures 6 to 8 the metal layers shown and described in [the figure].

[0093] Figure 9 Conceptually illustrates another example of a circuit path in the substrate 602. In Figure 9 [the figure], the power interconnect may be located in the fourth metal layer (e.g., the M4 layer). The power interconnect may be configured to be electrically coupled to a power management integrated circuit (PMIC) 601.

[0094] The circuit path 932 between the power management integrated circuit (PMIC) 601, the integrated device 103, and the passive device 107 includes a first plurality of interconnects that extend through the fourth metal layer, extend upward toward the third metal layer through via interconnects, extend along the third metal layer, extend downward toward the fourth metal layer through via interconnects, extend along the fourth metal layer, extend along the fourth metal layer, and extend toward the passive device 107, extend upward from the third metal layer and toward the second metal layer through via interconnects, extend upward toward the first metal layer through via interconnects, and extend toward the integrated device 103. It should be noted that a portion of the circuit path 932 between the fourth metal layer and the third metal layer may not contact the power interconnect on the fourth metal layer.

[0095] The circuit path 952 between the power management integrated circuit (PMIC) 601, the integrated device 105, and the passive device 109 includes a second plurality of interconnects that extend through the fourth metal layer, extend downward toward the passive device 109, and extend upward from the fourth metal layer and toward the third metal layer through via interconnects, extend upward toward the second metal layer through via interconnects, extend upward toward the first metal layer, and extend toward the integrated device 105.

[0096] The circuit path 932 and the circuit path 952 may be configured to be coupled to each other through at least one interconnect (e.g., a power interconnect) on the second metal layer. The power interconnect may be considered part of the circuit path 932 and / or the circuit path 952. The circuit path 932 and the circuit path 952 may be considered part of the same circuit path.

[0097] In some specific embodiments, the circuit path of power may include and / or extend through at least one ferrite bead (e.g., a ferrite bead device). The ferrite bead may be coupled to the board substrate and / or the package substrate. The ferrite bead (e.g., a ferrite bead device) may be a discrete component coupled to the board substrate and / or the package substrate through a plurality of solder interconnects. The ferrite bead may help increase the inductance. One or more ferrite beads may be coupled to the first surface of the substrate and / or the second surface of the substrate. One or more ferrite beads may be embedded in the substrate.

[0098] Figure 10 Circuit diagrams 1000 and 1010 are illustrated. Circuit diagram 1000 includes an integrated device 1003, an integrated device 1005, a passive device 107, a passive device 109, and a power management integrated circuit (PMIC) 601 coupled to a board substrate (e.g., 102, 202) or a package substrate (e.g., 302, 402). The integrated device 1003 may represent the integrated device 103 or the integrated device 303. The integrated device 1005 may represent the integrated device 105 and / or the integrated device 305.

[0099] Circuit diagram 1000 includes various inductances among various components. Using power interconnects helps to provide a low-impedance path for power, but can result in poor noise isolation between the shared power of integrated device 1003 and integrated device 1005. That is, the impact of power on one integrated device (e.g., 1003) can affect the power quality at another integrated device (e.g., 1005), and vice versa. To increase the noise isolation between the power to one integrated device and the power to another integrated device, the isolation inductances at LA3 and LV3 of circuit diagram 1000 can be increased. Extending the length of the circuit path through various metal layers (e.g., extending up and down one or more times) can increase the inductance of the circuit path. This method can improve power isolation and reduce the total power delivery noise from an aggressor on the shared power network (e.g., the shared interconnect for power) by providing improved isolation between the powers to different integrated devices (e.g., by adding inductance through the interconnect) and reducing the noise transfer between the integrated devices.

[0100] In circuit diagram 1000, integrated device 1003 is the aggressor, meaning that the noise generated in integrated device 1003 due to the activities of integrated device 1003 (such as turning on and off) or signal switching in the active mode affects the power provided to integrated device 1005 through the power interconnect. However, in some embodiments, integrated device 1005 can be the aggressor, meaning that the noise generated in integrated device 1005 due to the activities of integrated device 1005 (such as turning on and off) or signal switching in the active mode affects the power provided to integrated device 1003 through the power interconnect. Adding more inductance (e.g., increasing inductance LA3 and / or inductance LV3) to the circuit of circuit diagram 1000 can help isolate integrated device 1003 and integrated device 1005 such that integrated device 1003 does not affect integrated device 1005 due to the activities of integrated device 1003, and vice versa.

[0101] Circuit diagram 1010 includes integrated devices 303, integrated device 305, passive devices 107, and passive device 109 coupled to a package substrate (such as 302, 402) and a board substrate (such as 102, 202). Circuit diagram 1010 includes various inductances between various components. Using power interconnects helps provide a low-impedance path for power, but can result in poor noise isolation between the shared power of integrated device 303 and integrated device 305. That is, the effect of power on one integrated device (e.g., 303) can affect the power quality at another integrated device (e.g., 305), and vice versa. To increase the noise isolation between the power to one integrated device and the power to another integrated device, isolation inductors at LA3 and LV3 of circuit diagram 1010 can be increased. Extending the length of the circuit path through various metal layers (e.g., extending up and down one or more times) can increase the inductance of the circuit path. This method can improve power isolation and reduce the total power delivery noise from interfering parties on the shared power grid by providing improved isolation between the power to different integrated devices (e.g., by adding inductance through the interconnects) and reducing the noise transfer between the integrated devices.

[0102] In circuit diagram 1010, integrated device 303 is the interfering party, meaning that the noise generated in integrated device 303 due to the activities of integrated device 303 (such as turning on and off) or signal switching in the active mode affects the power provided to integrated device 305 through the power interconnect. However, in some specific implementations, integrated device 305 can be the interfering party, meaning that the noise generated in integrated device 305 due to the activities of integrated device 305 (such as turning on and off) or signal switching in the active mode affects the power provided to integrated device 303 through the power interconnect. Adding more inductance (e.g., increasing inductor LA3 and / or inductor LV3) to the circuit of circuit diagram 1010 can help isolate integrated device 303 and integrated device 305 such that integrated device 303 does not affect integrated device 305 due to the activities of integrated device 303, and vice versa.

[0103] In some specific implementations, point A and point B can conceptually represent the connection points of the added inductance in a circuit path. In some specific implementations, the circuit path between point A and point B can conceptually represent an added interconnect configured to provide inductance and / or additional inductance in the circuit path, including via interconnects. The added interconnect (e.g., via interconnect) helps to provide isolation. Point B can conceptually represent the connection to the lead, pin (e.g., capacitor pin), and / or terminal of the passive device 109, where point B contacts the lead, pin, and / or terminal of the passive device 109, which is the reason for inductance LV2 = 0. Point A can conceptually represent the coupling to the passive device 107. However, point A does not directly contact the lead, pin, and / or terminal of the passive device 107. It should be noted that point A and point B can be located in any metal layer. The added path between point A and point B increases the path length from an integrated device (e.g., 303, 1003) to an integrated device (e.g., 305, 1005) to increase the isolation between the two integrated devices.

[0104] It should be noted that multiple solder interconnects (e.g., ball grid array) can be used for one integrated device. It should also be noted that several capacitors (e.g., multiple decoupling capacitors (decap)) can be used for one integrated device. For example, Figure 10 CapA in can represent multiple decoupling capacitors in parallel. In addition, Figure 10 CapV in can represent multiple decoupling capacitors in parallel.

[0105] It should be noted that Figure 10 CapA and CapV in can each have inductance and resistance, but are not shown in the figure. For simplicity, it is assumed that CapA and CapV are lumped elements with ideal capacitance, but in the real world, there is inductance (e.g., lead inductance) and / or resistance in the capacitor.

[0106] The integrated device (e.g., 303, 1003) can represent multiple devices. One or more integrated devices can share CapA. The integrated device (e.g., 305, 1005) can represent several integrated devices. One or more integrated devices can share CapV.

[0107] Note that capacitors can be coupled to a substrate (e.g., a board substrate, a package substrate) in many different ways. For example, a capacitor can be coupled to the bottom surface of the substrate. Such a capacitor can be referred to as a land-side capacitor. In some specific embodiments, one or more capacitors can be coupled to the top surface of the substrate. Such a capacitor can be referred to as a die-side capacitor. In some specific embodiments, one or more capacitors can be coupled to the substrate such that the capacitor is embedded in and / or located within the substrate. Such a capacitor can be referred to as an embedded capacitor. In some specific embodiments, a combination of land-side capacitors, die-side capacitors, and / or embedded capacitors can be used. Examples of different arrangements and / or configurations of capacitors are further illustrated and described in at least Figures 17 to 19 below.

[0108] As described above, at least one ferrite bead (e.g., a ferrite toroid device) can be used in combination with the inductance added by the interconnects. The ferrite bead can be coupled to the board substrate and / or the package substrate. The ferrite bead (e.g., the ferrite bead device) can be a discrete component coupled to the board substrate and / or the package substrate through a plurality of solder interconnects. One or more ferrite beads can be coupled to the first surface of the substrate and / or the second surface of the substrate. One or more ferrite beads can be embedded in the substrate. The ferrite bead can help increase the isolation inductance between integrated devices.

[0109] Figure 11 illustrates Figure 10 how the circuit diagram 1000 in can correspond to the substrate 602, the integrated device 103, the integrated device 105, the passive device 107, and the passive device 109. For example, Figure 11 illustrates how LA3 and LV3 can be measured, and / or how LA1 can be measured. Figure 11 Points A and B of can correspond to points A and B of the circuit diagram 1000. The circuit diagram 1000 can be applicable to other configurations of the substrate, integrated devices, and passive devices shown and described in the present disclosure. Using additional via interconnects, additional pad interconnects, and / or additional trace interconnects in the circuit path helps create a more inductive path, which helps provide improved isolation without having to add and / or couple discrete inductors to the substrate (e.g., a board substrate, a package substrate), which helps reduce the total cost of the package. In some specific embodiments, 100 pH to 1.5 nH and / or greater isolation (L) can be achieved by adding and / or providing additional via interconnects, additional pad interconnects, and / or additional trace interconnects.

[0110] It should be noted that the specific embodiments of the additional via interconnects, pad interconnects, and / or trace interconnects used to extend the length of the circuit path are not limited to any particular substrate. In some specific embodiments, in Figures 1 to 9 and Figure 11The additional via interconnects, additional pad interconnects, and / or additional trace interconnects described herein may be implemented in a package substrate and / or a board substrate (e.g., a board, a printed circuit board). Accordingly, the concepts described for a package substrate may also be implemented in a board substrate. Similarly, the concepts described for a board substrate may also be implemented in a package substrate.

[0111] Figure 12 Illustrated are packages 1200 and 1210 coupled to a board 1202 (e.g., a board substrate). In this example, at least two packages share a power source. Package 1200 includes a package substrate 1230, integrated devices 103, 105, and an encapsulation layer 108. Similarly, package 1210 includes a package substrate 1230, integrated devices 103, 105, and an encapsulation layer 108. Package substrate 1230 includes at least one dielectric layer 1232 and a plurality of interconnects 1234.

[0112] Package 1200 is coupled to a first surface (e.g., a top surface) of board 1202 via a plurality of solder interconnects 110. Package 1210 is coupled to a first surface (e.g., a top surface) of board 1202 via a plurality of solder interconnects 1212. Board 1202 includes at least one board dielectric layer 1220 and a plurality of board interconnects 1222. Passive device 107 is coupled to a second surface (e.g., a bottom surface) of substrate 1202 via a plurality of solder interconnects 170. Passive device 109 is coupled to a second surface (e.g., a bottom surface) of substrate 1202 via a plurality of solder interconnects 190. Any of the circuit paths described above for Figures 1 to 9 and Figure 11 may be implemented in package substrate 1230 and / or board 1202 (e.g., a board substrate).

[0113] Figures 1 to 9 and Figures 11 to 12Two separate integrated devices that exemplify a shared power distribution network are shown. However, in some embodiments, a single integrated device having two or more processing cores may each have its own power requirements. In such cases, the processing cores of a single integrated device may share a power distribution network. The design and / or configuration of the shared power distribution network and its attendant circuit paths shown in this disclosure may be applicable to a single integrated device having multiple processing cores, each with its own power requirements. Thus, in the above example, a first circuit path may be configured to couple to a first processing core of integrated device 103, and a second circuit path may be configured to couple to a second processing core of integrated device 103. Additionally, the design and / or configuration of the shared power distribution network may be applicable to more than two integrated devices. For example, some embodiments may include a third integrated device and a third passive device that share a power distribution network with a first integrated device, a second integrated device, a first passive device, and a second passive device. It should be noted that various embodiments may use any combination of the configurations and / or designs described in this disclosure.

[0114] The above configuration is not limited to only two integrated devices. In some embodiments, the above configuration may be implemented using more than two integrated devices and more than two passive devices coupled to a board substrate and / or coupled to a package substrate. Additionally, more than two integrated devices may share a single power source. The concept of adding inductors as described in this disclosure may be applicable to other integrated devices that share a power source with at least one integrated device.

[0115] Exemplary processes for manufacturing substrates

[0116] In some embodiments, a manufacturing substrate includes several processes. Figures 13A to 13C Exemplary processes for providing or manufacturing a package (e.g., a package substrate) are illustrated. In some embodiments, the processes of Figures 13A to 13C may be used to provide or manufacture a substrate. However, the processes of Figures 13A to 13C may be used to manufacture any of the substrates described in this disclosure. In some embodiments, the processes of Figures 13A to 13C may be used and / or modified, or the modifications of Figures 13A to 13C may be used to manufacture board substrate 102 (e.g., a board, a printed circuit board).

[0117] It should be noted that Figures 13A to 13C the processes may combine one or more stages to simplify and / or clarify the processes for providing or manufacturing a substrate. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0118] As Figure 13AAs shown, Stage 1 illustrates the state after providing carrier 1300. Seed layer 1301 and interconnect 1302 may be located on carrier 1300. Interconnect 1302 may be located on seed layer 1301. A plating process and an etching process may be used to form interconnect 1302. In some embodiments, carrier 1300 may be provided with seed layer 1301 and a metal layer that is patterned to form interconnect 1302. Interconnect 1302 may represent at least some of the interconnects from among multiple interconnects 122.

[0119] Stage 2 illustrates the state after forming dielectric layer 1320 on carrier 1300, seed layer 1301, and interconnect 1302. A deposition process and / or a lamination process may be used to form dielectric layer 1320. Dielectric layer 1320 may include prepreg and / or polyimide. Dielectric layer 1320 may include a photoimageable dielectric. However, different embodiments may use different materials for dielectric layer 1320.

[0120] Stage 3 illustrates the state after forming multiple cavities 1310 in dielectric layer 1320. A lithography process or a laser process may be used to form multiple cavities 1310.

[0121] Stage 4 illustrates the state after forming interconnects 1312 in and on dielectric layer 1320 (including in and on multiple cavities 1310). For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0122] Stage 5 illustrates the state after forming dielectric layer 1322 on dielectric layer 1320 and interconnects 1312. A deposition process and / or a lamination process may be used to form dielectric layer 1322. Dielectric layer 1322 may include prepreg and / or polyimide. Dielectric layer 1322 may include a photoimageable dielectric. However, different embodiments may use different materials for dielectric layer 1322.

[0123] As Figure 13B shown, Stage 6 illustrates the state after forming multiple cavities 1330 in dielectric layer 1322. A lithography process or a laser process may be used to form multiple cavities 1330.

[0124] Stage 7 illustrates the state after forming interconnects 1314 in and on dielectric layer 1322 (including in and on multiple cavities 1330). For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0125] Stage 8 illustrates the state after forming dielectric layer 1324 over dielectric layer 1322 and interconnect 1312. Dielectric layer 1324 can be formed using a deposition process and / or a lamination process. Dielectric layer 1324 can include prepreg and / or polyimide. Dielectric layer 1324 can include a photoimageable dielectric. However, different embodiments can use different materials for the dielectric layer.

[0126] Stage 9 illustrates the state after forming a plurality of cavities 1340 in dielectric layer 1324. The plurality of cavities 1340 can be formed using a photolithography process (e.g., exposure and development) or a laser process.

[0127] As Figure 13C shown, stage 10 illustrates the state after forming interconnects 1316 in and over dielectric layer 1324 (including in and over the plurality of cavities 1340). For example, vias, pads, and / or traces can be formed. The interconnects can be formed using a plating process.

[0128] Stage 11 illustrates the state after decoupling (e.g., separating, removing, abrading) carrier 1300 from at least one dielectric layer 1320 and seed layer 1301, and removing (e.g., etching away) a portion of seed layer 1301 to leave substrate 402 including at least one dielectric layer 120 and a plurality of interconnects 122. The at least one dielectric layer 120 can represent dielectric layer 1320, dielectric layer 1322, and / or dielectric layer 1324. The plurality of interconnects 122 can represent interconnects 1302, 1312, 1314, and / or 1316.

[0129] Stage 12 illustrates the state after forming solder mask layer 140 and solder mask layer 142. Solder mask layer 140 and solder mask layer 142 can be formed using a lamination process and / or a deposition process.

[0130] Different embodiments can use different processes to form metal layers and / or interconnects. In some embodiments, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process can be used to form metal layers.

[0131] Exemplary processes for manufacturing substrates

[0132] In some embodiments, fabricating a substrate includes several processes. Figures 14A - 14C Illustrated are exemplary operations for providing or fabricating a substrate. In some embodiments, the Figures 14A to 14C operations can be used to provide or fabricate substrate 402. However, the Figures 14A to 14C processes can be used to fabricate any of the substrates described in the present disclosure.

[0133] It should be noted thatFigures 14A - 14C The operations may combine one or more stages to simplify and / or clarify the operations for providing or fabricating a substrate. In some specific implementations, the order of the processes may be changed or modified. In some specific implementations, one or more of these processes may be substituted or replaced without departing from the scope of the present disclosure.

[0134] As Figure 14A shown, Stage 1 illustrates the state after providing the core layer 420. The core layer 420 may include a seed layer 1402 on a first surface of the core layer 420 and a seed layer 1404 on a second surface of the core layer 420. The core layer 420 may be a dielectric layer.

[0135] Stage 2 illustrates the state after forming a plurality of cavities 1405 through the core layer 420, the seed layer 1402, and the seed layer 1404. A lithography process and / or a laser process may be used to form the plurality of cavities 1405.

[0136] Stage 3 illustrates the state after forming interconnects within and on the core layer 420. A plurality of core interconnects 422 may be formed in the plurality of cavities 1405. A plurality of interconnects 1412 may be formed above (e.g., over) a first surface of the core layer 420. The interconnect 1402 may be part of the plurality of interconnects 1412. A plurality of interconnects 1414 may be formed above (e.g., under) a second surface of the core layer 420. The seed layer 1404 may be part of the plurality of interconnects 1414. A mask process, a plating process, and / or an etching process may be used to form the plurality of core interconnects 422, the plurality of interconnects 1412, and / or the plurality of interconnects 1414.

[0137] Stage 4 illustrates the state after forming a dielectric layer 1420 above (e.g., over) a first surface of the core layer 420 and the plurality of interconnects 1412. Stage 4 also illustrates the state after forming a dielectric layer 1430 above (e.g., under) a second surface of the core layer 420 and the plurality of interconnects 1414. A deposition process and / or a lamination process may be used to form the dielectric layer 1420 and the dielectric layer 1430. The dielectric layer 1420 and the dielectric layer 1430 may be materials different from the core layer 420.

[0138] Stage 5 illustrates the state after forming a plurality of cavities 1421 in the dielectric layer 1420 and a plurality of cavities 1431 in the dielectric layer 1430. A lithography process may be used to form the plurality of cavities 1421 and the plurality of cavities 1431. A mask process, an exposure process, and / or a development process may be used to form the plurality of cavities 1421 and the plurality of cavities 1431.

[0139] As Figure 14BAs shown, stage 6 illustrates the state after forming interconnects among and on the surfaces of dielectric layer 1420 and dielectric layer 1430. A plurality of interconnects 1422 can be formed on the first surface of dielectric layer 1420 and above (e.g., over) a plurality of cavities 1421. A plurality of interconnects 1432 can be formed on the second surface of dielectric layer 1430 and above (e.g., under) a plurality of cavities 1431. A mask process, plating process, and / or etching process can be used to form the plurality of interconnects 1422 and / or the plurality of interconnects 1432.

[0140] Stage 7 illustrates the state after forming dielectric layer 1440 on the first surface of dielectric layer 1420 and above (e.g., over) a plurality of interconnects 1422. Stage 7 also illustrates the state after forming dielectric layer 1450 on the second surface of dielectric layer 1430 and above (e.g., under) a plurality of interconnects 1432. A deposition process and / or a lamination process can be used to form dielectric layer 1440 and dielectric layer 1440. Dielectric layer 1440 and / or dielectric layer 1450 can be the same dielectric layer as dielectric layer 1420 and / or dielectric layer 1430.

[0141] Stage 8 illustrates the state after forming a plurality of cavities 1441 in dielectric layer 1440 and a plurality of cavities 1451 in dielectric layer 1450. A lithography process can be used to form the plurality of cavities 1441 and the plurality of cavities 1451. A mask process, exposure process, and / or development process can be used to form the plurality of cavities 1441 and the plurality of cavities 1451. At least one dielectric layer 421 can represent dielectric layer 1420 and / or dielectric layer 1440. At least one dielectric layer 423 can represent dielectric layer 1430 and / or dielectric layer 1450.

[0142] As Figure 14C shown, stage 9 illustrates the state after forming interconnects among and on the surfaces of dielectric layer 1440 and dielectric layer 1450. A plurality of interconnects 1442 can be formed on the first surface of dielectric layer 1440 and above (e.g., over) a plurality of cavities 1441. A plurality of interconnects 1452 can be formed on the second surface of dielectric layer 1450 and above (e.g., under) a plurality of cavities 1451. A mask process, plating process, and etching process can be used to form the plurality of interconnects 1442 and / or the plurality of interconnects 1452. The plurality of interconnects 1422 and / or the plurality of interconnects 1442 can be represented by a plurality of interconnects 425, as shown at stage 10. The plurality of interconnects 1432 and / or the plurality of interconnects 1452 can be represented by a plurality of interconnects 425, as shown at stage 10. A plurality of core interconnects 422 can be part of the plurality of interconnects 425.

[0143] Stage 10 illustrates the state after the formation of solder mask layer 140 and solder mask layer 142. The solder mask layer 140 and the solder mask layer 142 can be formed using a lamination process and / or a deposition process.

[0144] Different embodiments can use different processes to form the metal layer and / or the interconnects. In some embodiments, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process can be used to form the metal layer.

[0145] Exemplary processes for manufacturing packages including substrates

[0146] In some embodiments, manufacturing the package includes several processes. Figures 15A to 15B Illustrated is an exemplary process for providing or manufacturing a package including a substrate. In some embodiments, Figures 15A to 15B the process can be used to provide or manufacture Figure 3 package 300. However, Figures 15A to 15B the process can be used to manufacture any of the packages described in the present disclosure.

[0147] It should be noted that Figures 15A to 15B the process can combine one or more stages to simplify and / or clarify the process for providing or manufacturing the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be replaced or substituted without departing from the scope of the present disclosure.

[0148] As Figure 15A shown, stage 1 illustrates the state after providing substrate 302. Substrate 302 includes a core layer 320, at least one dielectric layer 324, at least one dielectric layer 326, a plurality of interconnects 325, solder mask layer 140 and solder mask layer 142. In some embodiments, substrate 302 can be provided. Different implementations can use different substrates with different numbers of metal layers. The substrate can include a coreless substrate, a cored substrate, or an embedded trace substrate (ETS). Substrate 302 can be a package substrate.

[0149] Stage 2 illustrates the state after the integrated device 303 is coupled to the first surface (e.g., the top surface) of the substrate 302 through a plurality of solder interconnects 330. A solder reflow process can be used to couple the integrated device 303 to the substrate 302. Stage 2 also illustrates the state after the integrated device 305 is coupled to the first surface (e.g., the top surface) of the substrate 302 through a plurality of solder interconnects 350. A solder reflow process can be used to couple the integrated device 305 to the substrate 302.

[0150] Stage 3 illustrates the state after providing (e.g., forming) an encapsulation layer 108 over a substrate 302. The encapsulation layer 108 may encapsulate the integrated device 303 and the integrated device 305. The encapsulation layer 108 may include a molding, a resin, and / or an epoxy resin. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the encapsulation layer 108. The encapsulation layer 108 may be photo-etchable. The encapsulation layer 108 may be a component for encapsulation.

[0151] As Figure 15B shown, stage 4 illustrates the state after a passive device 107 is coupled to a second surface (e.g., bottom surface) of the substrate 302 through a plurality of solder interconnects 170. A solder reflow process may be used to couple the passive device 107 to the substrate 302. Stage 4 also illustrates the state after a passive device 109 is coupled to the second surface (e.g., bottom surface) of the substrate 302 through a plurality of solder interconnects 190. A solder reflow process may be used to couple the passive device 109 to the substrate 302.

[0152] Stage 5 illustrates the state after a plurality of solder interconnects 110 are coupled to the substrate 302. A solder reflow process may be used to couple the plurality of solder interconnects 110 to the substrate 302.

[0153] Exemplary flowchart of a method for manufacturing a package including a substrate

[0154] In some specific embodiments, manufacturing a package includes several processes. Figure 16 An exemplary flowchart of a method 1600 for providing or manufacturing a package including a substrate is illustrated. In some specific embodiments, Figure 16 the method 1600 may be used to provide or manufacture the Figure 3 package 300 described in the present disclosure. However, the method 1600 may be used to provide or manufacture any of the packages (e.g., 100, 200, 400, 500) described in the present disclosure.

[0155] It should be noted that Figure 16 the method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some specific embodiments, the order of the processes may be changed or improved.

[0156] The method (at 1605) provides a substrate (e.g., 302, 402). The substrate 302 can be provided by a vendor or fabricated. Different embodiments can use different processes to fabricate the substrate 302. Examples of processes that can be used to fabricate the substrate include semi-additive process (SAP) and modified semi-additive process (mSAP). The substrate 302 can be a package substrate. The substrate 302 includes a core layer 320, at least one dielectric layer 324, at least one dielectric layer 326, a plurality of interconnects 325, a solder mask layer 140, and a solder mask layer 142. In some embodiments, a board substrate 102 can be provided. Different implementations can use different substrates with different numbers of metal layers. The substrate can include a coreless substrate, a cored substrate, or an embedded trace substrate (ETS). In some embodiments, at least one dielectric layer can include a prepreg layer. Figure 15A Stage 1 of Figure 15A illustrates and describes an example of providing a package substrate.

[0157] The method (at 1610) couples an integrated device (e.g., 303) to a first surface of the substrate 302. For example, the integrated device 303 is coupled to a first surface (e.g., the top surface) of the substrate 302. The integrated device 303 is coupled to the substrate 302 through a plurality of solder interconnects 130. A solder reflow process can be used to couple the integrated device 103 to the substrate 302. The integrated device 305 is coupled to a first surface (e.g., the top surface) of the substrate 302. The integrated device 305 is coupled to the substrate 302 through a plurality of solder interconnects 150. A solder reflow process can be used to couple the integrated device 105 to the substrate 302. Figure 15A Stage 2 of Figure 15A illustrates and describes an example of coupling an integrated device to a package substrate.

[0158] The method (at 1615) forms an encapsulation layer (e.g., 108) over the substrate (e.g., 302). The encapsulation layer 108 can be provided and formed over and / or around the substrate 302 and the integrated devices 303 and 305. The encapsulation layer 108 can include a molding, a resin, and / or an epoxy resin. A compression molding process, a transfer molding process, or a liquid molding process can be used to form the encapsulation layer 108. The encapsulation layer 108 can be photo-etchable. The encapsulation layer 108 can be a component for encapsulation. Figure 15A Stage 3 of Figure 15A illustrates and describes an example of forming an encapsulation layer.

[0159] The method (at 1620) couples a passive device (e.g., 107) to a second surface of the substrate 302. For example, the passive device 107 is coupled to the second surface (e.g., bottom surface) of the substrate 302. The passive device 107 is coupled to the substrate 302 by a plurality of solder interconnects 170. A solder reflow process can be used to couple the passive device 107 to the substrate 302. The passive device 109 is coupled to the second surface (e.g., bottom surface) of the substrate 302. The passive device 109 is coupled to the substrate 302 by a plurality of solder interconnects 190. A solder reflow process can be used to couple the passive device 109 to the substrate 302. Figure 15B Stage 4 of Figure 15B illustrates and describes an example of coupling a passive device to a substrate.

[0160] The method (at 1625) couples a plurality of solder interconnects (e.g., 110) to the substrate 302. A solder reflow process can be used to couple the plurality of solder interconnects 110 to the substrate 302. Figure 15B Stage 5 of Figure 15B illustrates and describes an example of coupling solder interconnects to a substrate.

[0161] The packages (e.g., 300, 400, 500) described in this disclosure can be manufactured one at a time, or can be manufactured together (as part of one or more wafers) and then singulated into individual packages.

[0162] Exemplary board substrates and package substrates

[0163] Figure 17 Illustrated is a cross-sectional view of package 1700, which includes a substrate 402, integrated devices 303, 305, passive devices 107, 109, and an encapsulation layer 108. The integrated devices 303, 305, and the encapsulation layer 108 can be coupled to the substrate 402 in a manner similar to Figure 3 the encapsulation substrate 302 of Figure 3 . The integrated device 303 is coupled to the first surface (e.g., top surface) of the substrate 402 by a plurality of solder interconnects 330. The integrated device 305 is coupled to the first surface (e.g., top surface) of the substrate 402 by a plurality of solder interconnects 350. The passive device 107 is coupled to the first surface (e.g., top surface) of the substrate 402 by a plurality of solder interconnects 170. The passive device 109 is coupled to the first surface (e.g., top surface) of the substrate 402 by a plurality of solder interconnects 190. Thus, the passive devices 107 and 109 are on the same surface of the substrate 402 as the integrated devices 303 and 305. The passive devices 107 and 109 can be considered die-side passive devices.

[0164] Integrated devices 303, 305, passive devices 107, and 109 may be configured to be electrically coupled together via circuit path 1732. Circuit path 1732 may include multiple interconnects (e.g., a first plurality of interconnects, a second plurality of interconnects, a third plurality of interconnects) from multiple interconnects 425.

[0165] Circuit path 1732 may include multiple interconnects from multiple interconnects 425 that are configured to define at least one inductor by at least one interconnect on one metal layer, another interconnect on another metal layer, and at least one via interconnect. The inductor is integrated in package substrate 402 and is configured to be coupled to a power supply. The inductor may include one or more multiple windings (from interconnects) up and down two or more metal layers of package substrate 402. The inductor defined by at least one via interconnect (e.g., an additional via interconnect) may be positioned along the circuit path between passive device 107 and passive device 109. The inductor defined by at least one via interconnect (e.g., an additional via interconnect) may be positioned along the circuit path between integrated device 303 and integrated device 305. The inductor is positioned along a common path (e.g., a common circuit path) between integrated device 303 and integrated device 305 and between passive device 107 and passive device 109. Thus, additional windings (e.g., vertical windings and / or horizontal windings) of the interconnects that are part of the circuit path between passive device 107 and passive device 109 and part of the circuit path between integrated device 303 and integrated device 305 contribute to increasing the inductance, which helps reduce noise transfer between the integrated devices. Examples of the common path are illustrated and described in detail in Figure 5 Examples of the common path are illustrated and described in detail in

[0166] Figure 18 A cross-sectional view of configuration 1800 including board substrate 202, integrated devices 103, 105, passive devices 107, and 109 is illustrated. Integrated devices 103 and 105 may be coupled to board substrate 202 in a manner similar to Figure 1 board substrate 102.

[0167] The integrated device 103 is coupled to a first surface (e.g., the top surface) of the board substrate 202 by a plurality of solder interconnects 130. The integrated device 105 is coupled to a first surface (e.g., the top surface) of the board substrate 202 by a plurality of solder interconnects 150. The passive device 107 is coupled to a first surface (e.g., the top surface) of the board substrate 202 by a plurality of solder interconnects 170. The passive device 109 is coupled to a first surface (e.g., the top surface) of the board substrate 202 by a plurality of solder interconnects 190. Thus, the passive device 107 and the passive device 109 are located on the same surface of the board substrate 202 as the integrated device 103 and the integrated device 105. The passive device 107 and the passive device 109 can be considered die-side passive devices.

[0168] The integrated device 103, the integrated device 105, the passive device 107, and the passive device 109 can be configured to be electrically coupled together through a circuit path 1832. The circuit path 1832 can include a plurality of interconnects (e.g., a first plurality of interconnects, a second plurality of interconnects, a third plurality of interconnects) from the plurality of interconnects 122.

[0169] The circuit path 1832 can include a plurality of interconnects from the plurality of interconnects 122, which are configured to define at least one inductor by at least one interconnect on one metal layer, another interconnect on another metal layer, and at least one via interconnect. The inductor is integrated in the board substrate 202 and is configured to be coupled to a power supply. The inductor can include one or more complex windings (from interconnects) up and down two or more metal layers of the board substrate 202. The inductor defined by at least one via interconnect (e.g., an additional via interconnect) can be positioned along the circuit path between the passive device 107 and the passive device 109. The inductor defined by at least one via interconnect (e.g., an additional via interconnect) can be positioned along the circuit path between the integrated device 103 and the integrated device 105. The inductor is positioned along a common path (e.g., a common circuit path) between the integrated device 103 and the integrated device 105 and between the passive device 107 and the passive device 109. Thus, the additional windings (e.g., vertical windings and / or horizontal windings) of the interconnects that are part of the circuit path between the passive device 107 and the passive device 109 and part of the circuit path between the integrated device 103 and the integrated device 105 contribute to increasing the inductance, which helps reduce noise transfer between the integrated devices. Examples of the common path are exemplified and described in detail in at least Figure 5 Examples of the common path are exemplified and described in detail.

[0170] Figure 19Illustrates a cross-sectional view of package 1900, which includes substrate 402, integrated devices 303, integrated device 305, passive devices 107, passive device 109, and encapsulation layer 108. Integrated devices 303, integrated device 305, and encapsulation layer 108 may be coupled to substrate 402 in a manner similar to Figure 3 package substrate 302. Integrated device 303 is coupled to a first surface (e.g., top surface) of substrate 402 via a plurality of solder interconnects 330. Integrated device 305 is coupled to a first surface (e.g., top surface) of substrate 402 via a plurality of solder interconnects 350. Passive device 107 is coupled to substrate 402 such that passive device 107 is located within substrate 402. Passive device 109 is coupled to substrate 402 such that passive device 109 is located within substrate 402. Passive devices 107 and 109 may be considered embedded passive devices.

[0171] Integrated devices 303, integrated device 305, passive devices 107, and passive device 109 may be configured to be electrically coupled together via circuit path 1932. Circuit path 1932 may include a plurality of interconnects (e.g., a first plurality of interconnects, a second plurality of interconnects, a third plurality of interconnects) from a plurality of interconnects 425.

[0172] Circuit path 1932 may include a plurality of interconnects from a plurality of interconnects 425, which are configured to define at least one inductor by at least one interconnect on one metal layer, another interconnect on another metal layer, and at least one via interconnect. The inductor is integrated within package substrate 402 and is configured to be coupled to a power supply. The inductor may include one or more multiple windings (from interconnects) up and down two or more metal layers of package substrate 402. The inductor defined by at least one via interconnect (e.g., additional via interconnect) may be positioned along the circuit path between passive devices 107 and passive device 109. The inductor defined by at least one via interconnect (e.g., additional via interconnect) may be positioned along the circuit path between integrated devices 303 and integrated device 305. The inductor is positioned along a common path (e.g., common circuit path) between integrated devices 303 and integrated device 305 and between passive devices 107 and passive device 109. Thus, additional windings (e.g., vertical windings and / or horizontal windings) of the interconnects that are part of the circuit path between passive devices 107 and passive device 109 and part of the circuit path between integrated devices 303 and integrated device 305 contribute to increasing the inductance, which helps reduce noise transfer between the integrated devices. Examples of the common path are illustrated and described in detail in at least Figure 5 wherein.

[0173] Exemplary electronic devices

[0174] Figure 20 Illustrates various electronic devices that can be integrated with any one of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, mobile phone device 2002, laptop computer device 2004, fixed-position terminal device 2006, wearable device 2008, or motor vehicle 2010 may include device 2000 as described herein. For example, device 2000 can be any one of the devices and / or integrated circuit (IC) packages described herein. Figure 20 The devices 2002, 2004, 2006, and 2008 and vehicle 2010 illustrated in are merely exemplary. Other electronic devices may also feature device 2000, which includes but is not limited to a group of devices (e.g., electronic devices) including the following: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), global positioning system (GPS)-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-position data units (such as meter reading equipment), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions or any combination thereof.

[0175] Figures 1 to 12 、 Figures 13A to 13C 、 Figures 14A to 14C 、 Figures 15A to 15B and / or Figures 16 to 20 One or more of the components, processes, features, and / or functions illustrated in and / or may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figures 1 to 12 、 Figures 13A to 13C 、 Figures 14A to 14C 、 Figures 15A to 15B and / or Figures 16 to 20 and their corresponding descriptions in the present disclosure are not limited to dies and / or ICs. In some specific embodiments, Figures 1 to 12 、 Figures 13A to 13C 、 Figures 14A to 14C 、 Figures 15A to 15B and / or Figures 16 to 20And its corresponding description can be used to manufacture, produce, provide, and / or fabricate devices and / or integrated devices. In some specific implementations, the devices may include die, integrated devices, integrated passive devices (IPD), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, package-on-package (PoP) devices, heat sink devices, and / or interposers.

[0176] It should be noted that the drawings in the present disclosure may represent actual representations and / or conceptual representations of various components, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of each component and / or part in the drawings may be exemplary. In some specific implementations, each component and / or part in the drawings may be optional.

[0177] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any particular implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of the present disclosure. Similarly, the term "aspect" does not require that all aspects of the present disclosure include the described features, advantages, or modes of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects (e.g., a mechanical coupling). For example, if object A physically contacts object B, and object B contacts object C, then objects A and C may still be considered to be coupled to each other even if they are not in direct physical contact with each other. Object A that is coupled to object B may be coupled to at least a portion of object B. The term "electrically coupled" may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., a signal, power, ground) can be transferred between the two objects. Two objects that are electrically coupled may or may not have an electric current flowing between the two objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything above the fourth) is arbitrary. Any of the described components can be the first component, the second component, the third component, or the fourth component. For example, a component that is referred to as the second component can be the first component, the second component, the third component, or the fourth component. The terms "enclose", "enclosing", and / or any derivatives thereof mean that an object can partially enclose or fully enclose another object. The terms "top" and "bottom" are arbitrary. A component located at the top can be above a component located at the bottom. The top component can be considered the bottom component, and vice versa. As described in the present disclosure, a first component located "above" a second component can mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component can be above (e.g., on top of) a first surface of the second component, while a third component can be above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It should also be noted that, as used in the context of one component being on another component in the present application, the term "above" can be used to indicate that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component being above a second component can mean: (1) the first component is above the second component but does not directly contact the second component; (2) the first component is above (e.g., on the surface of) the second component; and / or (3) the first component is in (e.g., embedded in) the second component. A first component located "in" a second component can be partially located in the second component or fully located in the second component. A value of about X to XX can refer to a value between X and XX, including X and XX. The values between X and XX can be discrete or continuous. As used in the present disclosure, the term "about 'value X'" or "substantially value X" means within 10 percent of 'value X'.For example, a value of about 1 or approximately 1 will mean a value in the range of 0.9 to 1.1.

[0178] In some specific embodiments, an interconnect is an element or component in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some specific embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some specific embodiments, an interconnect may include a conductive material that may be configured to provide a circuit path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different specific embodiments may use different processes and / or procedures to form an interconnect. In some specific embodiments, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spraying, and / or plating processes may be used to form an interconnect.

[0179] It should also be noted that the various disclosures herein may be described as processes depicted as operation diagrams, flowcharts, structure diagrams, or block diagrams. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0180] Further examples are described below to facilitate understanding of the present disclosure.

[0181] Aspect 1: A device, the device comprising: a substrate including at least one dielectric layer; and a plurality of interconnects formed on at least a plurality of metal layers of the substrate, wherein the plurality of metal layers include a first metal layer and a second metal layer, wherein the plurality of interconnects include power interconnects, and wherein the power interconnects are configured to be electrically coupled to a power source. The device includes: a first integrated device coupled to a first surface of the substrate; a second integrated device coupled to the first surface of the substrate; a first passive device coupled to the substrate; and a second passive device coupled to the substrate. The first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnects through a first plurality of interconnects from the plurality of interconnects. At least one interconnect from the first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to a power source, wherein the first plurality of interconnects includes a first interconnect located on the first metal layer, a second interconnect located on the second metal layer, and a via interconnect coupling the first interconnect and the second interconnect.

[0182] Aspect 2: The apparatus according to aspect 1, wherein the substrate comprises a board substrate or a package substrate.

[0183] Aspect 3: The apparatus according to aspects 1 to 2, wherein the first passive device is coupled to the first surface of the substrate, and wherein the second passive device is coupled to the first surface of the substrate.

[0184] Aspect 4: The apparatus according to aspects 1 to 2, wherein the first passive device is coupled to the second surface of the substrate, and wherein the second passive device is coupled to the second surface of the substrate.

[0185] Aspect 5: The apparatus according to aspects 1 to 2, wherein the first passive device is located in the substrate, and wherein the second passive device is located in the substrate.

[0186] Aspect 6: The apparatus according to aspects 1 to 5, wherein the inductor is positioned along a common circuit path between the first integrated device, the second integrated device, the first passive device, and the second passive device.

[0187] Aspect 7: The apparatus according to aspects 1 to 6, wherein the first integrated device and the second integrated device are configured to share a common power source.

[0188] Aspect 8: The apparatus according to aspect 7, the apparatus further comprising: a power management integrated circuit (PMIC) configured to provide the common power source for the first integrated device and the second integrated device.

[0189] Aspect 9: The apparatus according to aspects 1 to 8, wherein the first passive device comprises a first capacitor, and wherein the second passive device comprises a second capacitor.

[0190] Aspect 10: The apparatus according to aspects 1 to 9, wherein the apparatus is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0191] Aspect 11: An apparatus, the apparatus comprising: a board substrate; a first integrated device coupled to a first surface of the board substrate; a second integrated device coupled to the first surface of the board substrate; a first passive device coupled to a second surface of the board substrate; and a second passive device coupled to the second surface of the board substrate. The board substrate includes at least one dielectric layer; and a plurality of interconnects formed on at least a plurality of metal layers of the board substrate. The plurality of metal layers includes a first metal layer and a second metal layer. The plurality of interconnects includes power interconnects. The power interconnects are configured to be electrically coupled to a power supply. The first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnects through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to a power supply, wherein the first plurality of interconnects includes a first interconnect located on the first metal layer, a second interconnect located on the second metal layer, and a via interconnect coupling the first interconnect and the second interconnect.

[0192] Aspect 12: The apparatus according to aspect 11, wherein the first plurality of interconnects includes a common circuit path located between the first integrated device, the second integrated device, the first passive device, and the second passive device, wherein the first plurality of interconnects includes a plurality of interconnects located on the first metal layer, a plurality of interconnects located on the second metal layer, and a plurality of via interconnects located between the first metal layer and the second metal layer, and wherein the first plurality of interconnects is capable of defining a plurality of windings of the inductor.

[0193] Aspect 13: The apparatus according to aspects 11 to 12, wherein the first integrated device and the second integrated device share power provided through the power interconnects.

[0194] Aspect 14: The apparatus according to aspects 11 to 13, wherein the first metal layer is different from the second metal layer, and wherein the first metal layer can be any metal layer of the board substrate.

[0195] Aspect 15: The apparatus according to aspects 11 to 13, wherein the first metal layer is different from the second metal layer, and wherein the second metal layer can be any metal layer of the board substrate.

[0196] Aspect 16: The apparatus according to aspects 11 to 15, the apparatus further comprising: a power management integrated circuit coupled to the board substrate, wherein the power management integrated circuit is configured to be coupled to the inductor through the power interconnect.

[0197] Aspect 17: The apparatus according to aspects 11 to 16, the apparatus further comprising: a ferrite bead device coupled to the board substrate.

[0198] Aspect 18: The apparatus according to aspects 11 to 17, wherein the plurality of metal layers further comprises a third metal layer and a fourth metal layer, wherein the first plurality of interconnects includes a plurality of interconnects located on the first metal layer, a plurality of interconnects located on the second metal layer, a plurality of via interconnects located between the first metal layer and the second metal layer, a plurality of interconnects located on the third metal layer, a plurality of via interconnects located between the second metal layer and the third metal layer, a plurality of interconnects located on the fourth metal layer, and a plurality of interconnects located between the third metal layer and the fourth metal layer, and wherein the first plurality of interconnects is capable of defining a plurality of windings of the inductor.

[0199] Aspect 19: The apparatus according to aspects 11 to 18, wherein the plurality of interconnects includes a plurality of trace interconnects configured to provide at least one circuit path for input / output signals, and wherein the power interconnect has a width greater than the width of the plurality of trace interconnects configured to provide input / output signals.

[0200] Aspect 20: The apparatus according to aspect 19, wherein the width of the power interconnect is at least 50% greater than the width of the plurality of trace interconnects.

[0201] Aspect 21: A device, the device comprising: a package substrate; a first integrated device coupled to a first surface of the package substrate; a second integrated device coupled to the first surface of the package substrate; a first passive device coupled to a second surface of the package substrate; and a second passive device coupled to the second surface of the package substrate. The package substrate includes at least one dielectric layer; and a plurality of interconnects formed on at least a plurality of metal layers of the package substrate. The plurality of metal layers includes a first metal layer and a second metal layer. The plurality of interconnects includes power interconnects. The power interconnects are configured to be electrically coupled to a power supply. The first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnects through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to a power supply, wherein the first plurality of interconnects includes a first interconnect located on the first metal layer, a second interconnect located on the second metal layer, and a via interconnect coupling the first interconnect and the second interconnect.

[0202] Aspect 22: The device according to aspect 21, wherein the first plurality of interconnects includes a common circuit path located between the first integrated device, the second integrated device, the first passive device, and the second passive device, wherein the first plurality of interconnects includes a plurality of interconnects located on the first metal layer, a plurality of interconnects located on the second metal layer, and a plurality of via interconnects located between the first metal layer and the second metal layer, and wherein the first plurality of interconnects is capable of defining a plurality of windings of the inductor.

[0203] Aspect 23: The device according to aspects 21 to 22, wherein the first integrated device and the second integrated device share power provided through the power interconnects.

[0204] Aspect 24: The device according to aspects 21 to 23, wherein the first metal layer is different from the second metal layer, and wherein the first metal layer can be any metal layer of the package substrate.

[0205] Aspect 25: The device according to aspects 21 to 23, wherein the first metal layer is different from the second metal layer, and wherein the second metal layer can be any metal layer of the package substrate.

[0206] Aspect 26: The apparatus according to aspects 21 to 25, the apparatus further comprising: a power management integrated circuit coupled to the package substrate, wherein the power management integrated circuit is configured to be coupled to the inductor through the power interconnect.

[0207] Aspect 27: The apparatus according to aspects 21 to 26, the apparatus further comprising: a ferrite bead device coupled to the package substrate.

[0208] Aspect 28: The apparatus according to aspects 21 to 27, wherein the plurality of metal layers further comprises a third metal layer and a fourth metal layer, wherein the first plurality of interconnects includes a plurality of interconnects located on the first metal layer, a plurality of interconnects located on the second metal layer, a plurality of via interconnects located between the first metal layer and the second metal layer, a plurality of interconnects located on the third metal layer, a plurality of via interconnects located between the second metal layer and the third metal layer, a plurality of interconnects located on the fourth metal layer, and a plurality of interconnects located between the third metal layer and the fourth metal layer, and wherein the first plurality of interconnects is capable of defining a plurality of windings of the inductor.

[0209] Aspect 29: The apparatus according to aspects 21 to 28, wherein the plurality of interconnects includes a plurality of trace interconnects configured to provide at least one circuit path for input / output signals, and wherein the power interconnect has a width greater than the width of the plurality of trace interconnects configured to provide input / output signals.

[0210] Aspect 30: The apparatus according to aspect 29, wherein the width of the power interconnect is at least 50% greater than the width of the plurality of trace interconnects.

[0211] The various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not to limit the scope of the appended claims. Thus, the teachings can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An apparatus, the apparatus comprising: a substrate, the substrate comprising: at least one dielectric layer; and a plurality of interconnects formed on at least a plurality of metal layers of the substrate, wherein the plurality of metal layers includes a first metal layer and a second metal layer, wherein the plurality of interconnects includes power interconnects, and wherein the power interconnects are configured to be electrically coupled to a power source; a first integrated device coupled to a first surface of the substrate; a second integrated device coupled to the first surface of the substrate; a first passive device coupled to the substrate; and a second passive device coupled to the substrate, wherein the first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnects via a first plurality of interconnects from the plurality of interconnects, and wherein at least one interconnect from the first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to a power source, wherein the first plurality of interconnects includes a first interconnect located on the first metal layer, a second interconnect located on the second metal layer, and a via interconnect coupling the first interconnect and the second interconnect.

2. The apparatus according to claim 1, wherein the substrate includes a board substrate or a package substrate.

3. The apparatus according to claim 1, wherein the first passive device is coupled to the first surface of the substrate, and wherein the second passive device is coupled to the first surface of the substrate.

4. The apparatus according to claim 1, wherein the first passive device is coupled to a second surface of the substrate, and wherein the second passive device is coupled to the second surface of the substrate.

5. The apparatus according to claim 1, wherein the first passive device is located within the substrate, and wherein the second passive device is located within the substrate.

6. The apparatus according to claim 1, wherein the inductor is positioned along a common circuit path between the first integrated device, the second integrated device, the first passive device, and the second passive device.

7. The apparatus according to claim 1, wherein the first integrated device and the second integrated device are configured to share a common power source.

8. The device according to claim 7, wherein the device further comprises: A power management integrated circuit (PMIC), the power management integrated circuit (PMIC) being configured to provide the common power source for the first integrated device and the second integrated device.

9. The apparatus according to claim 1, wherein the first passive device includes a first capacitor, and wherein the second passive device includes a second capacitor.

10. The device according to claim 1, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

11. A device, the device comprising: a board substrate, the board substrate comprising: at least one dielectric layer; and a plurality of interconnects formed on at least a plurality of metal layers of the board substrate, wherein the plurality of metal layers includes a first metal layer and a second metal layer, wherein the plurality of interconnects includes power interconnects, and wherein the power interconnects are configured to be electrically coupled to a power source; a first integrated device coupled to a first surface of the board substrate; a second integrated device coupled to the first surface of the board substrate; a first passive device coupled to a second surface of the board substrate; and a second passive device coupled to the second surface of the board substrate, wherein the first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnects through a first plurality of interconnects from the plurality of interconnects, and wherein the first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to a power source, wherein the first plurality of interconnects includes a first interconnect located on the first metal layer, a second interconnect located on the second metal layer, and a via interconnect coupling the first interconnect and the second interconnect.

12. The device according to claim 11, wherein the first plurality of interconnects includes a common circuit path between the first integrated device, the second integrated device, the first passive device, and the second passive device, wherein the first plurality of interconnects includes a plurality of interconnects located on the first metal layer, a plurality of interconnects located on the second metal layer, and a plurality of via interconnects located between the first metal layer and the second metal layer, and wherein the first plurality of interconnects is capable of defining a plurality of windings of the inductor.

13. The device according to claim 11, wherein the first integrated device and the second integrated device share power provided through the power interconnects.

14. The device according to claim 11, wherein the first metal layer is different from the second metal layer, and wherein the first metal layer can be any metal layer of the board substrate.

15. The device according to claim 11, wherein the first metal layer is different from the second metal layer, and wherein the second metal layer can be any metal layer of the board substrate.

16. The device according to claim 11, wherein the device further comprises: A power management integrated circuit coupled to the board substrate, wherein the power management integrated circuit is configured to be coupled to the inductor through the power interconnects.

17. The device according to claim 11, wherein the device further comprises: A ferrite bead device, the ferrite bead device being coupled to the board substrate.

18. The device according to claim 11, wherein the plurality of metal layers further includes a third metal layer and a fourth metal layer, wherein the first plurality of interconnects includes a number of interconnects on the first metal layer, a number of interconnects on the second metal layer, a number of via interconnects between the first metal layer and the second metal layer, a number of interconnects on the third metal layer, a number of via interconnects between the second metal layer and the third metal layer, a number of interconnects on the fourth metal layer, and a number of interconnects between the third metal layer and the fourth metal layer, and wherein the first plurality of interconnects is capable of defining a number of windings of the inductor.

19. The device according to claim 11, wherein the plurality of interconnects includes a plurality of trace interconnects configured to provide at least one circuit path for input / output signals, and wherein the power interconnect has a width greater than the width of the plurality of trace interconnects configured to provide input / output signals.

20. The device according to claim 19, wherein the width of the power interconnect is at least 50% greater than the width of the plurality of trace interconnects.

21. A device, the device comprising: A package substrate, the package substrate including: At least one dielectric layer; and A plurality of interconnects formed on at least a plurality of metal layers of the package substrate, wherein the plurality of metal layers includes a first metal layer and a second metal layer, wherein the plurality of interconnects includes power interconnects, and wherein the power interconnects are configured to be electrically coupled to a power supply; A first integrated device coupled to a first surface of the package substrate; A second integrated device coupled to the first surface of the package substrate; A first passive device coupled to a second surface of the package substrate; and A second passive device coupled to the second surface of the package substrate, wherein the first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnects through a first plurality of interconnects from the plurality of interconnects, and wherein the first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to a power supply, wherein the first plurality of interconnects includes a first interconnect on the first metal layer, a second interconnect on the second metal layer, and a via interconnect coupled to the first interconnect and the second interconnect.

22. The device according to claim 21, wherein the first plurality of interconnects includes a common circuit path between the first integrated device, the second integrated device, the first passive device, and the second passive device, Wherein the first plurality of interconnects includes a plurality of interconnects located on the first metal layer, a plurality of interconnects located on the second metal layer, and a plurality of via interconnects located between the first metal layer and the second metal layer, and wherein the first plurality of interconnects is capable of defining a plurality of windings of the inductor.

23. The apparatus according to claim 21, wherein the first integrated device and the second integrated device share power configured to be provided through the power interconnects.

24. The apparatus according to claim 21, wherein the first metal layer is different from the second metal layer, and wherein the first metal layer can be any metal layer of the package substrate.

25. The apparatus according to claim 21, wherein the first metal layer is different from the second metal layer, and wherein the second metal layer can be any metal layer of the package substrate.

26. The device according to claim 21, wherein the device further comprises: A power management integrated circuit, the power management integrated circuit being coupled to the package substrate, wherein the power management integrated circuit is configured to be coupled to the inductor through the power interconnects.

27. The apparatus according to claim 21, the apparatus further comprising: A ferrite bead device, the ferrite bead device being coupled to the package substrate.

28. The apparatus according to claim 21, wherein the plurality of metal layers further includes a third metal layer and a fourth metal layer, wherein the first plurality of interconnects includes a plurality of interconnects located on the first metal layer, a plurality of interconnects located on the second metal layer, a plurality of via interconnects located between the first metal layer and the second metal layer, a plurality of interconnects located on the third metal layer, a plurality of via interconnects located between the second metal layer and the third metal layer, a plurality of interconnects located on the fourth metal layer, and a plurality of interconnects located between the third metal layer and the fourth metal layer, and wherein the first plurality of interconnects is capable of defining a plurality of windings of the inductor.

29. The apparatus according to claim 21, wherein the plurality of interconnects includes a plurality of trace interconnects configured to provide at least one circuit path for input / output signals, and wherein the power interconnect has a width greater than the width of the plurality of trace interconnects configured to provide input / output signals.

30. The apparatus according to claim 29, wherein the width of the power interconnect is at least 50% greater than the width of the plurality of trace interconnects.

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