Low residual voltage ESD device and preparation method thereof

Abstract

The invention discloses a low residual voltage ESD device and a preparation method thereof, and the preparation method comprises the steps: providing a P-type substrate, and exposing an N-type injection region and a P-type injection region through a mask layer; injecting inert ions into the N-type injection region and the P-type injection region at the same time to form an amorphous structure layer; injecting phosphorus ions into the N-type injection region, forming an N-type trigger region on the surface of the amorphous structure layer in the N-type injection region, injecting boron ions into the P-type injection region, and forming a P-type anode region on the surface of the amorphous structure layer in the P-type injection region; annealing the P-type substrate for multiple times, and manufacturing a passivation layer on the surface of the P-type substrate; and etching and trepanning the passivation layer to obtain a contact hole to expose the surfaces of the N-type injection region and the P-type injection region, and growing an electrode layer in the contact hole to obtain the low-residual-voltage ESD device. According to the invention, the ultra-shallow junction is formed through the amorphous structure layer and low-energy ion implantation, so that the on-resistance of the ESD device can be greatly reduced, and the residual voltage of the voltage clamp is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly relates to a low-residual voltage ESD device and a preparation method thereof. Background Art

[0002] As the semiconductor process node enters below 7nm, the core voltage of the chip drops to 1V or even below 0.8V, but the clamping residual voltage of traditional ESD devices (such as diodes, SCRs) is usually higher than 5V.

[0003] In advanced processes, the thickness of the gate oxide layer is only a few angstroms, and the breakdown voltage may be lower than 2V. The residual voltage (5V) of traditional ESD devices far exceeds this threshold, resulting in the failure of protection. For example, in the fabrication of FinFETs with a 7nm process, the breakdown voltage of the NMOS gate oxide is about 1.8V. If the residual voltage of the ESD device is 5V, the electrostatic shock will directly break down the gate oxide, causing permanent damage.

[0004] Therefore, in the prior art, there is also a problem that when an ESD device is applied to a circuit, it cannot quickly discharge a large current when subjected to a large current impact, resulting in device damage and protection failure. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a low-residual voltage ESD device and a preparation method thereof, aiming to solve the above problems recorded in the background art.

[0006] One aspect of the present invention is to provide a preparation method of a low-residual voltage ESD device, and the preparation method includes: Providing a P-type substrate; Coating a photoresist on the surface of the P-type substrate, exposing and developing to obtain a mask layer, exposing N-type implantation regions and P-type implantation regions that are separated from each other; Simultaneously implanting inert ions into the N-type implantation region and the P-type implantation region of the P-type substrate to form an amorphous structure layer; Implanting phosphorus ions into the N-type implantation region to form an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region, and implanting boron ions into the P-type implantation region to form a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region, and removing the mask layer; Performing multiple annealing treatments on the P-type substrate, and fabricating a passivation layer on the surface of the P-type substrate; Etching openings in the passivation layer to obtain contact holes to expose the surfaces of the N-type implantation region and the P-type implantation region, and growing an electrode layer in the contact holes to obtain a low-residual voltage ESD device.

[0007] According to one aspect of the above technology, the step of simultaneously implanting inert ions into the N-type implantation region and the P-type implantation region of the P-type substrate to form an amorphous structure layer includes: Simultaneously implanting silicon ions into the N-type implantation region and the P-type implantation region of the P-type substrate to form an amorphous structure layer; Among them, the implantation energy of silicon ion implantation into the N-type implantation region and the P-type implantation region is 16 keV - 24 keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 .

[0008] According to one aspect of the above technology, in the step of implanting phosphorus ions into the N-type implantation region to form an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region, the implantation energy of phosphorus ion implantation is 3 keV - 4 keV, and the implantation dose is 1×10 15 cm -2 -3×10 15 cm -2 ; In the step of implanting boron ions into the P-type implantation region to form a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region, the implantation energy of boron ion implantation is 1 keV - 4 keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 .

[0009] According to one aspect of the above technology, the step of performing multiple annealing treatments on the P-type substrate and fabricating a passivation layer on the surface of the P-type substrate includes: Performing a first annealing treatment on the P-type substrate according to preset first process parameters, and performing a second annealing treatment according to preset second process parameters after the first annealing treatment ends; In a hydrogen atmosphere, performing a third annealing treatment on the P-type substrate according to preset third process parameters, and fabricating a passivation layer on the surface of the P-type substrate.

[0010] According to one aspect of the above technology, the step of performing a first annealing treatment on the P-type substrate according to preset first process parameters and performing a second annealing treatment according to preset second process parameters after the first annealing treatment ends includes: In a nitrogen atmosphere, performing a first annealing treatment on the P-type substrate according to preset first process parameters, and performing a second annealing treatment according to preset second process parameters after the first annealing treatment ends; Among them, in the first process parameters, the first annealing temperature is 550°C - 630°C, and the first annealing time is 25s - 40s. In the second process parameters, the second annealing temperature is 960°C - 1080°C, and the second annealing time is 1s - 3s.

[0011] According to one aspect of the above technology, in a hydrogen atmosphere, in the step of performing a third annealing treatment on the P-type substrate according to preset third process parameters and fabricating a passivation layer on the surface of the P-type substrate, in the third process parameters, the third annealing temperature is 370°C - 420°C, and the third annealing time is 12 min - 15 min.

[0012] According to one aspect of the above technology, the passivation layer is an overlapping structure of Si3N4 / SiO2, and the thickness is 60 nm - 80 nm.

[0013] According to one aspect of the above technology, the step of etching openings in the passivation layer to obtain contact holes to expose the surfaces of the N-type implantation region and the P-type implantation region, and growing an electrode layer in the contact holes to obtain a low-residual-voltage ESD device includes: Etching windows in the passivation layer to obtain an N-pole contact hole and a P-pole contact hole to respectively expose the surfaces of the N-type implantation region and the P-type implantation region; Simultaneously depositing VO2 material in the N-pole contact hole and the P-pole contact hole onto the surfaces of the N-type implantation region and the P-type implantation region, and etching to form an electrode finger structure; Sputtering Pt material on the electrode finger structure and photolithographing to form a thermosensitive electrode layer with a curved structure to obtain a low-residual-voltage ESD device.

[0014] Another aspect of the present invention is to provide a low-residual-voltage ESD device prepared by the preparation method described in the above technical solution.

[0015] Compared with the prior art, the beneficial effects of using the low-residual-voltage ESD device and its preparation method shown in the present invention are as follows: By implanting inert ions into the N-type implantation region and the P-type implantation region of the P-type substrate in the present invention to form an amorphous structure layer, then performing phosphorus ion implantation into the N-type implantation region to form an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region, and performing boron ion implantation into the P-type implantation region to form a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region, a ultra-shallow junction is formed through the amorphous structure layer and low-energy ion implantation, which can greatly reduce the on-resistance of the ESD device, reduce the voltage clamping residual voltage, and through the cooperation of the ultra-shallow junction and the low-resistance electrode layer, the ESD device can quickly discharge a large current under a nanosecond-level ESD pulse, thereby better protecting circuit devices. Description of the Drawings

[0016] The above and / or additional aspects and advantages of the present invention will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, where: Figure 1 It is a schematic flow chart of a preparation method of a low-residual-voltage ESD device in an embodiment of the present invention; Figure 2 It is a schematic structural diagram of the preparation process of a low-residual-voltage ESD device in an embodiment of the present invention; Explanation of the symbols of the components in the drawings: P-type substrate 10, mask layer 20, N-type implantation region 30, N-region amorphous structure layer 31, N-type trigger region 32, P-type implantation region 40, P-region amorphous structure layer 41, P-type anode region 42, passivation layer 50, N-region contact hole 51, P-region contact hole 52, electrode layer 60, N-region electrode 61, P-region electrode 62. Detailed implementation manners

[0017] To make the objectives, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific implementation manners of the present invention is provided in conjunction with the drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0018] It should be noted that when an element is referred to as being "fixed on" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right", and similar expressions used herein are only for the purpose of illustration.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used herein in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0020] Embodiment 1 Please refer to Figure 1 And Figure 2 , the first embodiment of the present invention provides a preparation method of a low-residual-voltage ESD device for manufacturing a low-residual-voltage ESD device. It should be noted that in this embodiment, the ESD device belongs to an SCR-type device, and the preparation method includes steps S10 - step S60: Step S10, provide a P-type substrate.

[0021] In this embodiment, the P-type substrate 10 is made of a wide-bandgap material (such as SiC, GaN) or a low-resistivity silicon-based material (such as SOI) to reduce the on-resistance of the device, thereby reducing the residual voltage of the device.

[0022] Preferably, in this embodiment, the P-type substrate 10 is made of SiC material.

[0023] Step S20: Coating photoresist on the surface of the P-type substrate, exposing and developing to obtain a mask layer, exposing the mutually separated N-type implantation regions and P-type implantation regions.

[0024] In this embodiment, before coating photoresist on the surface of the P-type substrate 10, it is first necessary to soak and rinse the P-type substrate 10 with deionized water, and then dry it to improve the cleanliness of the P-type substrate 10.

[0025] Furthermore, photoresist is coated on the surface of the P-type substrate 10 in the epitaxial growth direction, specifically by spin-coating photoresist, and then exposed and developed to obtain a mask layer 20 attached to the surface of the P-type substrate 10, and the mutually separated N-type implantation regions 30 and P-type implantation regions 40 in the P-type substrate 10 are exposed.

[0026] Among them, the number of both the N-type implantation regions 30 and the P-type implantation regions 40 can be multiple.

[0027] Step S30: Simultaneously implant inert ions into the N-type implantation regions and P-type implantation regions of the P-type substrate to form an amorphous structure layer.

[0028] In this embodiment, the step of simultaneously implanting inert ions into the N-type implantation regions 30 and P-type implantation regions 40 of the P-type substrate 10 to form an amorphous structure layer includes: Simultaneously implanting silicon ions into the N-type implantation regions 30 and P-type implantation regions 40 of the P-type substrate 10 to form an amorphous structure layer; Among them, the implantation energy of silicon ion implantation into the N-type implantation regions 30 and P-type implantation regions 40 is 16 keV - 24 keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 .

[0029] Specifically, using silicon ions as dopants to perform silicon ion implantation on the N-type implantation regions 30 and P-type implantation regions 40, an N-region amorphous structure layer 31 located at the bottom of the N-type implantation region 30 and a P-region amorphous structure layer 41 located at the bottom of the P-type implantation region 40 are obtained, and its implantation energy is 10 keV - 30 keV, preferably 16 keV - 24 keV, and the implantation dose is 4×10 14 cm-2 -6×10 14 cm -2 , preferably 5×10 14 cm -2 , to break the surface lattice to form an amorphous structure layer, thereby suppressing the channel penetration of subsequent doped ions, ensuring the uniformity of the shallow junction, and the junction depth < 50 nm.

[0030] Step S40: Inject phosphorus ions into the N-type implantation region to form an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region, and inject boron ions into the P-type implantation region to form a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region, and remove the mask layer.

[0031] In this embodiment, in the step of injecting phosphorus ions into the N-type implantation region 30 to form an N-type trigger region 32 on the surface of the amorphous structure layer in the N-type implantation region 30, the implantation energy of the phosphorus ions is 3 keV - 4 keV, and the implantation dose is 1×10 15 cm -2 -3×10 15 cm -2 .

[0032] In addition, in the step of injecting boron ions into the P-type implantation region 40 to form a P-type anode region 42 on the surface of the amorphous structure layer in the P-type implantation region 40, the implantation energy of the boron ions is 1 keV - 4 keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 .

[0033] Specifically, in this embodiment, the penetration depth of low-energy ions is controlled by setting a very low energy of ion implantation. For example, the implantation energy of phosphorus ions is 3 keV - 4 keV, preferably 4 keV, and the implantation energy of boron ions is 1 keV - 4 keV, preferably 2 keV.

[0034] In addition, the implantation dose needs to be adjusted according to the target doping concentration. The implantation doses of phosphorus ions and boron ions are usually 1×10 14 cm -2 -1×10 16 cm -2 , specifically, the implantation dose of phosphorus ions is 1×10 15 cm -2 -3×10 15 cm -2 , preferably 2×10 15 cm -2 , and the implantation dose of boron ions is 4×10 14 cm-2 -6×10 14 cm -2 , preferably 5×10 14 cm -2 。

[0035] Similarly, to avoid channeling effects during low-energy ion implantation, the wafer, i.e., the P-type substrate 10, needs to be tilted at a certain angle for ion implantation, such as 10°-30°, to deviate from the main crystal orientation for ion implantation.

[0036] Step S50, perform multiple annealing treatments on the P-type substrate and fabricate a passivation layer on the surface of the P-type substrate.

[0037] By performing inert ion implantation on the N-type implantation region 30 and the P-type implantation region 40 of the P-type substrate 10, the surface lattice is damaged to form an amorphous structure layer, so as to suppress the channel penetration of subsequent doped ions through the amorphous structure layer, ensuring that the shallow junction has good uniformity. Then, phosphorus ion implantation and boron ion implantation are respectively performed on the N-type implantation region 30 and the P-type implantation region 40 of the P-type substrate 10, and an N-type trigger region 32 is formed on the surface of the amorphous structure layer in the N-type implantation region 30, and a P-type anode region 42 is formed on the surface of the amorphous structure layer in the P-type implantation region 40.

[0038] In this embodiment, after the N-type trigger region 32 and the P-type anode region 42 are formed, the entire P-type substrate 10 will be annealed multiple times, for example, including low-temperature annealing and high-temperature annealing. Specifically, low-temperature annealing is used to repair the lattice damage caused by ion implantation, and high-temperature annealing is used to quickly activate the dopant and suppress impurity diffusion.

[0039] And after low-temperature annealing and high-temperature annealing, another annealing treatment will be performed, and the annealing temperature is lower than that of the low-temperature annealing process to passivate the interface dangling bonds and residual defects, achieve defect passivation, thereby reducing the leakage current in the junction region and improving the device reliability.

[0040] Step S60, etch openings in the passivation layer to obtain contact holes to expose the surfaces of the N-type implantation region and the P-type implantation region, and grow an electrode layer in the contact holes to obtain a low-residual-voltage ESD device.

[0041] In this embodiment, after the passivation layer 50 is fabricated on the surface of the P-type substrate 10, since the passivation layer 50 covers the entire surface of the P-type substrate 10, including covering the surfaces of the N-type implantation region 30 and the P-type implantation region 40, in order to achieve electrical connection between the device and the circuit board, it is also necessary to etch openings in the passivation layer 50 to obtain contact holes, that is, electrode connection holes, including the N-region contact hole 51 and the P-region contact hole 52 that expose the N-type implantation region 30 and the P-type implantation region 40. Then, an electrode layer 60 with a metal structure is fabricated in the contact holes by the ALD process, including the N-region electrode 61 and the P-region electrode 62, such as a Ti / AlCu electrode with a lower resistivity, and finally the overall structure of the low-residual-voltage ESD device is obtained.

[0042] Compared with the prior art, the beneficial effects of using the preparation method of the low-residual-voltage ESD device shown in this embodiment are as follows: In this embodiment, inert ions are implanted into the N-type implantation region 30 and the P-type implantation region 40 of the P-type substrate 10 to form an amorphous structure layer. Then, phosphorus ions are implanted into the N-type implantation region 30 to form an N-type trigger region 32 on the surface of the amorphous structure layer in the N-type implantation region 30, and boron ions are implanted into the P-type implantation region 40 to form a P-type anode region 42 on the surface of the amorphous structure layer in the P-type implantation region 40. By forming a ultra-shallow junction through the amorphous structure layer and low-energy ion implantation, the on-resistance of the ESD device can be significantly reduced, the voltage clamping residual voltage can be decreased, and through the cooperation of the ultra-shallow junction and the low-resistance electrode layer 60, the ESD device can quickly discharge a large current under a nanosecond-level ESD pulse, thereby better protecting the circuit devices.

[0043] Embodiment Two Please refer to Figure 2 This second embodiment of the present invention also provides a preparation method of a low-residual-voltage ESD device. The preparation method shown in this embodiment is basically the same as the preparation method shown in the first embodiment, and the difference lies in: In this embodiment, the steps of performing multiple annealing treatments on the P-type substrate 10 and fabricating the passivation layer 50 on the surface of the P-type substrate 10 include: Performing a first annealing treatment on the P-type substrate 10 according to a preset first process parameter, and performing a second annealing treatment according to a preset second process parameter after the first annealing treatment ends; Performing a third annealing treatment on the P-type substrate 10 according to a preset third process parameter in a hydrogen atmosphere, and fabricating the passivation layer 50 on the surface of the P-type substrate 10.

[0044] Furthermore, the steps of performing a first annealing treatment on the P-type substrate 10 according to a preset first process parameter and performing a second annealing treatment according to a preset second process parameter after the first annealing treatment ends include: In a nitrogen atmosphere, the P-type substrate 10 is subjected to a first annealing treatment according to preset first process parameters, and after the first annealing treatment is completed, a second annealing treatment is carried out according to preset second process parameters; Among them, in the first process parameters, the first annealing temperature is 550°C - 630°C, the first annealing time is 25s - 40s, in the second process parameters, the second annealing temperature is 960°C - 1080°C, and the second annealing time is 1s - 3s.

[0045] Furthermore, in a hydrogen atmosphere, the P-type substrate 10 is subjected to a third annealing treatment according to preset third process parameters, and in the step of fabricating the passivation layer 50 on the surface of the P-type substrate 10, in the third process parameters, the third annealing temperature is 370°C - 420°C, and the third annealing time is 12 min - 15 min.

[0046] In addition, the passivation layer 50 is an overlapping structure of Si3N4 / SiO2, and the thickness is 60 nm - 80 nm.

[0047] Specifically, in this embodiment, it includes a two-step annealing process of rapid thermal annealing, including the above-mentioned first annealing treatment and second annealing treatment. During the first annealing treatment, it is required to be carried out in an N2 atmosphere, the first annealing temperature is 550°C - 630°C, preferably 590°C, and the first annealing time is 25s - 40s, preferably 35s, so as to repair the lattice damage between the P-type substrate 10, the N-type trigger region 32, and the P-type anode region 42 through the first annealing treatment.

[0048] During the second annealing treatment, it is also carried out in an N2 atmosphere, the second annealing temperature is 960°C - 1080°C, preferably 1020°C, and the second annealing time is 1s - 3s. Usually, a 1s spike annealing treatment is adopted to activate the dopants in the N-type trigger region 32 and the P-type anode region 42 and inhibit dopant diffusion.

[0049] During the third annealing treatment, it is required to be carried out in an H2 atmosphere, the third annealing temperature is 370°C - 420°C, preferably 400°C, and the third annealing time is 12 min - 15 min, preferably 13 min, so as to passivate the interface dangling bonds between the P-type substrate 10, the N-type trigger region 32, and the P-type anode region 42, thereby reducing the leakage current.

[0050] Compared with the first embodiment, the beneficial effect of adopting the preparation method shown in this embodiment is that: In this embodiment, a two-step thermal annealing process is adopted, including low-temperature repair and high-temperature activation, which can effectively repair the ion implantation damage, reduce the defect density in the junction region, and the hydrogen annealing further passivates the interface dangling bonds and reduces the carrier traps. Through the above-mentioned amorphization treatment by inert ion implantation and hydrogen passivation, the lattice defects are reduced, and permanent damage after the ESD pulse impact can be avoided, so that the service life of the ESD device can be effectively improved.

[0051] Embodiment 3 The third embodiment of the present invention also provides a preparation method of a low-residual voltage ESD device. The preparation method shown in this embodiment is basically similar to the preparation method shown in the first embodiment, and the differences are as follows: In this embodiment, the steps of etching and opening holes in the passivation layer 50 to obtain contact holes to expose the surfaces of the N-type implantation region 30 and the P-type implantation region 40, and growing an electrode layer 60 in the contact holes to obtain a low-residual voltage ESD device include: Etching and opening windows in the passivation layer 50 to obtain an N-pole contact hole and a P-pole contact hole to respectively expose the surfaces of the N-type implantation region 30 and the P-type implantation region 40; Simultaneously depositing VO2 material on the surfaces of the N-type implantation region 30 and the P-type implantation region 40 in the N-pole contact hole and the P-pole contact hole, and etching to form an electrode finger structure; Sputtering Pt material on the electrode finger structure and photolithographing to form a thermosensitive electrode layer 60 with a curved structure to obtain a low-residual voltage ESD device.

[0052] Specifically, in this embodiment, after the production of the N-type trigger region 32, the P-type anode region 42, the annealing treatment, and the production of the passivation layer 50 are completed, the passivation layer 50 will be subjected to photolithographic windowing treatment to obtain an N-type contact hole and a P-type contact hole, respectively exposing the surfaces of the N-type implantation region 30 and the P-type implantation region 40. Then, VO2 (vanadium dioxide) material is deposited by magnetron sputtering or atomic layer deposition, specifically in the form of a thin film, and the thickness is usually 20nm-40nm. Then, the VO2 thin film is dry-etched to form an electrode finger structure to connect the cathode of the N-type trigger region 32 and the anode of the P-type anode region 42 through the electrode finger structure. Finally, Pt material, or Pt / TiN material, is sputtered on the VO2 thin film region, that is, the electrode finger structure, as a heating electrode, and the Joule effect is used to locally heat up to trigger the phase change of the VO2 material.

[0053] It should be supplemented and explained here that in the normal state, the VO2 material is in an insulating state, and the resistance > 10 3Ω·cm, the ESD current is mainly discharged through the SCR (i.e., the main body of the SCR-type ESD device). When the ESD pulse impact occurs, the SCR conducts to generate heat and the thermosensitive electrode layer 60 actively heats up, causing the temperature of the VO2 material to exceed the phase transition point and gradually transform into the metallic state, forming a low-resistance bypass, further reducing the voltage clamping residual voltage. After the ESD pulse impact ends, the temperature drops, and the VO2 material returns to the insulating state again, avoiding permanent damage caused by local melting, and ultimately being able to avoid the residue of the leakage current path.

[0054] Comparative Example 1 The first comparative example also provides a preparation method for a low-residual voltage ESD device, which is an improved traditional SCR process. This preparation method includes: 1. Substrate preparation: Provide a low-resistivity SOI silicon-based substrate with a resistivity of 0.1 Ω·cm.

[0055] 2. Implantation process: Directly define the N / P regions by photolithography without pre-implantation of inert ions; The implantation energy of phosphorus ions is 6 keV, and the implantation dose is 2×10 15 cm -2 ; The implantation energy of boron ions is 3 keV, and the implantation dose is 5×10 14 cm -2 .

[0056] 3. Annealing treatment In an N2 atmosphere, a two-step annealing process is adopted. The first annealing is at 600 °C for 30 s, and the second annealing is at 1000 °C for 2 s, without hydrogen annealing.

[0057] 4. Passivation layer fabrication Fabricate a Si3N4 / SiO2 passivation layer.

[0058] 5. Electrode fabrication Fabricate the same Ti / AlCu electrodes as in the embodiments of the present invention.

[0059] Based on the above preparation method, a low-residual voltage ESD device is prepared, and its performance is compared with the low-residual voltage ESD devices shown in the first and second embodiments of the present invention. The comparison results are shown in Table 1: Table 1

[0060] As can be seen from Table 1, through the combined optimization of ultra-shallow junctions (<35 nm) and low-resistance electrodes, the residual voltage of the present invention is reduced to below 2 V (compared with 5 V+ in the traditional process), with a reduction of more than 60%. If only the substrate and electrodes are improved (Comparative Example 1), the residual voltage is only reduced to 5.2 V, proving that the amorphous structure layer + three-step annealing in the embodiments of the present invention can effectively reduce the residual voltage level, thereby enhancing the protection effect.

[0061] Comparative Example 2 The second comparative example also provides a method for preparing a low-residual-voltage ESD device. The difference between this preparation method and the first embodiment is as follows: Omit the inert ion implantation, and the rest is exactly the same as the first embodiment.

[0062] Based on the above preparation method, a low-residual-voltage ESD device is prepared, and its performance is compared with the low-residual-voltage ESD device shown in the first embodiment of the present invention. The comparison results are shown in Table 2: Table 2

[0063] As can be seen from Table 2, if the amorphous structure layer is omitted (Comparative Example 2), even if the same annealing and electrode processes as in the first embodiment of the present invention are used, the residual voltage still reaches 4.5 V, and the on-resistance reaches 0.7 Ω, showing an obvious gap compared with the first embodiment of the present invention.

[0064] Table 3 is a comparison table of key parameters of the first and second embodiments of the present invention and Comparative Examples 1 and 2: Table 3

[0065] As can be seen from Table 3, for the low-residual-voltage ESD device prepared by using the preparation method shown in the embodiments of the present invention, through the design of ultra-shallow junctions and low-resistance electrodes, the on-resistance of the ESD device can be greatly reduced, the voltage clamping residual voltage can be reduced, and through the cooperation of the ultra-shallow junction and the low-resistance electrode layer, the ESD device can quickly discharge large currents, thereby better protecting circuit devices.

[0066] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0067] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent for the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention shall be subject to the appended claims.

Claims

1. A preparation method of a low residual voltage ESD device, characterized in that, The preparation method includes: Providing a P-type substrate; Coating a photoresist on the surface of the P-type substrate, exposing and developing it to obtain a mask layer, and exposing the mutually separated N-type implantation regions and P-type implantation regions; Simultaneously implanting inert ions into the N-type implantation region and the P-type implantation region of the P-type substrate to form an amorphous structure layer; Implanting phosphorus ions into the N-type implantation region, forming an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region, and implanting boron ions into the P-type implantation region, forming a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region, and removing the mask layer; Performing multiple annealing treatments on the P-type substrate and fabricating a passivation layer on the surface of the P-type substrate; Etching openings in the passivation layer to obtain contact holes to expose the surfaces of the N-type implantation region and the P-type implantation region, and growing an electrode layer in the contact holes to obtain a low-residual-voltage ESD device.

2. The preparation method of the low residual voltage ESD device according to claim 1, characterized in that, The step of simultaneously implanting inert ions into the N-type implantation region and the P-type implantation region of the P-type substrate to form an amorphous structure layer includes: Simultaneously implanting silicon ions into the N-type implantation region and the P-type implantation region of the P-type substrate to form an amorphous structure layer; Among them, the implantation energy of silicon ions into the N-type implantation region and the P-type implantation region is 16 keV - 24 keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 .

3. The manufacturing method of the low residual voltage ESD device according to claim 1, characterized in that, In the step of implanting phosphorus ions into the N-type implantation region to form an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region, the implantation energy of the phosphorus ion implantation is 3 keV - 4 keV, and the implantation dose is 1×10 15 cm -2 -3×10 15 cm -2 ; In the step of implanting boron ions into the P-type implantation region to form a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region, the implantation energy of the boron ion implantation is 1 keV - 4 keV, and the implantation dose is 4×10 14 cm -2 -6×10 14 cm -2 .

4. The manufacturing method of the low residual voltage ESD device according to claim 1, characterized in that, The step of performing multiple annealing treatments on the P-type substrate and fabricating a passivation layer on the surface of the P-type substrate includes: Performing a first annealing treatment on the P-type substrate according to preset first process parameters, and performing a second annealing treatment according to preset second process parameters after the first annealing treatment ends; Performing a third annealing treatment on the P-type substrate according to preset third process parameters in a hydrogen atmosphere, and fabricating a passivation layer on the surface of the P-type substrate.

5. The preparation method of the low-residual-voltage ESD device according to claim 4, characterized in that, The step of performing a first annealing treatment on the P-type substrate according to preset first process parameters and performing a second annealing treatment according to preset second process parameters after the first annealing treatment ends includes: Performing a first annealing treatment on the P-type substrate according to preset first process parameters and performing a second annealing treatment according to preset second process parameters after the first annealing treatment ends in a nitrogen atmosphere; Among them, in the first process parameters, the first annealing temperature is 550°C - 630°C, the first annealing time is 25s - 40s, in the second process parameters, the second annealing temperature is 960°C - 1080°C, and the second annealing time is 1s - 3s.

6. The manufacturing method of the low residual voltage ESD device according to claim 4, characterized in that, In the step of performing a third annealing treatment on the P-type substrate according to preset third process parameters in a hydrogen atmosphere and fabricating a passivation layer on the surface of the P-type substrate, in the third process parameters, the third annealing temperature is 370°C - 420°C, and the third annealing time is 12min - 15min.

7. The manufacturing method of the low residual voltage ESD device according to claim 5, characterized in that, The passivation layer is an overlapping structure of Si3N4 / SiO2, and the thickness is 60nm - 80nm.

8. The manufacturing method of the low-residual voltage ESD device according to any one of claims 1-7, characterized in that, The step of etching openings in the passivation layer to obtain contact holes to expose the surfaces of the N-type implantation region and the P-type implantation region, and growing an electrode layer in the contact holes to obtain a low-residual-voltage ESD device includes: Etching windows in the passivation layer to obtain an N-pole contact hole and a P-pole contact hole to respectively expose the surfaces of the N-type implantation region and the P-type implantation region; Deposit VO2 material onto the surfaces of the N-type implantation region and the P-type implantation region simultaneously in the N-pole contact hole and the P-pole contact hole, and etch to form an electrode interdigitated structure; Sputter Pt material on the electrode interdigitated structure, and perform photolithography to form a thermosensitive electrode layer with a curved structure, thereby obtaining a low-residual voltage ESD device.

9. A low-residual voltage ESD device, characterized in that, Prepared by the preparation method according to any one of claims 1-8.

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