42results about "Computing operations for equation solving" patented technology

A system comprises a workload evaluator that is operable to receive a representative workload that is representative of competing demands for capacity of at least one shared computing resource. The workload evaluator evaluates the representative workload and computes a metric representing a degree of burstiness of demands present in the representative workload. The metric representing degree of burstiness of the representative workload may be used for estimating an upper bound on quality of service provided by a workload manager to the representative workload. The metric may also be used for evaluating at least one scheduler parameter setting of the workload manager to aid in determining an optimal parameter setting based at least in part on the estimated impact of the representative workload on QoS provided by the workload manager.

A computer-implemented method is provided for monitoring model performance. The method may include obtaining configuration information and obtaining operational information about a computational model and a system being modeled. The computational model and the system may include a plurality of input parameters and one or more output parameters. The system may generate respective actual values of the one or more output parameters, and the computational model may predict respective values of the one or more output parameters. The method may also include applying an evaluation rule from a rule set, based on the configuration information, to the operational information to determine whether the rule is satisfied.

System and method for controlling / analyzing a process by solving a system of linear equations in real-time. Linear equations that model the process are stored. In an off-line stage a partitioning strategy is determined based on the linear equations, including determining groups of values for recursively partitioning a set of values measured and / or computed from the process. In an on-line stage: current process data are received from the process, including measurements from the process, and composing a set of values; the linear equations are recursively solved for a first group of the set, where the first group partitions the set into respective subsets of values, and where the recursively solving produces solved values for respective first groups of the set / subset of values; the linear equations are solved for remaining unsolved values in the set, thereby producing solved values for the set, which are stored and are useable to control / analyze the process.

A recursive approach to quantum computing employs an initial solution, determines intermediate solutions, evaluates the intermediate solutions and repeats using the intermediate solution, if the intermediate solution does not satisfy solution criteria. A best one of the intermediate solutions may be employed in the recursion.

An acoustic tool that provides a reduced tool mode and enhanced accuracy for estimating shear wave propagation slowness in slow formations is disclosed. In one embodiment, the acoustic tool comprises: an acoustic source, an array of acoustic receivers, and an internal controller. The acoustic source excites waves that propagate in a quadrupole mode. The internal controller processes signals from the array of acoustic receivers to determine a peak phase semblance having a slowness value that varies with frequency. The minimum slowness value associated with the peak phase semblance provides an accurate estimate of the shear wave propagation slowness. The acoustic source preferably includes four source elements. The elements that are 90° apart are preferably driven in inverse-phase to obtain the quadrupole excitation pattern.

A method is provided for processing received data symbols in an orthogonal frequency division multiplexing (OFDM) transmission scheme, and an OFDM baseband receiver which performs this method, in order to support frequency selective noise estimation, especially in interference limited environments, and to offer improved estimation performance and reduced computational complexity. This is achieved by determining time and frequency selective levels of combined noise and interference, computing noise normalization values for a respective time-frequency region of the time-frequency plane that applies in the transmission scheme employed, from said time and frequency selective noise plus interference levels, applying said noise normalization values to the received data symbols to obtain normalized data symbols, applying said noise normalization values to the channel estimates, to obtain normalized channel estimates, determining communication parameter estimates from said normalized channel estimates, and determining demodulated and decoded data from said normalized data symbols using said normalized channel estimates.

A system and method for simultaneous construction of a corresponding CAD model and physical model, wherein the CAD model comprises a plurality of CAD representations each corresponding to a physical component part that is used to construct the physical model. During construction of a physical model using individual component parts, the CAD system can identify a given component part and retrieve its CAD representation from a CAD library. In addition, the CAD system allows the user to build a CAD representation of a given component part if its CAD representation is not stored in the CAD library. After the CAD representation of the component part is generated, the CAD system will track the motion (position and orientation) of the part as it is maneuvered into a desired position in the physical model. The position and orientation, as well as the CAD representation of the component part as it exists in the physical model is saved in a CAD model database. During assembly, the CAD system can render an image of the CAD model as each component part is placed in the physical model.

A system comprises a workload evaluator that is operable to receive a representative workload that is representative of competing demands for capacity of at least one shared computing resource. The workload evaluator evaluates the representative workload and computes a metric representing a degree of burstiness of demands present in the representative workload. The metric representing degree of burstiness of the representative workload may be used for estimating an upper bound on quality of service provided by a workload manager to the representative workload. The metric may also be used for evaluating at least one scheduler parameter setting of the workload manager to aid in determining an optimal parameter setting based at least in part on the estimated impact of the representative workload on QoS provided by the workload manager.

The invention provides bounded model checking of a program with respect to a property of interest comprising unfolding the program for a number of steps to create a program formula; translating the property of interest into an automaton; encoding the transition system of the automaton into a Boolean formula creating a transition formula; conjoining the program formula with the transition formula to create a conjoined formula; and deciding the satisfiability of the conjoined formula.

The mixer circuit includes a differential rf input driver; a differential local oscillator input circuit coupled to the differential rf input driver; a non-linear load coupled to the differential local oscillator input circuit wherein the non-linear load compensates for non-linearity of the differential rf input driver. The non-linear load has a V-I (voltage-current) transfer function the inverse of the input driver. This improves the mixer linearity without sacrificing the Gain or Noise Figure.

Schedulability determination method of determining whether real-time scheduling of tasks is possible using processors, includes calculating Lk and Σi=1 . . . NMi*Uk,i, (1≦k,i≦N;k,i:integer) where Lk corresponds to task-k, Mi represents number of the one or more processors simultaneously used by task-i, Uk,i corresponds to task-k and task-i, and N represents number of tasks, and determining that real-time scheduling of tasks is possible using processors, if tasks all satisfy conditions, Σi=1 . . . NMi*Uk,i≦Lk for all k (1≦k≦N), wherein Lk corresponds to task-k which is to be detected to satisfy corresponding one of conditions, Lk being expressed as followsif Mk≦(M+1) / 2,Lk=(M−Mk+1)−(M−2Mk+1)Ck / Dk, andUk,i is expressed as followsif Mk≦(M+1) / 2, Mi<(M+1) / 2, and Xk,i≦0,  (1)Uk,i=Ci / Ti{1+(Ti−Di) / Dk}+Ci / Dk,if Mk≦(M+1) / 2, Mi<(M+1) / 2, and 0<Xk,i<Ci / Ti,  (2)Uk,i=Ci / Ti{1+(Ti−Di) / Dk}+(Ci−Xk,i*Ti) / Dk, andif Mk≦(M+1) / 2, Mi<(M+1) / 2 and Ci / Ti≦Xk,i,  (3)Uk,i=Ci / Ti{1+(Ti−Di) / Dk},where M represents number of processors, Ti represents interval of task-i, Ci represents process time for processing task-i, Di represents relative deadline of task-i, and Xk,i=(Mk−Mi+(M−2Mk+1)Ck / Dk) / (M−2Mi+1).

A method is described for generating a challenge-response pair in an electric machine as the basis for an authentication. The electric machine has at least one stator and at least one rotor. A voltage signal or current signal which causes induction between the rotor and the stator is generated as the challenge, and a variable which is a function of the caused induction is determined as the response.

A dynamically configurable logic gate can include a controller configured to provide a first threshold reference signal; an adder configured to sum the first threshold reference signal and at least one input signal to generate a summed signal; a chaotic updater configured to apply a nonlinear function to the summed signal; and a subtractor configured to determine an output signal by taking a difference between a second threshold reference signal and the processed summed signal from the chaotic updater. The logic gate can operate as one of a plurality of different logic gates responsive to adjusting at least one of the threshold reference signals.

System and method for controlling / analyzing a process by solving a system of linear equations in real-time. Linear equations that model the process are stored. In an off-line stage a partitioning strategy is determined based on the linear equations, including determining groups of values for recursively partitioning a set of values measured and / or computed from the process. In an on-line stage: current process data are received from the process, including measurements from the process, and composing a set of values; the linear equations are recursively solved for a first group of the set, where the first group partitions the set into respective subsets of values, and where the recursively solving produces solved values for respective first groups of the set / subset of values; the linear equations are solved for remaining unsolved values in the set, thereby producing solved values for the set, which are stored and are useable to control / analyze the process.

The disclosed invention is a grid that monitors a design simulation to support design verification coverage analysis. The disclosed invention includes n ordered axis declarations 72 that each correspond to a functional attribute and list at least two valid functional states, logic expressions 78 that test for the functional states and set axis variables, and a grid declaration 80 that converts the axis variables to a unique linear index value corresponding to the cross-product of the achieved functional states and records hits. The linear index is calculated by multiplying the integer value of each axis variable (except the nth axis variable) by the product of the sizes of each higher-order axis than the axis to which said axis variable corresponds, summing the results, and adding the integer value of the nth said axis variable.

A method is described for generating a challenge-response pair in an electric machine as the basis for an authentication. The electric machine has at least one stator and at least one rotor. A voltage signal or current signal which causes induction between the rotor and the stator is generated as the challenge, and a variable which is a function of the caused. induction is determined as the response.

A method for device level simulation of a circuit modeled by a set of CCR graphs, a computer system programmed to perform such a method, and a computer readable medium which stores code for implementing such a method. Typically, the circuit includes MOS transistors having unknown gate potentials, each CCR graph includes a top rail, and a bottom rail, and variable nodes, each of the transistors having unknown gate potential is modeled in the CCR graphs as a selectable resistor having a selected one of a first resistance and a much larger second resistance, and the method includes the steps of determining potentials at variable nodes of one of the CCR graphs with each selectable resistor of the graph having its first resistance (and also with each selectable resistor of the graph having its second resistance) without determining effective resistances between the variable nodes of the graph and the top rail or bottom rail.

A computer-implemented method computes the steady-state and control voltage of a voltage controlled oscillator, given a known frequency or a known period of oscillation of the voltage controlled oscillator. Differential algebraic equations representative of the voltage controlled oscillator are generated, where the differential algebraic equations includes a known period or frequency of oscillation and an unknown control voltage of the voltage controlled oscillator. The differential algebraic equations are modified using a finite difference method, a shooting method, or a harmonic balance method, to obtain a set of matrix equations corresponding to the differential algebraic equations. A solution to the matrix equations is obtained using a Krylov subspace method, using a preconditioner for the Krylov subspace method that is derived from a Jacobian matrix corresponding to the matrix equations, where the solution includes the control voltage of the voltage controlled oscillator in steady state.

A user is requested to input specifications of a semiconductor device. Based on the specifications, a plurality of circuit patterns are generated by a CP method, and a design parameter is calculated for each of the circuit patterns. The user is provided with information of the plurality of circuit patterns together with the design parameters. The user selects a desired circuit pattern, whereas the server calculates manufacturing costs of the device and presents them to the user. The user checks the costs and then places an order.

A dot product multiplier for matrix operations for an A matrix of order 1×m with a coefficient B matrix of order m×m. Processing Elements (PEs) are arranged in an m×m array, the columns of the array summed to provide a dot product result. Each of the PEs contains a sign determiner and a plurality of analog multiplier cells, one multiplier cell for each value bit. The multipliers operate over four clock cycles, initializing a capacitor charge according to sign on a first clock phase, sharing charge on a second phase, canceling charge on a third phase, and outputting the resultant charge on a fourth phase, the resultant charge on each column representing the dot product for that column.

Each ordinary differential equation of simultaneous ordinary differential equations is solved with an embedded Runge-Kutta method. A difference Δ between an N-th order approximation and an (N+1)th order approximation is computed, and it is determined whether the difference is smaller than a predetermined threshold Δ0. If Δ≦Δ0, then a step size is determined using a predetermined computation formula containing Δ0 / Δ, and then the process proceeds to next computation. A strand having an error of Δ>Δ0 is directed to execute recomputation using a step size calculated based on Δ0 / Δ. Then the strand having the error executes recomputation by using a computed interpolated value. When the strand's error becomes smaller than the threshold Δ0 the strand reaches the same time step as the strands computing the other ordinary differential equations having no error. The process thereby proceeds to next computation of the whole simultaneous ordinary differential equations.

Described is a method for accurately reconstructing analog signals. The present invention considers a general parameter estimation problem, extends the utility of compressive sensing to real scenarios, and is able to accurately estimate center frequencies and amplitudes. Specifically, an unknown continuous analog signal comprising a set of arbitrary frequencies and amplitudes is received. A set of non-uniform samples of the unknown continuous analog signal is then obtained at multiple times. Finally, an iterative reconstruction process is utilized to determine a set of frequencies and a set of amplitudes that best fit the set of non-uniform samples in a global minimum problem in order to accurately reconstruct the continuous analog signal.