Multi-layer stacked chip and clock control method thereof

Abstract

The invention provides a multi-layer laminated chip and a clock control method thereof, the memory chip can prepare a corresponding clock according to a current function needing to be operated, and clock synchronization among a plurality of memory chips needing to be operated synchronously is realized through clock training, so that the memory chip can be operated synchronously. And the communication delay between layers of the memory chip and the resource occupation of the asynchronous FIFO are reduced, so that the communication cost between multiple layers of laminated chips is reduced. Further. A memory chip can identify information such as a current function and / or an operation mode needing to be operated according to a notification, so that clock arbitration and distribution are carried out, division of an on-chip clock domain can be dynamically adjusted along with different operation functions, automatic division and control of the clock domain are realized, and the operation efficiency is improved. Therefore, the cost and the dynamic power consumption of chip clock domain division are reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a multi-layer stacked package chip and a clock control method therefor. Background Art

[0002] With the advent of the era of information data explosion, the market demand for memories continues to grow. Currently, multi-chip stacked package technology is generally used to reduce the space occupied by multi-chip packaging, achieve the minimization of the size of storage devices, and high storage density in devices of the same size.

[0003] Among them, how to achieve clock synchronization between multi-layer stacked package chips, and thereby reduce the communication cost between multi-layer stacked package chips, is one of the hot issues that need to be urgently solved by those skilled in the art. Summary of the Invention

[0004] The purpose of the present invention is to provide a multi-layer stacked package chip and a clock control method therefor, so as to further reduce the communication cost and data synchronization problems between multi-layer stacked package chips.

[0005] To achieve the above purpose, the present invention provides a clock control method for a multi-layer stacked package chip. The multi-layer stacked package chip has a main chip with a three-dimensional stack package and multiple memory chips. The clock control method includes: The main chip notifies each memory chip that needs to work synchronously to prepare a clock according to the current function to be run. Each of the memory chips that needs to work synchronously performs clock arbitration respectively according to the received notification, and thereby generates corresponding clock signals, control signals, and multi-chip synchronization signals. Each of the memory chips that needs to work synchronously opens its coupled clock loop according to the control signal, and thereby feeds back the clock signal to the main chip. The main chip detects the phase difference between the clock signals of each of the memory chips that needs to work synchronously, and generates a reference clock according to the detection result. Each of the memory chips that needs to work synchronously adjusts its internal working clock signal according to the reference clock until the phase synchronization is achieved between the working clock signals of each of the memory chips that needs to work synchronously. Each of the memory chips that needs to work synchronously receives instructions and works synchronously according to the multi-chip synchronization signal and the working clock signal after phase synchronization.

[0006] Optionally, the main chip performs function status decoding to obtain the current function to be run, and thereby notifies each memory chip that needs to work synchronously to prepare a clock.

[0007] Optionally, the multiple memory chips are hybrid-bonded to each other and to the main chip through through-silicon vias, and the clock circuit is disposed in the hybrid-bonded through-silicon via layer.

[0008] Optionally, the clock circuit includes a main clock path and a backup clock path, the backup clock path is used to back up the main clock path, and the clock control method further includes: in the case where the main clock path coupled to the memory chip is offset or the through-silicon via fails, enabling the memory chip to switch the backup clock path to be turned on.

[0009] Optionally, the steps for each of the memory chips that need to work synchronously to adjust the internal clock signal according to the reference clock include: Performing through-silicon via impedance calibration on the reference clock; Coarsely adjusting the phase alignment of the internal working clock signal with the calibrated reference clock; Sending a corresponding training sequence to perform phase synchronization training on the working clock signal, and capturing the transition edge of the trained working clock signal during the training process to calculate the phase difference between the trained working clock signal and the calibrated reference clock, and further performing phase compensation on the trained working clock signal until the trained working clock signal and the calibrated reference clock achieve phase synchronization.

[0010] Optionally, after each memory chip receives the notification, it identifies the current function and / or operating mode that needs to be run according to the notification, and performs clock arbitration and allocation according to the identification result, and then only turns on the clock domain where the function module required for the current function and / or operating mode is located.

[0011] Optionally, when each memory chip performs clock arbitration and allocation, it performs clock arbitration and allocation in the order of decreasing priority of test mode, user register, and user function.

[0012] Optionally, the function module includes at least two of the following (1) to (5): (1) A write module, which is used to write data into the memory chip, the write module is located in the write clock domain, and when the instruction is a write instruction, the clock control method only turns on the write clock domain; (2) A read module, which is used to read data from the memory chip, the read module is located in the read clock domain, and when the instruction is a read instruction, the clock control method only turns on the read clock domain; (3) A built-in self-test module, which is used to perform a built-in self-test on the memory chip to detect bad points in the memory chip. The built-in self-test module is located in the logic test control clock domain. When the instruction is a built-in self-test instruction, the clock control method only enables the logic test control clock domain; (4) A redundancy repair module, which is used to perform redundancy repair on the bad points in the memory chip. The redundancy repair module is located in the redundancy repair clock domain. When the instruction is a redundancy repair instruction, the clock control method only enables the redundancy repair clock domain; (5) A wafer test module, which is used to perform a wafer test on the memory chip after the memory chip is completed in wafer manufacturing and before packaging. The wafer test module is located in the test mode clock domain. When the instruction is a wafer test instruction, the clock control method only enables the test mode clock domain.

[0013] Based on the same inventive concept, the present invention also provides a multi-layer stacked package chip, which has a main chip with three-dimensional stacked packages and multiple memory chips, wherein, The main chip is used to notify each of the memory chips that need to work synchronously to prepare a clock according to the current function to be run, detect the phase difference between the clock signals fed back by each of the memory chips that need to work synchronously, and generate a reference clock according to the detection result; The memory chip has: Multiple functional modules, which are used to implement corresponding functions; A clock arbitration and distribution circuit, which is used to receive the notification, perform clock arbitration according to the notification to generate corresponding clock signals, control signals and multi-chip synchronization signals, and after the working clock signals of each of the memory chips that need to work synchronously achieve phase synchronization, enable the corresponding functional modules to work according to the multi-chip synchronization signals and the phase-synchronized working clock signals; A clock adjustment circuit, coupled to the clock arbitration and distribution circuit and the corresponding clock loop, which is used to open the clock loop it is coupled to according to the control signal to feed back the clock signal generated by the clock arbitration and distribution circuit to the main chip, and receive the reference clock through the clock loop, and adjust the working clock signal inside the memory chip according to the reference clock until the working clock signals of each of the memory chips that need to work synchronously achieve phase synchronization.

[0014] Optionally, the main chip includes: A function status decoder, which is used to perform function status decoding to obtain the current function to be run; A notification module, coupled to the function status decoder and the clock arbitration and distribution circuits of each memory chip, and configured to notify each memory chip that needs to work synchronously to prepare for the clock according to the decoding result of the function status decoder; A phase detector, coupled to the clock circuits coupled to each memory chip, and configured to detect the phase difference between the clock signals fed back by each of the memory chips that need to work synchronously; A reference clock source, coupled to the phase detector and the clock adjustment circuits of each memory chip, and configured to generate a corresponding reference clock according to the detection result of the phase detector.

[0015] Optionally, the multiple memory chips and between them and the main chip are bonded by through-silicon via hybrid bonding, and the clock circuit is arranged in the through-silicon via hybrid bonding layer.

[0016] Optionally, the clock circuit includes a main clock path and a backup clock path, the backup clock path is used to back up the main clock path, and the main chip is further configured to: in the case that the main clock path of the memory chip is offset or the through-silicon via fails, enable the clock arbitration and distribution circuit of the memory chip to switch on the backup clock path.

[0017] Optionally, the clock adjustment circuit includes: A TSV driving unit, coupled to the clock arbitration and distribution circuit and the corresponding clock circuit, and configured to turn on the clock circuit according to the control signal to feed back the clock signal generated by the clock arbitration and distribution circuit to the main chip, and receive the reference clock through the clock circuit, and perform through-silicon via impedance calibration on the reference clock; A digital control delay line, coupled to the TSV driving unit and the clock arbitration and distribution circuit, and configured to first roughly align the phase of the working clock signal output by the delay line with the calibrated reference clock, and then send a corresponding training sequence to the delay line to perform phase synchronization training on the working clock signal output by the delay line, and capture the rising edge of the trained clock signal during the training process to calculate the phase difference between the trained working clock signal and the calibrated reference clock, and further perform phase compensation on the trained working clock signal until the trained working clock signal and the calibrated reference clock achieve phase synchronization, and send the phase-synchronized working clock signal to the clock arbitration and distribution circuit.

[0018] Optionally, the multiple functional modules inside each memory chip are located in different clock domains; the clock arbitration and distribution circuit includes: An identification module, which is configured to identify the current function and / or operating mode to be run according to the notification after receiving the notification; An arbitration and distribution module, coupled to the identification module, the clock adjustment circuit, and each of the function modules, and configured to perform clock arbitration and distribution according to the identification result of the identification module, and then only turn on the clock domain where the function module required for the current function and / or operating mode is located.

[0019] Optionally, when performing clock arbitration and distribution, the arbitration and distribution module also performs clock arbitration and distribution in the order of decreasing priority of the test mode, user register, and user function.

[0020] Optionally, each of the memory chips that need to work synchronously receives instructions and works synchronously according to the multi-chip synchronization signal and the phase-synchronized working clock signal. The function module includes at least two of the following (1) to (5): (1) A write module, which is configured to write data into the memory chip. The write module is located in the write clock domain. When the instruction is a write instruction, the arbitration and distribution module only turns on the write clock domain; (2) A read module, which is configured to read data from the memory chip. The read module is located in the read clock domain. When the instruction is a read instruction, the arbitration and distribution module only turns on the read clock domain; (3) A built-in self-test module, which is configured to perform a built-in self-test on the memory chip to detect bad points in the memory chip. The built-in self-test module is located in the logic test control clock domain. When the instruction is a built-in self-test instruction, the arbitration and distribution module only turns on the logic test control clock domain; (4) A redundancy repair module, which is configured to perform redundancy repair on the bad points in the memory chip. The redundancy repair module is located in the redundancy repair clock domain. When the instruction is a redundancy repair instruction, the arbitration and distribution module only turns on the redundancy repair clock domain; (5) A wafer test module, which is configured to perform a wafer test on the memory chip after the memory chip is completed and before packaging. The wafer test module is located in the test mode clock domain. When the instruction is a wafer test instruction, the arbitration and distribution module only turns on the test mode clock domain.

[0021] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects: 1. Its memory chips can prepare corresponding clocks according to the current functions to be run as needed, and through clock training, achieve clock synchronization between multiple memory chips that need to run synchronously, reducing the communication delay between layers of memory chips and the resource occupancy of asynchronous FIFOs, thereby reducing the communication cost between multi-layer stacked packages.

[0022] 2. Its memory chips can, according to information such as the current functions and / or operating modes to be run identified by communication, perform clock arbitration and distribution, enabling the division of the on-chip clock domain to be dynamically adjusted differently according to different functions being run, achieving automatic division and control of the clock domain, thereby reducing the cost and dynamic power consumption of chip clock domain division. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them: Figure 1 is a schematic flowchart of a clock control method for a multi-layer stacked package chip according to an embodiment of the present invention.

[0024] Figure 2 is a schematic diagram of the package structure of a multi-layer stacked package chip according to an embodiment of the present invention.

[0025] Figure 3 is a schematic diagram of the internal architecture of the main chip in a multi-layer stacked package chip according to an embodiment of the present invention.

[0026] Figure 4 is a schematic diagram of the internal architecture of the memory chip in a multi-layer stacked package chip according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, well-known features of the art are not described in order to avoid obscuring the present invention. It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments presented herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout the figures indicate the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0028] Please refer to Figure 1 and Figure 2 , an embodiment of the present invention provides a clock control method for a multi-layer stacked package chip. The multi-layer stacked package chip has a main chip 10 with a three-dimensional stack and n + 1 memory chips 30 to 3n, where n ≥ 1 and is an integer. Among them, the main chip 10 is located in the lower layer, and the n + 1 memory chips 30 to 3n are stacked in sequence above the main chip 10.

[0029] In addition, the main chip 10 can implement the conversion of the interface between the master device (Master, i.e., the device that accesses the memory, not shown) and the n + 1 memory chips 30 to 3n, and complete the address decoding and data format conversion (such as data bit width) between the master device and the n + 1 memory chips 30 to 3n, and convert the operation instructions such as read, write, and refresh issued by the master device into signals that the n + 1 memory chips 30 to 3n can recognize, to implement the necessary control for the master device to access the n + 1 memory chips 30 to 3n, such as refresh operations, read and write operations (including the control of address signals, data signals, and various instruction signals), so that the master device can access (or "use", "operate") the storage resources (i.e., the corresponding storage units) on the n + 1 memory chips 30 to 3n according to the needs of the user.

[0030] The master device may include any type of processor device with computing and processing capabilities, such as a central processing unit (CPU), a digital signal processor (DSP), a network processor, an application processor (AP), a field programmable gate array (FPGA), a dedicated processor, etc. The processor device may be configured to execute instructions or software (including code, operating system, application program, etc.), firmware, or a combination thereof that can be executed by one or more computers.

[0031] The n + 1 memory chips 30 to 3n may be DRAMs or any other suitable type of memory die structure respectively. Among them, the DRAM may be any suitable one such as synchronous DRAM (SDRAM), wide I / O DRAM, etc. The n + 1 memory chips 30 to 3n may be implemented as unbuffered dual in-line memory modules (UDIMMs), registered DIMMs (RDIMMs), load-reduced DIMMs (LRDIMMs), fully buffered DIMMs (FBDIMMs), small outline DIMMs (SODIMMs), etc. respectively.

[0032] In other embodiments, the master chip may also be a buffer chip with a memory controller inside, and the master device is arranged outside the master chip. When the master device is integrated into a logic chip, the logic chip is stacked and packaged below the master chip.

[0033] In one example, the n + 1 memory chips 30 to 3n and between them and the master chip 10 are hybrid bonded (Hybrid Bonding, which can be abbreviated as "HB") through through-silicon vias (TSVs). In the multi-layer stacked and packaged chips of this example, a corresponding layer of through-silicon via hybrid bonding layer is provided between every two adjacent layers of chips. Therefore, there are n + 1 layers of through-silicon via hybrid bonding layers 20 to 20n.

[0034] Please continue to refer to Figure 1 and Figure 2 、 Figure 4 , the clock control method of the multi-layer stacked and packaged chips in this embodiment includes: S1, the master chip 10 notifies each memory chip (at least two of the memory chips 30 to 3n, defined as 3i to 3j, j - i ≥ 2) that needs to work synchronously according to the current function to be run to prepare the clock; S2, each of the memory chips 3i to 3j that needs to work synchronously performs clock arbitration respectively according to the received notification, and then generates corresponding clock signals clki to clkj, working clock signals clkwi to clkwj, control signals, and multi-chip synchronization signals. Among them, the multi-chip synchronization signals of each of the memory chips 3i to 3j correspond to the same instruction (such as a write instruction), and then the memory chips 3i to 3j jointly implement the function of the same instruction (such as writing all the data input by the same write instruction). S3. Each of the memory chips 3i - 3j that need to work synchronously turns on its coupled clock loop according to the control signal, and then feeds back the generated clock signals clki - clkj to the main chip 10. S4. The main chip 10 detects the phase differences between the clock signals clki - clkj of each of the memory chips 3i - 3j that need to work synchronously, and generates a reference clock clkref based on the detection result. S5. Each of the memory chips 3i - 3j that need to work synchronously adjusts its internal working clock signals clkwi - clkwj according to the reference clock clkref until the clock signals clkwi - clkwj of each of the memory chips 3i - 3j that need to work synchronously achieve phase synchronization. The initial value of the working clock signal of each memory chip can be equal to the clock signal it sends to the main chip 10. For example, the initial value of the working clock signal clkwi of memory chip 3i is equal to clki. S6. Each of the memory chips 3i - 3j that need to work synchronously receives the instructions to be executed and works synchronously according to the generated multi - chip synchronization signal and the phase - synchronized clock signals clkwi - clkwj. S7. After the instruction runs to completion, each of the memory chips 3i - 3j that need to work synchronously turns off its clock signals clki - clkj and working clock signals clkwi - clkwj, and waits to run the next function.

[0035] In one example, please refer to Figure 1 , in step S1, the main chip 10 decodes the functional status of the instruction to be executed to obtain the current function to be run (such as write data write or refresh), and then notifies each of the memory chips 3i - 3j that need to work synchronously to prepare the clock, enabling each of the memory chips 3i - 3j to prepare to run the instruction.

[0036] In one example, please refer to Figure 1 and Figure 2 , the clock loops 200 coupled to each of the memory chips 30 - 3n are all set in the corresponding through - silicon via hybrid bonding layers 20 - 20n, and include a main clock path 200a and a backup clock path 200b. The backup clock path 200b is used to back up the main clock path 200a.

[0037] Optionally, please refer to Figure 2, the primary clock path 200a and the backup clock path 200b in each through-silicon via hybrid bonding layer are both constructed through the through-silicon vias and the redistribution lines in the through-silicon via hybrid bonding layer. The positions of the redistribution lines are arranged according to the transmission path of the clock signal, and the present invention does not make specific limitations thereto. For example, in the through-silicon via hybrid bonding layers 20 to 20n, the primary clock path 200a of the lower layer is on the left side of the chip, and the primary clock path 200a of the upper layer is on the right side of the chip. Thus, the primary clock paths 200a in the through-silicon via hybrid bonding layers 20 to 20n together form a serpentine trace structure. Similarly, the backup clock paths 200b in the through-silicon via hybrid bonding layers 20 to 20n together form a serpentine trace structure.

[0038] The clock control method of this example further includes: each memory chip 30 to 3n normally opens the primary clock path 200a in the clock loop 200 according to the control signal. However, if the primary clock path 200a is offset or the through-silicon via (TSV) fails, the memory chip 200b switches to open the backup clock path 200b of the clock loop 200 according to the control signal. Thereby ensuring the chip function.

[0039] In one example, please combine Figure 1 and Figure 4 , in step S2, after each memory chip 3i to 3j receives the notification from the main chip 10, it identifies the current function and / or operating mode to be run according to the notification, and performs clock arbitration and allocation according to the identification result, and then only turns on the clock domain where the function modules required to run the current function and / or operating mode are located. Thereby realizing the dynamic partitioning and control of a finer-grained clock domain and reducing power consumption.

[0040] Optionally, please combine Figure 1 and Figure 4 , in step S2, when each memory chip 3i to 3j performs clock arbitration and allocation, if the instruction is illegal or in conflict, the clock arbitration and allocation are performed in the order of the priority from high to low of the test mode (which is also an operating mode), user registers, and user functions (that is, the automatic control of the clock).

[0041] For example, please combine Figure 1 and Figure 4 , taking the memory chip 3i as an example, the function modules 300 in each memory chip 30 to 3n include at least two of the following (1) to (5): (1)Write module 303b, which is used to write data into the storage array (ARRAY) 300 of the memory chip 3i. The write module 303b is located in the write clock domain. When the instruction to be executed is a write instruction (write) (i.e., the function the user needs to execute is to write data), in step S2, only the write clock domain is enabled. Thus, in step S6, only the functional modules 303 such as the write module 303b in the write clock domain are enabled to work, and the functional modules 303 in other clock domains are disabled; (2)Read module 303a, which is used to read data from the storage array 300 of the memory chip 3i. The read module 303a is located in the read clock domain. When the instruction to be executed is a read instruction (read) (i.e., the function the user needs to execute is to read data), in step S2, only the read clock domain is enabled. Thus, in step S6, only the functional modules 303 such as the read module 303a in the read clock domain are enabled to work, and the functional modules 303 in other clock domains are disabled; (3)Built-in self-test (BIST) module 303c, which is used to perform a built-in self-test on the storage array 300 of the memory chip 3i to detect bad points (error bits) in the storage array 300 of the memory chip. The built-in self-test module 303c is located in the Logic Test Control (which can be abbreviated as "LTC") clock domain. When the instruction to be executed is a built-in self-test instruction (i.e., the function the user needs to execute is a built-in self-test), in step S2, only the Logic Test Control clock domain is enabled. Thus, in step S6, only the functional modules 303 such as the built-in self-test module 303c in the Logic Test Control clock domain are enabled to work, and the functional modules 303 in other clock domains are disabled; (4)Redundancy repair (RDN) module 303d, which is used to perform redundancy repair on the bad points in the memory chip 3i. The redundancy repair module is located in the redundancy repair clock domain. When the instruction to be executed is a redundancy repair instruction (i.e., the function the user needs to execute is redundancy repair), in step S2, only the redundancy repair clock domain is enabled. Thus, in step S6, only the functional modules 303 such as the redundancy repair module 303d in the redundancy repair clock domain are enabled to work, and the functional modules 303 in other clock domains are disabled; (5) Wafer test module 303e, which is used to perform wafer testing on the memory chip after the wafer manufacturing of the memory chip is completed and before packaging, or perform relevant tests on the memory chip using probes at any required and appropriate stage before or after leaving the factory. The wafer test module 303e is located in the test mode (TMODE) clock domain. When the instruction to be executed is a wafer test instruction (i.e., the function that the user needs to execute is wafer testing or probe CP testing), only the test mode clock domain is enabled in step S2. Thus, only the functional modules 303 such as the wafer test module 303e in the wafer test clock domain are enabled to work in step S6, and the functional modules 303 in other clock domains are disabled.

[0042] Thus, according to the currently required function to be executed, the working clock of the functional module for implementing the currently required function can be switched, and at the same time, the enabling of each functional module for implementing the currently required function can be controlled, and the remaining functional modules can be disabled, so as to achieve a more fine-grained dynamic partitioning and control of the clock domain and reduce power consumption.

[0043] Taking the memory chip 3i as an example below, the steps for each memory chip 3i to 3j that need to work synchronously to adjust their internal working clock signals clkwi to clkwj according to the reference clock clkref in step S5 will be described in detail. In one example, please refer to Figure 1 and Figure 4 , the steps for the memory chip 3i to adjust its internal working clock signal clkwi according to the reference clock clkref include: First, perform through-silicon via impedance calibration on the reference clock clkref to obtain the calibrated reference clock clkref'. Then, roughly align the phase of its internal working clock signal clkwi with the calibrated reference clock clkref'. Among them, the initial value of the working clock signal clkwi can be equal to clki. Next, send a corresponding training sequence to perform phase synchronization training (training) on its working clock signal clkwi, and capture the transition edge of the trained working clock signal clkwi during the training process to calculate the phase difference between the trained working clock signal clkwi and the calibrated reference clock clkref', and then perform phase compensation on the trained working clock signal clkwi until the trained working clock signal clkwi is phase-synchronized with the calibrated reference clock clkref'.

[0044] Among them, when the internal working clock signals clkwi to clkwj of each memory chip 3i to 3j are all phase-synchronized with their calibrated reference clock clkref', each memory chip 3i to 3j achieves synchronization.

[0045] Thus, the clock transmission of the TSV path is corrected to achieve reliable driving of the clock signal transmitted on the clock loop 200, ensuring the integrity and reliability of the clock signal on the clock path, and further ensuring the reliability of the clock synchronization of the memory chips 3i to 3j that need to work synchronously.

[0046] Based on the same inventive concept, please refer to Figures 2 to 4 , this embodiment also provides a multi-layer stacked package chip, which can implement clock control between multiple chips by using the clock control method of the multi-layer stacked package chip of this embodiment. The multi-layer stacked package chip has a main chip 10 with a three-dimensional stack and n + 1 memory chips 30 to 3n, where n ≥ 1 and is an integer. Among them, the main chip 10 is located in the lower layer, and the n + 1 memory chips 30 to 3n are stacked on top of the main chip 10 in sequence.

[0047] In an example, please refer to Figure 2 , the n + 1 memory chips 30 to 3n and between them and the main chip 10 are hybrid bonded (Hybrid Bonding, which can be abbreviated as "HB") through through-silicon vias (TSVs). That is, the multi-layer stacked package chip of this example also includes n + 1 layers of through-silicon via hybrid bonding layers 20 to 20n, and each layer of through-silicon via hybrid bonding layer is correspondingly arranged between every two adjacent chips in the multi-layer stacked package chip.

[0048] Each layer of through-silicon via hybrid bonding layer is provided with a corresponding clock loop 200, and the clock loop 200 includes a main clock path 200a and a backup clock path 200b, and the backup clock path 200b is used to back up the main clock path 200a. Each layer of through-silicon via hybrid bonding layer 20 to 20n in the clock loop 200 is also provided with a corresponding clock loop 200, and the clock loop 200 includes a main clock path 200a and a backup clock path 200b, and the backup clock path 200b is used to back up the main clock path 200a.

[0049] Optionally, the main clock path 200a and the backup clock path 200b in each layer of through-silicon via hybrid bonding layer are both constructed through the through-silicon vias and the redistribution lines in the through-silicon via hybrid bonding layer. The position of the redistribution lines is arranged according to the transmission path of the clock signal, and the present invention does not make specific limitations on this. For example, in the through-silicon via hybrid bonding layers 20 to 20n, the main clock path 200a of the lower layer is on the left side of the chip, and the main clock path 200a of the upper layer is on the right side of the chip. Thus, the main clock paths 200a in the through-silicon via hybrid bonding layers 20 to 20n together form a serpentine trace structure. Similarly, the backup clock paths 200b in the through-silicon via hybrid bonding layers 20 to 20n together form a serpentine trace structure.

[0050] Between each memory chip 30 to 3n and the main chip 10, under normal circumstances, a clock signal is transmitted through the main clock path 200a in the clock circuit 200. However, if the main clock path 200a is offset or the through-silicon via (TSV) fails, the backup clock path 200b of the clock circuit 200 is switched to transmit the clock signal, thereby ensuring the chip function.

[0051] In this embodiment, please refer to Figure 1 and Figure 2 , the main chip 10 is used to notify each memory chip (at least two of the memory chips 30 to 3n, defined as 3i to 3j, j - i ≥ 2) that needs to work synchronously according to the current function to be run to prepare the clock (implementing Figure 1 step S1 in), and detect the phase difference between the clock signals clki to clkj fed back by each memory chip 3i to 3j that needs to work synchronously through the clock circuit 200 to which it is coupled, and generate a reference clock clkref according to the detected result (implementing Figure 1 step S4 in).

[0052] Among them, the n + 1 memory chips 30 to 3n can be respectively DRAM or any other suitable type of memory die structure, and the present invention does not make specific limitations thereto. Among them, DRAM can be any suitable one such as synchronous DRAM (SDRAM), wide I / O DRAM, etc. The n + 1 memory chips 30 to 3n can be respectively implemented as unbuffered dual in-line memory modules (UDIMMs), registered DIMMs (RDIMMs), load-reduced DIMMs (LRDIMMs), fully buffered DIMMs (FBDIMMs), small outline DIMMs (SODIMMs), etc.

[0053] The main chip 10 can also implement the conversion of the interface between the main device (Master, that is, the device accessing the memory, not shown) and the n + 1 memory chips 30 to 3n, and complete the address decoding and data format conversion (such as data bit width) between the main device and the n + 1 memory chips 30 to 3n, and convert the operation instructions such as read, write, and refresh issued by the main device into signals that the n + 1 memory chips 30 to 3n can recognize, and implement the necessary control for the main device to access the n + 1 memory chips 30 to 3n, such as refresh operations, read and write operations, etc. (including the control of address signals, data signals, and various instruction signals), so that the main device can access (or say "use", "operate") the storage resources (i.e., the corresponding storage units) on the n + 1 memory chips 30 to 3n according to the needs of the user.

[0054] The master device may include any type of processor device with computing and processing capabilities, such as a central processing unit (CPU), a digital signal processor (DSP), a network processor, an application processor (AP), a field programmable gate array (FPGA), a dedicated processor, etc. The processor device may be configured to execute instructions or software (including code, operating system, or application programs, etc.), firmware, or a combination thereof that can be executed by one or more computers.

[0055] In other embodiments, the master chip 10 may also be a buffer chip with a memory controller inside. The master device is disposed outside the master chip 10. When the master device is integrated into a logic chip, the logic chip is stacked and packaged below the master chip 10.

[0056] Please refer to Figure 3 , in one example, the master chip 10 includes a function status decoder 101, a notification module 102, a phase detector 103, and a reference clock source 104. The function status decoder 101, the notification module 102, the phase detector 103, and the reference clock source 104 may all be integrated in a memory controller (not shown) inside the master chip 10.

[0057] Among them, please refer to Figure 2 , Figure 3 and Figure 4 , the function status decoder 101 is used to perform function status decoding on the current instruction to obtain the current function to be run. The notification module 102 is coupled to the function status decoder 101 and the clock arbitration and distribution circuits 301 of each memory chip 30~3n, and is used to notify the clock arbitration and distribution circuits 301 of each memory chip 3i~3j that need to work synchronously in the memory chips 30~3n to prepare clocks clki~clkj according to the decoding result of the function status decoder 101 (that is, the function status decoder 101 and the notification module 102 are used to implement Figure 1 step S1). Among them, 0≤i≤j≤n, and i, j, and n are all integers.

[0058] Please refer to Figures 2 to 4 , the phase detector 103 is coupled to the clock loops 200 coupled to each memory chip 30~3n, and is used to detect the phase difference between the clock signals clki~clkj fed back by each memory chip 3i~3j that need to work synchronously through their coupled clock loops 200. The reference clock source 104 is coupled to the phase detector 103 and the clock adjustment circuits 302 of each memory chip 30~3n, and is used to generate a corresponding reference clock clkref according to the detection result of the phase detector to provide it to each memory chip 3i~3j that need to work synchronously.

[0059] Please refer to Figure 1 ,Figure 2 and Figure 4 In this embodiment, each memory chip 30 to 3n has a storage array 300, a clock arbitration and distribution circuit 301, a clock adjustment circuit 302, and a plurality of functional modules 303. Among them, the plurality of functional modules 303 can implement a plurality of different functions.

[0060] Taking the memory chip 3i (0 ≤ i ≤ n, and i is an integer) as an example, the functions of the clock arbitration and distribution circuit 301 and the clock adjustment circuit 302 will be described in detail below.

[0061] Please refer to Figure 1 、 Figure 2 and Figure 4 In the memory chip 3i, the clock arbitration and distribution circuit 301 is coupled to the main chip 10 and is used to receive the notification sent by the main chip 10, and perform clock arbitration according to the notification to generate corresponding clock signals clki, control signals (not marked), and multi-chip synchronization signals (not marked). Among them, on the one hand, the clock signal clki is sent to the main chip 10 through the clock loop 200 in the through-silicon via bonding layer below it, and on the other hand, it is sent to the clock adjustment circuit 302 to generate a working clock signal clkwi. The clock arbitration and distribution circuit 301 is also used to enable the corresponding functional module 303 in the memory chip 3i to work according to the multi-chip synchronization signal and the phase-synchronized working clock signal clkwi output by the clock adjustment circuit 302 after the working clock signals clkwi to clkwj of the memory chips 3i to 3j that need to work synchronously are phase-synchronized. That is, for the memory chip 3i, the clock arbitration and distribution circuit 301 in the memory chip 3i is used to implement Figure 1 step S2 in Figure 1 and further enable the corresponding functional module 303 to implement

[0062] In an example, please refer to Figure 4 In the memory chip 3i, its clock arbitration and distribution circuit 301 may include an identification module 301a and an arbitration and distribution module 301b.

[0063] The identification module 301a is used to receive the notification sent by the main chip 10 and identify the current function and / or operation mode that needs to run according to the received notification. Among them, the identification module 301a can be any suitable design such as a decoding circuit, a state control circuit, or a register, etc. The present invention has no specific limitation on this.

[0064] The arbitration and distribution module 301b is coupled to the identification module 301a, the clock adjustment circuit 302, and each functional module 303, and is used to perform clock arbitration and distribution according to the identification result of the identification module 301a to generate corresponding clock signals clki, control signals (not labeled), and multi-chip synchronization signals. And after the working clock signals clkwi~clkwj of the memory chips 3i~3j that need to work synchronously achieve phase synchronization, according to the multi-chip synchronization signal and the phase-synchronized working clock signal clkwi output by the clock adjustment circuit 302, only the clock domain where the functional module 303 required by the current function and / or operating mode is located is enabled, and then a corresponding enable signal en is generated to enable the functional module 303 in this clock domain to work. Among them, when the arbitration and distribution module 301b performs clock arbitration and distribution, if the instruction is illegal or in conflict, the clock arbitration and distribution are performed in the order of decreasing priority of the test mode, user register, and user function.

[0065] Optionally, each memory chip 3i~3j that needs to work synchronously receives instructions and works synchronously according to the multi-chip synchronization signal and the phase-synchronized working clock signals clkwi~clkwj. The functional module 303 in the memory chip 3i includes at least two of the following (1)~(5): (1) A write module 303b, which is used to write data into the storage array (ARRAY) 300 of the memory chip 3i. The write module 303b is located in the write clock domain. When the instruction to be executed is a write instruction (write) (that is, the function the user needs to execute is to write data), and after the working clock signals clkwi~clkwj of the memory chips 3i~3j that need to work synchronously achieve phase synchronization, when the arbitration and distribution module 301b distributes the clock (that is, distributes the working clock signal clkwi), only the write clock domain is enabled, and then only the functional module 303 such as the write module 303b in this write clock domain is enabled to work, and the functional module 303 in other clock domains is disabled by the arbitration and distribution module 301b; (2) A read module 303a, which is used to read data from the storage array 300 of the memory chip 3i. The read module 303a is located in the read clock domain. When the instruction to be executed is a read instruction (read) (that is, the function the user needs to execute is to read data), and after the working clock signals clkwi~clkwj of the memory chips 3i~3j that need to work synchronously achieve phase synchronization, when the arbitration and distribution module 301b distributes the clock (that is, distributes the working clock signal clkwi), only the read clock domain is enabled, and then only the functional module 303 such as the read module 303a in this read clock domain is enabled to work, and the functional module 303 in other clock domains is disabled by the arbitration and distribution module 301b; (3) Built-in self-test (BIST) module 303c, which is used to perform a built-in self-test on the memory array 300 of the memory chip 3i to detect error bits in the memory array 300 of the memory chip. The built-in self-test module 303c is located in the logic test control (LTC) clock domain. When the instruction to be executed is a built-in self-test instruction (i.e., the function the user needs to execute is a built-in self-test), and after the working clock signals clkwi~clkwj of the memory chips 3i~3j that need to work synchronously are phase-synchronized, when the arbitration and distribution module 301b distributes the clock (i.e., distributes the working clock signal clkwi), it only enables the built-in self-test clock domain, and thus only enables the built-in self-test module 303c and other functional modules 303 in the built-in self-test clock domain to work, and the functional modules 303 in other clock domains are disabled by the arbitration and distribution module 301b; (4) Redundancy repair (RDN) module 303d, which is used to perform redundancy repair on the error bits in the memory chip 3i. The redundancy repair module is located in the redundancy repair clock domain. When the instruction to be executed is a redundancy repair instruction (i.e., the function the user needs to execute is redundancy repair), and after the working clock signals clkwi~clkwj of the memory chips 3i~3j that need to work synchronously are phase-synchronized, when the arbitration and distribution module 301b distributes the clock (i.e., distributes the working clock signal clkwi), it only enables the redundancy repair clock domain, and thus only enables the redundancy repair module 303c and other functional modules 303 in the redundancy repair clock domain to work, and the functional modules 303 in other clock domains are disabled by the arbitration and distribution module 301b; (5) Wafer test module 303e, which is used to perform a wafer test on the memory chip 3i after the memory chip 3i is completed in wafer manufacturing and before packaging, or to perform relevant tests on the memory chip 3i using probes at any suitable stage before or after leaving the factory. The wafer test module 303e is located in the test mode (TMODE) clock domain. When the instruction to be executed is a wafer test instruction (i.e., the function the user needs to execute is a wafer test or a CP probe test), and after the working clock signals clkwi~clkwj of the memory chips 3i~3j that need to work synchronously are phase-synchronized, when the arbitration and distribution module 301b distributes the clock (i.e., distributes the working clock signal clkwi), it only enables the wafer test clock domain, and thus only enables the wafer test module 303e and other functional modules 303 in the wafer test clock domain to work, and the functional modules 303 in other clock domains are disabled by the arbitration and distribution module 301b.

[0066] Thus, according to the current function that needs to be run, the arbitration and distribution module 301b can switch the working clock clkwi of the function module that implements the current function (for example, when data needs to be read, clkwi switches to the read clock; when data needs to be written, clkwi switches to the write clock; when a refresh is required, clkwi switches to the refresh clock). At the same time, it controls the enabling of each function module that implements the current function and disables the remaining function modules, thereby achieving a more fine-grained dynamic partitioning and control of the clock domain and reducing power consumption.

[0067] Please continue to refer to Figure 2 and Figure 4 , the clock adjustment circuit 302 of the memory chip 3i is coupled to its clock arbitration and distribution circuit 301 and the corresponding clock loop 200, and is used to open the clock loop 200 coupled thereto according to the control signal sent by the clock arbitration and distribution circuit 301, so as to feedback the clock signal clki generated by the clock arbitration and distribution circuit 301 to the main chip 10 (i.e., implementing Figure 1 step S3 in Figure 1 ), and receive the reference clock clkref sent by the main chip 10 through the opened clock loop, and perform phase adjustment on the working clock signal clkwi of the memory chip 3i according to the reference clock clkref until the working clock signals clkwi~clkwj of each memory chip 3i~3j that need to work synchronously achieve phase synchronization (i.e., implementing

[0068] step S5 in Figure 4 ).

[0069] The TSV driving unit 302a is coupled to the clock arbitration and distribution circuit 301, the digital control delay line 302b, and the corresponding clock loop 200, and is used to open the clock loop 200 coupled thereto according to the control signal sent by the clock arbitration and distribution circuit 301, so as to feedback the clock signal clki generated by the clock arbitration and distribution circuit 301 to the main chip 10 (i.e., implementing Figure 1 step S3 in

[0070] The digital control delay line 302b is coupled to the TSV driving unit 302a and the clock arbitration and distribution circuit 301, and is used to first roughly align the phase of the working clock signal clkwi output by the delay line with the calibrated reference clock clkref', and then send a corresponding training sequence to the delay line to perform phase synchronization training on the working clock signal clkwi output by the delay line, and capture the rising edge of the trained working clock signal clkwi during the training process to calculate the phase difference between the trained working clock signal clkwi and the calibrated reference clock clkref', and then perform phase compensation on the trained working clock signal clkwi until the trained working clock signal clkwi and the calibrated reference clock clkref' are phase synchronized, and send the phase synchronized working clock signal clkwi to the clock arbitration and distribution circuit 301. At this time, the clock arbitration and distribution circuit 301 can distribute the working clock signal clkwi to the corresponding functional module 303, thereby realizing the corresponding function. That is, the TSV driving unit 302a and the digital control delay line 302b jointly implement Figure 1 step S5 in

[0071] Among them, the initial value of the working clock signal of each memory chip can be equal to the clock signal it sends to the main chip 10. For example, the initial value of the working clock signal clkw0 of the memory chip 30 can be equal to the clock signal clk0 it sends to the main chip 10. The initial value of the working clock signal clkwi of the memory chip 3i can be equal to the clock signal clki it sends to the main chip 10, the initial value of the working clock signal clkwj of the memory chip 3j can be equal to the clock signal clkj it sends to the main chip 10, and the initial value of the working clock signal clkwn of the memory chip 3n can be equal to the clock signal clkn it sends to the main chip 10.

[0072] It should be understood that in addition to the above circuit modules, the main chip 10 and each memory chip 30~3n in this embodiment may also have other circuit modules for implementing other functions. For example, the main chip 10 or the memory chips 30~3n may also include a circuit for error correction of the memory chip (such as ECC correction), a circuit for clock and frequency control (such as a phase-locked loop PLL), a circuit for managing power consumption and temperature, a first-in-first-out queue register (FIFO), and any other required circuits. These circuits are not the focus of the present invention, so they will not be described in detail here.

[0073] In addition, the division of each circuit module inside the main chip 10 and each memory chip 30 - 3n in this embodiment is illustrative, mainly a logical function division. There may be other division methods in actual implementation. Each circuit module inside the main chip 10 or each memory chip in the embodiments of this application may be integrated in one physical module, may exist physically separately for each circuit module, or two or more circuit modules may be integrated in one physical module. The above - integrated circuit modules may be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer may be a general - purpose computer, a special - purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer - readable storage medium or transmitted from one computer - readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer - readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as an SSD), etc.

[0074] In summary, in the multi - layer stacked package chip and its clock control method provided by the present invention, the memory chip can prepare the corresponding clock according to the currently required function, and through clock training, achieve clock synchronization between multiple memory chips that need to run synchronously, reducing the communication delay between layers of the memory chips and the resource occupancy of the asynchronous FIFO, thereby reducing the communication cost between the multi - layer stacked package chips. In addition, the memory chip can identify information such as the currently required function and / or operating mode based on notifications, and then perform clock arbitration and distribution, enabling the division of the on - chip clock domain to be dynamically adjusted according to different running functions, achieving automatic division and control of the clock domain, thereby reducing the cost of chip clock domain division and dynamic power consumption.

[0075] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the technical field of the present invention based on the above disclosure fall within the protection scope of the technical solution of the present invention.

Claims

1. A clock control method for a multi-layer stacked chip, characterized in that, The multi-layer stacked chip has a main chip with three-dimensional stacking and multiple memory chips. The clock control method includes: The main chip notifies each of the memory chips that need to work synchronously to prepare the clock according to the current function to be run. Each of the memory chips that need to work synchronously performs clock arbitration respectively according to the received notification, and then generates corresponding clock signals, control signals and multi-chip synchronization signals. Each of the memory chips that need to work synchronously opens its coupled clock loop according to the control signal, and then feeds back the clock signal to the main chip. The main chip detects the phase difference between the clock signals of each of the memory chips that need to work synchronously, and generates a reference clock according to the detection result. Each of the memory chips that need to work synchronously adjusts its internal working clock signal according to the reference clock until the working clock signals of each of the memory chips that need to work synchronously achieve phase synchronization. Each of the memory chips that need to work synchronously receives instructions and works synchronously according to the multi-chip synchronization signal and the working clock signal after phase synchronization.

2. The clock control method according to claim 1, characterized in that, The main chip performs function state decoding to obtain the current function to be run, and then notifies each of the memory chips that need to work synchronously to prepare the clock.

3. The clock control method according to claim 1, characterized in that, The multiple memory chips are hybrid bonded through through-silicon vias between them and with the main chip, and the clock loop is arranged in the through-silicon via hybrid bonding layer.

4. The clock control method according to claim 3, wherein The clock loop includes a main clock path and a backup clock path. The backup clock path is used to back up the main clock path. The clock control method further includes: in the case where the main clock path coupled to the memory chip is offset or the through-silicon via fails, enabling the memory chip to switch on the backup clock path.

5. The clock control method according to claim 3, wherein The step that each of the memory chips that need to work synchronously adjusts its internal working clock signal according to the reference clock includes: Performing through-silicon via impedance calibration on the reference clock; Coarsely adjusting the phase alignment of its internal working clock signal with the calibrated reference clock; Sending a corresponding training sequence to perform phase synchronization training on the working clock signal, and capturing the transition edge of the trained working clock signal during the training process to calculate the phase difference between the trained working clock signal and the calibrated reference clock, and then performing phase compensation on the trained working clock signal until the trained working clock signal and the calibrated reference clock achieve phase synchronization.

6. The clock control method according to any one of claims 1-5, characterized in that, After each memory chip receives the notification, it identifies the current function and / or operating mode to be run according to the notification, and performs clock arbitration and distribution according to the identification result, and then only turns on the clock domain where the function modules required for the current function and / or operating mode are located.

7. The clock control method according to claim 6, wherein When each memory chip performs clock arbitration and distribution, it performs clock arbitration and distribution in the order of decreasing priority of test mode, user register, and user function.

8. The clock control method according to claim 6, characterized in that, The function modules include at least two of the following (1) to (5): (1)A write module, which is used to write data into the memory chip. The write module is located in the write clock domain. When the instruction is a write instruction, the clock control method only enables the write clock domain; (2)A read module, which is used to read data from the memory chip. The read module is located in the read clock domain. When the instruction is a read instruction, the clock control method only enables the read clock domain; (3)A built-in self-test module, which is used to perform a built-in self-test on the memory chip to detect defective points in the memory chip. The built-in self-test module is located in the logic test control clock domain. When the instruction is a built-in self-test instruction, the clock control method only enables the logic test control clock domain; (4)A redundancy repair module, which is used to perform redundancy repair on the defective points in the memory chip. The redundancy repair module is located in the redundancy repair clock domain. When the instruction is a redundancy repair instruction, the clock control method only enables the redundancy repair clock domain; (5)A wafer test module, which is used to perform a wafer test on the memory chip after the memory chip is completed in wafer manufacturing and before packaging. The wafer test module is located in the test mode clock domain. When the instruction is a wafer test instruction, the clock control method only enables the test mode clock domain.

9. A multi-layer stacked package chip, the multi-layer stacked package chip having a three-dimensional stacked main chip and multiple memory chips, characterized in that the main chip is used to notify each of the memory chips that need to work synchronously to prepare a clock according to the current function to be run, detect the phase difference between the clock signals fed back by each of the memory chips that need to work synchronously, and generate a reference clock according to the detection result; the memory chip has: a plurality of functional modules for implementing corresponding functions; a clock arbitration and distribution circuit, which is used to receive the notification, perform clock arbitration according to the notification to generate corresponding clock signals, control signals and multi-chip synchronization signals, and after the working clock signals of each of the memory chips that need to work synchronously achieve phase synchronization, enable the corresponding functional modules to work according to the multi-chip synchronization signals and the phase-synchronized working clock signals; a clock adjustment circuit, coupled to the clock arbitration and distribution circuit and the corresponding clock loop, which is used to open the clock loop it is coupled to according to the control signal to feedback the clock signal generated by the clock arbitration and distribution circuit to the main chip, and receive the reference clock through the clock loop, and adjust the working clock signal inside the memory chip according to the reference clock until the working clock signals of each of the memory chips that need to work synchronously achieve phase synchronization.

10. The multi-layer stacked package chip according to claim 9, wherein, The main chip includes: a function status decoder for performing function status decoding to obtain the current function to be run; a notification module, coupled to the function status decoder and the clock arbitration and distribution circuit of each memory chip, and used to notify each memory chip that needs to work synchronously to prepare a clock according to the decoding result of the function status decoder; A phase detector, coupled to the clock circuits coupled to each memory chip, and configured to detect the phase differences between the clock signals fed back by each memory chip that needs to work synchronously; A reference clock source, coupled to the phase detector and the clock adjustment circuits of each memory chip, and configured to generate a corresponding reference clock according to the detection result of the phase detector.

11. The multi-layer stacked encapsulated chip according to claim 9, wherein, The multiple memory chips and between them and the main chip are hybrid bonded through through-silicon vias, and the clock circuit is disposed in the hybrid bonding layer of the through-silicon vias.

12. The multi-layer stacked encapsulated chip according to claim 11, wherein, The clock circuit includes a main clock path and a backup clock path, the backup clock path is used to backup the main clock path, and the main chip is further configured to: in the case where the main clock path of the memory chip is offset or the through-silicon via fails, cause the clock adjustment circuit of the memory chip to switch the backup clock path to be turned on.

13. The multi-layer stacked and sealed chip according to claim 11, wherein The clock adjustment circuit includes: A TSV driving unit, coupled to the clock arbitration and distribution circuit and the corresponding clock circuit, and configured to turn on the clock circuit according to the control signal to feed back the clock signal generated by the clock arbitration and distribution circuit to the main chip, and receive the reference clock through the clock circuit, and perform through-silicon via impedance calibration on the reference clock; A digital control delay line, coupled to the TSV driving unit and the clock arbitration and distribution circuit, and configured to first coarsely align the phase of the working clock signal output by the delay line with the calibrated reference clock, and then send a corresponding training sequence to the delay line to perform phase synchronization training on the working clock signal output by the delay line, and capture the transition edges of the trained clock signal during the training process to calculate the phase difference between the trained working clock signal and the calibrated reference clock, and further perform phase compensation on the trained working clock signal until the trained working clock signal and the calibrated reference clock achieve phase synchronization, and send the phase-synchronized working clock signal to the clock arbitration and distribution circuit.

14. The multi-layer stacked chip according to any one of claims 9-13, characterized in that, The multiple functional modules inside each memory chip are located in different clock domains; The clock arbitration and distribution circuit includes: An identification module, configured to identify the current function and / or operating mode that needs to run according to the notification after receiving the notification; An arbitration and distribution module, coupled to the identification module, the clock adjustment circuit and each functional module, and configured to perform clock arbitration and distribution according to the identification result of the identification module, and thus only turn on the clock domain where the functional module required for the current function and / or operating mode is located.

15. The multi-layer stacked and sealed chip according to claim 14, characterized in that, When performing clock arbitration and distribution, the arbitration and distribution module also performs clock arbitration and distribution in the order of decreasing priority of test mode, user register, and user function.

16. The multi-layer stacked and sealed chip according to claim 14, wherein Each memory chip that needs to work synchronously receives instructions and works synchronously according to the multi-chip synchronization signal and the phase-synchronized working clock signal, and the functional module includes at least two of the following (1) to (5): (1)Write module, which is used to write data into the memory chip. The write module is located in the write clock domain. When the instruction is a write instruction, the arbitration and allocation module only enables the write clock domain; (2)Read module, which is used to read data from the memory chip. The read module is located in the read clock domain. When the instruction is a read instruction, the arbitration and allocation module only enables the read clock domain; (3)Built-in self-test module, which is used to perform a built-in self-test on the memory chip to detect defective points in the memory chip. The built-in self-test module is located in the logic test control clock domain. When the instruction is a built-in self-test instruction, the arbitration and allocation module only enables the logic test control clock domain; (4)Redundancy repair module, which is used to perform redundancy repair on the defective points in the memory chip. The redundancy repair module is located in the redundancy repair clock domain. When the instruction is a redundancy repair instruction, the arbitration and allocation module only enables the redundancy repair clock domain; (5)Wafer test module, which is used to perform a wafer test on the memory chip after the memory chip is completed with wafer fabrication and before packaging. The wafer test module is located in the test mode clock domain. When the instruction is a wafer test instruction, the arbitration and allocation module only enables the test mode clock domain.

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