Integrated circuit device and operating method thereof

Abstract

An integrated circuit (IC) device includes first and second dies. The first die includes a first transmit circuit, a first receive circuit, and a first circuit. The first transmission circuit transmits an output clock signal corresponding to the first clock signal. The first receiving circuit receives an input clock signal and an input signal, and outputs a first signal corresponding to the input signal based on the input clock signal. The first circuit outputs a second signal corresponding to the first signal based on the first clock signal. The second die includes a second receiving circuit coupled to the first transmitting circuit to receive the output clock signal, and a second transmitting circuit coupled to the first receiving circuit and transmitting an input signal and an input clock signal corresponding to the output clock signal to the first receiving circuit based on the output clock signal. The embodiment of the invention also discloses a method for operating the integrated circuit device.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit devices and methods of operating the same. Background Art

[0002] The complexity of integrated circuit (IC) devices is increasing continuously and they generally operate at higher clock frequencies while the power consumption and / or voltage are reduced. Providing an accurate clock signal in such IC devices is a design concern. Clock accuracy is a consideration, especially in three-dimensional (3D) IC devices where multiple chips (or dies) are stacked and bonded to each other and / or stacked and bonded to a substrate, middleware, wafer, etc. Summary of the Invention

[0003] According to one aspect of embodiments of the present application, there is provided an integrated circuit device including a first semiconductor die and a second semiconductor die. The first semiconductor die includes: a first transmitting circuit configured to transmit an output clock signal corresponding to a first clock signal; a first receiving circuit configured to receive an input clock signal and an input signal, and output a first signal corresponding to the input signal based on the input clock signal; and a first circuit configured to output a second signal corresponding to the first signal based on the first clock signal. The second semiconductor die includes: a second receiving circuit coupled to the first transmitting circuit to receive the output clock signal; and a second transmitting circuit coupled to the first receiving circuit and configured to transmit the input signal to the first receiving circuit based on the output clock signal, and transmit the input clock signal corresponding to the output clock signal to the first receiving circuit.

[0004] According to another aspect of embodiments of the present application, there is provided an integrated circuit device including: a clock input buffer including an input configured to be coupled to a die-to-die interface structure and an output; a phase-locked loop including a reference input coupled to the output of the clock input buffer, a feedback input, an output, and a feedback path coupled between the feedback input and the output of the phase-locked loop, the feedback path including a delay circuit; and a clock output buffer including an input coupled to the output of the phase-locked loop and an output configured to be coupled to another die-to-die interface structure.

[0005] According to still another aspect of embodiments of the present application, there is provided a method of operating an integrated circuit device including: transmitting an output signal and an output clock signal associated with the output signal to a semiconductor die; receiving an input signal and an input clock signal associated with the input signal from the semiconductor die, the input signal corresponding to the output signal and the input clock signal corresponding to the output clock signal; selecting a clock signal based on a comparison of data in the output signal with data obtained from the input signal; and obtaining additional data from an additional input signal received from the semiconductor die based on the selected clock signal. Brief Description of the Drawings

[0006] As will be best understood by reference to the following detailed description when read in conjunction with the accompanying drawings, it should be noted that the various components are not drawn to scale in accordance with standard practice in the industry. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A is a schematic circuit diagram of an IC device according to some embodiments.

[0008] Figure 1B is a schematic timing diagram showing Figure 1A the various signals in the operation of the IC device according to some embodiments.

[0009] Figure 2 is a schematic circuit diagram of a clock management circuit according to some embodiments.

[0010] Figure 3 is a schematic circuit diagram of an IC device according to some embodiments.

[0011] Figure 4A is a schematic circuit diagram of an IC device according to some embodiments.

[0012] Figure 4B is a schematic timing diagram showing Figure 4A the various signals in the operation of the IC device according to some embodiments.

[0013] Figures 4C - 4D is a schematic circuit diagram of various IC devices according to some embodiments.

[0014] Figures 5A - 5B is a schematic circuit diagram of various IC devices according to some embodiments.

[0015] Figures 6A - 6C is a flowchart of various methods according to some embodiments.

[0016] Figure 7 is a schematic diagram of a clock distribution system for an IC device according to some embodiments.

[0017] Figures 8A - 8B is a schematic diagram of various IC devices according to some embodiments.

[0018] Figure 9 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0019] Figure 10 is a block diagram of an IC device manufacturing system and an IC manufacturing process associated therewith according to some embodiments. DETAILED DESCRIPTION

[0020] Numerous different embodiments or examples for implementing different features of the subject matter of the present invention are provided hereinbelow. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. are contemplated. For example, in the following description, forming the first component above or on the second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components are formed between the first and second components such that the first and second components may not be in direct contact. Also, the present invention may repeat reference numerals and / or letters in the various examples. Such repetition is for the purpose of simplicity and clarity, but does not in itself indicate a relationship between the various embodiments and / or configurations being discussed. The source / drain may refer to the source or the drain individually or collectively, depending on the context.

[0021] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. Spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0022] In some embodiments, a first semiconductor die is coupled to a second semiconductor die. Each of the first semiconductor die and the second semiconductor die includes a transmit circuit (or output circuit) and a receive circuit (or input circuit), which are correspondingly coupled to the receive circuit and the transmit circuit of the other semiconductor die. In at least one embodiment, the second semiconductor die returns a clock signal received from the first semiconductor die to the first semiconductor die, and also uses the returned clock signal to send data to the first semiconductor die. In some embodiments, a circuit (such as a flip-flop) is coupled to the receive circuit of the first semiconductor die and is configured to output data received from the second semiconductor die in response to an active clock edge of the clock signal of the first semiconductor die. The active clock edge may be selected between the rising edge and the falling edge to ensure correct data output. In at least one embodiment, one or more effects can be achieved, including but not limited to data accuracy, additional timing margin for the clock for die-to-die interconnect to achieve maximum robustness and minimum delay for the interface (I / F) timing, a robust input / output (I / O) interface without using a first-in-first-out (FIFO) circuit, thereby saving power and area, sufficient setup time and / or hold time without being affected by duty cycle error and / or jitter, etc.

[0023] In some embodiments, the second semiconductor die includes a phase-locked loop (PLL) coupled to its receiving circuit. The PLL is configured to generate a clock signal based on a clock signal provided from the first semiconductor die for use by the second semiconductor die to send data to the first semiconductor die. In at least one embodiment, the PLL includes at least one delay circuit in its feedback path, the delay circuit being configured to match and compensate for the delay on the communication channel between the first semiconductor die and the second semiconductor die. In at least one embodiment, when such a PLL is included in the second semiconductor die, the flip-flop is omitted from the first semiconductor die. In at least one embodiment, the clock signal for the second semiconductor die to send data to the first semiconductor die can be selected between the clock signal provided from the first semiconductor die and the clock signal generated by the PLL. Thus, in one or more embodiments, one or more effects can be achieved, including but not limited to improved timing margins, and valuable Si testing can still be performed despite additional power and / or area losses on the second semiconductor die. In one or more embodiments described herein, further advantages and / or effects can be achieved.

[0024] Figure 1A is a schematic circuit diagram of an IC device 100 according to some embodiments.

[0025] IC device 100 includes a first semiconductor die 110 (labeled "Die 1" in Figure 1A and a second semiconductor die 120 (labeled "Die 2" in Figure 1A ), which are electrically and / or physically coupled by a plurality of die-to-die (D2D) interface structures 130. In some embodiments, semiconductor die 110 and semiconductor die 120 are stacked together and physically bonded and electrically coupled in a three-dimensional (3D) IC arrangement. In some embodiments, semiconductor die 110 and semiconductor die 120 are arranged side by side on another substrate, wafer, interposer, or die (not shown) and physically bonded thereto, and are electrically coupled together through another substrate, wafer, interposer, chip, etc. in another 3D IC arrangement. Examples of 3D IC arrangements include but are not limited to CoWoS (chip-on-wafer-on-substrate), InFO (integrated fan-out) wafer-level packaging, SoIC (system-on-integrated-chip), etc. In some embodiments, IC device 100 includes more than two semiconductor dies that are electrically and / or physically coupled to each other. In some embodiments, IC device 100 has one die, such as semiconductor die 110 or semiconductor die 120, while omitting the other die, for example, before bonding multiple dies together to form a 3D IC arrangement. Regarding Figures 8A - 8BDescribes non - limiting examples of various 3D IC arrangements. Examples of the D2D interface structure 130 include, but are not limited to, through - silicon vias (TSVs), hybrid bumps, micro - bumps (ubumps), etc.

[0026] Each of the semiconductor dies 110, 120 includes one or more functional circuits and one or more input / output (I / O) circuits electrically coupled to the one or more functional circuits. In at least one embodiment, each of the semiconductor dies 110, 120 includes a plurality of I / O circuits electrically coupled to each functional circuit. In Figure 1A it, the functional circuits and I / O circuits are designated by the respective labels "Core" and "I / O", and are schematically distinguished from each other by a dotted line between the labels "Core" and "I / O". Specifically, as Figure 1A shown, the semiconductor die 110 includes I / O circuits located to the right of the respective dotted line and at least one functional circuit located to the left of the respective dotted line. Similarly, as Figure 1A shown, the semiconductor die 120 includes I / O circuits located to the left of the corresponding dotted line and at least one functional circuit located to the right of the corresponding dotted line. The difference between the shown functional circuits and I / O circuits is an example. Other arrangements are within the scope of various embodiments.

[0027] The functional circuits of the semiconductor die are configured to perform the intended functions of the semiconductor die, such as data processing or data storage. Examples of one or more circuits, logics, or units included in the functional circuits include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OR - AND - Invert (OAI), MUX, Flip - flop, BUFF, Latch, delay, clock, memory, etc. The circuits, logics, or units included in the functional circuits include functional transistors or core transistors. Examples of transistors in the functional circuits and other circuits described herein (e.g., I / O circuits) include, but are not limited to, metal - oxide - semiconductor field - effect transistors (MOSFETs), complementary metal - oxide - semiconductor (CMOS) transistors, P - channel metal - oxide - semiconductor (PMOS) transistors, N - channel metal - oxide - semiconductor (NMOS) transistors, bipolar junction transistors (BJTs), high - voltage transistors, high - frequency transistors, P - channel and / or N - channel field - effect transistors (PFET / NFET), FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc.

[0028] The I / O circuits are electrically coupled to the functional circuits on the same semiconductor die and are configured as interface circuits between the functional circuits and external circuits outside the semiconductor die. InFigure 1A In an example configuration, the representative I / O circuits of die 110 include a first transmit circuit 111 and a first receive circuit 112, while the representative I / O circuits of die 120 include a second receive circuit 121 and a second transmit circuit 122.

[0029] The transmit circuit 111 of die 110 includes a flip-flop FF1, a data output buffer Tx1, and a clock output buffer Tx2. The flip-flop FF1 includes an input configured to receive a signal D1 from the functional circuits of die 110, a clock input configured to receive a clock signal CLK1, and an output. For simplicity, conductive structures (e.g., nodes, inputs, outputs, etc.) and their signals are designated by the same reference numbers or labels. For example, both the clock input of the flip-flop FF1 and the clock signal provided to it are designated by the same label "CLK1". The data output buffer Tx1 includes an input coupled to the output of the flip-flop FF1 and an output coupled to a corresponding D2D interface structure (referred to herein as channel Ch1). The clock output buffer Tx2 includes an input configured to receive a clock signal Clk_in1 through a clock driver (or clock buffer) 115 and an output coupled to a corresponding D2D interface structure (referred to herein as channel Ch2). In at least one embodiment, the clock driver 115 is omitted. Die 110 also includes a clock tree CT1 configured to propagate the clock signal Clk_in1 to other circuits. For example, the clock signal CLK1 corresponds to the clock signal Clk_in1 that is propagated through the clock tree CT1 and reaches the clock input of the flip-flop FF1.

[0030] The receiving circuit 121 of the semiconductor die 120 is coupled to the transmitting circuit 111 of the semiconductor die 110 through channel Ch1 and channel Ch2. The receiving circuit 121 includes a flip-flop FF2, a data input buffer Rx1, and a clock input buffer Rx2. The data input buffer Rx1 includes an input coupled to the output of the data output buffer Tx1 through channel Ch1, and an output. The flip-flop FF2 includes an input coupled to the output of the data input buffer Rx1 to receive the signal D2, a clock input configured to receive the clock signal CLK2, and an output. The signal D2 corresponds to the signal D1 transmitted by the transmitting circuit 111 through channel Ch1, which is received and provided by the data input buffer Rx1. The output of the flip-flop FF2 is configured to provide the signal D2 to the functional circuit of the semiconductor die 120. The clock input buffer Rx2 includes an input coupled to the output of the clock output buffer Tx2 through channel Ch2, and an output configured to output the clock signal Clk_out1. The clock signal Clk_out1 corresponds to the clock signal Clk_in1 transmitted through the clock driver 115, which is transmitted by the clock output buffer Tx2 through channel Ch2, received and provided by the clock input buffer Rx2. The semiconductor die 120 further includes a clock tree CT2, which is configured to propagate the clock signal Clk_out1 to other circuits. For example, the clock signal CLK2 corresponds to the clock signal Clk_out1 propagated through the clock tree CT2 and reaching the clock input of the flip-flop FF2. In Figure 1A the example configuration, the clock signal CLK2 is an inverted clock signal, i.e., the high level of the clock signal CLK2 corresponds to the low level of the clock signal Clk_out1, and vice versa.

[0031] In Figure 1A the example configuration, the semiconductor die 120 further includes a multiplexer MUX2. The multiplexer MUX2 includes a first input, a second input, a selection input, and an output. The first input (labeled "0" in Figure 1A is coupled to the output of the clock input buffer Rx2 to receive the clock signal Clk_out1. The second input terminal ( Figure 1AThe one labeled as “1”) is configured to receive the clock signal Clk_loc2 of the semiconductor die 120. The select input is configured to receive a select signal Sel2, for example, from a control circuit in the functional circuitry of the semiconductor die 120. The output of the multiplexer MUX2 is coupled to the transmit circuit 122. Depending on the value of the select signal Sel2, the multiplexer MUX2 is configured to output a clock signal Clk_in2 corresponding to either the clock signal Clk_out1 or the clock signal Clk_loc2. For example, in response to the value of the select signal Sel2 being logic “0”, the multiplexer MUX2 is configured to output the clock signal Clk_in2 corresponding to the clock signal Clk_out1, and in response to the value of the select signal Sel2 being logic “1”, the multiplexer MUX2 is configured to output the clock signal Clk_in2 corresponding to the clock signal Clk_loc2.

[0032] In some embodiments, the clock signal Clk_in1 corresponds to the master clock signal provided from the semiconductor die 110 to the semiconductor die 120, and the clock signal Clk_loc2 corresponds to the local clock signal of the semiconductor die 120. In at least one embodiment, the clock signal Clk_loc2 is independent of the clock signal Clk_in1 and its variants (e.g., the clock signal CLK1, the clock signal CLK2, the clock signal Clk_out1, etc.). For example, the clock signal Clk_loc2 and the clock signal Clk_in1 have different clock sources. The clock signal Clk_loc2 is an example of a second clock signal. In at least one embodiment, the multiplexer MUX2 allows for a selection (e.g., selected by a control circuit in the functional circuitry of the semiconductor die 120) to use either the master clock signal provided by the semiconductor die 110 or the local clock signal of the semiconductor die 120 to send data to the semiconductor die 110. The former enables the achievement of one or more of the effects described herein in one or more embodiments, such as additional timing margins, clock robustness, etc. The latter is useful in situations or applications where it is desired for two coupled semiconductor dies to communicate with each other using their own independent clocks.

[0033] In the following description, unless otherwise stated, the multiplexer MUX2 outputs the clock signal Clk_in2 corresponding to the clock signal Clk_out1, that is, the clock signal received from the semiconductor die 110 is returned to the semiconductor die 110 for sending data from the semiconductor die 120 to the semiconductor die 110. In this configuration, the clock signal Clk_in2 is sometimes referred to as the return clock signal. In at least one embodiment, the multiplexer MUX2 is omitted, and the output of the clock input buffer Rx2 is coupled to the transmit circuit 122 in an arrangement corresponding to the clock signal Clk_out1 being the clock signal Clk_in2.

[0034] The transmission circuit 122 of the semiconductor die 120 includes a flip-flop FF3, a data output buffer Tx3, and a clock output buffer Tx4. The flip-flop FF3 includes an input configured to receive a signal D3 from the functional circuit of the semiconductor die 120, a clock input configured to receive a clock signal CLK3, and an output. The data output buffer Tx3 includes an input coupled to the output of the flip-flop FF3 and an output coupled to a corresponding D2D interface structure (referred to herein as channel Ch3). The clock output buffer Tx4 includes an input configured to receive a clock signal Clk_in2 through a clock driver 125 and an output coupled to a corresponding D2D interface structure (referred to herein as channel Ch4). In at least one embodiment, the clock driver 125 is omitted. The semiconductor die 120 further includes a clock tree CT3 configured to propagate the clock signal Clk_in2 to other circuits. For example, the clock signal CLK3 corresponds to the clock signal Clk_in2 that is propagated through the clock tree CT3 and reaches the clock input of the flip-flop FF3.

[0035] The receiving circuit 112 of the semiconductor die 110 is coupled to the transmission circuit 122 of the semiconductor die 120 through channel Ch3 and channel Ch4. The receiving circuit 112 includes a flip-flop FF4, a data input buffer Rx3, and a clock input buffer Rx4. The data input buffer Rx3 includes an input coupled to the output of the data output buffer Tx3 through channel Ch3 and an output configured to output a signal D4. The signal D4 corresponds to the signal D3 that is transmitted by the transmission circuit 122 through channel Ch3, received by the data input buffer Rx3, and provided. The flip-flop FF4 includes an input coupled to the output of the data input buffer Rx3 to receive the signal D4, a clock input configured to receive a clock signal CLK4, and an output configured to provide a signal D5 corresponding to the signal D4. The clock input buffer Rx4 includes an input coupled to the output of the clock output buffer Tx4 through channel Ch4 and an output configured to output a clock signal Clk_out2. The clock signal Clk_out2 corresponds to the clock signal Clk_in2 that is transmitted by the clock output buffer Tx4 through channel Ch4 through the clock driver 125, received by the clock input buffer Rx4, and provided. The semiconductor die 110 further includes a clock tree CT4 configured to propagate the clock signal Clk_out2 to other circuits. For example, the clock signal CLK4 corresponds to the clock signal Clk_out2 that is propagated through the clock tree CT4 and reaches the clock input of the flip-flop FF4. In Figure 1A the example configuration, the clock signal CLK4 is an inverted clock signal, i.e., the high level of the clock signal CLK4 corresponds to the low level of the clock signal Clk_out2, and vice versa.

[0036] In Figure 1AIn the example configuration, the semiconductor die 110 further includes a multiplexer MUX1 and a flip-flop FF5. The multiplexer MUX1 includes a first input, a second input, a select input, and an output. The first input (labeled "0" in Figure 1A is configured to receive the inverted input of the clock signal CLK1, and the second input (labeled "1" in Figure 1A is configured to receive the non-inverted input of the clock signal CLK1. In other words, the clock signal CLK1 and the inverted clock signal of the clock signal CLK1 (referred to herein as "inverted clock signal CLK1") are input to the multiplexer MUX1. The select input is configured to receive a select signal Sel1, for example, from a control circuit in the functional circuit of the semiconductor die 110. The output of the multiplexer MUX1 is coupled to the clock input of the flip-flop FF5. According to the value of the select signal Sel1, the multiplexer MUX1 is configured to output a clock signal CLK5 corresponding to either the clock signal CLK1 or the inverted clock signal CLK1. For example, in response to the select signal Sel1 having a logic "0" value, the multiplexer MUX1 is configured to output a clock signal CLK5 corresponding to the inverted clock signal CLK1, and in response to the select signal Sel1 having a logic "1" value, the multiplexer MUX1 is configured to output a clock signal CLK5 corresponding to the clock signal CLK1. Logic "1" is an example of one of the first and second values of the select signal Sel1, and logic "0" is an example of the other of the first and second values of the select signal Sel1. The flip-flop FF5 includes an input coupled to the output of the flip-flop FF4 to receive a signal D5, a clock input coupled to the output of the multiplexer MUX1 to receive a clock signal CLK5, and an output configured to provide a signal D6 corresponding to the signal D5 to the functional circuit of the semiconductor die 110. In some embodiments, the multiplexer MUX1 and / or the flip-flop FF5 are omitted.

[0037] The flip - flop is configured to output the signal or data received at the flip - flop input based on the clock signal at the flip - flop clock input. For example, flip - flop FF1 outputs the signal D1 received at the input of flip - flop FF1 in response to the edge of the clock signal CLK1 (also referred to herein as the “valid clock edge”) at the clock input of flip - flop FF1. For simplicity, the valid clock edge of all flip - flops described herein is the rising edge. For example, flip - flop FF1 outputs signal D1 in response to the rising edge of clock signal CLK1. As another example, flip - flop FF2 outputs signal D2 in response to the rising edge of clock signal CLK2. However, since clock signal CLK2 is an inverted clock signal, flip - flop FF2 outputs signal D2 in response to the falling edge of clock signal Clk_out1 (some time delay associated with clock tree CT2). In some embodiments, at least one of the flip - flops described herein has a falling edge as the valid clock edge. The described flip - flops are examples. Other circuits configured to output the signal or data received at their input based on a clock signal are within the scope of various embodiments.

[0038] The described multiplexer MUX1 or multiplexer MUX2 is an example. Other selection circuits configured to allow selection of one signal (e.g., a clock signal) among two or more signals (e.g., clock signals) are within the scope of various embodiments. The described logic “0” and logic “1” are examples. Other configurations that replace the described logic “0” with logic “1” and vice versa are within the scope of various embodiments. Examples of one or more circuits in at least one of the described input buffer and / or output buffer include, but are not limited to, buffers, latches, level shifters, inverters, etc. In some embodiments, for semiconductor die 110, data output buffer Tx1 and data input buffer Rx3 configure the data I / O circuit, while clock output buffer Tx2 and clock input buffer Rx4 configure the clock I / O circuit. In some embodiments, for semiconductor die 120, data output buffer Tx3 and data input buffer Rx1 constitute the data I / O circuit, while clock output buffer Tx4 and clock input buffer Rx2 constitute the clock I / O circuit. According to some embodiments, multiplexer MUX1, multiplexer MUX2 are examples of clock management circuits, or at least a part thereof.

[0039] Viewed from semiconductor die 110, the transmitting circuit 111 is configured to transmit output signal 116 and output clock signal 117 to the receiving circuit 121 through channel Ch1 and channel Ch2 respectively, and the receiving circuit 112 is configured to receive input signal 118 and input clock signal 119 from the transmitting circuit 122 through channel Ch3 and channel Ch4 respectively.

[0040] Specifically, the transmitting circuit 111 is configured to transmit an output signal 116 based on a clock signal CLK1 at the clock input terminal of the flip-flop FF1. The output signal 116 corresponds to the signal D1 input to the flip-flop FF1. The clock signal CLK1 is an example of a first clock signal. The receiving circuit 121 is configured to receive the output signal 116 from the transmitting circuit 111 and provide the received output signal 116 from the data input buffer Rx1 as the signal D2.

[0041] The transmitting circuit 111 is further configured to transmit an output clock signal 117, which includes a clock signal Clk_in1 passing through the clock driver 115 and the clock output buffer Tx2 and corresponding to the clock signal CLK1. The receiving circuit 121 is configured to receive the output clock signal 117 from the transmitting circuit 111 and provide the received output clock signal 117 from the output of the clock input buffer Rx2 as the clock signal Clk_out1. In response to the selection signal Sel1 being logic "0", the clock signal Clk_out1 is provided to the transmitting circuit 122 as the clock signal Clk_in2 by the multiplexer MUX2 through the clock driver 125 and the clock tree CT3.

[0042] The transmitting circuit 122 is configured to transmit an input signal 118 to the receiving circuit 112 based on a clock signal CLK3, which is the clock signal Clk_in2 propagated through the clock tree CT3 to the clock input of the flip-flop FF3. The input signal 118 corresponds to the signal D3 input to the flip-flop FF3. In some embodiments, the signal D3 is responsive to the signal D1, for example, when the semiconductor die 110 and the semiconductor die 120 cooperate in the same application or during the calibration process described herein. In at least one embodiment, the signal D3 is independent of the signal D1. The transmitting circuit 122 is configured to transmit an input clock signal 119 to the receiving circuit 112. The input clock signal 119 corresponds to the clock signal Clk_in2 passing through the clock driver 125 and the clock output buffer Tx4.

[0043] The receiving circuit 112 is configured to receive the input signal 118 and the input clock signal 119 and provide the received input signal 118 and input clock signal 119 as the signal D4 at the output of the data input buffer Rx3 and the clock signal Clk_out2 at the output of the clock input buffer Rx4, respectively. The receiving circuit 112 is further configured to output a signal D5 based on a clock signal CLK4, which is the clock signal Clk_out2 propagated through the clock tree CT4 to the clock input of the flip-flop FF4. The signal D5 is an example of a first signal.

[0044] The flip-flop FF5 is configured to provide a signal D6 corresponding to the signal D5 based on a clock signal CLK5 at the clock input of the flip-flop FF5. The clock signal CLK5 is provided by a multiplexer MUX1 based on a selection signal Sel1 and corresponds to the clock signal CLK1. The flip-flop FF5 and the multiplexer MUX1 constitute an example of a first circuit configured to output a second signal (i.e., the signal D6) corresponding to a first signal (i.e., the signal D5) based on a first clock signal (i.e., the clock signal CLK1).

[0045] As described herein, various signals in the IC device 100 are provided based on corresponding clock signals. Thus, clock accuracy is a consideration for ensuring that the IC device 100 operates correctly according to design and / or expectation. During the transmission of clock signals between the semiconductor die 110 and the semiconductor die 120, many time delays and / or jitters occur and may affect clock accuracy and / or latency. Time delay is generally a constant or predictable parameter corresponding to the increase in time required for a signal (e.g., a clock signal) to propagate from one point to another along a signal path. On the other hand, jitter appears as fluctuations in time delay. Example types of jitter include deterministic jitter (Dj) and random jitter (Rj). Dj is a predictable jitter. While Rj is unpredictable.

[0046] The time delay of a circuit element or a signal path depends on various physical and / or electrical characteristics of the individual circuit elements on the circuit element or the signal path. As Figure 1A and Figure 1B shown, the clock signal Clk_in1 has a clock edge, such as a rising edge, at a timing T0. The clock signal Clk_in1 passes through a first signal path including a clock driver 115, a clock output buffer Tx2, a channel Ch2, and a clock input buffer Rx2 and arrives at the semiconductor die 120 as the clock signal Clk_out1. The clock edge at the timing T0 of the clock signal Clk_in1 becomes or corresponds to the clock edge at the timing T1 of the clock signal Clk_out1. The difference between the timings T1 and T0 is the time delay td1 of the described first signal path, as Figure 1A schematically shown. The jitter J1 on the first signal path between the timings T0 and T1 typically occurs on the channel Ch2, as Figure 1A schematically shown.

[0047] The clock signal Clk_out1 passes through a second signal path, which includes a multiplexer MUX2, a clock driver 125, a clock output buffer Tx4, a clock input buffer Rx4, and arrives at the semiconductor die 110 as the clock signal Clk_out2. The clock edge of the timing T1 of the clock signal Clk_out1 becomes or corresponds to the clock edge of the timing T2 of the clock signal Clk_out2. The difference between the timing T2 and the timing T1 is the time delay td2 of the described second signal path, as Figure 1A schematically shown in.

[0048] Figure 1A The additional time delays shown in include the time delays t_mt, t_sr, t_st, t_mr, t_mux, td3 of the clock trees CT1, CT2, CT3, CT4, the multiplexer MUX1, and the flip-flop FF4. In at least one embodiment, the multiplexer MUX2 has a time delay similar to that of the multiplexer MUX1. However, the time delay of the multiplexer MUX2 has been included in the time delay td2 and is not considered separately here. In some embodiments, the multiplexer MUX2 is omitted, or the time delay of the multiplexer MUX2 can be ignored, and the time delay td2 corresponds to the time delay between the clock signal Clk_in2 and the clock signal Clk_out2.

[0049] The clock signal Clk_out2 passes through the clock tree CT4 and arrives at the clock input of the flip-flop FF4 as the clock signal CLK4. The clock edge of the clock signal Clk_out2 having the timing T2 becomes or corresponds to the clock edge of the clock signal CLK4, for example, the falling edge of the clock signal CLK4, because the clock signal CLK4 is an inverted clock signal. In response to the falling edge of the clock signal CLK4, the flip-flop FF4 outputs the corresponding edge of the signal D5 at the timing T3. The difference between the timing T3 and the timing of the falling edge of the clock signal CLK4 is the time delay td3 of the flip-flop FF4, as Figure 1A and Figure 1B schematically indicated in. The jitter J2 along the second signal path and through the clock tree CT4 and the flip-flop FF4 generally occurs on the channel Ch4, as Figure 1A also schematically indicated in.

[0050] Figure 1B is a schematic timing diagram of various signals in the operation of the IC device 100 according to some embodiments Figure 1A shown.

[0051] Figure 1BThe signals shown include clock signal Clk_in1, clock signal CLK4, signal D5, clock signal CLK1, clock signal CLK5_0, and clock signal CLK5_1. Clock signal CLK5_0 is the clock signal CLK5 when the value of selection signal Sel1 is logic "0", and multiplexer MUX1 is configured to output the inverted clock signal CLK1. Clock signal CLK5_1 is the clock signal CLK5 when the value of selection signal Sel1 is logic "1", and multiplexer MUX1 is configured to output clock signal CLK1.

[0052] As described herein, clock signal Clk_in1 has a clock edge 151 at timing T0. In Figure 1B the example configuration, clock edge 151 is a rising edge. Clock signal Clk_in1 has a clock period T, which is also the clock period of the other clock signals, namely clock signal CLK4, clock signal CLK1, clock signal CLK5_0, and clock signal CLK5_1.

[0053] Clock signal CLK4 has a clock edge 152 at timing T3. As Figure 1B shown, clock signal CLK4 is an inverted clock signal relative to clock signal Clk_in1, and has a clock edge 152 (which is a falling edge) corresponding to the clock edge 151 (which is a rising edge) of clock signal Clk_in1. The time delay between clock signal Clk_in1 and clock signal CLK4 is the time delay between the corresponding clock edges 151, 152, i.e., td1 + td2 + t_mr. In Figure 1B the example configuration, the falling edges 152, 153, 154, etc. of clock signal CLK4 are valid clock edges, in response to which flip-flop FF4 provides signal D5.

[0054] Signal D5 includes multiple bits d0, d1, d2, etc. Each bit d0, d1, d2, etc. is provided by flip-flop FF4 in response to the corresponding one of the valid clock edges of clock signal CLK4. For example, bit d0 is provided in response to clock edge 152, bit d1 is provided in response to clock edge 153, bit d2 is provided in response to clock edge 154, and so on.

[0055] Signal D5 includes a signal portion 155 corresponding to bit d0. The start 157 of signal portion 155 corresponding to bit d0 appears at timing T3, with a time delay td3 from the corresponding clock edge 152. The end 159 of signal portion 155, which is also the start of the subsequent signal portion of signal D5 containing bit d1, has the same time delay td3 from the corresponding clock edge 153. The time difference (i.e., duration) between the start 157 and the end 159 of signal portion 155 containing bit d0 is the clock period T.

[0056] The clock signal CLK1 (based on which the signal D5 input to the flip-flop FF5 is output as the signal D6) has clock edges 160, 162, 164 at intervals of half of the clock period T. The clock edge 160 of the clock signal CLK1 is the rising edge corresponding to the clock edge 151 of the clock signal Clk_in1. The time delay between the clock signal Clk_in1 and the clock signal CLK1 is the time delay between the corresponding clock edges 151, 160, i.e., the time delay t_mt of the clock tree CT1. The clock edges of the clock signal CLK1 after the clock edge 160 include a falling edge 162 and a rising edge 164. The falling edge 162 and the rising edge 164 correspond to the timings ta and tb for outputting or reading out the signal D5 as the signal D6 from the flip-flop FF5. The falling edge 162 is an example of one of the first and second edges of the clock signal CLK1 for reading out the signal D5, and the rising edge 164 is an example of the other of the first and second edges of the clock signal CLK1 for reading out the signal D5. The timing ta or the timing tb can be selected by the corresponding value of the selection signal Sel1.

[0057] For example, the selection signal Sel1 having a logic "0" value corresponds to selecting the timing ta for reading out the signal D5. As described herein, in response to the selection signal Sel1 having a logic "0" value, the clock signal CLK5_0 corresponding to the inverted clock signal CLK1 is output from the multiplexer MUX1 to the clock input of the flip-flop FF5. The clock signal CLK5_0 has a falling edge 171 corresponding to the rising edge 160 of the clock signal CLK1, and a rising edge 172 corresponding to the falling edge 162 of the clock signal CLK1. The time delay between the clock signal CLK1 and the clock signal CLK5_0 is the time delay between the corresponding clock edges 160, 171, i.e., the time delay t_mux of the multiplexer MUX1 ( Figure 1B not indicated in). The rising edges 172 and subsequent rising edges 176, 177 of the clock signal CLK5_0 are the valid clock edges of the flip-flop FF5. Specifically, the rising edge 172 is the valid clock edge in response to which the bit d0 of the signal D5 is read out by the flip-flop FF5 as part of the signal D6. The time delay between the rising edge 172 of the clock signal CLK5_0 and the corresponding falling edge 162 of the clock signal CLK1 is the time delay between the clock signal CLK5_0 and the clock signal CLK1, and corresponds to the time delay t_mux of the multiplexer MUX1.

[0058] To ensure correct operation, the flip-flop FF5 must meet certain requirements, including setup time and hold time. Setup time and hold time are sometimes referred to as timing margins. Setup time is the predetermined minimum amount of time required for the signal at the data input of the flip-flop to stabilize before the active clock edge arrives at the clock input of the flip-flop. Hold time is the predetermined minimum amount of time required for the signal at the data input to stabilize after the active clock edge arrives at the clock input. As Figure 1B shown, for the selected timing ta or when the select signal Sel1 is logic "0", the setup time t_setup_ta of the flip-flop FF5 is the time difference between the start 157 of the signal portion 155 of the signal D5 and the rising edge 172 of the clock signal CLK5_0, and the hold time t_hold_ta of the flip-flop FF5 is the time difference between the end 159 of the signal portion 155 of the signal D5 and the rising edge 172 of the clock signal CLK5_0. The timing T3 of the start 157 of the signal portion 155 is expressed as (T0 + td1 + td2 + t_mr + td3), the timing of the end 159 of the signal portion 155 is expressed as (T0 + td1 + td2 + t_mr + td3 + T), and t_setup_ta and t_hold_ta are determined by the following equations:

[0059] t_setup_a = (T0 + t_mt + T / 2 – Jpw + t_mux) – (T0 + td1 + td2 + t_mr + td3)

[0060] = T / 2 + t_mux – t_x – Jpw (1)

[0061] t_hold_a = (T0 + td1 + td2 + t_mr + td3 + T) – (T0 + t_mt + T / 2 + Jpw + t_mux)

[0062] = t_x + T / 2 – Jpw – t_mux (2)

[0063] In equations (1)-(2), Jpw is the duty cycle error (or clock duty cycle error), and t_x = td1 + td2 + t_mr + td3 - t_mt. In some embodiments, the duty cycle error Jpw is omitted or negligible. As Figure 1B shown, t_x is the time delay between the signal D5 and the clock signal CLK1 without jitter. In some cases where there is clock jitter, the cycle jitter is the uncorrelated jitter of one or more clock buffers associated with the clock signal CLK1 and the clock signal CLK4. Assume that the random jitter has a distribution of, for example, σ 1_4 = 0.1ps, the peak-to-peak jitter is 2ps, with 20×σ 1_4 .

[0064] For another example, a selection signal Sel1 having a logic "1" value corresponds to a timing tb for selecting the readout signal D5. As described herein, in response to the selection signal Sel1 having a logic "1" value, a clock signal CLK5_1 corresponding to the clock signal CLK1 is output from the multiplexer MUX1 to the clock input of the flip-flop FF5. The clock signal CLK5_1 has a rising edge 173 corresponding to the rising edge 160 of the clock signal CLK1, and another rising edge 174 corresponding to the rising edge 164 of the clock signal CLK1. The time delay between the clock signal CLK1 and the clock signal CLK5_1 is the time delay between the corresponding clock edges 160 and 173, i.e., the time delay t_mux of the multiplexer MUX1 ( Figure 1B not marked in). The rising edges 174, 178, and 179 of the clock signal CLK5_1 are the valid clock edges of the flip-flop FF5. Specifically, the rising edge 174 is the valid clock edge for the flip-flop FF5 to respond to bit d0 of its readout signal D5. The time delay between the rising edge 174 of the clock signal CLK5_1 and the corresponding rising edge 164 of the clock signal CLK1 is the time delay between the clock signal CLK5_1 and the clock signal CLK1, and corresponds to the time delay t_mux of the multiplexer MUX1.

[0065] As described herein, the flip-flop FF5 needs to meet certain requirements, including setup time and hold time, to ensure normal operation. As Figure 1B shown, for the selected timing tb or when the selection signal Sel1 is logic "1", the setup time t_setup_tb of the flip-flop FF5 is the time difference between the start 157 of the signal portion 155 of the signal D5 and the rising edge 174 of the clock signal CLK5_1, while the hold time t_hold_tb of the flip-flop FF5 is the time difference between the end 159 of the signal portion 155 of the signal D5 and the rising edge 174 of the clock signal CLK5_1. Specifically, t_setup_tb and t_hold_tb are determined by the following equations:

[0066] t_setup_tb = (T0 + t_mt + t_mux + T) – (T0 + td1 + td2 + t_mr + td3)

[0067] = T + t_mux – t_x (3)

[0068] t_hold_tb = (T0 + td1 + td2 + t_mr + td3 + T) – (T0 + t_mt + t_mux + T)

[0069] = t_x – t_mux (4)

[0070] In a non - limiting example, at an operating frequency of 4 GHz, T is 250 ps, and for an advanced process, it is estimated that t_x is equal to or less than 60 ps during process voltage temperature (PVT) variations and power supply drops. From Equation (1), t_setup_a = T / 2 + t_mux – t_x – Jpw, corresponding to a timing margin of approximately 60 ps, where T / 2 = 125 ps and t_x is equal to or less than 60 ps. From Equation (2), t_hold_a = t_x + T / 2 – Jpw – t_mux, corresponding to a timing margin of approximately 180 ps, which is sufficient to address various timing - related issues discussed herein.

[0071] When t_x is close to T / 2 or greater than T / 2, i.e., Figure 1B the signal D5 further shifts to the right, and timing tb provides a better timing margin than timing ta and is selected for reading out the signal D5 in one or more embodiments. For example, from Equation (3), t_setup_b = T + t_mux - t_x. When t_x is close to T / 2 (or 125 ps in the above non - limiting example), timing tb provides the best setup time and hold time.

[0072] When one of the setup time t_setup_ta and the hold time t_hold_ta is less than the corresponding predetermined minimum time amount, signal stability and / or data accuracy are affected, and it is not suitable to use timing ta or the corresponding clock signal CLK5_0 to read out the signal D5. Similarly, when one of t_setup_tb and t_hold_tb is less than the corresponding predetermined minimum time amount, it is not suitable to use timing tb or the corresponding clock signal CLK5_1 to read out the signal D5.

[0073] In at least one embodiment, it is advantageous that the corresponding setup time and hold time are equal or as close as possible so that the signal D5 is read out by an effective clock edge (e.g., rising edge 172 or rising edge 174) located at or near the “eye” or center of the corresponding signal portion (e.g., signal portion 155) of the signal D5. This reading at the “eye” or center is associated with both the setup time and the hold time being equal to half of the clock period (i.e., T / 2). These timing margins are optimal and can overcome various problems, including but not limited to jitter, skew mismatch, channel impairment, clock duty - cycle error, etc.

[0074] In some embodiments, the selection of timing ta or timing tb corresponds to the selection of reading out signal D5 through the falling edge or rising edge of clock signal CLK1 by flip-flop FF5 and / or the selection of providing an inverted clock signal CLK1 or clock signal CLK1 to the clock input of flip-flop FF5. In at least one embodiment, at the design stage, the corresponding setup time and hold time are determined or estimated by using one or more of equations (1)-(4) to select whether to use timing ta or timing tb to read out signal D5 at flip-flop FF5. As can be seen from equations (1)-(4), most components (such as t_x, t_mux, T) are known or can be determined based on various physical and / or electrical characteristics of the circuit elements on the signal path. Based on the determined setup time and hold time, timing ta or timing tb with better determined setup time and hold time (e.g., a smaller difference between the setup time and the hold time) is selected. The value of selection signal Sel1 corresponding to the selected timing ta or timing tb (e.g., logic "0" or logic "1") is stored in a storage circuit coupled to the selection input of multiplexer MUX1, as described with respect to Figure 2 as described. Alternatively or additionally, in some embodiments, whether to use timing ta or timing tb to read out signal D5 at flip-flop FF5 is selected during manufacturing and / or operation through a calibration process, as described with respect to Figure 3 as described.

[0075] In some embodiments, by returning the clock signal Clk_out1 received at semiconductor die 120 back to semiconductor die 110 and also using the returned clock signal (i.e., clock signal Clk_in2) to send data from semiconductor die 120 to semiconductor die 110, the inventors' observation that the signal paths corresponding to jitter J1 and jitter J2 have the same or substantially the same inherent delay can be utilized. Thus, in one or more embodiments, it is not necessary to provide a delay matching device on semiconductor die 110 as in some other methods. In some embodiments, data sampling or reading out of signal D2 and / or signal D4 from the corresponding flip-flop FF2 and / or flip-flop FF4 has optimal, more robust, and / or better timing margins than some other methods that have a delay matching device with a master clock on the chip.

[0076] In some embodiments, by including flip-flop FF5 and multiplexer MUX1 in semiconductor die 110, an optimal timing margin for reading out signal D5 can be achieved. Specifically, due to the extended signal path of clock signal Clk_in1 from semiconductor die 110 to semiconductor die 120 and back to semiconductor die 110, the time delay along this extended signal path (e.g., td1 + td2 + td3) is also large. In some cases, this large time delay td1 + td2 + td3 can reduce the originally available timing margin (e.g., setup time or hold time) to a very short amount of time, which may not be sufficient to accommodate one or more issues such as jitter, skew mismatch, channel impairment, clock duty cycle error, etc. By providing two options through multiplexer MUX1 for reading out signal D5 in response to the rising edge or falling edge of clock signal CLK1, in one or more embodiments, the better one of the two options can be selected, i.e., the option with a smaller difference between the setup time and hold time for reading signal D5, to achieve the optimal timing margin without being affected by duty cycle error and / or jitter.

[0077] From Figure 1B It can be seen that reading out signal D5 based on timing ta or in response to the falling edge of clock signal CLK1 is associated with a delay of T / 2 (half period), while reading out signal D5 based on timing tb or in response to the rising edge of clock signal CLK1 is associated with a delay of T (full period). In some embodiments, when the timing margins of the two options are the same or substantially the same, e.g., the differences between the setup time and hold time of the two options are the same or substantially the same, timing ta is superior to timing tb due to the shorter delay.

[0078] In some embodiments, flip-flop FF5 and multiplexer MUX1 are omitted, e.g., where td1 + td2 + td3 is small compared to the clock period T.

[0079] In some embodiments, the clock signal Clk_in1 transmitted between the semiconductor die 110 and the semiconductor die 120 provides a common clock domain between the semiconductor die 110 and the semiconductor die 120. Thus, clock synchronization can be avoided in one or more embodiments, whereas in other methods where each method uses two different and / or independent clock domains for one of the coupled chips, clock synchronization is required. In such other methods, various circuits for clock synchronization are needed, such as a first-in-first-out (FIFO) circuit associated with the receiving circuit of each die, and may result in an increase in power consumption and / or latency. The IC device according to some embodiments does not have such a FIFO circuit on any of the coupled semiconductor dies, while enabling the D2D interface, and has one or more advantages including, but not limited to, minimal circuit overhead, reduced circuit complexity, reduced latency, power and / or area savings of the FIFO circuit, etc.

[0080] In some embodiments, the described clock arrangement for the IC device 100 advantageously applies to a situation where one of the semiconductor dies does not have its own clock and is configured to operate based on a clock signal provided by another semiconductor die. In an example of this case, the semiconductor die 110 is a logic die, while the semiconductor die 120 is a memory die without a clock. In one or more embodiments, the logic die and the memory die share one clock domain provided by the logic die (e.g., provided by the clock signal Clk_in1), while avoiding the FIFO circuit latency.

[0081] In some embodiments, the provision of the multiplexer MUX2 enhances the clock arrangement flexibility and / or compatibility. The multiplexer MUX2 allows for a controllable switch between a common clock domain mode and a separate clock domain mode according to a controllable value of the selection signal Sel2. The common clock domain mode is when the clock signal Clk_in1 corresponding to the main clock signal is provided from the semiconductor die 110 to the semiconductor die 120 and is sent back from the semiconductor die 120 to the semiconductor die 110 together with data, and has one or more achievable advantages as described herein. The separate clock domain mode is when the semiconductor die 120 communicates with the semiconductor die 110 using a separate (or independent) clock signal Clk_loc2 in a specific application or situation.

[0082] Figure 2 is a schematic circuit diagram of a clock management circuit 200 according to some embodiments. In some embodiments, the clock management circuit 200 is part of an IC device corresponding to the IC device 100. Figure 2 in one or more other Figures 1A to 8B components corresponding to components in Figures 1A to 8B are denoted by the same reference numerals as those in

[0083] The clock management circuit 200 includes the multiplexer MUX1 as described with respect to Figure 1A and the storage circuit 205. In the Figure 2 example configuration, the storage circuit 205 includes registers. Other storage circuit configurations are within the scope of various embodiments. The storage circuit 205 is configured to store at least one value of the selection signal Sel1 therein. The storage circuit 205 is coupled to the selection input of the multiplexer MUX1 to provide the stored value of the selection signal Sel1 to the multiplexer MUX1. Thus, the multiplexer MUX1 is configured by the stored value in the storage circuit 205 to output either the clock signal CLK1 (in response to the stored value being logic "0") or the inverted clock signal CLK1 (in response to the stored value being logic "1") as the clock signal CLK5 to the flip - flop FF5 ( Figure 2 not shown in).

[0084] In some embodiments, the value stored in the storage circuit 205 is determined at the design stage, for example, by using one or more of equations (1)-(4) to determine or estimate the setup time and hold time corresponding to the timings ta and tb. Based on the determined setup time and hold time, the timing ta or tb with better - determined setup time and hold time is selected, and the value of the selection signal Sel1 corresponding to the selected timing ta or tb is stored in the storage circuit 205. Alternatively or additionally, in some embodiments, during the manufacture and / or operation of the IC device including the clock management circuit 200, the value stored in the storage circuit 205 is determined and / or updated periodically and / or on - demand, for example, by a calibration process as described with respect to Figure 3 . According to some embodiments, one or more of the advantages described herein can be achieved by the clock management circuit 200 and / or the IC device including the clock management circuit 200.

[0085] Figure 3 is a schematic circuit diagram of an IC device 300 according to some embodiments. In some embodiments, the IC device 300 corresponds to one or more of the IC devices described with respect to Figures 1A - 1B 、 Figure 2 . Figure 3 Components having one or more other Figures 1A to 8B corresponding components in are denoted by the same reference numerals as in the other Figures 1A to 8B .

[0086] In addition to the components described for the IC device 100, the IC device 300 further includes a control circuit 310 in the semiconductor die 110, and an electrical connection 320 that couples the output of the flip-flop FF2 to the input of the flip-flop FF3 in the semiconductor die 120. In some embodiments, the control circuit 310 is part of the functional circuitry of the semiconductor die 110. The control circuit 310 includes: a first input 311 configured to receive a signal D1 to be sent to the semiconductor die 120; a second input 312 coupled to the output of the flip-flop FF5 to receive a signal D6; and an output 313 coupled to the select input of the multiplexer MUX1. In some embodiments, the control circuit 310 itself sends the signal D1 to the flip-flop FF1 for sending to the semiconductor die 120. In some embodiments, during the described calibration process, electrical connections for providing the signal D1 to the first input 311, providing the signal D6 to the second input 312, and the electrical connection 320 are temporarily established, for example, by closing one or more switches (not shown). After the calibration process is completed, the temporarily established electrical connections are disconnected, for example, by opening one or more switches, for normal operation.

[0087] During a calibration process according to some embodiments, the signal D1 sent from or sent to the control circuit 310 includes a test signal. The test signal is sent from the semiconductor die 110 to the semiconductor die 120 through the channel Ch1, then diverted through the electrical connection 320, and sent back from the semiconductor die 120 to the semiconductor die 110 through the channel Ch3. The clock signal Clk_in1 is sent from the semiconductor die 110 to the semiconductor die 120 through the channel Ch2, and then returned to the semiconductor die 110 through the channel Ch4, as described for the IC device 100.

[0088] In at least one embodiment, the test signal includes a number of test patterns. For example, the test patterns include a predetermined or known sequence of bits. If the round-trip communication between the semiconductor die 110 and the semiconductor die 120 is correctly configured and operated, the returned test pattern expected to be read out from the flip-flop FF5 and provided to the control circuit 310 as the signal D6 will be the same as the original test pattern included in the signal D1 and known to the control circuit 310.

[0089] In some embodiments, by sending a first value of the select signal Sel1 through output 313 to multiplexer MUX1, control circuit 310 sets flip-flop FF5 to read out a first return test mode of signal D5 in response to the falling edge of domain clock signal CLK1. Next, by sending a different second value of the select signal Sel1 through output 313 to multiplexer MUX1, control circuit 310 sets flip-flop FF5 to read out a second return test mode of signal D5 in response to the rising edge of clock signal CLK1. Each of the two return test modes read out corresponding to different clock edges of clock signal CLK1 is compared with the corresponding known or original test mode included in signal D1. The known or original test mode included in signal D1 is an example of first data. The return test mode read out from signal D5 is an example of second data.

[0090] In at least one embodiment, there is a case where one of the two return test modes fails while the other return test mode passes the comparison test. For example, the first return test mode is different from the corresponding original test mode and is determined by control circuit 310 to have failed the test, while the second return test mode is the same as the corresponding original test mode and is determined by control circuit 310 to have passed the test. Control circuit 310 sends, through output 313, the value of the select signal Sel1 (e.g., logic “1”) corresponding to the clock edge (e.g., rising edge) of clock signal CLK1 used to read out the passing return test mode to the select input of multiplexer MUX1 to configure flip-flop FF5 so that subsequently the rising edge of clock signal CLK1 is used to read out additional signals sent from semiconductor die 120 to semiconductor die 110 during communication in normal operation.

[0091] In some embodiments, there is a case where both of the two return test modes pass the comparison test. In this case, control circuit 310 selects the falling edge of clock signal CLK1 for communication during normal operation. As described herein, the reason is that the delay (T / 2) caused by data reading based on the falling edge of clock signal CLK1 is shorter than the delay (T) caused by data reading based on the rising edge of clock signal CLK1. Control circuit 310 sends, through output 313, the value of the select signal Sel1 (e.g., logic “0”) corresponding to the falling edge of clock signal CLK1 to the select input of multiplexer MUX1 to configure flip-flop FF5 so that subsequently the falling edge of clock signal CLK1 is used to read out additional signals sent from semiconductor die 120 to semiconductor die 110 during communication in normal operation.

[0092] In some embodiments, there are cases where both return test modes fail the comparison test. In such cases, the control circuit 310 re - runs the test one or more times, and if the return test mode still fails the comparison test, the control circuit 310 notifies the external device and / or the human operator that the IC device 300 has failed the D2D communication test and should be further inspected, for example, for repair.

[0093] In at least one embodiment, the described calibration process ends with the control circuit 310 determining or setting the selection signal Sel1 to a specific value corresponding to the falling or rising edge of the clock signal CLK1, and subsequently the flip - flop FF5 uses this specific value to read an additional signal sent from the semiconductor die 120 to the semiconductor die 110 during normal operation.

[0094] In some embodiments, the control circuit 310 includes a storage circuit corresponding to the storage circuit 205. After completing the calibration process, the control circuit 310 stores the determined (or set) value of the selection signal Sel1 into the storage circuit to configure the flip - flop FF5, for example, as described with respect to Figure 2 above.

[0095] In at least one embodiment, the control circuit 310 is configured to perform the calibration process periodically or on demand and update the set value of the selection signal Sel1 as needed. The reason is to ensure correct and / or efficient communication between the semiconductor die 110 and the semiconductor die 120 despite PVT variations. According to some embodiments, the IC device 300 may achieve one or more of the advantages described herein.

[0096] Figure 4A is a schematic circuit diagram of an IC device 400A according to some embodiments. In some embodiments, the IC device 400A corresponds to one or more of the IC devices described with respect to Figures 1A - 1B 、 Figures 2 - 3 above. Figure 4A Components having one or more other Figures 1A to 8B corresponding components in Figures 1A to 8B are denoted by the same reference numerals as in the other

[0097] In addition to the components described for the IC device 100, the IC device 400A further includes a PLL 420, a delay circuit 425, and a clock tree 427; however, the IC device 400A omits the multiplexer MUX2 of the IC device 100. The PLL 420 includes a reference input 421, a feedback input 422, and an output 423. The reference input 421 is coupled to the output of the clock input buffer Rx2 to receive the clock signal Clk_out1 received from the semiconductor die 110. A feedback path 424 is coupled between the feedback input 422 and the output 423. The delay circuit 425 is included in the feedback path 424. In Figure 4A the example configuration, the clock tree 427 is coupled between the output 423 and the input of the delay circuit 425, and the output of the delay circuit 425 is coupled to the feedback input 422. In at least one embodiment, the clock tree 427 is omitted. The PLL 420 is configured to provide a clock signal Clk_in2 at the output 423 corresponding to the clock signal Clk_out1 at the reference input 421.

[0098] The delay circuit 425 includes one or more circuit elements 426 configured to affect the time delay t_match of the feedback signal on the feedback path 424 from the output 423 to the feedback input 422. Examples of the circuit element 426 include, but are not limited to, buffers, drivers, inverters, etc. The time delay t_match in the feedback path 424 causes the clock signal Clk_in2 at the output 423 of the PLL 420 to have a corresponding phase lead relative to the clock signal Clk_out1 at the reference input 421 of the PLL 420, as described with respect to Figure 4B that.

[0099] In at least one embodiment, the time delay t_match of the delay circuit 425 corresponds to the sum of the time delay td1 and the time delay td2. In at least one embodiment, t_match = td1 + td2. In some embodiments, it is difficult to make t_match reach the exact value of td1 + td2 due to, for example, various factors and / or variations. In at least one embodiment, t_match can be made as close as possible to td1 + td2. For example, as described herein with respect to equations (1)-(4), the various components in these equations (including td1 and td2) are known or can be determined based on the various physical and / or electrical characteristics of the corresponding circuit elements. For example, the time delay td1 can be determined from the various physical and / or electrical characteristics of the clock driver 115, the clock output buffer Tx2, the D2D interface structure of the configuration channel Ch2, and the clock input buffer Rx2. Similarly, the time delay td2 can be determined from the various physical and / or electrical characteristics of the clock driver 125, the clock output buffer Tx4, the D2D interface structure of the configuration channel Ch4, and the clock input buffer Rx4. In at least one embodiment, the circuit elements contributing to the time delay td1 are similar (if not identical) to the circuit elements contributing to the time delay td2 and the time delay td1 is considered to be the same as the time delay td2. In at least one embodiment, at the design stage, td1 and td2 are calculated, and based on the sum td1 + td2, the delay circuit 425 is configured to include a sufficient number and / or type of circuit elements to provide a t_match that is equal to or substantially equal to td1 + td2.

[0100] Figure 4B is a schematic timing diagram showing the clock signal Clk_out1 and the clock signal Clk_in2 in the operation of the IC device 400A according to some embodiments. As described with respect to Figures 1A - 1B the clock edge 151 of the timing T0 with the clock signal Clk_in1 becomes or corresponds to the clock edge of the timing T1 with the clock signal Clk_out1. The clock edge of the timing T1 with the clock signal Clk_out1 is designated as the clock edge 428 in Figure 4B The clock signal Clk_out1 is used as a reference signal, and the delay circuit 425 in the PLL 420 and its feedback path 424 outputs the clock signal Clk_in2 based on this reference signal. The clock edge 428 of the clock signal Clk_out1 corresponds to the clock edge 429 of the clock signal Clk_in2. From Figure 4BAs can be seen, clock edge 429 is one time period earlier or has a phase lead 430 with respect to the corresponding clock edge 428. In other words, the clock signal Clk_in2 at the output 423 of the PLL 420 has a phase lead 430 with respect to the clock signal Clk_out1 at the reference input 421 of the PLL 420. In at least one embodiment, the phase lead 430 is equal to the time delay t_match of the delay circuit 425. In some embodiments, due to various factors and / or variations, the phase lead 430 is slightly different from the time delay t_match but is still quite close.

[0101] Return Figure 4A , in one or more embodiments, the phase lead 430 of the clock signal Clk_in2 with respect to the clock signal Clk_out1 provides the effect of "shifting" the timing and signals after the clock signal Clk_in2 "backward" in time by an amount corresponding to the phase lead 430. For example, in at least one embodiment, Figure 1B The timing diagram in Figure 4A is applicable to describe the timing and signals in Figure 1B , except that the clock signal CLK4 and the signal D5 are "shifted backward" in time or shifted to the left in Figure 1B by an amount corresponding to the phase lead 430. In some embodiments, the amount of time by which the clock signal CLK4 and the signal D5 are shifted is the phase lead 430 minus the jitter exhibited by the PLL 420 at the signal D5, including Rj and / or Dj. In one or more embodiments, the described "backward" shift improves the timing margin at the flip-flop FF5.

[0102] In at least one embodiment, as described herein, the delay circuit 425 is configured to provide a time delay t_match based on the sum of td1 + td2. For example, t_match is equal to or substantially equal to td1 + td2. Thus, the PLL 420 provides a phase lead 430 equal to or substantially equal to td1 + td2, and the clock signal CLK4 and the signal D5 are "shifted backward" in time by an amount approximately matching the sum of td1 + td2. As described herein, due to various factors and / or variations, including but not limited to the jitter caused by the PLL 420 described herein, an exact match of td1 + td2 is difficult. In one or more embodiments, the process of configuring the delay circuit 425 to have a t_match based on td1 + td2 is a method of "shifting" the clock signal CLK4 and the signal D5 "backward" in time by an amount approximately matching td1 + td2. In one or more embodiments, this arrangement improves the timing margin at the flip-flop FF5.

[0103] In some embodiments, the configuration of the PLL 420 on the described semiconductor die 120 can be used for Si test purposes, especially when the total jitter (Rj+Dj) exhibited by the PLL 420 at signal D5 is much less than td1+td2. In some embodiments, the Si test includes testing the functional correctness of the fabricated IC device in a setup corresponding to the actual operating environment.

[0104] The arrangement having the PLL 420 and the delay circuit 425 in the described feedback path 424 is an example of a second circuit that is configured to receive a clock signal (e.g., the clock signal Clk_out1) and output another clock signal (e.g., the clock signal Clk_in2) corresponding to the received clock signal and having a phase lead with respect to the received clock signal. Other configurations of such a second circuit are within the scope of various embodiments. In some embodiments, the second circuit is an example of, or at least part of, a clock management circuit. According to some embodiments, the IC device 400A can achieve one or more of the advantages described herein.

[0105] Figure 4C 、 Figure 4D is a schematic circuit diagram of corresponding IC devices 400C, 400D according to some embodiments. In some embodiments, the IC devices 400C, 400D correspond to one or more of the IC devices described with respect to Figures 1A - 1B 、 Figures 2 - 3 、 Figures 4A - 4B One or more of the described IC devices. Figures 4C - 4D One or more of which have one or more other Figures 1A to 8B Components corresponding components in are denoted by the same reference numerals as the other Figures 1A to 8B In.

[0106] In Figure 4C the IC device 400C is similar to the IC device 400A, except that the IC device 400C omits the multiplexer MUX1 and the flip-flop FF5 of the IC device 400A. As described herein, the first circuit including the multiplexer MUX1 and the flip-flop FF5 on the semiconductor die 110 and the second circuit including the PLL 420 and the delay circuit 425 on the semiconductor die 120 are both configured to improve the timing margin for reading the data received at the transmit circuit 122 of the semiconductor die 120. In some embodiments, both the first circuit and the second circuit are included to improve the timing margin, e.g., as described in the example configuration with respect to Figure 4A In at least one embodiment, one of the first circuit and the second circuit is sufficient to improve the timing margin, and the other of the first circuit and the second circuit is omitted. For example, in Figure 1A the example configuration of, the second circuit on the semiconductor die 120 is omitted. For another example, in Figure 4CThe first circuit on the semiconductor die 110 is omitted in the example configuration.

[0107] In Figure 4D IC device 400D is similar to IC device 400A but further includes multiplexer MUX2. As described with respect to Figure 1A The multiplexer MUX2 includes: a first input (labeled "0"), coupled to the output of the clock input buffer Rx2 to receive the clock signal Clk_out1; a select input, configured to receive the select signal Sel2; an output, coupled to the flip-flop FF3 and the clock output buffer Tx4 through the clock tree CT3 and the clock driver 125, respectively. The multiplexer MUX2 further includes: a second input (labeled "1"), coupled to the input of the clock tree 427 and the delay circuit 425 to receive the clock signal Clk_sla2. The clock signal Clk_sla2 in the IC device 400D corresponds to the clock signal Clk_in2 in the IC device 400C.

[0108] In a manner similar to that described with respect to Figure 1A The multiplexer MUX2 is configured to output a clock signal Clk_in2 corresponding to either the clock signal Clk_out1 or the clock signal Clk_sla2 according to the value of the select signal Sel2. For example, in response to a select signal Sel2 having a value of logic "0", the multiplexer MUX2 is configured to output a clock signal Clk_in2 corresponding to the clock signal Clk_out1. In this configuration, the IC device 400D is configured and operates in a manner similar to the IC device 100 having a select signal Sel2 of logic "0" described herein. As another example, in response to a select signal Sel2 having a value of logic "1", the multiplexer MUX2 is configured to output a clock signal Clk_in2 corresponding to the clock signal Clk_sla2. In this configuration, the IC device 400D is configured and operates in a manner similar to the IC device 400A described herein. In at least one embodiment, the multiplexer MUX2 provides an additional option for controllable clock management to achieve an appropriate and / or optimal timing margin for reading the data output by the receive circuit 112. According to some embodiments, one or more of the advantages described herein can be achieved by one or more of the IC devices 400C, 400D.

[0109] Figure 5A and Figure 5B are schematic circuit diagrams of corresponding IC devices 500A, 500B according to some embodiments. In some embodiments, the IC devices 500A, 500B correspond to one or more of the IC devices described for Figures 1A - 1B and Figures 2 - 3 and Figures 4A - 4D described. Figures 5A - 5Bhas one or more others among one or more of Figures 1A to 8B The components of the corresponding components in are the same as those of the others Figures 1A to 8B are denoted by the same reference numerals.

[0110] In Figure 5A In, the IC device 500A includes a first semiconductor die 510 (labeled "die") and a second semiconductor die 520 (labeled "die 2"), which are electrically and physically coupled through a plurality of die-to-die (D2D) interface structures 530. In some embodiments, the semiconductor die 510, the semiconductor die 520, and the interface structure 530 correspond to the semiconductor die 110, the semiconductor die 120, and the interface structure 130. For simplicity, Figure 5A in, various components of the semiconductor die 510 and the semiconductor die 520 are omitted, such as one or more functional circuits, one or more data I / O circuits, etc.

[0111] The semiconductor die 510 includes a clock generator (or clock source) 502, a clock tree 504, and a plurality of clock I / O circuits 513A - 513C. The number of clock I / O circuits of the semiconductor die 510 (three) is an example. Other numbers of clock I / O circuits are within the scope of various embodiments. Examples of the clock source 502 and the clock tree 504 are referenced Figure 7 for description. Examples of the clock I / O circuits 513A - 513C are referenced Figure 1A for description. For example, in at least one embodiment, each of the clock I / O circuits 513A - 513C includes a clock output buffer corresponding to the clock output buffer Tx2, and a clock input buffer corresponding to the clock input buffer Rx4.

[0112] The semiconductor die 520 includes a plurality of clock I / O circuits 523A - 523C. Examples of the clock I / O circuits 523A - 523C are referenced Figure 1A for description. For example, in at least one embodiment, each of the clock I / O circuits 523A - 523C includes a clock output buffer corresponding to the clock output buffer Tx4, and a clock input buffer corresponding to the clock input buffer Rx2.

[0113] Each of the clock I / O circuits 523A - 523C of semiconductor die 520 is coupled to a corresponding one of the clock I / O circuits 513A - 513C of semiconductor die 510 through a corresponding pair of interface structures 530. For example, the clock input buffer of clock I / O circuit 523C is coupled to the clock output buffer of clock I / O circuit 513C through an interface structure (or channel) Ch2, and the clock output buffer of clock I / O circuit 523C is coupled to the clock input buffer of clock I / O circuit 513C through another interface structure (or channel) Ch4.

[0114] For each clock I / O circuit 523A - 523C of semiconductor die 520, the output of the clock input buffer (e.g., 526) is coupled to the input of the clock output buffer (e.g., 527) through an electrical connection 528. In some embodiments, this configuration corresponds to one or more of the configurations described with respect to Figure 1A , Figure 4D where the select signal Sel2 of multiplexer MUX2 is logic "0". In at least one embodiment, IC device 500A is configured to operate in one or more of the manners described with respect to Figures 1A - 4D . According to some embodiments, IC device 500A may achieve one or more of the advantages described herein.

[0115] In Figure 5B , IC device 500B includes a first semiconductor die 510 and a second semiconductor die 521, which are electrically and physically coupled through a plurality of D2D interface structures 530. The semiconductor die 510 and the interface structures 530 are as described with respect to Figure 5A .

[0116] Semiconductor die 521 includes a plurality of clock I / O circuits 523A - 523C, as described with respect to Figure 5A . Semiconductor die 521 also includes a clock tree 540, a PLL 550, and a delay circuit 555. In some embodiments, the clock tree 540, the PLL 550, and the delay circuit 555 correspond to the clock tree 427, the PLL 420, and the delay circuit 425 described with respect to one or more of Figures 4A - 4D .

[0117] Refer to Figure 7An example of a clock tree 540 is described. For example, the clock tree 540 includes a top or upper layer 542, one or more lower layers (not shown), and a clock grid structure 544. In at least one embodiment, the clock tree 540 also includes a post-grid clock tree coupled to the clock grid structure 544. For simplicity, this post-grid clock tree is considered part of the clock grid structure 544. The clock signal received at the upper layer 542 propagates through one or more lower layers to the clock grid structure 544, where the propagated clock signal is transmitted to various components including clock I / O circuits 523A - 523C. In some embodiments, the clock tree 504 on the semiconductor die 510 is configured and / or operates in a similar manner.

[0118] At least one of the clock I / O circuits 523A - 523C, such as clock I / O circuit 523A, has an output 536 of a corresponding clock input buffer coupled to a reference input of the PLL 550. The output of the PLL 550 is coupled to the upper layer 542 of the clock tree 540. The input of the delay circuit 555 is coupled to a point on the clock grid structure 544. The output of the delay circuit 555 is coupled to the feedback input of the PLL550. In some embodiments, this configuration corresponds to one or more of the configurations described with respect to Figure 4A , Figure 4C and Figure 4D where the select signal Sel2 of the multiplexer MUX2 is logic "1". In some embodiments, the semiconductor die 520 and the semiconductor die 521 are implemented by a single semiconductor die that can be controllably switched between the configuration of the semiconductor die 520 and the configuration of the semiconductor die 521. In at least one embodiment, the IC device 500B is configured to operate in one or more of the manners described with respect to Figures 1A - 4D . According to some embodiments, the IC device 500B can achieve one or more of the advantages described herein.

[0119] Figure 6A is a flowchart of a method 600A according to some embodiments. In some embodiments, the method 600A includes a calibration process as described with respect to Figure 3 . In at least one embodiment, the method 600A is executed at an IC device corresponding to one or more of the IC devices described with respect to Figure 1A , Figure 4A , Figure 4D , Figure 5A , Figure 5B . The method 600A includes operations 612, 614, 616, 618.

[0120] At operation 612, an output signal and an output clock signal associated with the output signal are sent to the semiconductor die. For example, as described with respect to Figure 3As described, in at least one embodiment, the output signal includes signal D1, which is a test signal and is sent from semiconductor die 110 to semiconductor die 120 through channel Ch1. The output clock signal includes clock signal Clk_in1, which is sent from semiconductor die 110 to semiconductor die 120 through channel Ch2 together with signal D1.

[0121] At operation 614, an input signal and an input clock signal associated with the input signal are received from a semiconductor die, where the input signal corresponds to the output signal and the input clock signal corresponds to the output clock signal. For example, as described regarding Figure 3 the input signal includes signal D1 received by semiconductor die 120, is redirected through electrical connection 320, and is sent back to semiconductor die 110 through channel Ch3 and received as signal D5. The input clock signal includes clock signal Clk_out1 received by semiconductor die 120, and then returns to semiconductor die 110 through channel Ch4 via multiplexer MUX2 with selection signal Sel2 being logic "0".

[0122] At operation 616, a clock signal is selected based on a comparison of the data in the output signal with the data obtained from the input signal. For example, as described regarding Figure 3 the data in the output signal (i.e., signal D1) includes one or more predetermined or known original test patterns. The data in the output signal includes returned test patterns, which are the original test patterns in signal D1 and are obtained through the back-and-forth communication between semiconductor die 110 and semiconductor die 120 as described in operations 612 and 614. If the returned test pattern matches (e.g., is the same as) the original test pattern, then the clock signal (e.g., clock signal CLK5) configured for reading the returned test pattern is correctly selected and chosen for further communication. Otherwise, an alternative configuration of clock signal CLK5 is selected. In Figure 3 an example configuration, the alternative configuration of clock signal CLK5 includes clock signal CLK1 corresponding to selection signal Sel1 being logic "1", and an inverted clock signal CLK1 corresponding to selection signal Sel1 being logic "0". In at least one embodiment, the selection of the clock signal for reading the returned test pattern includes selecting the corresponding value of selection signal Sel1, such as logic "0" or logic "1".

[0123] At operation 618, additional data is obtained from an additional input signal received from the semiconductor die based on the selected clock signal. For example, as described regarding Figure 1A 、 Figure 1B and Figure 3As described, in operation 616, a particular value of selection signal Sel1 is selected, and at flip-flop FF5, a corresponding configuration of clock signal CLK5 is also selected, and additional data in additional input signals (other than test signals or returned test signals) is read out, for example, during normal operation (other than calibration procedures) between semiconductor die 110 and semiconductor die 120.

[0124] In at least one embodiment, the selected value of signal Sel1 at operation 616 is stored in a storage circuit. In some embodiments, the described calibration process includes operations 612, 614, 616, as schematically indicated by arrow 620, and is repeated as needed and / or periodically. According to some embodiments, one or more of the advantages described herein can be achieved by method 600A.

[0125] Figure 6B is a flowchart of method 600B according to some embodiments. In some embodiments, method 600B is performed at an IC device corresponding to one or more of the IC devices described with respect to Figures 4A - 4D 、 Figure 5B The method 600B includes operations 632, 634, 636.

[0126] At operation 632, an input signal and an input clock signal associated with the input signal are received from a semiconductor die. For example, in Figure 4A Looking from semiconductor die 120, the input signal received from semiconductor die 110 includes signal D2, and the input clock signal associated with signal D2 and received from semiconductor die 110 includes clock signal Clk_out1.

[0127] At operation 634, an output clock signal having a phase lead relative to the input clock signal is generated based on the input clock signal. For example, in Figure 4A Looking from semiconductor die 120, the output clock signal includes clock signal Clk_in2. As described with respect to Figure 4A 、 Figure 4B The clock signal Clk_in2 is generated based on the clock signal Clk_out1 and has a phase lead of 430 relative to the clock signal Clk_out1.

[0128] At operation 636, (i) an output signal based on the output clock signal and (ii) the output clock signal are sent to the semiconductor die. For example, as described with respect to Figure 4AAs described above, the output signal includes a signal D3 that is sent to the semiconductor die 110 through channel Ch3 based on the clock signal Clk_in2, which is provided as the clock signal CLK3 to the flip-flop FF3. The clock signal Clk_in2 is also sent to the semiconductor die 110 through channel Ch4. According to some embodiments, one or more of the advantages described herein may be achieved by method 600B.

[0129] Figure 6C is a flowchart of method 600C according to some embodiments. In some embodiments, method 600C is performed during a design phase for designing an IC device corresponding to one or more IC devices described with respect to Figures 4A - 4D , Figure 5A described. In some embodiments, method 600C is performed in whole or in part by a processor and / or at least one EDA system, as described herein with respect to Figure 9 described. In some embodiments, the EDA system can be used as part of a design house of an IC manufacturing system, as described with respect to Figure 10 described. Method 600C includes operations 652, 654, 656, 658.

[0130] At operation 652, a first time delay is determined between (i) the master clock signal of a first semiconductor die and (ii) an output clock signal corresponding to the master clock signal received by a clock input buffer of a second semiconductor die. For example, as described with respect to Figure 4A described, a first time delay td1 is determined between the master clock signal (e.g., clock signal Clk_in1) of the first semiconductor die 110 and the output clock signal (e.g., clock signal Clk_out1). The clock signal Clk_out1 corresponds to the master clock signal received by the clock input buffer Rx2 of the second semiconductor die 120. The time delay td1 occurs on a first path that includes various circuit elements, such as clock driver 115, clock output buffer Tx2, a D2D interface structure configuring channel Ch2, and clock input buffer Rx2.

[0131] At operation 654, a second time delay is determined between (a) a return clock signal that corresponds to the output clock signal and is sent by a clock output buffer of the second semiconductor die to the first semiconductor die and (b) an input clock signal corresponding to the return clock signal received at the first semiconductor die. For example, as described with respect to Figure 4AAs described above, a second time delay td2 is determined between a returned clock signal (e.g., clock signal Clk_in2) and an input clock signal (e.g., clock signal Clk_out2). The clock signal Clk_in2 corresponds to the clock signal Clk_out1 and is sent by the clock output buffer Tx4 of the semiconductor die 120 to the semiconductor die 110. The clock signal Clk_out2 corresponds to the clock signal Clk_in2 received at the semiconductor die 110. The time delay td2 occurs on a second path that includes various circuit elements such as a clock driver 125, a clock output buffer Tx4, a D2D interface structure of the configuration channel Ch4, and a clock input buffer Rx4.

[0132] In at least one embodiment, based on various physical and / or electrical characteristics of the circuit elements in the first path and the second path, the time delay tdl and the time delay td2 can be determined. In some embodiments, the physical and / or electrical characteristics of the circuit elements are obtained from one or more of the standard cells that make up the circuit elements, the configuration of the conductors for wiring to couple the standard cells, the configuration of the D2D interface structure to be formed for coupling the semiconductor die 110 and the semiconductor die 120, one or more simulations of the operation of the IC device 100, etc. In some embodiments, operation 654 is performed before operation 652, or at least partially concurrently with operation 652. In at least one embodiment, when the configurations of the first path and the second path are the same or substantially the same, i.e., tdl is the same or substantially the same as td2, then one of operations 652 and 654 is omitted.

[0133] At operation 656, based on the first time delay and the second time delay, the time delay of a delay circuit is configured, where the delay circuit is located in the feedback path of a phase-locked loop (PLL) coupled between the clock input buffer and the clock output buffer of the second semiconductor die. For example, as regarding Figure 4AAs described above, based on the sum of td1 + td2, the time delay t_match of the delay circuit 425 in the feedback path 424 of the PLL 420 is configured. The PLL 420 is coupled between the clock input buffer Rx2 and the clock output buffer Tx4 of the semiconductor die 120. In at least one embodiment, the time delay t_match is configured to be equal to or as close as possible to td1 + td2. The delay circuit 425 includes circuit elements 426, and each circuit element 426 is in turn constructed from one or more standard cells, such as delay cells, buffer cells, inverter cells, etc. In at least one embodiment, based on the predetermined or known time delays of the standard cells that make up the circuit elements 426, a combination of standard cells forming the delay circuit 425 is generated such that the time delay t_match is equal to or as close as possible to td1 + td2. In some embodiments, one or more simulations are performed to generate or adjust the combination of standard cells forming the delay circuit 425. In some embodiments, the final design of the IC device 100 obtained at operation 656 is in the form of a layout stored in a non-transitory computer-readable recording medium.

[0134] At operation 658, an IC device is fabricated to include a first semiconductor die and a second semiconductor die that are bonded and electrically coupled to each other. For example, the stored layout is used for Figure 10 the IC fabrication system described in, to fabricate the semiconductor die 110 and the semiconductor die 120. In some embodiments, the semiconductor die 110 and the semiconductor die 120 are bonded and electrically coupled together in one or more configurations described herein, such as with respect to Figures 8A - 8B described. In some embodiments, operation 656 is omitted. According to some embodiments, one or more of the advantages described herein can be achieved by an IC device designed and / or fabricated by the method 600C.

[0135] The method includes exemplary operations, but they need not be implemented in the order shown. Operations can be added, replaced, rearranged, and / or eliminated as appropriate, in accordance with the spirit and scope of embodiments of the present invention. Embodiments that combine different features and / or different embodiments are within the scope of the present invention and will be apparent to those of ordinary skill in the art after viewing the present invention.

[0136] Figure 7 is a schematic diagram of a clock distribution system 700 for an IC device according to some embodiments. In at least one embodiment, the clock distribution system 700 is disposed on a semiconductor die of the IC device.

[0137] The clock distribution system 700 is configured to receive a clock signal 704 from a clock source 702 and distribute the clock signal 704 to various circuits in the IC device. The clock distribution system 700 includes a plurality of clock drivers 710 - 719 arranged at various positions in the clock distribution system 700, a pre-grid clock tree 720, a clock grid structure 730, and a plurality of post-grid clock trees 741 - 744. A plurality of clock loads or clock receivers 751 - 755 are electrically coupled to the clock distribution system 700 to receive the clock signal distributed therefrom.

[0138] In some embodiments, the clock source 702 includes one or more of an oscillator circuit, a phase-locked loop (PLL), a clock divider circuit, etc. Other clock source configurations are within the scope of various embodiments. In at least one embodiment, the clock source 702 is an internal clock source included in the IC device including the clock distribution system 700. In at least one embodiment, the clock source 702 is an external clock source arranged outside the IC device and electrically coupled to the IC device, e.g., via one or more input / output (IO) pins of the IC device. Other configurations of the clock source 702 are within the scope of various embodiments.

[0139] In some embodiments, each of the clock drivers 710 - 719 includes one or more of a buffer, an inverter, an amplifier, a logic gate, etc. Other clock driver configurations are within the scope of various embodiments. As Figure 7 The arrangement of the clock drivers 710 - 719 in the clock distribution system 700 shown is an example. Other configurations are within the scope of various embodiments. For example, according to some embodiments, one or more of the clock drivers 710 - 719 are omitted and / or one or more additional clock drivers are added.

[0140] In Figure 7 the example configuration, the pre-grid clock tree 720 includes an upper layer 721 and a lower layer 722. The upper layer 721 includes a metal pattern, sometimes referred to as the backbone of the pre-grid clock tree 720, and is electrically coupled to the output of the clock driver 710. The clock driver 710 also has an input electrically coupled to the clock source 702 to receive the clock signal 704 and is configured to transmit the clock signal 704 to the pre-grid clock tree 720. Opposite ends of the metal pattern of the upper layer 721 are electrically coupled to the inputs of the clock drivers 711 - 712. The lower layer 722 includes metal patterns 723, 724, sometimes referred to as the branches of the pre-grid clock tree 720, and are correspondingly electrically coupled to the outputs of the clock drivers 711 - 712. Opposite ends of the metal pattern 723 are electrically coupled to the inputs of the clock drivers 713 - 714. Opposite ends of the metal pattern 724 are electrically coupled to the inputs of the clock drivers 715 - 716. Figure 7An example configuration of the pre-gridded clock tree 720 in [the context] is an H-tree. Other clock tree configurations are within the scope of the various embodiments described herein. For example, in one or more embodiments, the clock grid structure 730 includes one or more than two layers. In at least one embodiment, the pre-gridded clock tree 720 is omitted.

[0141] The clock grid structure 730 is electrically coupled to the outputs of the clock drivers 713 - 716. The clock grid structure 730 includes a plurality of metal patterns arranged in one or more metal layers, and all the metal patterns are electrically coupled to each other to short-circuit the outputs of the clock drivers 713 - 716. Thus, the same clock signal or substantially the same clock signal can be retrieved at any point on the clock grid structure 730. The clock grid structure 730 includes a plurality of tap points from which clock signals are obtained to be delivered to clock loads in the IC device circuit. In Figure 7 the example configuration, for illustrative purposes, five tap points 731 - 735 are indicated. The actual number and / or location of tap points on the clock grid structure 730 depends on how the clock loads are distributed in the IC device circuit. Figure 7 The configuration of the clock grid structure 730 with two sets of parallel wiring in [the context] is an example, sometimes referred to as a "Manhattan" configuration. Other clock grid structure configurations are within the scope of the various embodiments. In at least one embodiment, the clock grid structure 730 is omitted.

[0142] The post-gridded clock trees 741 - 744 are electrically coupled to the clock grid structure 730 at the corresponding tap points 731 - 734. The post-gridded clock trees 741 - 743 are electrically coupled to the corresponding tap points 731 - 733 through the corresponding clock drivers 717 - 719, and are configured to deliver clock signals to the corresponding clock loads 751 - 753. The post-gridded clock tree 744 is directly electrically coupled to the corresponding tap point 744 without an intermediate clock driver, and is configured to deliver clock signals to the corresponding clock load 754. The clock load 755 is directly electrically coupled to the tap point 735 without an intermediate clock driver or post-gridded clock tree. In some embodiments, each of the clock loads 751 - 755 includes a flip-flop or the like. Other clock load configurations are within the scope of the various embodiments. In at least one embodiment, one or more or all of the post-gridded clock trees 741 - 743 are omitted.

[0143] Figure 7The configuration of the clock distribution system 700 in [the figure] is an example. Other clock distribution system configurations are within the scope of various embodiments. For example, in one or more embodiments, the pre-grid clock tree 720 is omitted, and the output of the clock driver 710 is electrically coupled to the central point 737 of the clock grid structure 730. In at least one embodiment, the clock grid structure 730 is omitted, and at least one metal pattern of the pre-grid clock tree 720 is configured as a clock backbone to which clock loads are electrically coupled. In one or more embodiments, the clock distribution system 700 includes one or more clock trees 720, 741 - 744 and no clock grid structure.

[0144] Figure 8A is a schematic diagram of an IC device 800A according to some embodiments.

[0145] The IC device 800A is a 3D IC, including semiconductor dies 810, 820 stacked and coupled to a middleware 830 along the Z-axis. The semiconductor die 810 includes a plurality of I / O circuits 814, which are coupled and bonded to corresponding interconnections 836 in the middleware 830 through bumps 816. The semiconductor die 820 includes a plurality of I / O circuits 824, which are coupled and bonded to corresponding interconnections 836 in the middleware 830 through bumps 826, thereby coupling to the corresponding I / O circuits 814 of the semiconductor die 810. Thus, the semiconductor die 810 is coupled to the semiconductor die 820 through bumps 816, 826 and the middleware 830. In some embodiments, each I / O circuit 814, 816 includes a data I / O circuit or a clock I / O circuit.

[0146] In some embodiments, the IC device 800A corresponds to one or more IC devices described with respect to Figures 1A - 5B and / or the semiconductor die 810 corresponds to one or more semiconductor dies 110, 510, and / or the semiconductor die 820 corresponds to one or more semiconductor dies 120, 520, 521. In at least one embodiment, the combination of each bump 816, the corresponding interconnection 836, and the corresponding bump 826 corresponds to an interface structure 130 or an interface structure 530.

[0147] Figure 8B is a schematic diagram of an IC device 800B according to some embodiments. Having Figure 8A the corresponding components in Figure 8B the components in Figure 8A are denoted by the same reference numerals as

[0148] In IC device 800B, the middleware 830 of IC device 800A is omitted. The semiconductor die 810 and the semiconductor die 820 are joined and electrically coupled in a face-to-face configuration. For example, each bump 816 of the semiconductor die 810 is located above and joined to a corresponding bump 826 of the semiconductor die 820. The combination of each bump 816 and the corresponding bump 826 corresponds to an interface structure 130 or an interface structure 530. According to some embodiments, one or more of the advantages described herein may be achieved by one or more of IC devices 800A, 800B. Figure 8A , Figure 8B The 3D IC configurations described in

[0149] Figure 9 is a block diagram of an electronic design automation (EDA) system 900 according to some embodiments.

[0150] In some embodiments, the EDA system 900 includes an APR system. According to some embodiments, the method of representing a design layout described herein represents a wire routing arrangement according to one or more embodiments and, for example, may be implemented using the EDA system 900.

[0151] In some embodiments, the EDA system 900 is a general-purpose computing device that includes a hardware processor 902 and a non-transitory computer-readable recording medium 904. Among other things, the recording medium 904 is encoded, i.e., stores, computer program code 906, i.e., a set of executable instructions. The instructions 906 executed by the hardware processor 902 represent (at least in part) an EDA tool that implements part or all of the processes and / or methods described herein according to one or more embodiments (hereinafter, the processes and / or methods).

[0152] The processor 902 is electrically coupled to the computer-readable recording medium 904 via a bus 908. The processor 902 is also electrically coupled to an I / O interface 910 via the bus 908. A network interface 912 is also electrically coupled to the processor 902 via the bus 908. The network interface 912 is connected to a network 914 such that the processor 902 and the computer-readable recording medium 904 can be connected to external components via the network 914. The processor 902 is configured to execute the computer program code 906 encoded in the computer-readable recording medium 904 such that the system 900 can be used to execute part or all of the processes and / or methods. In one or more embodiments, the processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0153] In one or more embodiments, the computer-readable recording medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable recording medium 904 includes semiconductor or solid-state memories, magnetic tapes, mobile computer floppy disks, random access memory (RAM), read-only memory (ROM), hard disks, and / or optical disks. In one or more embodiments using optical disks, the computer-readable recording medium 904 includes compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disk (DVD).

[0154] In one or more embodiments, the recording medium 904 stores computer program code 906 that is configured to make the system 900 (where such execution (at least in part) represents an EDA tool) available to perform part or all of the process and / or method. In one or more embodiments, the recording medium 904 also stores information that facilitates the performance of part or all of the process and / or method. In one or more embodiments, the recording medium 904 stores a standard cell library 907 including such standard cells as disclosed herein.

[0155] The EDA system 900 includes an I / O interface 910. The I / O interface 910 is coupled to an external circuit. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor direction keys that convey information and commands to the processor 902.

[0156] The EDA system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 allows the system 900 to communicate with a network 914 to which one or more other computer systems are connected. The network interface 912 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 900.

[0157] The system 900 is configured to receive information through the I / O interface 910. The information received through the I / O interface 910 includes one or more of instructions, data, design rules, standard cell library, and / or other parameters for processing by the processor 902. The information is transmitted to the processor 902 through the bus 908. The EDA system 900 is configured to receive UI-related information through the I / O interface 910. This information is stored as a user interface (UI) 942 in the computer-readable recording medium 904.

[0158] In some embodiments, part or all of the process and / or method is implemented as a stand-alone software application for execution by a processor. In some embodiments, part or all of the recited process and / or method is implemented as a software application that is part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in of a software application. In some embodiments, at least one of the process and / or method is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 900. In some embodiments, tools such as or other suitable layout generation tools are used to generate a layout diagram including standard cells.

[0159] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / on-board storage or memory units, such as optical discs (such as DVDs), magnetic disks (such as hard disks), and semiconductor memories (such as ROM, RAM, memory cards, etc.).

[0160] Figure 10 is a block diagram of an integrated circuit (IC) manufacturing system 1000 and an IC manufacturing process associated therewith. In some embodiments, based on the layout diagram, for example, the manufacturing system 1000 is used to manufacture (A) one or more semiconductor masks or (B) at least one component in at least one layer of a semiconductor integrated circuit.

[0161] In Figure 10 , the IC manufacturing system 1000 includes entities that interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing the IC device 1060, such as a design house 1020, a mask house 1030, and an IC manufacturer / fabrication facility ("Fab") 1050. The entities in the system 1000 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 1020, the mask house 1030, and the IC Fab 1050 are owned by a single larger company. In some embodiments, two or more of the design house 1020, the mask house 1030, and the IC Fab 1050 coexist in a common facility and use common resources.

[0162] Design studio (or design team) 1020 generates an IC design layout 1022. The IC design layout 1022 includes various geometric patterns designed for the IC device 1060. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers and constitute various components of the IC device 1060 to be fabricated. The individual layers are combined to form various IC functions. For example, a part of the IC design layout 1022 includes various IC components, such as active regions, gate electrodes, source and drain electrodes, metal wires or vias for interlayer interconnects, and openings for pads formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design studio 1020 implements an appropriate design process to form the IC design layout 1022. The design process includes one or more of logic design, physical design, or placement and routing operations. The IC design layout 1022 is presented in one or more data files having geometric pattern information. For example, the IC design layout 1022 can be expressed in the GDSII file format or the DFII file format.

[0163] The mask room 1030 includes data preparation 1032 and mask fabrication 1044. The mask room 1030 uses the IC design layout 1022 to fabricate one or more masks 1045 for fabricating the individual layers of the IC device 1060 according to the IC design layout 1022. The mask room 1030 performs mask data preparation 1032, in which the IC design layout 1022 is translated into a representative data file ("RDF"). The mask data preparation 1032 provides the RDF to the mask fabrication 1044. The mask fabrication 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1045 or a semiconductor wafer 1053. The mask layout data preparation 1032 processes the design layout 1022 to conform to the specific characteristics of the mask writer and / or the requirements of the IC Fab 1050. In Figure 10 this, the mask data preparation 1032 and the mask fabrication 1044 are shown as separate elements. In some embodiments, the mask data preparation 1032 and the mask fabrication 1044 can be collectively referred to as mask data preparation.

[0164] In some embodiments, the mask data preparation 1032 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other processing effects, etc. The OPC adjusts the IC design layout 1022. In some embodiments, the mask data preparation 1032 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0165] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that uses a set of mask creation rules to inspect the IC design layout 1022 that has already been processed in OPC. The set of mask creation rules includes certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in the semiconductor manufacturing process and the like. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for the restrictions during mask fabrication 1044, which may undo a portion of the modifications performed by OPC to satisfy the mask creation rules.

[0166] In some embodiments, mask data preparation 1032 includes lithography process checking (LPC) that simulates the process to be implemented by the IC Fab 1050 to fabricate the IC device 1060. The LPC simulates the process based on the IC design layout 1022 to create a simulated fabricated device, such as the IC device 1060. The process parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to the tools used to fabricate the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after a simulated fabricated device is created by the LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 1022.

[0167] It should be understood that the above description of mask data preparation 1032 has been simplified for clarity. In some embodiments, data preparation 1032 includes additional features, such as logic operations (LOP), to modify the IC design layout 1022 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1022 during data preparation 1032 may be performed in various different orders.

[0168] After mask data preparation 1032 and during mask manufacturing 1044, a mask 1045 or a set of masks 1045 is manufactured based on the modified IC design layout 1022. In some embodiments, mask manufacturing 1044 includes performing one or more lithographic exposures based on the IC design layout 1022. In some embodiments, an electron beam (e-beam) or a multi-electron beam mechanism is used to form a pattern on the mask (photomask or reticle) 1045 based on the modified IC design layout 1022. The mask 1045 can be formed using various techniques. In some embodiments, the mask 1045 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, for exposing an image-sensitive material layer (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and passes through the transparent regions. In one example, the binary mask version of the mask 1045 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a photomask 1045 is formed using a phase shift technique. In the phase shift mask (PSM) version of the mask 1045, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by mask manufacturing 1044 is used in a variety of processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 1053, in an etching process to form various etched regions in the semiconductor wafer 1053, and / or in other suitable processes.

[0169] IC Fab 1050 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC Fab 1050 is a semiconductor manufacturing plant. For example, there can be a manufacturing plant for the front-end manufacturing (front-end (FEOL) manufacturing) of multiple IC products, while a second manufacturing plant can provide back-end manufacturing (back-end (BEOL) manufacturing) for the interconnect and packaging of IC products, and a third manufacturing plant can provide other services for the manufacturing operations.

[0170] IC Fab 1050 includes manufacturing tools 1052 that are configured to perform various manufacturing operations on the semiconductor wafer 1053 to manufacture IC devices 1060 according to a mask (e.g., mask 1045). In various embodiments, the manufacturing tools 1052 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0171] IC Fab 1050 manufactures IC device 1060 using mask 1045 fabricated by mask chamber 1030. Thus, ICFab 1050 uses IC design layout 1022 at least indirectly to manufacture IC device 1060. In some embodiments, semiconductor wafer 1053 is made into IC device 1060 by ICFab 1050 using mask 1045. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 1053 also includes one or more of various doped regions, dielectric components, multi-level interconnections, etc. (formed in subsequent manufacturing steps).

[0172] In some embodiments, an integrated circuit (IC) device includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first transmission circuit, a first reception circuit, and a first circuit. The first transmission circuit is configured to transmit an output clock signal corresponding to a first clock signal. The first reception circuit is configured to receive an input clock signal and an input signal and output a first signal corresponding to the input signal based on the input clock signal. The first circuit is configured to output a second signal corresponding to the first signal based on the first clock signal. The second semiconductor die includes a second transmission circuit and a second reception circuit. The second reception circuit is coupled to the first transmission circuit to receive the output clock signal. The second transmission circuit is coupled to the first reception circuit and is configured to transmit the input signal to the first reception circuit based on the output clock signal and transmit the input clock signal corresponding to the output clock signal to the first reception circuit.

[0173] In some embodiments, the first transmission circuit is further configured to transmit an output signal based on the first clock signal, the second reception circuit is further configured to receive the output signal from the first transmission circuit, and the second transmission circuit is configured to transmit the input signal in response to the output signal.

[0174] In some embodiments, the first circuit is configured to: in response to a first value of a first selection signal, output the second signal in response to a first edge of the first clock signal, and in response to a second value of the first selection signal, output the second signal in response to a second edge of the first clock signal, the second value being different from the first value, the first edge being one of the rising edge and the falling edge of the first clock signal, and the second edge being the other of the rising edge and the falling edge of the first clock signal.

[0175] In some embodiments, the first circuit is configured to: in response to a first value of a select signal, output a second signal in response to a first edge of a first clock signal, and in response to a second value of the select signal, output the second signal in response to a second edge of the first clock signal, the second value being different from the first value, and the first edge and the second edge being separated by half a clock cycle.

[0176] In some embodiments, the first circuit includes: a flip-flop including an input coupled to a first receiving circuit to receive a first signal, an output of the flip-flop configured to output a second signal, and a clock input, and a multiplexer including a non-inverting input configured to receive the first clock signal, an inverting input configured to receive the first clock signal, a select input configured to receive the select signal, and an output coupled to the clock input of the flip-flop.

[0177] In some embodiments, the first circuit further includes a storage circuit having an output coupled to the select input of the multiplexer, and the storage circuit stores a predetermined value of the select signal, the predetermined value corresponding to the multiplexer configured to output the first clock signal received at the non-inverting input to the clock input of the flip-flop, or the multiplexer configured to output the first clock signal received at the inverting input to the clock input of the flip-flop.

[0178] In some embodiments, the first transmitting circuit is further configured to transmit an output signal corresponding to a test signal based on the first clock signal, the second receiving circuit is further configured to receive the output signal from the first transmitting circuit and provide the output signal to the second transmitting circuit, the second transmitting circuit is configured to transmit an input signal corresponding to the output signal, and the first semiconductor die further includes a control circuit configured to: select one of a rising edge and a falling edge of the first clock signal based on a comparison of first data in the test signal and second data in the second signal, and control the first circuit to output the second signal in response to the selected edge of the first clock signal.

[0179] In some embodiments, the first circuit includes: a flip-flop including an input coupled to a first receiving circuit to receive a first signal, an output of the flip-flop configured to output a second signal, and a clock input, and a multiplexer including a non-inverting input configured to receive the first clock signal, an inverting input configured to receive the first clock signal, a select input coupled to an output of the control circuit to receive a select signal corresponding to the selected edge, and an output coupled to the clock input of the flip-flop.

[0180] In some embodiments, the second semiconductor die further includes a multiplexer, the multiplexer including: a first input configured to receive an output clock signal, a second input configured to receive a second clock signal of the second semiconductor die, the second clock signal being independent of the first clock signal of the first semiconductor die, a selection input configured to receive a selection signal, and an output coupled to the second transmission circuit.

[0181] In some embodiments, the second semiconductor die further includes a second circuit, the second circuit being coupled to the second receiving circuit to receive an output clock signal, and the second circuit being configured to output an input clock signal corresponding to the output clock signal, wherein the input clock signal has a phase lead relative to the output clock signal.

[0182] In some embodiments, the second semiconductor die further includes a phase-locked loop, the phase-locked loop including: a reference input coupled to the second receiving circuit to receive an output clock signal, a feedback input, an output of the phase-locked loop configured to output an input clock signal corresponding to the output clock signal, and a feedback path coupled between the output and the feedback input, the feedback path including a delay circuit.

[0183] In some embodiments, the time delay of the delay circuit corresponds to the sum of a first time delay and a second time delay, the first time delay being between the main clock signal of the first semiconductor die, the main clock signal corresponding to the first clock signal, and the output clock signal at the output of the second receiving circuit, and the second time delay being between the output clock signal at the output of the second receiving circuit and the input clock signal at the output of the first receiving circuit.

[0184] In some embodiments, the second semiconductor die further includes a clock tree coupled between the output of the phase-locked loop and the delay circuit.

[0185] In some embodiments, the first semiconductor die includes a plurality of first clock I / O circuits, each including: a first clock input buffer, and a first clock output buffer, the second semiconductor die includes a plurality of second clock I / O circuits, each including: a second clock input buffer, a first clock output buffer coupled to a corresponding first clock I / O circuit of the plurality of first clock I / O circuits, and a second clock output buffer coupled to the first clock input buffer of the corresponding first clock I / O circuit, the second receiving circuit includes the second clock input buffer of one of the plurality of second clock I / O circuits, and the second transmission circuit includes the second clock output buffer of one of the second clock I / O circuits.

[0186] In some embodiments, the second semiconductor die further includes a multiplexer, the multiplexer including: a first input coupled to a reference input of a phase-locked loop to receive an output clock signal, a second input configured to the output of the phase-locked loop, a selection input configured to receive a selection signal, and an output coupled to an output of a second transmission circuit.

[0187] In some embodiments, an integrated circuit (IC) device includes a clock input buffer, a phase-locked loop (PLL), and a clock output buffer. The clock input buffer includes an input and an output configured to be coupled to a die-to-die (D2D) interface structure. The PLL includes a reference input coupled to the output of the clock input buffer, a feedback input, an output, and a feedback path coupled between the feedback input and the output of the PLL, the feedback path including a delay circuit. The clock output buffer includes an input coupled to the output of the PLL and an output configured to be coupled to another D2D interface structure.

[0188] In some embodiments, the integrated circuit device further includes: a clock tree coupled between the output of the phase-locked loop and the delay circuit.

[0189] In some embodiments, the integrated circuit device further includes: a multiplexer including: a first input coupled to a reference input of a phase-locked loop, a second input configured to the output of the phase-locked loop, a selection input configured to receive a selection signal, and an output coupled to an input of the clock output buffer.

[0190] In some embodiments, a method of operating an integrated circuit device includes sending an output signal and an output clock signal associated with the output signal to a semiconductor die. The method further includes receiving an input signal and an input clock signal associated with the input signal from the semiconductor die, the input signal corresponding to the output signal and the input clock signal corresponding to the output clock signal. The method further includes selecting a clock signal based on a comparison of data in the output signal with data obtained from the input signal. The method further includes obtaining additional data from an additional input signal received from the semiconductor die based on the selected clock signal.

[0191] In some embodiments, the method further includes: obtaining first data from the input signal based on a first clock signal corresponding to the output clock signal; and obtaining second data from the input signal based on an inverted clock signal of the first clock signal, wherein sending includes sending the output signal based on the first clock signal, comparing includes: performing a first comparison of data in the output signal with the first data, and performing a second comparison of data in the output signal with the second data, and selecting includes selecting the first clock signal or the inverted clock signal as the selected clock signal based on the first comparison and the second comparison.

[0192] The components of several embodiments are described above, enabling those skilled in the art to better understand each embodiment of the present invention. Those skilled in the art should understand that it is easy to use the present invention as a basis to design or modify other processes and structures to achieve the same purpose and / or realize the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also be aware that these equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit device, comprising: A first semiconductor die, comprising: A first transmission circuit configured to transmit an output clock signal corresponding to a first clock signal; A first reception circuit configured to receive an input clock signal and an input signal, and Output a first signal corresponding to the input signal based on the input clock signal; and A first circuit configured to output a second signal corresponding to the first signal based on the first clock signal; and A second semiconductor die, comprising: A second reception circuit coupled to the first transmission circuit to receive the output clock signal; and A second transmission circuit coupled to the first reception circuit and configured to: Transmit the input signal to the first reception circuit based on the output clock signal, and Transmit the input clock signal corresponding to the output clock signal to the first reception circuit.

2. The integrated circuit device according to claim 1, wherein The first transmission circuit is further configured to transmit an output signal based on the first clock signal, The second reception circuit is further configured to receive the output signal from the first transmission circuit, and The second transmission circuit is configured to transmit the input signal in response to the output signal.

3. The integrated circuit device according to claim 1, wherein The first circuit is configured to output the second signal in response to a first value of a first selection signal, in response to a first edge of the first clock signal, and Output the second signal in response to a second value of the first selection signal, in response to a second edge of the first clock signal, The second value is different from the first value, The first edge is one of a rising edge and a falling edge of the first clock signal, and The second edge is the other of the rising edge and the falling edge of the first clock signal.

4. The integrated circuit device according to claim 1, wherein The first circuit is configured to output the second signal in response to a first value of a selection signal, in response to a first edge of the first clock signal, and Output the second signal in response to a second value of the selection signal, in response to a second edge of the first clock signal, The second value is different from the first value, and The first edge is half a clock cycle away from the second edge.

5. The integrated circuit device according to claim 1, wherein, The first circuit comprises: A flip-flop, comprising: An input coupled to the first reception circuit to receive the first signal, The flip-flop is configured to output an output of the second signal, and A clock input, and A multiplexer, comprising: A non-inverting input configured to receive the first clock signal, An inverting input configured to receive the first clock signal, A selection input configured to receive a selection signal, and An output coupled to the clock input of the flip-flop.

6. The integrated circuit device according to claim 1, wherein The first transmission circuit is further configured to transmit an output signal corresponding to a test signal based on the first clock signal, The second reception circuit is further configured to receive the output signal from the first transmission circuit and provide the output signal to the second transmission circuit, The second transmission circuit is configured to transmit the input signal corresponding to the output signal, and The first semiconductor die further includes a control circuit configured to select one of the rising edge and the falling edge of the first clock signal based on a comparison between first data in the test signal and second data in the second signal, and control the first circuit to output the second signal in response to the selected edge of the first clock signal.

7. The integrated circuit device according to claim 6, wherein, The first circuit includes: A flip-flop including: An input coupled to the first receiving circuit to receive the first signal, The flip-flop being configured to output an output of the second signal, and A clock input, and A multiplexer including: A non-inverting input configured to receive the first clock signal, An inverting input configured to receive the first clock signal, A selection input coupled to an output of the control circuit to receive a selection signal corresponding to the selected edge, and An output coupled to the clock input of the flip-flop.

8. The integrated circuit device according to claim 1, wherein The second semiconductor die further includes a multiplexer including: A first input configured to receive the output clock signal, A second input configured to receive a second clock signal of the second semiconductor die, the second clock signal being independent of the first clock signal of the first semiconductor die, A selection input configured to receive a selection signal, and An output coupled to an output of the second sending circuit.

9. An integrated circuit device, comprising: A clock input buffer including: An input configured to be coupled to a die-to-die interface structure, and An output; A phase-locked loop including: A reference input coupled to an output of the clock input buffer, A feedback input, An output, and A feedback path coupled between the feedback input and the output of the phase-locked loop, the feedback path including a delay circuit; and A clock output buffer including: An input coupled to an output of the phase-locked loop, and An output configured to be coupled to another die-to-die interface structure.

10. A method of operating an integrated circuit device, comprising: Sending an output signal and an output clock signal associated with the output signal to a semiconductor die; Receiving an input signal and an input clock signal associated with the input signal from the semiconductor die, the input signal corresponding to the output signal, the input clock signal corresponding to the output clock signal; Selecting a clock signal based on a comparison between data in the output signal and data obtained from the input signal; And Obtaining additional data from an additional input signal received from the semiconductor die based on the selected clock signal.

Images