Capacitor health diagnosis

Abstract

The subject of the invention is capacitor health diagnosis. A capacitor health diagnostic circuit is provided that is configured to run a diagnostic test to determine a capacity of the at least one snubber capacitor. The diagnostic test includes a multi-stage discharge test performed under varying current conditions to determine a leakage current of the at least one capacitor and determine a capacitance of the at least one capacitor based at least in part on the determined leakage current.

Description

Technical Field

[0001] The present invention relates to a capacitor health diagnosis circuit and method. Background Art

[0002] In the field of industrial process automation, controllers typically have a power-off function that is operable to hold the process value measured immediately before power-off for reuse when powered on. An example includes a conveyor belt for loading a bulk material ship. When restarting after a power-off, the control application should continue with the exact same load count value as before the power-off. As the complexity of process control systems increases, the challenge of implementing the power-off function in a cost-effective manner becomes more challenging. Summary of the Invention

[0003] To better solve one or more of these problems, in a first aspect of the present invention, a capacitor health diagnosis circuit is provided that is configured to determine the health state of at least one buffer capacitor. Specifically, the capacitor health diagnosis circuit is operable to run a diagnostic test to determine the capacitance of at least one buffer capacitor. The diagnostic test includes a multi-stage discharge test performed under varying current conditions to determine the leakage current of the at least one capacitor, and the capacitance of the at least one capacitor is determined at least in part based on the determined leakage current.

[0004] More specifically, the diagnostic test may include: in a first stage, performing a first-stage discharge test to determine a first-stage discharge time, and in a second stage, performing a second-stage discharge test to determine a second-stage discharge time, where each of the first discharge time and the second discharge time is measured relative to a predetermined voltage difference across the capacitor. The at least one capacitor is discharged in parallel with a predefined constant current in the second stage and without the predefined constant current in the first stage to achieve varying current conditions. The capacitor health diagnosis circuit is configured to determine the leakage current of the at least one capacitor based on the first discharge time and the second discharge time and based on the predefined constant current.

[0005] The discharge test may be performed using at least one timer that forms part of a device (e.g., a controller of a process control system) powered by at least one capacitor. For cost effectiveness, the timer may be an internal timer of a component that forms part of a device for purposes other than capacitor health diagnosis. In one example, the timer is an internal timer or counter of a logic circuit that executes a control application for process control in an industrial automation system or that supports the execution of the control application. Such a counter provides high resolution at low cost, enabling the capacitor health diagnosis circuit to be implemented in a cost-effective manner.

[0006] The predetermined voltage difference used in the discharge test can correspond to the difference between the default voltage applied to at least one capacitor and a predefined set point. The capacitor health diagnostic circuit can include a DC-DC converter configured to convert an input voltage into the default voltage. The DC-DC converter can include an error amplifier configured to sense the output voltage (or a scaled version thereof) of the DC-DC converter and control the DC-DC converter to generate the default voltage as the output voltage. The error amplifier can be configured to compare the sensed output voltage with an internal reference voltage and control the DC-DC converter based on the comparison between the sensed output voltage and the internal reference voltage. Conveniently, the predefined set point used in the discharge test can be based on the internal reference voltage of the error amplifier. In one example, the DC-DC converter includes a boost converter, also known as a step-up voltage converter. In the case where the capacitor health diagnostic circuit includes a boost converter to convert the input voltage into the default voltage, the predefined set point can conveniently be based on the internal reference voltage of the error amplifier in the boost converter. The sensed output voltage (or a scaled version thereof) is provided as a feedback signal (FB) to the DC-DC converter. The error amplifier of the DC-DC converter performs a comparison between the feedback signal and the internal reference voltage and determines whether to periodically switch the DC-DC converter based on the comparison result. The DC-DC converter outputs a switching signal (SW) that can be in a dynamic state (the DC-DC converter is switching) or a static state (the DC-DC converter is not switching), depending on the comparison result. In an advantageous implementation described herein, the state of this switching signal is directly used to generate a start signal or a stop signal for controlling a timer without any separate voltage comparator to detect the voltage level during the discharge test. Thus, by reusing components for other purposes, the timer can be controlled in a resource-efficient manner.

[0007] By performing a multi-stage discharge test under varying current conditions, when determining the leakage current, the errors caused by the inaccuracies of one or more components can cancel each other out.

[0008] The capacitor health diagnostic circuit can also be configured to issue a warning when the remaining capacity is insufficient to perform a power-off sequence. The capacitor health diagnostic circuit can also be configured to issue a pre-warning when the determined capacitance drops below a predetermined threshold. The capacitor health diagnostic circuit can also be configured to predict when maintenance should be performed based at least in part on the determined capacitance.

[0009] The capacitor health diagnostic circuit can also be configured to predict the aging of the at least one capacitor bank based on historical data related to previously performed power-off sequences.

[0010] The capacitor health diagnostic circuit may also be configured to perform multi-stage discharging using the change in capacitor voltage within a voltage range higher than a predetermined capacitor voltage required to perform a power-off sequence. In this way, capacitor health diagnosis can be performed during normal operation without compromising the power-off function.

[0011] According to a second aspect, there is provided a controller for a process control system, the controller including the capacitor health diagnostic circuit of the first aspect. The controller may be configured to execute a control application for controlling an industrial process. In one example, the logic circuit of the capacitor health diagnostic circuit may be implemented by the same logic circuit that executes the control application. The control application may generate process data, which may be obtained or extracted by the controller for retention during a power failure. The controller may be configured to store the process data in a non-volatile memory for a predetermined amount of time, such as at least one hour during a power failure. The controller may update the process data maintained during normal operation frequently until a power failure. For example, the controller may periodically place the process data to be retained in a static / dynamic RAM having an infinite number of write cycles and fast access time before writing the process data to a non-volatile memory (such as F-RAM, M-RAM or nvSRAM) at power-off.

[0012] According to a third aspect, there is provided a process control system including the capacitor health diagnostic circuit of the first aspect and / or the controller of the second aspect.

[0013] According to a fourth aspect, there is provided an industrial automation system including the capacitor health diagnostic circuit of the first aspect and / or the controller of the second aspect and / or the process control system of the third aspect.

[0014] According to a fifth aspect, there is provided a capacitor health diagnostic method. It is configured to determine the health state of the at least one buffer capacitor. The method includes running a diagnostic test to determine the capacitance of the at least one buffer capacitor. The diagnostic test includes a multi-stage discharging test performed under varying current conditions to determine the leakage current of the at least one capacitor, and determining the capacitance of the at least one capacitor based at least in part on the determined leakage current.

[0015] The method of the fifth aspect may be computer-implemented. With necessary modifications, the optional features of the first aspect may form part of any of the second to fifth aspects.

[0016] According to a sixth aspect, there is provided a computing system configured to execute the method of the fifth aspect.

[0017] According to a seventh aspect, there is provided a computer program (product) comprising instructions which, when executed by a computing system, enable or cause the computing system to perform the method of the fifth aspect.

[0018] According to an eighth aspect, there is provided a computer-readable (storage) medium comprising instructions which, when executed by a computing system, enable or cause the computing system to perform the method of the fifth aspect. The computer-readable medium may be transient or non-transient, volatile or non-volatile.

[0019] By using at least one capacitor as described herein to power the controller in the event of a power failure, a battery is not required.

[0020] It should be understood that the techniques described herein apply not only to the controllers of process control systems, but also to any device that uses a capacitor as an energy source.

[0021] A “(process) automation system” refers to an industrial or production installation including one or more pipelines, production lines, and / or assembly lines for converting one or more feedstocks into products and / or for assembling one or more components into a final product.

[0022] As used herein, the term “obtain” may include, for example, receiving from another system, device, or process; receiving via interaction with a user; loading or retrieving from a storage device or memory; measuring or capturing using a sensor or other data acquisition device.

[0023] As used herein, the term “determine” encompasses a wide variety of actions and may include, for example, calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, database, or another data structure), ascertaining, etc. Further, “determine” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Moreover, “determine” may include parsing, selecting, picking, establishing, etc.

[0024] The indefinite articles “a” or “an” do not exclude a plurality. Further, the articles “a” and “an” as used herein shall generally be construed to mean “one or more” unless otherwise stated or clearly indicated as the singular form from the context.

[0025] Unless otherwise stated, or clearly apparent from the context, the phrases "one or more of A, B, and C", "at least one of A, B, and C", and "A, B, and / or C" as used herein are intended to represent all possible permutations of one or more of the listed items. That is, the phrase "A and / or B" means (A), (B), or (A and B), and the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0026] The term "comprising" does not exclude other elements or steps. Further, the terms "comprising", "including", "having", etc. may be used interchangeably herein.

[0027] The present invention may include one or more aspects, examples, or features, either alone or in combination, whether specifically disclosed in such combination or alone. Any optional feature or sub-aspect of one of the above aspects is suitably applicable to any other aspect.

[0028] The above aspects will become apparent and be elucidated with reference to the detailed description provided hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] A detailed description will now be given, by way of example only, with reference to the accompanying drawings, in which:

[0030] Figure 1 A process control system for controlling an industrial process is shown; and

[0031] Figure 2 A capacitor health diagnostic circuit according to the present disclosure is shown. DETAILED DESCRIPTION

[0032] Figure 1 A process control system 100 for controlling an industrial process executed by an automation system (not shown) is shown. The process control system 100 includes a plurality of controllers 102 - A, 102 - B, 102 - C, 102 - D, collectively referred to as controllers 102, which are physically and communicatively coupled to each other via a mounting terminal unit (MTU) 110 (commonly referred to as a backplane). The controllers 102 are configured to communicate with other components of the automation system, such as field devices or engineering tools as described herein. The engineering tool (commonly implemented as a software package) is used to create configuration data for the process control system 100, which can be downloaded to the controllers 102. For the purpose of such communication, the controllers 102 are equipped with Ethernet ports, as shown at 114, and associated communication interface circuits. Each controller 102 also includes its own network switch.

[0033] Each controller in the controller 102 is configured to control a corresponding process executed by an automation system (not shown). The process control system 100 can be applied to any industrial field that requires process automation, such as energy, oil and gas, chemicals, petrochemicals, etc. The controller 102 processes the process control and monitoring of the automation system by receiving input signals from sensors and instruments and outputting control signals for controlling plant equipment such as pumps, valves, conveyor belts, mixers, and heaters. Any such sensor, instrument, or plant equipment can form part of one or more field devices in the field devices. The controller 102 is configured to execute a process control application to generate a control signal based on the input signal. Each control application can include control logic that indicates how the corresponding controller should respond to all input signals with appropriate control signals to maintain the normal function of the process. In a non-limiting example, the control application complies with the international standard IEC61131. Each controller in the controller 102 includes a logic circuit configured to execute the corresponding control application. The logic circuit can include a CPU, MCU, SOC, FPGA, DSP, and / or AI engine, as well as any memory used in signal processing. The logic circuit can also be configured to execute any one or more other operations described herein.

[0034] One or more of the controllers in the controller 102 are also provided with a power-off function that is operable to hold the process value measured immediately before the power-off for reuse when power is restored. According to the present disclosure, the power-off circuit of the controller 102 includes at least one buffer capacitor for buffering sufficient energy to complete the power-off sequence, and at least one data storage device (e.g., non-volatile memory) for storing application data after the power-off circuit detects a power failure. The power-off sequence includes the power-off circuit capturing the state of the control application to be held in the data storage device. In a non-limiting example, the power-off sequence includes the following steps: 1) detecting power loss; 2) obtaining control application status data from the control application; 3) storing the control application status data in the data storage device. The power-off circuit can also be configured to execute a power-on sequence to resume the execution of the control application after power is restored.

[0035] The capacitance of at least one buffer capacitor is important for the completion of the power-off sequence. During normal operation, the controller is powered by the system power supply, and at least one capacitor is reverse-blocked. In this state, at least one capacitor slowly discharges through its self-leakage current. In addition, aging capacitors suffer from capacitance loss and / or higher self-discharge. The loss of capacitance endangers the completion of the power-off sequence. Higher self-discharge results in additional power dissipation during normal operation.

[0036] Accordingly, a controller in accordance with the present disclosure includes a capacitor health diagnostic circuit configured to determine the health state of at least one buffer capacitor. In particular, the capacitor health diagnostic circuit runs diagnostic tests to determine the capacitance of at least one buffer capacitor. The diagnostic tests may be performed periodically or sporadically, such as during normal operation, to determine sufficient charge retention for satisfactory power-off handling. The controller 102 of the present disclosure utilizes an internal high-resolution counter, which is typically available even in low-cost logic circuits (such as a microcontroller unit (MCU) or a system-on-chip (SoC)), in order to implement the capacitor health diagnostic circuit in a cost-effective manner.

[0037] Figure 2 A capacitor health diagnostic circuit 200 according to one example is shown. The capacitor health diagnostic circuit 200 includes the following elements.

[0038] A voltage input 202 provides an input voltage VIN to subsequent circuits. The input voltage VIN may be a direct system input power (such as 24V) or an intermediate voltage (such as 5.1V).

[0039] A boost voltage / boost function converter 204 (more simply referred to as a "boost converter") includes a topology power converter that is operable to produce a boosted output voltage Uo that is higher than the input voltage VIN.

[0040] An inductor 206 is used by the boost converter 204 to store and release energy during each switching cycle of the converter 204 to assist in generating the boosted output voltage.

[0041] A reverse-blocking diode 208 prevents current from returning to the voltage input 202.

[0042] A capacitor bank 210 provides energy storage for the power-off sequence. In one non-limiting example, at least 5 joules are stored at a default boost voltage of 50V. Any type of capacitor may be used.

[0043] A dummy load 212 is used to determine the leakage current I 泄 leak of the circuit served by the boost voltage Uo.

[0044] A voltage feedback network 214 receives a trigger signal at a first switch SW1 to trigger the start of a diagnostic test by causing the voltage feedback network 214 to change the output voltage of the boost converter 204 in the manner described below.

[0045] A signal detection / decoupling network 216 obtains a switching signal SW from the boost converter 204 and drives a second switch SW2 to generate a status signal indicating that discharge is complete and a desired voltage has been reached.

[0046] The controllable constant current source 218 controls the third switch SW3 during the diagnostic step. The constant current provided by the current source 218 is defined as I 放电 = Vref / RS, where Vref is a reference voltage generated by the current source 218, for example. The current source 218 is implemented using a low-cost voltage reference device TLV431 in a non-limiting example, which is typically accurate to within 1%.

[0047] As described above, the logic circuit 220 of the controller 102 may include a CPU, an SoC, and / or an MCU, which are operable to perform the functions described herein, including diagnostic tests. The logic circuit 220 also includes an internal timer function and / or a pulse counting function. The logic circuit 220 outputs a control signal for the first switch SW1 at the general-purpose input / output GPIO_A, receives a status signal from the signal detection / decoupling network 216 at GPIO_B, and outputs a control signal for the third switch SW3 at GPIO_C.

[0048] By default, the logic circuit 220 drives GPIO_A to logic high, such that the first switch SW1 is turned on and the output voltage Uo of the boost converter 204 is at the default voltage. At this stage, the logic circuit 220 ignores the status signal output by the second switch SW2. The third switch SW3 is turned on because the logic circuit 220 drives GPIO_C to logic high, such that the current source 218 is disabled. In this state, only the leakage current (e.g., a few microamperes) passes through the transistor of the current source 218.

[0049] To start running the diagnostic test for determining the capacitance of the capacitor bank 210, the logic circuit 220 drives GPIO_A to logic low in order to turn off the first switch SW1. The boost converter 204 detects an increase in the voltage at its feedback pin FB and stops switching, such that the output voltage Uo decreases to a lower value (e.g., 1 V lower than the default voltage) according to the leakage current (I 泄漏 ). The drive pin SW of the boost converter 204 enters a static state.

[0050] Then, the second switch SW2 passes a rising edge as the status signal to the logic circuit 220. The logic circuit 220 samples the status signal and uses the internal timer to record the time elapsed since the first switch SW1 was turned off.

[0051] When the voltage of the capacitor bank 210 reaches a predefined set point, the boost converter 204 resumes switching to move the output voltage Uo back to its default value. Then, the second switch SW2 conveys a falling edge to the logic circuit 220, which triggers the logic circuit 220 to stop the internal timer, record the first-stage discharge time T1, and reconnect the first switch SW1. In one example, the internal reference voltage used by the control loop amplifier in the boost converter 204 can be used as the set point.

[0052] According to the present disclosure, the diagnostic test includes multiple phases.

[0053] After the voltage of the capacitor bank 210 returns to the default value, the logic circuit 220 repeats the first stage as described above, but drives GPIO_C to logic high so that the current source 218 can provide a predefined constant current I 放电 . In the second stage, when the voltage of the capacitor bank 210 reaches the set point, the boost converter 204 resumes switching, and the second switch SW2 conveys a falling edge to the logic circuit 220, triggering the logic circuit 220 to stop the internal timer and record the second-stage discharge time T2.

[0054] The first-stage discharge time T1 is only affected by the leakage current I 泄漏 , while the second-stage discharge time T2 depends on the leakage current and the discharge current I provided by the current source 218 放电 . Using these two time measurements T1 and T2, the first measurement and the second measurement of the voltage difference ΔUo between the default voltage and the set point used by the boost converter 204 are obtained using the following approximations assuming a constant current.

[0055] First measurement: ΔUo * C = I 泄漏 * T1

[0056] Second measurement: ΔUo * C = (I 泄漏 + I 放电 ) * T2

[0057] Here, C is the total capacitance of the capacitor bank 210, which is assumed to remain constant between the two measurements.

[0058] The leakage current can be determined as I 泄漏 = (I 放电 ) * T2) / (T1 – T2).

[0059] Therefore, the capacitance C can be determined as C = (I 泄漏 ) * T1) / ΔUo.

[0060] The main sources of error are inaccuracies in the constant current source 218 (Vref and shunt resistor RS), inaccuracies in the feedback network resistors controlled by the first switch SW1, and the peak-to-peak ripple in the output voltage Uo. However, such errors can be eliminated after performing the two-stage measurement process as described herein.

[0061] The capacity diagnostic test as described herein can be performed when charging the capacitor bank 210 with sufficient energy to provide a power-off sequence.

[0062] The controller 102 can be configured to run additional diagnostic tests, such as to check for leakage current and generate an error signal if the leakage current exceeds one or more thresholds.

[0063] If the capacity of the capacitor bank 210 is insufficient to complete the power-off sequence, the logic circuit 220 can issue a warning. One or more pre-warnings can be issued at a capacity higher than that required for the power-off sequence. The determined capacity can be used, for example, to predict the capacity available for future power-off sequences based on data related to capacitor aging, temperature, electrical stress, and / or the behavior of the capacitor bank 210 during historical power-off sequences.

[0064] The logic circuit 220 described herein can be implemented using hardware, software, and / or firmware configured to perform any of the operations described herein. The hardware can include one or more processor cores, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), an application specific standard product (ASSP), a system on a chip system (SOC), a complex programmable logic device (CPLD), etc. The software can be implemented as a software package, code, instructions, instruction sets, and / or data recorded on at least one transient or non-transient computer-readable storage medium. The firmware can be implemented as code, instructions, or instruction sets and / or hard-coded data in a memory device (e.g., a non-volatile memory device).

[0065] If implemented in software, these functions can be stored or transmitted as one or more instructions or codes on a computer-readable medium. The computer-readable medium includes computer-readable storage media. The computer-readable storage media can be any available storage media accessible by a computer. By way of example and not limitation, such computer-readable storage media may include FLASH storage media, RAM, ROM, EEPROM, CD-ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store the required program code in the form of instructions or data structures and be accessible by a computer. As used herein, disk and optical disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc (BD), where disks generally reproduce data magnetically and optical discs generally reproduce data optically with a laser. In addition, propagated signals can be included within the scope of computer-readable storage media. The computer-readable medium also includes communication media, which includes any medium that facilitates the transfer of a computer program from one place to another. For example, a connection can be a communication medium. By way of illustration, if software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwave are included in the definition of communication media. Combinations of the above should also be included within the scope of computer-readable media.

[0066] The applicant hereby discloses each individual feature described herein in isolation and any combination of two or more such features to the extent that such features or combinations are capable of being implemented by a person skilled in the art based on the common general knowledge from the specification as a whole, regardless of whether such features or combinations of features solve any of the problems disclosed herein, and without limitation to the scope of the claims. The applicant points out that aspects of the present invention may include any such individual feature or combination of features.

[0067] It must be noted that embodiments of the present invention are described with reference to different categories. In particular, some examples are described with reference to methods, while other examples are described with reference to devices. However, those skilled in the art will conclude from the specification that, unless otherwise stated, any combination between features belonging to different categories is also considered to be disclosed by this application, in addition to any combination of features belonging to one category. However, all features can be combined to provide more synergistic effects than a simple sum of the features.

[0068] Although the present invention has been described in detail in the drawings and the foregoing description, such description and illustration shall be considered exemplary rather than restrictive. The present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and achieved by those skilled in the art by studying the drawings, the disclosure, and the appended claims.

[0069] The fact that certain measures are recited in mutually different dependent claims does not mean that a combination of these measures cannot be used to advantage.

[0070] Any reference signs in the claims shall not be construed as limiting the scope.

Claims

1. A capacitor health diagnosis circuit configured to run diagnostic tests to determine the capacitance of at least one buffer capacitor, wherein the diagnostic tests include a multi-stage discharge test performed under varying current conditions to determine the leakage current of the at least one capacitor and to determine the capacitance of the at least one capacitor at least in part based on the determined leakage current.

2. The capacitor health diagnosis circuit according to claim 1, wherein the diagnostic test includes: In a first stage, a first-stage discharge test is performed to determine a first-stage discharge time; and in a second stage, a second-stage discharge test is performed to determine a second-stage discharge time, wherein each of the first discharge time and the second discharge time is measured relative to a predetermined voltage difference across the capacitor.

3. The capacitor health diagnosis circuit according to claim 2, wherein the at least one capacitor discharges in parallel with a predefined constant current in the second stage and discharges without the predefined constant current in the first stage to achieve the varying current conditions.

4. The capacitor health diagnosis circuit according to claim 3, configured to determine the leakage current of the at least one capacitor based on the first discharge time and the second discharge time and based on the predefined constant current.

5. The capacitor health diagnosis circuit according to any one of the preceding claims, configured to perform the discharge test using at least one timer, the at least one timer forming part of a device to be powered by the at least one capacitor.

6. The capacitor health diagnosis circuit according to claim 5, wherein the at least one timer is an internal timer or counter of a logic circuit that executes a control application for process control in an industrial automation system.

7. The capacitor health diagnosis circuit according to any one of the preceding claims, wherein the predetermined voltage difference used in the discharge test corresponds to the difference between the default voltage applied to the at least one capacitor during normal operation and a predefined set point.

8. The capacitor health diagnosis circuit according to claim 7, including a boost converter for converting an input voltage to the default voltage, wherein the predefined set point is based on an internal reference voltage of a control loop amplifier in the boost converter.

9. The capacitor health diagnosis circuit according to any one of the preceding claims, further configured to issue a warning when the remaining capacity is insufficient to perform a power-off sequence.

10. The capacitor health diagnosis circuit according to any one of the preceding claims, further configured to predict the aging of at least one capacitor bank based on historical data related to previously performed power-off sequences.

11. The capacitor health diagnosis circuit according to any one of the preceding claims, further configured to perform the multi-stage discharge using a change in capacitor voltage within a voltage range higher than a predetermined capacitor voltage required to perform a power-off sequence.

12. A controller for a process control system, the controller including the capacitor health diagnosis circuit according to any one of the preceding claims.

13. A process control system includes a capacitor health diagnosis circuit according to any one of claims 1-11.

14. A method for capacitor health diagnosis includes running a diagnostic test to determine the capacitance of at least one buffer capacitor, wherein the diagnostic test includes a multi-stage discharge test performed under varying current conditions to determine the leakage current of the at least one capacitor, and determining the capacitance of the at least one capacitor at least in part based on the determined leakage current.

15. A computer-readable medium includes instructions that, when executed by a computing system, cause the computing system to perform the method according to any one of claims 1-11.

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