Wafer processing optimization method and device and semiconductor device

Abstract

The invention provides a wafer processing optimization method, a wafer processing optimization device and a semiconductor device, and belongs to the technical field of semiconductor device manufacturing. According to the wafer processing optimization method, the energy and the rotating speed of target ions are reasonably adjusted, matching is performed according to the type and the thickness of photoresist, the phenomenon that the photoresist is broken or falls off due to excessive bombardment of the ions is avoided, and the quality of the photoresist is improved. Therefore, the photoresist is kept stable in the ion implantation process, the surface of a wafer below is effectively protected, and a mask pattern in the photoetching process is prevented from being damaged, so that the subsequent photoetching process can be smoothly carried out, and the stability of the manufacturing process and the product quality are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and particularly to a method and apparatus for optimizing wafer processing and a semiconductor device. Background Art

[0002] The BCD process (Bipolar-CMOS-DMOS) is an integrated circuit manufacturing process that combines three different types of semiconductor technologies: Bipolar, CMOS (Complementary Metal Oxide Semiconductor), and DMOS (Double-diffused Metal Oxide Semiconductor), thereby making full use of the performance advantages of various devices and providing more design options. The BCD process also has very strict requirements for defect control. Coupled with the increasingly diverse chip functions, these have put forward higher requirements for the capabilities and control of chip manufacturing processes.

[0003] In the high-voltage power part circuit of BCD technology, the optimization of lithography process parameters is crucial for the reliability of the entire circuit. Lithography is a process technology in the integrated circuit manufacturing process that uses the principles of optics and chemical reactions to transfer patterns to the single crystal surface or dielectric layer through chemical and physical etching methods, thereby forming effective pattern windows or functional images. The lithography mask is the source of lithography patterns. These patterns are usually provided with data by customers and then fabricated by the mask factory.

[0004] During the ion implantation process at the N-type and P-type source / drain ends, the areas on the wafer that do not need to be implanted are blocked by photoresist. The photoresist in the N-type or P-type source / drain end areas that need to be implanted will undergo a photosensitive reaction during exposure, and then be removed by the developer, thereby allowing ions to be implanted into the silicon surface. At the same time, the lithography mask will block the light source to ensure that the areas that do not need to be implanted will not be removed by the developer. This series of processes realizes the selective area implantation of ions through the lithography process. However, in this process, there will be a problem of photoresist peeling off, which will affect the subsequent processing technology of the wafer. Summary of the Invention

[0005] The present invention provides a method and apparatus for optimizing wafer processing and a semiconductor device to solve the defect that photoresist is prone to peeling off during the ion implantation process in the prior art, and to achieve the effect of reducing the risk of photoresist peeling off.

[0006] The present invention provides a method for optimizing wafer processing, including: Determine a first dimension, coat the photoresist of the first dimension on the wafer and perform soft baking to remove a part of the solvent in the photoresist, cure the photoresist and cool it; Determine a second dimension at the edge of the wafer, and use edge exposure of the wafer to expose and remove all the photoresist within a second dimension range around the edge of the wafer; Determine that the wafer attached with photoresist enters the exposure machine to perform an exposure reaction on the light-transmitting part; Determine to bake the wafer to eliminate the standing wave effect during exposure and improve the photoresist topography; Remove the photoresist on the light-transmitting part of the wafer with a developer, and retain the photoresist on the non-light-transmitting part; Bombard the wafer with target ions with attached energy to perform ion implantation on the wafer; the energy and rotation speed of the target ions are determined based on the type of photoresist and the first dimension.

[0007] According to a wafer processing optimization method provided by the present invention, the determination of the first dimension includes: Determine the type of ion implantation process on the wafer, and determine the target type of photoresist according to the type of ion implantation process; Based on the target type of photoresist, the feature size to be processed, and the size of the exposure pattern, determine the first dimension.

[0008] According to a wafer processing optimization method provided by the present invention, the energy of the target ions is determined by the following method: Determine the type of ion implantation process on the wafer, and determine the target type of photoresist and the doping depth according to the type of ion implantation process; Based on the target type of photoresist and the first dimension, determine the first energy of the target ion implantation; Based on the doping depth of the wafer, determine the second energy of the target ion implantation; Based on the first energy and the second energy, determine the target energy range of the target ion implantation; Determine the value close to the lower limit of the interval of the target energy as the energy of the target ions.

[0009] According to a wafer processing optimization method provided by the present invention, the ion rotation speed of the target ions is determined by the following method: Determine the type of ion implantation process on the wafer, and determine the target type of photoresist and the doping depth according to the type of ion implantation process; Based on the target type of photoresist and the first dimension, determine the first rotation speed of the target ion implantation; Based on the doping depth of the wafer, determine the second rotation speed of the target ion implantation; Based on the first rotation speed and the second rotation speed, determine the target rotation speed range of the target ion implantation; Determine the value close to the lower limit of the interval of the target rotation speed as the rotation speed of the target ions.

[0010] A wafer processing optimization method provided by the present invention further includes, before bombarding a wafer with target ions with attached energy for ion implantation of the wafer: After removing the photoresist with a developer, bake the wafer to harden the unexposed photoresist after being soaked in the developer; the baking temperature is higher than the soft baking temperature after coating the photoresist.

[0011] A wafer processing optimization method provided by the present invention, determining a second dimension of the wafer edge, and using wafer edge exposure to expose and remove all the photoresist within the second dimension range around the wafer edge, includes: Determine the second dimension of the wafer edge, and form an annular exposure band in the wafer edge region, the width of the annular exposure band being the second dimension; Set a mask annular band with a target width inside the annular exposure band, and use wafer edge exposure to expose and remove all the photoresist within the second dimension range around the wafer edge except the mask annular band.

[0012] A wafer processing optimization method provided by the present invention, the ion implantation of the wafer includes: Use phosphorus ions and arsenic ions for implantation respectively as the source and drain regions of N-type doping, so that As N+ is surrounded by P N-; use boron ions for implantation as the source and drain regions of P-type doping.

[0013] The present invention also provides a wafer processing optimization device, including: A first processing module for determining a first dimension, coating a photoresist of the first dimension on the wafer and performing soft baking to remove a solvent part in the photoresist, curing the photoresist and cooling; A second processing module for determining a second dimension of the wafer edge, and using wafer edge exposure to expose and remove all the photoresist within the second dimension range around the wafer edge; An exposure module for determining that the wafer with attached photoresist enters an exposure machine platform to perform an exposure reaction on the light-transmitting part; A baking module for determining to bake the wafer to eliminate the standing wave effect during the exposure process and improve the photoresist topography; A cleaning module for removing the photoresist on the light-transmitting part of the wafer with a developer and retaining the photoresist on the non-light-transmitting part; An ion implantation module for bombarding the wafer with target ions with attached energy for ion implantation of the wafer; the energy and rotation speed of the target ions are determined based on the type of the photoresist and the first dimension.

[0014] The present invention also provides a semiconductor device, including a high-voltage power circuit. The semiconductor device is manufactured by using the BCD process, and the high-voltage power circuit is processed by using any one of the wafer processing optimization methods described above.

[0015] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements any one of the wafer processing optimization methods described above.

[0016] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements any one of the wafer processing optimization methods described above.

[0017] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements any one of the wafer processing optimization methods described above.

[0018] The wafer processing optimization method, device, and semiconductor device provided by the present invention, by reasonably adjusting the energy and rotation speed of the target ions and matching according to the type and thickness of the photoresist, avoid the photoresist from cracking or falling off due to excessive ion bombardment, which makes the photoresist remain stable during the ion implantation process, effectively protects the underlying wafer surface, ensures that the mask pattern in the lithography process is not damaged, and thus ensures that the subsequent lithography process can proceed smoothly, ensuring the stability of the manufacturing process and the product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 is one of the flow diagrams of the wafer processing optimization method provided by the present invention; Figure 2 is another flow diagram of the wafer processing optimization method provided by the present invention; Figure 3 is the structural diagram of the wafer processing optimization device provided by the present invention; Figure 4 is the structural diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts belong to the scope of protection of the present invention.

[0022] The following will describe Figures 1 - 4 the wafer processing optimization method, device, and semiconductor device of the present invention.

[0023] Lithography is a process technology in integrated circuit manufacturing that uses the principles of optical-chemical reactions and chemical and physical etching methods to transfer patterns onto the surface of a single crystal or a dielectric layer, forming effective pattern windows or functional images. In this embodiment, the lithography process aims at selective ion implantation. To resist the bombardment of high-speed ions on the photoresist during the ion implantation process and prevent abnormal peeling of the photoresist, the wafer processing optimization method of the embodiments of the present invention can enhance the bonding ability between the photoresist and the wafer surface, reduce the peeling of the photoresist, and ensure the normal progress of the subsequent lithography process.

[0024] As Figure 1 shown, the wafer processing optimization method of the embodiments of the present invention mainly includes step 110, step 120, step 130, step 140, step 150, and step 160.

[0025] Step 110: Determine a first dimension, coat a photoresist of the first dimension on the wafer and perform soft baking to remove a part of the solvent in the photoresist, cure the photoresist, and cool it.

[0026] The first dimension refers to the thickness of the photoresist, which is determined according to specific process requirements such as the depth of ion implantation and the size of the patterns on the wafer surface. A photoresist with an appropriate thickness can resist the bombardment of high-speed ions during the subsequent ion implantation process and avoid abnormal peeling of the photoresist.

[0027] The photoresist can be coated on the wafer surface evenly by a spin coater. Different spin coating speeds and times will directly affect the thickness of the photoresist. The faster the spin coating speed, the thinner the coating, and vice versa.

[0028] The purpose of soft baking is to volatilize a part of the solvent in the photoresist by low-temperature heating, usually between 90°C and 110°C, to cure the photoresist and increase its adhesiveness and stability. The soft baking time and temperature need to be precisely controlled, otherwise it will affect the properties of the photoresist, such as its resolution or adhesiveness.

[0029] After the soft baking is completed, the photoresist needs to be cooled to enter the subsequent exposure step.

[0030] Step 120: Determine the second dimension of the wafer edge, and use edge exposure of the wafer to expose all the photoresist within the second dimension range around the wafer edge for removal.

[0031] The second dimension refers to the width of the photoresist at the wafer edge. In the lithography process, the photoresist at the wafer edge needs to be removed. Because during subsequent ion implantation and chemical processing, the photoresist at the edge can easily cause uneven pattern formation or contaminate the equipment.

[0032] A dedicated edge exposure device can selectively expose a circle of photoresist on the wafer edge through a light beam. The exposed photoresist will be removed during the development stage, ensuring no photoresist residue at the edge and guaranteeing the smooth progress of subsequent processes.

[0033] Step 130: Determine that the wafer with photoresist attached enters the exposure machine to expose the light-transmitting part.

[0034] The wafer with photoresist enters the exposure machine. Common exposure devices include steppers or scanners. Exposure uses an optical system to transfer the pattern on the mask plate to the photoresist through light irradiation.

[0035] Some areas on the mask plate are light-transmitting. Light passes through these areas and irradiates the photoresist, and a chemical reaction occurs in the irradiated areas, causing the properties of the photoresist in these areas to change. The exposed photoresist area will become easily soluble and removable by the developer.

[0036] Step 140: Determine to bake the wafer to eliminate the standing wave effect during exposure and improve the photoresist morphology.

[0037] After exposure, the wafer will undergo a bake, called post-bake. Its main purpose is to eliminate the standing wave effect. During exposure, due to the interference effect of light, a standing wave pattern may form on the photoresist surface, resulting in uneven photoresist morphology. The post-bake eliminates these standing waves through heat diffusion to ensure a smooth photoresist morphology in the exposed area.

[0038] The post-bake can also further cure the photoresist, improve its mechanical strength and adhesion, and prepare for development and subsequent ion implantation.

[0039] The post-bake temperature and time are determined according to the type of photoresist, usually between 90°C and 130°C.

[0040] Step 150: Remove the photoresist in the light-transmitting part of the wafer with the developer, and retain the photoresist in the non-light-transmitting part.

[0041] Development involves immersing the wafer in a developer solution, which dissolves the photoresist in the exposed areas to form the desired pattern. The unexposed portions of the photoresist remain intact, continuing to cover the wafer surface and protecting these areas from subsequent ion implantation.

[0042] Common developer solutions include alkaline and acidic ones, and the specific choice depends on the type of photoresist used (positive or negative). The development time and the concentration of the developer solution need to be precisely controlled to ensure the accuracy and clarity of pattern transfer.

[0043] Step 160, bombarding the wafer with target ions with attached energy to perform ion implantation on the wafer.

[0044] The energy and rotation speed of the target ions are determined based on the type of photoresist and the first dimension.

[0045] In the step of bombarding the wafer with target ions (ion implantation), an ion implantation device is used to bombard the wafer with target ions (such as phosphorus, boron, etc.) at high speed to complete ion implantation. This step is used for doping the semiconductor material, thereby changing the electrical properties of certain regions of the wafer.

[0046] In semiconductor manufacturing, ion implantation is a process used to introduce specific types of impurity atoms into a silicon wafer (wafer), and these impurity atoms can change the electrical properties of the wafer.

[0047] Ion implantation of the wafer includes: separately using phosphorus ions and arsenic ions for implantation to serve as the source and drain regions for N-type doping, so that As N+ is surrounded by P N-; using boron ions for implantation to serve as the source and drain regions for P-type doping.

[0048] Phosphorus (P) is a common N-type dopant because it is an element in Group 5 of the periodic table and contains 5 outer electrons. Phosphorus doping adds free electrons (negative charge carriers) to silicon, thereby forming an N-type semiconductor region. When phosphorus ions are implanted, phosphorus atoms are implanted into the silicon crystal to form a relatively large area of N-type semiconductor. Since the concentration and energy of this doping are relatively low, it is called the N-region (weak N-type doping region), and its main function is to form a background N-type region.

[0049] Arsenic (As) is also an N-type dopant, also an element in Group 5, but its atomic radius is larger than that of phosphorus and its diffusion rate is slower, so it has a higher doping concentration and stronger N-type characteristics. Arsenic ions are usually used to form the source and drain regions, and due to the higher doping concentration, this part of the region is called the N+-region (strong N-type doping region).

[0050] During this process, the meaning of arsenic N+ being surrounded by phosphorus N- is that the N+ region formed by arsenic ions is located within the N- region. In this way, there is a larger N- region around the source and drain regions, which can help control the current flow, reduce the leakage current, and improve the device performance.

[0051] Boron (B) is a common P-type dopant. It is an element in Group 3 of the periodic table and contains 3 outer electrons. Boron doping creates holes (positive charge carriers) in silicon, thus forming a P-type semiconductor region.

[0052] In the source and drain regions of the P-type semiconductor, boron ions are implanted into the silicon wafer by ion implantation to form a P-type doped region. These regions correspond to the source and drain of the P-type transistor (PMOS). When implanting boron ions, it is usually set to low energy and high dose to ensure that boron atoms are located in a relatively shallow region and can effectively control the flow of holes.

[0053] During the N-type doping process, first a lower concentration of phosphorus ions is used to form the N- region, and then a higher concentration of arsenic ions is used to form the N+ region, which can ensure that the N+ region (strongly doped region) is located in the main current channel, while the peripheral N- region (weakly doped region) provides better electrical isolation and control.

[0054] For the P-type doped region, usually only one boron ion implantation with low energy and high dose is required to form the strongly P-type doped source and drain regions. The P-type doped regions are usually used for the source and drain of PMOS devices.

[0055] During the ion implantation process, the energy determines the depth of ion implantation, while the dose and rotation speed determine the doping concentration. For the N-type and P-type regions, by reasonably selecting the types, energies, and rotation speeds of different ions, the electrical properties of the source and drain regions can be precisely controlled.

[0056] After the ion implantation is completed, the wafer usually undergoes thermal annealing. By heating, the lattice damage caused during the ion implantation process is repaired, and the doped atoms are activated to enter the lattice positions. This step is crucial for ensuring the electrical performance of the device.

[0057] This process flow combines different ions (phosphorus, arsenic, boron) and regions with different doping concentrations (N+ region and N- region, P+ region) to form an efficient source and drain structure, which can provide good current control, low power consumption, and improve the stability of the device. In this way, the performance of semiconductor devices can be improved, while reducing key parameters such as leakage current and increasing the switching speed.

[0058] It can be understood that the energy of the target ion implantation determines the depth of the ions entering the wafer. The higher the energy, the deeper the ion implantation. This energy value is adjusted according to the type, thickness (first dimension) of the photoresist, and process requirements.

[0059] The rotation speed of the target ion implantation, which is the dose rate, represents the number of ions implanted per unit time and directly affects the doping concentration of the wafer. The determination of the rotation speed also depends on the bombardment resistance of the photoresist (determined by the first dimension and material) and the design requirements of the device.

[0060] Through the above steps, the photoresist is precisely processed on the wafer surface to form the required mask pattern, protecting part of the wafer area from ion implantation. The photoresist part after exposure and development will be removed, allowing ions to be precisely implanted into the specified area, thereby changing the electrical properties of these areas.

[0061] It can be understood that different types of photoresists have different chemical compositions and physical properties, especially the tolerance to ions during the ion implantation process. By selecting a suitable type of photoresist, it can be ensured that it will not be overly damaged or peeled off by the bombardment of high-speed ions during the ion implantation process. For example, certain types of photoresists have higher mechanical strength and radiation resistance, and can better resist the bombardment of ions.

[0062] The thickness of the photoresist, which is the first dimension, will directly affect its ability to resist ion bombardment. A photoresist with too thin a thickness is prone to cracking or peeling off during high-speed ion implantation, while a photoresist with a moderate thickness can provide an adequate physical barrier to resist the energy impact of ions. By reasonably selecting the thickness of the photoresist, most of the energy of the ions can be absorbed by the photoresist during implantation, reducing the damage to the resist layer structure and preventing the photoresist from peeling off due to excessive ion implantation energy.

[0063] The energy of the target ions needs to match the thickness of the photoresist. The energy of the target ions determines the depth of ion implantation. If the ion energy is too high, it may penetrate the photoresist and even cause excessive impact force, resulting in damage or peeling of the photoresist. On the contrary, too low energy may cause the ions not to reach the required depth. Therefore, it is necessary to adjust the energy of the ions according to the thickness (first dimension) of the photoresist so that it can reach the expected implantation depth without causing excessive damage to the photoresist.

[0064] The rotation speed of the target ions needs to match the tolerance of the photoresist. The rotation speed is the dose of implanted ions, which represents the number of ions bombarding the wafer per unit time. A higher rotation speed may generate a greater impact force on the photoresist surface, resulting in excessive damage to the photoresist. Therefore, it is necessary to reasonably adjust the rotation speed of the ions according to the type and thickness of the photoresist to ensure that while ensuring the implantation efficiency, the photoresist is prevented from peeling off due to high-dose ion implantation.

[0065] According to the wafer processing optimization method provided by the embodiments of the present invention, by reasonably adjusting the energy and rotation speed of the target ions and matching according to the type and thickness of the photoresist, it is avoided that the photoresist is broken or peeled off due to excessive ion bombardment, which enables the photoresist to remain stable during the ion implantation process, effectively protects the underlying wafer surface, ensures that the mask pattern in the lithography process is not damaged, and thus guarantees the smooth progress of the subsequent lithography process and ensures the stability of the manufacturing process and the product quality.

[0066] In some embodiments, determining the first dimension includes: determining the type of ion implantation process on the wafer and determining the target type of photoresist according to the type of ion implantation process; based on the target type of photoresist, the feature size to be processed, and the size of the exposure pattern, determining the first dimension.

[0067] In the lithography process, the first dimension refers to the thickness of the photoresist layer coated on the wafer. To ensure the accuracy of the lithography process and the successful transfer of the pattern, determining the photoresist thickness (i.e., the first dimension) is a key step.

[0068] First, it is necessary to clarify the type of ion implantation process that the wafer will undergo subsequently. Different ion implantation processes require photoresist layers with different thicknesses and characteristics as masks to prevent ion implantation in some areas. Common ion implantation processes include light doping and heavy doping, and the types of these processes determine the implantation energy and dose that the photoresist needs to withstand.

[0069] Furthermore, the target type of photoresist can be determined according to the type of ion implantation process. The ion implantation process determines the type of photoresist. For example, a heavy doping process may require a thicker photoresist to resist the bombardment of high-energy ions, while a light doping process may require a thinner photoresist. Selecting the appropriate type of photoresist ensures that the photoresist can effectively protect the wafer surface in the subsequent process steps.

[0070] The thickness of the photoresist is closely related to its chemical composition and physical properties. Different types of photoresists have different coating thickness ranges and application environments. For example, some photoresists may be more suitable for thinner coatings, while others are suitable for thicker coatings.

[0071] The feature size refers to the size of the microstructures (such as line width, gate, etc.) to be processed on the wafer. This size determines the aspect ratio required to maintain the integrity of the pattern during subsequent etching or implantation processes.

[0072] The thickness of the photoresist also needs to consider the complexity and size of the exposure pattern. Generally, larger patterns allow the use of thicker photoresists, while smaller and finer patterns require thinner photoresists to ensure accurate exposure and pattern transfer.

[0073] Taking the above factors into consideration, the first dimension of the photoresist, i.e., the optimal thickness of the photoresist, can be determined through experiments or empirical data.

[0074] In some embodiments, as Figure 2 shown, the energy of the target ions is determined by step 210, step 220, step 230, step 240, and step 250.

[0075] Step 210, determine the type of ion implantation process on the wafer, and determine the type of photoresist and the doping depth of the target species according to the type of ion implantation process.

[0076] Ion implantation processes can be divided into various types according to specific chip design requirements and different semiconductor materials. Different process types correspond to different doping requirements, such as doping depth, concentration, etc.

[0077] According to the selected ion implantation process type, select a suitable photoresist. Different types of photoresists have different tolerances during the ion implantation process. It is necessary to match a suitable photoresist according to the required doping depth and ion implantation conditions to ensure that it does not fall off abnormally during the implantation process.

[0078] According to the requirements of the ion implantation process, determine the depth to which the target ions need to be implanted into the wafer, i.e., the doping depth, which will directly affect the implantation energy of the ions because the energy determines the penetration depth of the ions in the material.

[0079] Step 220, based on the target type and the first dimension of the photoresist, determine the first energy of the target ion implantation.

[0080] The type and thickness of the photoresist will affect the penetration ability of the ions. A thicker photoresist can withstand higher energy implantation, while a thinner photoresist requires lower implantation energy. By considering the physical properties of the photoresist and its protective role during the ion implantation process, an ion implantation energy suitable for the photoresist is determined.

[0081] The first energy is based on the photoresist thickness and tolerance to ensure that the ions can penetrate and implant into the wafer without damaging the photoresist.

[0082] Step 230, based on the doping depth of the wafer, determine the second energy of the target ion implantation.

[0083] The doping depth of the wafer refers to the depth that the target ions need to reach when implanted into the wafer. This depth is determined by the design requirements, such as the thickness of the source and drain regions where ion implantation is required. The ions need to have sufficient energy to reach this depth.

[0084] According to the required doping depth, the second energy of ion implantation is calculated. This energy should ensure that the ions can penetrate the photoresist and reach the required depth in the wafer.

[0085] Step 240, based on the first energy and the second energy, determine the target energy range for the target ion implantation.

[0086] The first energy is determined based on the characteristics of the photoresist, mainly considering how to perform implantation without damaging the photoresist. The second energy is determined based on the doping depth to ensure that the ions can reach the target area of the wafer. By combining these two energy values, the target energy range is obtained, that is, the energy of ion implantation must be within this range, which will neither overly damage the photoresist nor fail to meet the requirements of the doping depth.

[0087] Step 250, determine the energy value of the target ion that is close to the lower limit of the target energy range.

[0088] Selecting the value close to the lower limit in the energy range can minimize the damage caused by ion bombardment to the photoresist while ensuring that the requirements of the doping depth can be met.

[0089] Finally, select the energy value close to the lower limit of the range as the implantation energy of the target ion, so that the ions can penetrate the photoresist and achieve the required implantation effect, while reducing the damage to the photoresist and ensuring the stability of subsequent processes.

[0090] In this embodiment, the type of the photoresist, the thickness, and the doping depth requirements of the wafer can be comprehensively considered to determine the appropriate target ion implantation energy. The energy of the target ion can not only ensure that the ions can be successfully implanted to the required depth, but also minimize the damage to the photoresist during implantation, thus ensuring the smooth progress of subsequent processes.

[0091] In some embodiments, the ion rotation speed of the target ion can be determined in the following manner.

[0092] First, the type of the ion implantation process on the wafer can be determined, and the target type of photoresist and the doping depth can be determined according to the type of the ion implantation process; based on the target type and the first dimension of the photoresist, determine the first rotation speed of the target ion implantation; based on the doping depth of the wafer, determine the second rotation speed of the target ion implantation.

[0093] On this basis, based on the first rotation speed and the second rotation speed, determine the target rotation speed range of the target ion implantation; determine the rotation speed of the target ion that is close to the lower limit of the target rotation speed range.

[0094] It is understandable that the type of ion implantation process on the wafer can be determined, and the type of photoresist and the doping depth of the target species can be determined according to the type of ion implantation process. The type of ion implantation process is selected according to the wafer design and process requirements. Different process types have different requirements for photoresist and ion implantation depth.

[0095] The selection of photoresist is based on the type of ion implantation process. Some photoresists have higher tolerance and can withstand higher rotation speeds and ion implantation intensities; while other photoresists are suitable for lower rotation speeds to avoid damage and peeling.

[0096] The doping depth refers to the depth to which ions need to be implanted into the wafer, which is usually determined by process requirements. The rotation speed will affect the uniformity and efficiency of ion implantation. Therefore, the doping depth is an important factor affecting the ion rotation speed.

[0097] The type and thickness of the photoresist will affect the bearing capacity of the photoresist during the ion bombardment process. Thicker photoresists can withstand higher rotation speeds, while thinner photoresists need to be controlled within a lower rotation speed range to prevent the colloidal layer from peeling off or being damaged.

[0098] By comprehensively considering the type and thickness of the photoresist, a suitable ion rotation speed, i.e., the first rotation speed, is determined. This rotation speed should ensure that the photoresist can stably cover the wafer surface during the ion bombardment process and will not cause damage or peeling of the photoresist due to excessive ion energy or rotation speed.

[0099] The doping depth determines the depth that the ions need to reach, and thus also affects the uniformity of ion implantation. Generally, a deeper doping depth requires a higher rotation speed to ensure the efficiency and depth distribution during the ion implantation process.

[0100] According to the required doping depth, the second rotation speed of the target ions is determined. This rotation speed should be high enough to ensure that the ions can be uniformly implanted into the wafer and reach the designed doping depth.

[0101] The first rotation speed considers the tolerance of the photoresist, while the second rotation speed is based on the requirements of the doping depth. These two rotation speeds determine the physical state and motion characteristics of the ions during the implantation process. Combining the two, a reasonable rotation speed range for the target ion implantation can be determined.

[0102] This range meets the requirements of neither damaging the photoresist nor achieving the designed doping depth. Usually, a reasonable rotation speed range is obtained by calculating the maximum tolerable rotation speed of the photoresist and the minimum rotation speed required for wafer doping.

[0103] On this basis, the value close to the lower limit of the target rotation speed range is determined as the rotation speed of the target ions. In order to reduce the damage and peeling of the photoresist, selecting the rotation speed value close to the lower limit within the rotation speed range helps to reduce the tearing or irregular peeling of the photoresist surface caused by high-speed ion bombardment, while ensuring the accuracy and effect of ion implantation.

[0104] Finally, the rotation speed of the target ions can be selected as a value close to the lower limit of the range, ensuring that the ions can reach the required doping depth on the wafer surface, while minimizing the damage to the photoresist to ensure the normal progress of subsequent processes.

[0105] In this embodiment, the rotation speed of the target ions can not only meet the process requirements of ion implantation, but also maximize the protection of the photoresist. The reasonable control of the rotation speed can not only ensure the stability of the photoresist, but also improve the uniformity and efficiency of ion implantation, ensuring the smooth progress of subsequent processing steps.

[0106] In some embodiments, before bombarding the wafer with the target ions with attached energy for ion implantation of the wafer, the wafer processing optimization method of the embodiments of the present invention further includes: after removing the photoresist with the developer, baking the wafer to harden the unexposed photoresist after being soaked in the developer; the baking temperature is higher than the soft baking temperature after coating the photoresist.

[0107] After the exposure is completed, the unexposed part of the photoresist on the wafer remains, while the exposed part of the photoresist is dissolved and removed in the developer. The developer usually has a certain degree of corrosiveness and will affect the photoresist surface. In particular, the unexposed photoresist may become softened due to soaking in the developer, affecting its subsequent stability.

[0108] After being soaked in the developer, the unexposed photoresist on the wafer may become relatively fragile. In order to enhance its impact resistance and tolerance, baking treatment can be performed again. Through baking, the unexposed photoresist can be further cured, enhancing its resistance to mechanical, chemical, and thermal shocks.

[0109] The soft baking after coating the photoresist is usually used to remove the solvent in the photoresist. The soft baking temperature is relatively low, usually around 90°C to 120°C, aiming to make the photoresist have sufficient fluidity to cover the entire wafer surface. While the baking temperature after development needs to be higher, usually 150°C to 180°C or even higher, which can accelerate the cross-linking reaction of the photoresist, making the photoresist more stable and not easily affected by ion bombardment and other subsequent processes.

[0110] High-temperature baking can promote the crosslinking reaction of the internal molecular structure in the photoresist, further enhancing the hardness and adhesion of the photoresist. The hardened photoresist can better resist the impact force during the ion implantation process and prevent the photoresist from peeling off or being damaged due to the high-speed bombardment of ions.

[0111] During the ion implantation process, high-speed target ions bombard the surface of the wafer, which can easily cause mechanical stress on the photoresist. If the photoresist is not sufficiently hardened, it may peel off due to ion impact, affecting the normal progress of subsequent processes. Therefore, high-temperature baking after development can reduce this problem and ensure the integrity of the photoresist in the ion implantation process.

[0112] By performing high-temperature baking after development, the unexposed photoresist is hardened, enhancing its bonding force with the wafer surface and its resistance to ion bombardment, reducing the risk of photoresist peeling off, and thus ensuring the stability of the ion implantation and subsequent processes.

[0113] In some embodiments, determining the second dimension of the wafer edge and using edge exposure of the wafer to expose and remove all the photoresist within a second dimension range around the wafer edge includes: determining the second dimension of the wafer edge, forming an annular exposure band in the wafer edge region, the width of the annular exposure band being the second dimension; setting a mask annular band with a target width inside the annular exposure band, and using the edge exposure of the wafer to expose and remove all the photoresist within a second dimension range around the wafer edge except the mask annular band.

[0114] The second dimension refers to the width of the photoresist that needs to be removed in the wafer edge region. For example, if a circle of photoresist on the wafer edge needs to be removed, then this width is the second dimension. By defining the second dimension, the range of the photoresist to be removed can be precisely controlled, avoiding removing too much or too little photoresist.

[0115] An annular exposure band will be formed in the wafer edge region, that is, the photoresist in the wafer edge region will be exposed in this band-shaped region. The width of the exposure band is the previously determined second dimension. This band-shaped region forms a closed loop around the entire edge of the wafer, thus ensuring the consistency of the removal of the photoresist at the wafer edge.

[0116] The function of the mask annular band is to place a "mask" inside the annular exposure band, and its width is the preset target width.

[0117] During the edge exposure of the wafer, in all the annular exposure bands, except for the area covered by the mask annular band, the photoresist will be exposed to light and thus dissolved and removed in the subsequent development step. The setting of the mask annular band enables only a circle of photoresist at the wafer edge to be exposed and thus removed through development. The photoresist inside the mask annular band will not be dissolved by the developer because it is not exposed, thus achieving precise control of the removal range.

[0118] This design ensures that the photoresist inside the mask ring belt is not exposed, thereby retaining this part of the photoresist to form a photoresist ring, strengthening the overall adhesion ability of the photoresist relative to the wafer. The photoresist on the mask ring belt can be exposed and removed again during the subsequent photolithography process after the ion implantation process is completed.

[0119] The wafer processing optimization device provided by the present invention will be described below. The wafer processing optimization device described below can be correspondingly referred to the wafer processing optimization method described above.

[0120] As Figure 3 shown, the wafer processing optimization method of the embodiment of the present invention mainly includes a first processing module 310, a second processing module 320, an exposure module 330, a baking module 340, a cleaning module 350, and an ion implantation module 360.

[0121] The first processing module 310 is used to determine a first dimension, coat a photoresist of the first dimension on the wafer and perform soft baking to remove a part of the solvent in the photoresist, cure the photoresist and cool it; The second processing module 320 is used to determine a second dimension at the edge of the wafer, and expose all the photoresist in a second dimension range around the edge of the wafer by edge exposure of the wafer to remove it; The exposure module 330 is used to determine that the wafer with photoresist attached enters the exposure machine to perform an exposure reaction on the light-transmitting part; The baking module 340 is used to determine baking the wafer to eliminate the standing wave effect during the exposure process and improve the photoresist morphology; The cleaning module 350 is used to remove the photoresist on the light-transmitting part of the wafer through the developer and retain the photoresist on the non-light-transmitting part; The ion implantation module 360 is used to bombard the wafer with target ions with attached energy to perform ion implantation on the wafer; the energy and rotation speed of the target ions are determined based on the type of photoresist and the first dimension.

[0122] According to the wafer processing optimization device provided by the embodiment of the present invention, by reasonably adjusting the energy and rotation speed of the target ions and matching according to the type and thickness of the photoresist, it is avoided that the photoresist is broken or peeled off due to excessive ion bombardment, which makes the photoresist remain stable during the ion implantation process, effectively protects the underlying wafer surface, ensures that the mask pattern in the photolithography process is not damaged, and thus ensures that the subsequent photolithography process can proceed smoothly, ensuring the stability of the manufacturing process and the product quality.

[0123] The embodiment of the present invention also provides a semiconductor device, including a high-voltage power circuit. The high semiconductor device is manufactured by using the BCD process, and the high-voltage power circuit is processed by using the wafer processing optimization method as described above.

[0124] Figure 4 Illustrates a schematic diagram of the physical structure of an electronic device, as Figure 4 shown. The electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communication bus 440. Among them, the processor 410, the communications interface 420, and the memory 430 complete mutual communication through the communication bus 440. The processor 410 can call the logical instructions in the memory 430 to execute a wafer processing optimization method, which includes: determining a first dimension, coating a photoresist of the first dimension on the wafer and soft baking to remove a solvent portion in the photoresist, curing the photoresist and cooling; determining a second dimension at the edge of the wafer, and using edge exposure of the wafer to expose all the photoresist in a second dimension range around the edge of the wafer to remove it; determining that the wafer with the attached photoresist enters an exposure machine to perform an exposure reaction on the light-transmitting portion; determining to bake the wafer to eliminate the standing wave effect during exposure and improve the photoresist topography; clearing the photoresist on the light-transmitting portion of the wafer with a developer, and retaining the photoresist on the non-light-transmitting portion; bombarding the wafer with target ions with attached energy to perform ion implantation on the wafer; the energy and rotation speed of the target ions are determined based on the type of the photoresist and the first dimension.

[0125] In addition, when the logical instructions in the above-mentioned memory 430 can be implemented in the form of software functional units and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc that can store program codes.

[0126] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the wafer processing optimization method provided by each of the above methods. The method includes: determining a first dimension, coating a photoresist of the first dimension on the wafer and performing soft baking to remove a solvent portion in the photoresist, curing the photoresist and cooling it; determining a second dimension at the edge of the wafer, and using edge exposure of the wafer to expose all of the photoresist within a second dimension range around the edge of the wafer to remove it; determining that the wafer with the attached photoresist enters an exposure machine to perform an exposure reaction on the light-transmitting portion; determining to bake the wafer to eliminate the standing wave effect during the exposure process and improve the photoresist topography; removing the photoresist on the light-transmitting portion of the wafer through a developer, and retaining the photoresist on the non-light-transmitting portion; bombarding the wafer with target ions with attached energy to perform ion implantation on the wafer; the energy and rotation speed of the target ions are determined based on the type of the photoresist and the first dimension.

[0127] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it realizes the wafer processing optimization method provided by each of the above methods. The method includes: determining a first dimension, coating a photoresist of the first dimension on the wafer and performing soft baking to remove a solvent portion in the photoresist, curing the photoresist and cooling it; determining a second dimension at the edge of the wafer, and using edge exposure of the wafer to expose all of the photoresist within a second dimension range around the edge of the wafer to remove it; determining that the wafer with the attached photoresist enters an exposure machine to perform an exposure reaction on the light-transmitting portion; determining to bake the wafer to eliminate the standing wave effect during the exposure process and improve the photoresist topography; removing the photoresist on the light-transmitting portion of the wafer through a developer, and retaining the photoresist on the non-light-transmitting portion; bombarding the wafer with target ions with attached energy to perform ion implantation on the wafer; the energy and rotation speed of the target ions are determined based on the type of the photoresist and the first dimension.

[0128] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative labor.

[0129] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wafer processing optimization method, characterized in that, Including: Determine a first dimension, coat a photoresist of the first dimension on the wafer and perform soft baking to remove a solvent portion in the photoresist, cure the photoresist and cool it; Determine a second dimension at the wafer edge, and use edge exposure of the wafer to expose and remove all the photoresist within a second dimension range around the wafer edge; Determine that the wafer with the photoresist attached enters an exposure machine to perform an exposure reaction on the light-transmitting portion; Determine to bake the wafer to eliminate the standing wave effect during exposure and improve the photoresist topography; Remove the photoresist in the light-transmitting portion of the wafer through a developer, and retain the photoresist in the non-light-transmitting portion; Bombard the wafer with target ions with attached energy to perform ion implantation on the wafer; The energy and rotation speed of the target ions are determined based on the type of photoresist and the first dimension.

2. The wafer processing optimization method according to claim 1, wherein The determining the first dimension includes: Determine the type of ion implantation process on the wafer, and determine the target type of photoresist according to the type of ion implantation process; Based on the target type of photoresist, the feature size to be processed, and the size of the exposure pattern, determine the first dimension.

3. The wafer processing optimization method according to claim 1, wherein The energy of the target ions is determined by the following method: Determine the type of ion implantation process on the wafer, and determine the target type of photoresist and the doping depth according to the type of ion implantation process; Based on the target type of photoresist and the first dimension, determine the first energy of the target ion implantation; Based on the doping depth of the wafer, determine the second energy of the target ion implantation; Based on the first energy and the second energy, determine the target energy range of the target ion implantation; Determine the value close to the lower limit of the interval of the target energy as the energy of the target ions.

4. The wafer processing optimization method according to claim 1, wherein The ion rotation speed of the target ions is determined by the following method: Determine the type of ion implantation process on the wafer, and determine the target type of photoresist and the doping depth according to the type of ion implantation process; Based on the target type of photoresist and the first dimension, determine the first rotation speed of the target ion implantation; Based on the doping depth of the wafer, determine the second rotation speed of the target ion implantation; Based on the first rotation speed and the second rotation speed, determine the target rotation speed range of the target ion implantation; Determine the value close to the lower limit of the interval of the target rotation speed as the rotation speed of the target ions.

5. The wafer processing optimization method according to claim 1, characterized in that, Before the bombarding the wafer with target ions with attached energy to perform ion implantation on the wafer, the method further includes: After removing the photoresist through the developer, bake the wafer so that the unexposed photoresist hardens after being soaked in the developer; the baking temperature is higher than the soft baking temperature after coating the photoresist.

6. The wafer processing optimization method according to claim 1, characterized in that, The determining the second dimension at the wafer edge, and using edge exposure of the wafer to expose and remove all the photoresist within the second dimension range around the wafer edge includes: Determine the second dimension at the wafer edge, form an annular exposure band in the wafer edge region, and the width of the annular exposure band is the second dimension; Set a mask annular band with a target width inside the annular exposure band, and use edge exposure of the wafer to expose and remove all the photoresist within the second dimension range around the wafer edge except the mask annular band.

7. The wafer processing optimization method according to claim 1, characterized in that The performing ion implantation on the wafer includes: Phosphorus ions and arsenic ions are respectively implanted as the source and drain regions for N-type doping, so that arsenic N+ is surrounded by phosphorus N-; boron ions are implanted as the source and drain regions for P-type doping.

8. A wafer processing optimization device applicable to the wafer processing optimization method according to any one of claims 1 to 7, characterized in that a first processing module, configured to determine a first dimension, coat a photoresist of the first dimension on the wafer and perform soft baking to remove a solvent part in the photoresist, cure the photoresist and cool it; a second processing module, configured to determine a second dimension at the edge of the wafer, and expose all the photoresist in a second dimension range around the edge of the wafer by using edge exposure of the wafer to remove it; an exposure module, configured to determine that the wafer with the photoresist attached enters an exposure machine to perform an exposure reaction on the light-transmitting part; a baking module, configured to determine that the wafer is baked to eliminate the standing wave effect during exposure and improve the photoresist topography; a cleaning module, configured to remove the photoresist in the light-transmitting part of the wafer through a developer, and retain the photoresist in the non-light-transmitting part; an ion implantation module, configured to bombard the wafer with target ions with attached energy to perform ion implantation on the wafer; the energy and rotation speed of the target ions are determined based on the type of the photoresist and the first dimension.

9. A semiconductor device, characterized in that, It includes a high-voltage power circuit. The high semiconductor device is manufactured by using the BCD process, and the high-voltage power circuit is processed by using the wafer processing optimization method according to any one of claims 1 to 7.

10. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the wafer processing optimization method according to any one of claims 1 to 7.

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