Ad converter and semiconductor device

Abstract

The invention provides a potential-time conversion type AD converter which does not use a constant current circuit with a complex component structure, has a simple structure, and can obtain stable operation. An AD converter (1) that converts an input potential (Vin) to a digital value is provided with: a capacitance element (24) that accumulates charges at a preset potential difference (a potential difference between a high-potential-side reference voltage (Vs) and a ground terminal); a discharge circuit (a second switching element (22), a discharge element (23)) that discharges the charge charged into the capacitor element (24) at a discharge current (Ids) determined by the input potential (Vin); a timer (26) that measures the discharge time (t) until the charge of the capacitor element (24) reaches a predetermined charge amount by the discharge of the discharge circuit (discharge element (23)); and a time-digital value conversion circuit (30) that converts the discharge time (t) measured by the timer (26) into a digital value.

Description

Technical Field

[0001] The present invention relates to a potential-time conversion type AD converter (analog-to-digital converter) that converts an analog input potential into a time to obtain a digital value. Background Art

[0002] As an AD converter, a potential-time conversion type AD converter (also called a Wilkinson type) is known (for example, refer to Patent Document 1). The potential-time conversion type AD converter has a capacitor charged (sampled) with an analog input potential and a TDC circuit (time measurement circuit: Time to Digital Converter). After cutting off (holding) the capacitor charged with the analog input potential from the input, the potential-time conversion type AD converter releases the charge accumulated in the capacitor with a constant current, and measures the time until the charge becomes 0 (becomes 0V) by the TDC circuit to obtain a digital value.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Laid-Open No. 62-109434 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] In the prior art, since it is necessary to release the charge charged in the capacitor with a constant current, a constant current circuit for releasing with a constant current is required. Generally, for a constant current circuit, there are problems that the component structure is complex and the design is also complicated. Although it is also possible to consider using a constant current diode that utilizes the breakdown phenomenon when a reverse voltage is applied to a diode, the constant current diode does not become a constant current circuit at a voltage of 1V or less.

[0008] The present invention has been made in view of this problem, and an object thereof is to provide a potential-time conversion type AD converter that does not use a constant current circuit with a complex component structure, has a simple structure, and can obtain a stable operation.

[0009] Means for Solving the Problems

[0010] In order to achieve the above object, the AD converter of the present invention is configured as follows.

[0011] The AD converter of the present invention converts an input potential into a digital value, and is characterized in that the AD converter includes: a capacitive element that accumulates charge with a preset potential difference; a discharge circuit that discharges the charge accumulated in the capacitive element with a discharge current determined by the input potential; a timer that measures a discharge time until the charge accumulated in the capacitive element reaches a specified charge amount through discharge by the discharge circuit; and a time-to-digital value conversion circuit that converts the discharge time measured by the timer into the digital value.

[0012] Advantages of the Invention

[0013] Since the AD converter of the present invention discharges with a discharge current Ids determined by the input potential Vin, it is possible to provide such a potential-time conversion type AD converter 1: which does not use a constant current circuit with a complicated component structure, has a simple structure, and can achieve stable operation. Description of the Drawings

[0014] Figure 1 is a block diagram showing the structure of an embodiment of the AD converter of the present invention.

[0015] Figure 2 is for explaining Figure 1 the operation of the AD converter shown.

[0016] Figure 3 is a diagram schematically showing the circuit structure during discharge.

[0017] Figure 4 is a diagram showing Figure 1 the correspondence between the discharge time and the input potential converted by the potential-time conversion circuit shown.

[0018] Figure 5 is a block diagram showing the structure of another embodiment of the AD converter of the present invention.

[0019] Figure 6 is a diagram showing Figure 5 the correspondence between the discharge time and the input potential converted by the potential-time conversion circuit shown.

[0020] Figure 7 is a block diagram showing the structure of another embodiment of the AD converter of the present invention. Detailed Embodiments

[0021] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

[0022] The AD converter 1 of the present embodiment is an analog-to-digital converter that converts an analog input potential into a digital value and outputs it. Refer to Figure 1, the AD converter 1 includes a voltage dividing circuit 10, a potential-time conversion circuit 20, and a time-digital value conversion circuit 30. The AD converter 1 is configured as a semiconductor device built into a digital switching power supply IC (semiconductor integrated circuit) or the like.

[0023] The voltage dividing circuit 10 is a series circuit in which resistors Ra and Rb are connected in series between the analog input potential and the ground terminal as the low-potential side reference voltage. The voltage dividing circuit 10 divides the analog input potential using the resistors Ra and Rb, and inputs the divided voltage as the input potential Vin to the potential-time conversion circuit 20. The voltage dividing circuit 10 is provided to converge the input potential Vin within the input range of the potential-time conversion circuit 20. When the analog input potential is within the input range of the potential-time conversion circuit 20, the voltage dividing circuit 10 can be omitted.

[0024] The potential-time conversion circuit 20 includes a first switching element 21, a second switching element 22, a discharging element 23, a capacitive element 24, an amplifier 25, and a timer 26.

[0025] The discharging element 23, the second switching element 22, and the first switching element 21 are connected in series between the high-potential side reference voltage Vs and the ground terminal. If the connection point of the second switching element 22 and the first switching element 21 is used as the node N, the capacitive element 24 is formed of a capacitor, for example, and is connected between the high-potential side reference voltage Vs and the node N. The input terminal of the amplifier 25 is connected to the node N, and the output terminal is connected to the timer 26.

[0026] The first switching element 21 is a switch that opens and closes the connection between the node N and the ground terminal, and is formed of an N-type MOS transistor, for example. The drain of the first switching element 21 is connected to the node N, the source is connected to the ground terminal, and the on / off is controlled by the charging signal charge (charging) input to the gate.

[0027] The first switching element 21 is a charging circuit that charges (accumulates) the capacitive element 24. The first switching element 21 becomes conductive when the charging signal charge is at a high level, and charges corresponding to the potential difference between the high-potential side reference voltage Vs and the ground terminal are accumulated in the capacitive element 24. The first switching element 21 becomes non-conductive when the charging signal charge is at a low level. After charging the capacitive element 24, by making the first switching element 21 non-conductive, the capacitive element 24 maintains the charged state.

[0028] The second switching element 22 is a switch that opens and closes the connection between the discharge element 23 and the node N, and is formed of, for example, a P-type MOS transistor. The drain of the second switching element 22 is connected to the node N, the source is connected to the discharge element 23, and the on / off state is controlled by the start signal start (start) input to the gate.

[0029] The discharge element 23 is formed of a P-type MOS transistor. The drain of the discharge element 23 is connected to the source of the second switching element 22, the source is connected to the high-potential-side reference voltage Vs, and the input potential Vin is input to the gate. The input range of the potential-time conversion circuit 20 is set to a range in which the discharge element 23 operates in the saturation region.

[0030] The second switching element 22 and the discharge element 23 are a discharge circuit that discharges the charge accumulated in the capacitor element 24. The second switching element 22 becomes conductive when the start signal start is at a low level, and the charge accumulated in the capacitor element 24 is discharged as the drain-source current of the discharge element 23, that is, the discharge current Ids. For the second switching element 22, a switching element is used such that the maximum value of the current flowing in the conductive state is sufficiently larger than the discharge current Ids and does not affect the characteristics of the discharge element 23 (the determined discharge current Ids).

[0031] The amplifier 25 is a discharge determination circuit that determines that the charge accumulated in the capacitor element 24 has been discharged to a specified charge amount. When the charge of the capacitor element 24 is discharged to the specified charge amount, the amplifier 25 outputs a stop signal stop (stop) to the timer 26. The amplifier 25 is formed of, for example, a CMOS inverter circuit. When the potential V of the node N that has risen due to discharge N reaches the threshold potential Vth of the amplifier 25 a the amplifier 25 inputs the stop signal stop to the timer 26.

[0032] The timer 26 measures the discharge time t from the input of the start signal start (the transition from high level to low level) to the input of the stop signal stop and outputs it. The timer 26 is a general digital timer and has a function of resetting the count, a function of starting the count, and a function of stopping the count. Regarding the clock that drives the timer 26, it can be supplied from the outside or generated inside the timer 26.

[0033] In addition, the timer 26 can be either synchronous or asynchronous with respect to the clock.

[0034] The time digital value conversion circuit 30 converts the discharge time t input from the potential-time conversion circuit 20 (timer 26) into a digital value and outputs it. The time digital value conversion circuit 30 converts the input discharge time t into a digital value, for example, using a calculation formula or a conversion table made according to the voltage division ratio of the voltage division circuit 10 or the characteristics of the discharge element 23, etc.

[0035] Next, with reference to Figure 2 the conversion operation based on the AD converter 1 will be described in detail.

[0036] First, as a preparatory operation before conversion, the AD converter 1 performs the following (1) to (3).

[0037] (1) By the transition of the charge signal charge to the high level, the first switching element 21 becomes conductive. By the first switching element 21 becoming conductive, thus, with respect to the capacitor element 24, charges move as shown by the arrow in (a) of Figure 2 and the capacitor element 24 is charged with the potential difference between the high-potential side reference voltage Vs and the ground terminal. In addition, in (1), the start signal start is at the high level and the second switching element 22 is in the off state.

[0038] (2) After a predetermined time, by the transition of the charge signal charge to the low level, the first switching element 21 becomes non-conductive. The capacitor element 24 becomes a state in which charges corresponding to the potential difference between the high-potential side reference voltage Vs and the ground terminal are stored. In (1) and (2), the potential V of the node N N is the same potential as the ground terminal and is lower than the threshold potential Vth of the amplifier 25 a low.

[0039] (3) By the input of the reset signal reset (reset), the timer 26 resets the count to 0.

[0040] Next, as the conversion operation, the AD converter 1 performs the following (4) to (8).

[0041] (4) By the transition of the start signal start to the low level, the second switching element 22 becomes conductive and the timer 26 starts counting.

[0042] (5) By the second switching element 22 becoming conductive, thus, charges move as shown by the arrow in (b) of Figure 2 and the charges stored in the capacitor element 24 are discharged at a discharge current Ids determined by the input potential Vin input to the gate of the discharge element 23.

[0043] (6) Due to the discharge at the discharge current Ids, the potential V of the node N Nrises. When the potential V of node N N rises and reaches the threshold potential Vth of the amplifier 25 a the amplifier 25 inputs a stop signal stop to the timer 26.

[0044] (7) By the input of the stop signal stop, the timer 26 measures the discharge time t from the input of the start signal start (the transition from high level to low level) to the input of the stop signal stop and inputs it to the time-to-digital value conversion circuit 30.

[0045] (8) The time-to-digital value conversion circuit 30 converts the discharge time t output from the potential-time conversion circuit 20 (timer 26) into a digital value.

[0046] Figure 3 Schematically shows the circuit structure during discharge. The second switching element 22 that does not affect the characteristics of the discharge element 23 is omitted. The potential V of node N N The discharge time t from the low level to the switching to the high level is determined by the charge amount Q accumulated in the capacitor element 24 and the discharge current Ids flowing through the discharge element 23. Here, the charge amount Q is determined by the capacitance C of the capacitor element 24 and the potential difference between the high-potential side reference voltage Vs and the ground terminal. And when the maximum value of the current flowing through the second switching element 22 that is turned on according to the start signal start is sufficiently larger than the discharge current Ids, the discharge current Ids is determined by the characteristics of the discharge element 23.

[0047] When the threshold potential of the discharge element 23 is set to Vth b and the drain-source voltage Vds and the gate-source voltage Vgs in the discharge element 23 are in the following relationship of Equation (1), the discharge element 23 operates in the saturation region.

[0048] [Equation 1]

[0049] (-Vds) > (-Vgs) - (-Vth b )---(1)

[0050] where, (-Vgs) > (-Vth b )

[0051] In the saturation region, the discharge current Ids flowing through the discharge element 23 is expressed by the following Equation (2). β is a coefficient determined by the characteristics (gate oxide film capacitance per unit area, hole mobility) of the discharge element 23 (P-type MOS transistor). W / L is a coefficient determined by the structure of the discharge element 23 (P-type MOS transistor).

[0052] [Equation 2]

[0053]

[0054] According to Equation (1), it can be seen that if the discharge element 23 is in the saturation region, the discharge current Ids is determined by Vgs regardless of Vds.

[0055] Vgs is (the reference voltage Vs on the high-potential side - the input potential Vin). That is, if the discharge element 23 is in the saturation region, the discharge current Ids is determined by the input potential Vin input to the gate of the discharge element 23.

[0056] Here, when Vin is in the range of 0 (V) to (-Vth b )(V) (that is, when (-Vgs) is in the range of Vs (V) to Vs - (-Vth b )(V)), during the period when the potential V of the node N N is in the range of 0 (V) to (-Vth b )(V) (that is, during the period when (-Vds) is in the range of Vs (V) to Vs - (-Vth b )(V)), the relationship of the above Equation (1) holds, and the discharge element 23 operates in the saturation region.

[0057] The above Equation (2) does not include Vds. Therefore, by setting the input range of the potential-time conversion circuit 20 within 0 (V) to (-Vth b )(V) and setting the threshold potential Vth a of the amplifier 25 to be below the threshold potential (-Vth b ) of the discharge element 23, thus, during the period when the potential V of the node N N rises from 0 (V) and reaches the threshold potential Vth a of the amplifier 25, the discharge element 23 can be regarded as a constant current source whose discharge current Ids is determined by the input potential Vin.

[0058] For example, in the case where (-Vth b ) = Vth a = 0.6 V and β (W / L) = 2, according to the above Equation (2), the discharge current Ids is calculated as

[0059] (-Ids) = {(1.2 - Vin) - 0.6} 2

[0060] obtained.

[0061] Also, when the capacitance C of the capacitor element 24 is 1 (F), the potential of the ground terminal is 0 (V), and the high-potential side reference voltage Vs is 1.2 (V), the electric charge amount Q stored in the capacitor element 24 is 1.2 (C). When the electric charge amount Q accumulated in the capacitor element 24 is discharged to a specified electric charge amount, that is, 0.6 (C), the potential V of the node N N rises from 0 (V) and reaches the threshold potential Vth of the amplifier 25 a = 0.6V. Therefore, by discharging, the potential V N reaches Vth from 0 (V) a The discharge time t for this is as follows:

[0062] t = 0.6 / (-Ids) = 0.6 / (0.6 - Vin) 2 , which is determined by the input potential Vin

[0063] Figure 4 shows the correspondence relationship of the discharge time t with respect to the input potential Vin. Referring to Figure 4 it can be seen that by setting the input range within 0 (V) to (-Vth b = 0.6) (V), the potential-time conversion circuit 20 can convert the input potential Vin into the discharge time t

[0064] Regarding the AD converter 1, the following (x) to (z) need to be noted

[0065] (x) The input range cannot be set to Vth b or more. If the input potential Vin is Vth b or more, the operating characteristics of the discharge element 23 (MOS transistor) change

[0066] (y) The input range cannot be set near Vth b . Near Vth b , the discharge time t increases quadratically with respect to the input potential Vin, so it is not practical

[0067] (z) The input voltage range (dynamic range) cannot be made large. Also, by increasing the voltage division ratio of the voltage division circuit 10, the input range (dynamic range) can be increased. However, near the input potential Vin of 0 (V), the change amount of the discharge time t with respect to the input potential Vin becomes small, resulting in a decrease in resolution

[0068] In the Figure 5 shown AD converter 1a, the input range (dynamic range) is extended by using three potential-time conversion circuits 200, 201, and 202

[0069] The voltage dividing circuit 10a of the AD converter 1a is a series circuit in which resistors Rc, Rd, and Re are connected in series between the analog input potential and the ground terminal as the low-potential side reference voltage. The voltage dividing circuit 10a inputs the analog input potential as the input potential Vin0 to the potential-time conversion circuit 200. The voltage dividing circuit 10a inputs the potential obtained by dividing the analog input potential using resistors Rc, Rd, and Re as the input potential Vin1 to the potential-time conversion circuit 201. The voltage dividing circuit 10a inputs the potential obtained by dividing the analog input potential using resistors Rc, Rd, and Re as the input potential Vin1 to the potential-time conversion circuit 201.

[0070] Based on the discharge times t0, t1, and t2 respectively input from the potential-time conversion circuits 200, 201, and 202, the time-digital value conversion circuit 30a of the AD converter 1a selects any one of the discharge times t0, t1, and t2, converts it into a digital value, and outputs it.

[0071] Refer to Figure 6 An example of the selection method for the time-digital value conversion circuit 30a to select the discharge times t0, t1, and t2 will be described.

[0072] Figure 6 Among them, A represents the relationship between the input potential Vin0 and the discharge time t0 in the potential-time conversion circuit 200, B represents the relationship between the input potential Vin0 and the discharge time t1 in the potential-time conversion circuit 201, and C represents the relationship between the input potential Vin0 and the discharge time t2 in the potential-time conversion circuit 202.

[0073] When the discharge time t0 input from the potential-time conversion circuit 200 is 32 or less, the time-digital value conversion circuit 30a converts the discharge time t0 into a digital value. Figure 6 In the example shown, within the range where the input potential Vin0 is 0 (V) to 0.5 (V), AD conversion using the potential-time conversion circuit 200 is performed.

[0074] When the discharge time t0 input from the potential-time conversion circuit 200 exceeds 32 and the discharge time t1 input from the potential-time conversion circuit 201 is 32 or less, the time-digital value conversion circuit 30a converts the discharge time t1 into a digital value. In Figure 6 In the example shown, within the range where the input potential Vin0 exceeds 0.5 (V) and is 0.87 (V) or less, AD conversion using the potential-time conversion circuit 201 is performed.

[0075] When both the discharge times t0 and t1 input from the potential-time conversion circuits 200 and 201 exceed 32, the time digital value conversion circuit 30a converts the discharge time t2 input from the potential-time conversion circuit 202 into a digital value. In Figure 6 In the example shown, within the range where the input potential Vin0 exceeds 0.87 (V), AD conversion using the potential-time conversion circuit 202 is performed.

[0076] In this way, by using multiple potential-time conversion circuits 20 to respectively input input potentials Vin with different voltage division ratios, the input range (dynamic range) can be expanded. The number of potential-time conversion circuits 20 is not particularly limited and can be appropriately set according to the desired input range.

[0077] Figure 7 It is an AD converter 1b that uses a discharge element 23b composed of an N-type MOS transistor. The AD converter 1b includes a voltage division circuit 10b, a potential-time conversion circuit 20b, and a time digital value conversion circuit 30.

[0078] The voltage division circuit 10b is a series circuit in which a resistor Rf and a resistor Rg are connected in series between the second reference voltage Vss on the high potential side and the analog input potential. The voltage division circuit 10b divides the analog input potential using the resistor Rf and the resistor Rg, and inputs the divided voltage as the input potential Vin to the potential-time conversion circuit 20b. The voltage division circuit 10b is provided to converge the input potential Vin within the input range of the potential-time conversion circuit 20b. When the analog input potential is within the input range of the potential-time conversion circuit 20b, the voltage division circuit 10b can be omitted.

[0079] The potential-time conversion circuit 20b includes a first switching element 21b, a second switching element 22b, a discharge element 23b, a capacitor element 24, an amplifier 25, and a timer 26.

[0080] The first switching element 21b, the second switching element 22b, and the discharge element 23b are connected in series between the high potential side reference voltage Vs and the ground terminal. If the connection point between the first switching element 21b and the second switching element 22b is taken as the node N, the capacitor element 24 is formed by a capacitor, for example, and is connected between the node N and the ground terminal. The input terminal of the amplifier 25 is connected to the node N, and the output terminal is connected to the timer 26.

[0081] The first switching element 21b is a switch that opens and closes the connection between the high potential side reference voltage Vs and the node N, and is composed of a P-type MOS transistor, for example. Regarding the first switching element 21, its drain is connected to the high potential side reference voltage Vs, its source is connected to the node N, and its on / off is controlled by the charging signal charge input to the gate.

[0082] The first switching element 21b is a charging circuit that charges (accumulates) the charge in the capacitor element 24. The first switching element 21b becomes conductive when the charging signal charge is at a low level, and the charge corresponding to the potential difference between the high-potential side reference voltage Vs and the ground terminal is accumulated in the capacitor element 24. The first switching element 21b becomes non-conductive when the charging signal charge is at a high level. After charging the capacitor element 24, by making the first switching element 21b non-conductive, the capacitor element 24 maintains the charged state.

[0083] The second switching element 22b is a switch that opens and closes the connection between the discharge element 23b and the node N, and is formed of, for example, an N-type MOS transistor. Regarding the second switching element 22b, its drain is connected to the node N, its source is connected to the discharge element 23b, and the on / off state is controlled by the start signal start input to the gate.

[0084] The discharge element 23b is formed of an N-type MOS transistor. Regarding the discharge element 23b, its drain is connected to the source of the second switching element 22, its source is connected to the ground terminal, and the input potential Vin is input to the gate. The input range of the potential-time conversion circuit 20b is set to a range in which the discharge element 23b operates in the saturation region.

[0085] The second switching element 22b and the discharge element 23b are a discharge circuit that discharges (releases) the charge accumulated in the capacitor element 24. The second switching element 22b becomes conductive when the start signal start is at a high level, and the charge accumulated in the capacitor element 24 is discharged at the discharge current Ids determined by the discharge element 23b. For the second switching element 22b, a switching element is used such that the maximum value of the current flowing in the conductive state is sufficiently larger than the discharge current Ids and does not affect the characteristics (the determined discharge current Ids) of the discharge element 23b.

[0086] The AD converter 1b causes the discharge element 23b formed of an N-type MOS transistor to operate in the saturation region and performs discharge at the discharge current Ids determined according to the input potential Vin. That is, even when using an N-type MOS transistor, AD conversion can be performed with the same operation as the AD converter 1.

[0087] As described above, the present embodiment is an AD converter 1 that converts an input potential Vin into a digital value, and includes: a capacitor element 24 that stores charges with a preset potential difference (the potential difference between the high-potential-side reference voltage Vs and the ground terminal); a discharge circuit (second switching element 22, discharge element 23) that discharges the charges charged in the capacitor element 24 with a discharge current Ids determined by the input potential Vin; a timer 26 that measures a discharge time t until the charges of the capacitor element 24 reach a specified charge amount through the discharge of the discharge circuit (discharge element 23); and a time-to-digital value conversion circuit 30 that converts the discharge time t measured by the timer 26 into a digital value.

[0088] According to this structure, since the discharge is performed with the discharge current Ids determined by the input potential Vin, it is possible to provide an AD converter 1 that does not use a constant-current circuit with a complicated component structure, has a simple structure, and can achieve stable operation.

[0089] Furthermore, in the present embodiment, an amplifier 25 is provided, and the amplifier 25 outputs a stop signal stop notifying that the specified charge amount has been reached based on the potential V N of the node N connecting the capacitor element 24 and the discharge circuit, and the timer 26 measures the discharge time t as the time from the input of the start signal start instructing the start of discharge to the discharge circuit (second switching element 22) to the input of the stop signal stop.

[0090] According to this structure, the AD converter 1 can detect that the capacitor element 24 has reached the specified charge amount with a simple structure.

[0091] Furthermore, in the present embodiment, the discharge circuit operates the MOS transistor (discharge element 23) whose gate is input with the input potential Vin in the saturation region, and discharges the charges stored in the capacitor element 24 with the drain-source current determined by the input potential Vin as the discharge current Ids.

[0092] With this structure, the AD converter 1 can generate the discharge current Ids determined by the input potential Vin by utilizing the characteristics of the MOS transistor with a clear operating principle.

[0093] Moreover, in the present embodiment, the input potential Vin divided by the voltage dividing circuit 10 is input to the gate of the MOS transistor (discharge element 23).

[0094] With this structure, the AD converter 1 can adjust the input potential Vin for the MOS transistor (discharge element 23) to operate in the saturation region.

[0095] Furthermore, in the present embodiment, there are provided a plurality of potential-time conversion circuits 200, 201, 202 each having a capacitive element 24, a discharge circuit, and a timer 26. The voltage divider circuit 10a inputs input potentials Vin0, Vin1, Vin2 divided at different voltage division ratios to the plurality of potential-time conversion circuits 200, 201, 202 respectively. The time-to-digital value conversion circuit 30a selects any one of the discharge times t0, t1, t2 respectively converted by the plurality of potential-time conversion circuits 200, 201, 202 and converts it into a digital value.

[0096] With this configuration, the AD converter 1a can expand the input range (dynamic range). The number of potential-time conversion circuits 20 can be appropriately set according to the desired input range.

[0097] In addition, the present invention is not limited to the above-described embodiments. Obviously, within the scope of the technical idea of the present invention, the embodiments can be appropriately changed. Further, the number, position, shape, etc. of the above-described constituent elements are not limited to the above embodiments, and can be set to appropriate numbers, positions, shapes, etc. in implementing the present invention. In addition, in each figure, the same reference numerals are assigned to the same constituent elements.

[0098] Reference Numeral Explanation

[0099] 1, 1a, 1b: AD converters

[0100] 10, 10a, 10b: Voltage divider circuits

[0101] 20, 20b, 200, 201, 202: Potential-time conversion circuits

[0102] 21, 21b: First switching elements

[0103] 22, 22b: Second switching elements

[0104] 23, 23b: Discharge elements

[0105] 24: Capacitive element

[0106] 25: Amplifier

[0107] 26: Timer

[0108] 30, 30a: Time-to-digital value conversion circuits.

Claims

1. An AD converter that converts an input potential into a digital value, characterized in that: The AD converter includes: A capacitive element that accumulates charge with a preset potential difference; A discharge circuit that discharges the charge accumulated in the capacitive element with a discharge current determined by the input potential; A timer that measures the discharge time until the charge accumulated in the capacitive element reaches a specified charge amount through the discharge of the discharge circuit; And A time-to-digital value conversion circuit that converts the discharge time measured by the timer into the digital value.

2. The AD converter according to claim 1, characterized in that: The AD converter includes an amplifier that outputs a stop signal indicating that the specified charge amount has been reached based on the potential of a node connecting the capacitive element and the discharge circuit, The timer measures the time from the input of a start signal instructing the start of discharge of the discharge circuit to the input of the stop signal as the discharge time.

3. The AD converter according to claim 1, characterized in that: The discharge circuit operates a MOS transistor whose gate is input with the input potential in the saturation region, and discharges the charge accumulated in the capacitive element with a drain-source current determined by the input potential as the discharge current.

4. The AD converter according to claim 3, characterized in that: The input potential divided by a voltage dividing circuit is input to the gate of the MOS transistor.

5. The AD converter according to claim 4, characterized in that: The AD converter includes multiple potential-to-time conversion circuits, each of which has the capacitive element, the discharge circuit, and the timer, The voltage dividing circuit inputs the input potential divided with different voltage division ratios to the multiple potential-to-time conversion circuits respectively, The time-to-digital value conversion circuit selects any one of the discharge times respectively converted by the multiple potential-to-time conversion circuits and converts it into the digital value.

6. A semiconductor device, characterized in that: The semiconductor device integrates the AD converter according to claim 1 on a substrate.

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