High-precision feed-forward noise shaping successive approximation analog-to-digital converter

Abstract

The invention discloses a high-precision feed-forward noise shaping successive approximation analog-to-digital converter. The analog-to-digital converter comprises a first CDAC module, a second CDAC module, a first feed-forward capacitor, a second feed-forward capacitor, a first integrating capacitor, a second integrating capacitor, a first elimination capacitor, a second elimination capacitor, a dynamic amplifier module and a dynamic comparator module. By adopting the technical scheme of the invention, the sampling noise which cannot be optimized by noise shaping is suppressed, and a better precision effect is generated.

Description

Technical Field

[0001] The present invention belongs to the technical field of noise shaping SAR ADC, and particularly relates to a high-precision feed-forward noise shaping successive approximation analog-to-digital converter with a sampling noise cancellation technique. Background Art

[0002] An analog-to-digital converter (ADC), as a bridge connecting the analog world and the digital world, is widely used in fields such as wireless communication, high-precision sensors, industrial control, and biomedicine. With the continuous development of information technology, the performance requirements for ADCs are getting higher and higher, gradually moving towards high precision, high speed, and low power consumption. Successive approximation register (SAR) ADCs are widely used in medium-high precision and medium-speed scenarios due to their advantages such as simple structure, large proportion of digital circuits, low power consumption, and high efficiency. Limited by the precision of comparators and capacitor mismatches, it is difficult for the precision of SAR ADCs to exceed 12 bits without calibration. Noise shaping (NS) SAR ADCs combine oversampling technology and noise shaping technology on the basis of SAR ADCs, which can effectively improve the overall precision of ADCs. As a hybrid architecture of SAR ADCs and Sigma-Delta ADCs, noise shaping SAR ADCs can modulate quantization noise and push it to high-frequency bands, significantly improving the signal-to-noise ratio within the signal bandwidth, and thus achieving higher resolutions using lower-resolution and lower-precision circuit modules, combining the advantages of both architectures, namely low power consumption and high precision. In recent years, it has gradually become a research hotspot in academia and industry. Noise shaping SAR ADCs can meet different bandwidth and precision requirements by selecting different orders and oversampling rates. Noise shaping SAR ADCs are closely related to the process, especially the bandwidth and FoM value, and have the smallest area under advanced processes.

[0003] Current noise shaping SAR ADCs mainly have two architectures, one is the cascaded integrator feed-forward (CIFF) noise shaping SAR ADC, and the other is the error feedback (EF) noise shaping SAR ADC.

[0004] In the feed-forward architecture, the conversion of the residual voltage is achieved through an infinite impulse response (IIR) filter, which can be in passive or active form. Compared with the EF architecture, the poles in the NTF of the CIFF architecture are easier to set, and there is no problem of system stability. The summation of the input signal and the residual voltage is achieved through a multi-input comparator or capacitor stacking.

[0005] The residual voltage in the feedback path is shaped by a Finite Impulse Response (FIR) filter, which is typically implemented by a residual amplifier with gain. The zeros of the feedback architecture are easier to set, but often require the introduction of delay, have stricter timing requirements, and there is a certain degree of instability.

[0006] Sampling noise is a major challenge currently limiting the signal-to-noise ratio of SAR ADCs. Sampling Noise Cancellation (SNC) technology can significantly reduce the size of the sampling capacitor, relaxing the requirements for the ADC input driver and reference buffer. Due to the existence of a feedback loop in the EF architecture, the use of SNC technology adds stability considerations. Since the CIFF architecture is an open-loop structure, the use of SNC technology does not cause stability problems. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a high-precision feedforward noise shaping successive approximation analog-to-digital converter with sampling noise cancellation technology.

[0008] To achieve the above object, the present invention adopts the following technical solutions:

[0009] A high-precision feedforward noise shaping SAR ADC, comprising: a first CDAC module, a second CDAC module, a first feedforward capacitor, a second feedforward capacitor, a first integration capacitor, a second integration capacitor, a first cancellation capacitor, a second cancellation capacitor, a dynamic amplifier module, and a dynamic comparator module; wherein,

[0010] The input end of the first CDAC module is connected to a first input voltage through a sampling switch, and the output end of the first CDAC module is respectively connected to the upper plate of the first feedforward capacitor and the first input end of the dynamic amplifier module;

[0011] The input end of the second CDAC module is connected to a second input voltage through a sampling switch, and the output end of the second CDAC module is respectively connected to the upper plate of the second feedforward capacitor and the second input end of the dynamic amplifier module.

[0012] Preferably, the upper plate of the first feedforward capacitor is connected to the upper plate of the first integration capacitor and the upper plate of the first cancellation capacitor through a noise shaping switch; the lower plate of the first feedforward capacitor is connected to the lower plate of the first integration capacitor, the lower plate of the first cancellation capacitor, and the first input end of the dynamic comparator module through a noise shaping switch.

[0013] Preferably, the upper plate of the second feedforward capacitor is connected to the upper plates of the second integrating capacitor and the second canceling capacitor through a noise shaping switch; the lower plate of the second feedforward capacitor is connected to the lower plates of the second integrating capacitor and the second canceling capacitor and the second input terminal of the dynamic comparator module through a noise shaping switch.

[0014] Preferably, the lower plate of the first integrating capacitor is connected to the common mode level through an error amplification switch; the lower plate of the second integrating capacitor is connected to the common mode level through an error amplification switch.

[0015] Preferably, the first output terminal of the dynamic comparator module is connected to the upper plate of the first canceling capacitor through a sampling noise cancellation switch; the first output terminal of the dynamic comparator module is connected to the upper plate of the first integrating capacitor through an error amplification switch.

[0016] Preferably, the second output terminal of the dynamic comparator module is connected to the upper plate of the second canceling capacitor through a sampling noise cancellation switch; the second output terminal of the dynamic comparator module is connected to the upper plate of the second integrating capacitor through an error amplification switch.

[0017] Preferably, the first output terminal of the dynamic amplifier module is connected to the lower plate of the second canceling capacitor through a sampling noise cancellation switch; the second output terminal of the dynamic amplifier is connected to the lower plate of the first canceling capacitor through a sampling noise cancellation switch.

[0018] The present invention is a first-order high-precision feedforward noise shaping SAR ADC applying sampling noise cancellation technology. In the design of the feedforward architecture, a dynamic amplifier combined with passive switched capacitors is used. At the same time, by optimizing the zero-pole positions of the noise transfer function, the designed noise transfer function of the present invention has a better noise suppression effect. To further improve the precision of the noise shaping SAR ADC, the present invention uses sampling noise cancellation technology and applies it to the feedforward architecture to suppress the sampling noise that cannot be optimized by noise shaping, resulting in a better precision effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0020] Figure 1 It is a schematic structural diagram of the high-precision feedforward noise shaping successive approximation analog-to-digital converter of the present invention;

[0021] Figure 2 It is a working timing diagram of the present invention;

[0022] Figure 3 is the signal flow diagram of the present invention;

[0023] Figure 4 is the schematic diagram of the SNC technology of the present invention;

[0024] Figure 5 is the simulation result diagram of the present invention;

[0025] Among them, 1 - the first CDAC module, 2 - the second CADC module, 3 - the dynamic amplifier module, 4 - the dynamic comparator module, 5 - the first cancellation capacitor, 6 - the second cancellation capacitor, 7 - the first integration capacitor, 8 - the second integration capacitor, 9 - the first feed - forward capacitor, 10 - the second feed - forward capacitor. Detailed implementation manners

[0026] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0027] To make the above - mentioned objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below in conjunction with the drawings and specific implementation manners.

[0028] Embodiment 1:

[0029] As Figure 1 shown, the embodiment of the present invention provides a high - precision feed - forward noise - shaping SAR ADC, including: a first CDAC module, a second CDAC module, a first feed - forward capacitor, a second feed - forward capacitor, a first integration capacitor, a second integration capacitor, a first cancellation capacitor, a second cancellation capacitor, a dynamic amplifier module, and a dynamic comparator module.

[0030] The input end of the first CDAC module is connected to the first input voltage VIP through the sampling switch φ S1 The output end of the first CDAC module is respectively connected to the upper plate of the first feed - forward capacitor C IIR1 , the first input end of the dynamic amplifier module, and is connected to the upper plate of the first integration capacitor C NS through the switch φ int1 , and is connected to the upper plate of the first cancellation capacitor C NS through the switch φ SNC1 .

[0031] The input end of the second CDAC module is connected to the second input voltage VIN through the sampling switch φ S1Connect to the second input voltage VIN. The output terminals of the second CDAC module are respectively connected to the upper plate of the second feed-forward capacitor C IIR2 and the second input terminal of the dynamic amplifier module through the switch φ NS to the upper plate of the second integration capacitor C int2 and are connected to the upper plate of the second cancellation capacitor C NS through the switch φ SNC2 .

[0032] The lower plate of the first feed-forward capacitor is connected to the first input terminal of the dynamic comparator module and is connected to the lower plate of the first integration capacitor through the switch φ NS and is connected to the lower plate of the first cancellation capacitor through the switch φ NS .

[0033] The lower plate of the first feed-forward capacitor is connected to the second input terminal of the dynamic comparator module and is connected to the lower plate of the second integration capacitor through the switch φ NS and is connected to the lower plate of the second cancellation capacitor through the switch φ NS .

[0034] The first output terminal of the dynamic comparator module is connected to the upper plate of the first integration capacitor Cint1 through the error amplification switch φ EX ; The first output terminal of the dynamic comparator module is connected to the upper plate of the first cancellation capacitor C S2 through the sampling noise cancellation switch φ SNC1 .

[0035] The second output terminal of the dynamic comparator is connected to the upper plate of the second integration capacitor C EX through the error amplification switch φ int2 ; The second output terminal of the dynamic comparator is connected to the upper plate of the second cancellation capacitor C s2 through the sampling noise cancellation switch φ SNC2 .

[0036] The second output terminal of the dynamic amplifier is connected to the lower plate of the first cancellation capacitor C s2 through the sampling noise cancellation switch φ SNC1 .

[0037] The first output terminal of the dynamic amplifier is connected to the lower plate of the second cancellation capacitor C s2 through the sampling noise cancellation switch φ SNC2 .

[0038] As an implementation manner of the local invention embodiment, let φs1 and φs2 be the upper and lower plate sampling clocks respectively, and φ COMP be the comparator clock, φ NS be the error shaping clock, φ EX be the residual voltage V res extraction clock, φDAMP is the dynamic amplifier clock.

[0039] As Figure 2 shown, for the specific noise shaping process, when φ s1 and φ s2 are at high level, the first CDAC module and the second CDAC module sample the first input signal VIP and the second input signal VIN respectively. After the sampling is completed, φ COMP is at high level, and the comparator module starts successive comparison. The whole ADC is in the quantization stage. When the last comparison is completed, φ COMP becomes low level. Next, it enters the residual voltage sampling stage. The first input terminal and the second input terminal of the dynamic amplifier module sample the output terminals of the first CDAC module and the second CDAC module respectively, amplify them by G times, and then store them in the first integration capacitor C int1 and the second integration capacitor C int2 . In the comparator quantization stage of the next cycle, φ NS is at high level. The first integration capacitor C int1 and the first feedforward capacitor C IIR1 , as well as the second integration capacitor C int2 and the second feedforward capacitor C IIR2 perform charge sharing to realize shaping the quantization noise and summing it with the input signal.

[0040] In the implementation of the actual circuit, the values of the first integration capacitor and the second integration capacitor are equal, and the values of the first feedforward capacitor and the second feedforward capacitor are equal. It can be obtained that:

[0041]

[0042] In the period of T = n - 1, after the ADC completes quantization, the residual voltages V res (z) at the output terminals of the first CDAC module and the second CDAC module are sampled and amplified by G times by the dynamic amplifier module, and stored in the first integration capacitor C int1 and the second integration capacitor C int2 .

[0043] V CIIR1 , 2(z) = GV res (z) (2)

[0044] In the period of T = n, the first integration capacitor C int1 and the first feedforward capacitor C IIR1 , the second integration capacitor C int2 and the second feedforward capacitor C IIR2 perform charge redistribution. Therefore,

[0045] VCIIR1 , 2(z)C IIR1，2 z -1 +V int1，2 (z)C int1，2 z -1 =V int1，2 (z)(C IIR1，2 +C int1，2 ) (3)

[0046] The noise shaping filter H IIR (z) can be obtained by calculation, and its transfer function is

[0047]

[0048] The overall noise transfer function NTF(z)

[0049]

[0050] The signal flow diagram of the present invention is as Figure 3 shown, and the input-output relationship can be obtained from the figure:

[0051]

[0052] By calculating the above two equations, it can be obtained that:

[0053]

[0054] It can be seen from the above formula that the noise transfer function has a zero at p and a zero at [G(1 - p) - p]z -1 . For the noise transfer function, the closer the zero position is to the unit circle, the better the noise shaping effect. However, for the first-order noise shaping SAR ADC, it is difficult to improve the noise suppression effect through zero optimization. Therefore, in the present invention, by adjusting the coefficients of the noise transfer function, it includes a pole, so as to have better noise suppression ability. Substituting p = 0.8 and G = 8, the system transfer function of the noise shaping SAR ADC of the present invention is obtained after arrangement:

[0055]

[0056] It can be seen from the above formula that the structure of the dynamic amplifier combined with the passive switched capacitor used in the present invention can be realized by adjusting the gain G of the dynamic amplifier module and the ratio of the first feedforward capacitor (the second feedforward capacitor) to the first integration capacitor (the second integration capacitor). This noise transfer function not only has a good noise suppression effect, but also reduces the gain requirement of the dynamic amplifier and the design difficulty.

[0057] As Figure 4The following shows the SNC technology designed for the CIFF architecture in the present invention. Since there is a feedback loop in the EF architecture, the stability issue needs to be considered, and the use of the sampling noise cancellation technology will increase the considerations. Since the CIFF architecture is an open-loop structure, the stability issue does not need to be considered, and the use of the sampling noise cancellation technology will not cause stability problems. The time difference between the upper and lower plates of the first CDAC module and the second CDAC module is extracted by sampling the KT / C noise, and its working process is as follows: When φ s1 becomes low, the switches of the lower plates of the first CDAC module and the second CDAC module are closed, and the sampled KT / C noise is fixed at the outputs of the first CDAC module and the second CDAC module. Before φ s2 is closed, the sampled KT / C noise is stored at the input of the dynamic amplifier module in the state of a definite value. Therefore, it can be replicated, amplified, and stored on the first cancellation capacitor CSNC1 and the second cancellation capacitor CSNC2 through the dynamic amplifier module. The non-ideals such as the distortion caused by the lower plate switch resistance are also stored on the first cancellation capacitor CSNC1 and the second cancellation capacitor CSNC2 during this period. At this time, the voltages on the first cancellation capacitor CSNC1 and the second cancellation capacitor CSNC2 can be expressed as

[0058] V SNC1，2 =G(V in (t2)-V in (t1)+v NL +v ns ) (10)

[0059] where v NL is the total non-linearity, v ns is the sampled noise voltage, assuming no additional non-linearity is introduced. The sampled KT / C noise cancellation is summed with the CIFF. The first cancellation capacitor CSNC1, the second cancellation capacitor CSNC2 will be connected in parallel with the first feed-forward capacitor CIIR1, the second feed-forward capacitor CIIR2, and the first integration capacitor CINT1, the second integration capacitor CINT2. The voltage at the Vx node during the conversion stage can be expressed as

[0060] V x =D DAC -V in (t2)+V INT +(1-K CIFF G)(v NL +v ns +V in (t2)-V in (t1))+K CIFF Gv amp (11)

[0061] where D DACis the flip voltage after the capacitor array quantization is completed, V in (t2) is the input sampling signal, K CIFF is the attenuation factor caused by charge sharing, G represents the gain of the amplifier, v amp is the equivalent input noise voltage of the amplifier.

[0062] The total sampling error voltage observed by the comparator in the SAR conversion stage can be expressed as (1 - K CIFF G), where K CIFF can be expressed as

[0063]

[0064] By designing K CIFF G to be equal to 1, the noise v ns and v NL .

[0065] The noise shaping SAR ADC of the present invention can achieve an SNDR of 82.8 dB without adding a sampling noise cancellation technique. After adding the sampling noise cancellation technique, its SNDR reaches 85.7 dB, as Figure 5 shown.

[0066] The embodiments described above are only descriptions of the preferred embodiments of the present invention, and do not limit the scope of the present invention. Without departing from the design spirit of the present invention, various deformations and improvements made by those of ordinary skill in the art to the technical solutions of the present invention shall fall within the protection scope determined by the claims of the present invention.

Claims

1. A high-precision feedforward noise shaping successive approximation analog-to-digital converter, characterized in that, A noise transfer function with a better noise suppression effect and the application of a sampling noise cancellation technique in a CIFF circuit, including: a first CDAC module, a second CDAC module, a first feedforward capacitor, a second feedforward capacitor, a first integration capacitor, a second integration capacitor, a first cancellation capacitor, a second cancellation capacitor, a dynamic amplifier module, and a dynamic comparator module; wherein, The input end of the first CDAC module is connected to a first input voltage through a sampling switch, and the output end of the first CDAC module is respectively connected to the upper plate of the first feedforward capacitor and the first input end of the dynamic amplifier module; The input end of the second CDAC module is connected to a second input voltage through a sampling switch, and the output end of the second CDAC module is respectively connected to the upper plate of the second feedforward capacitor and the second input end of the dynamic amplifier module.

2. The high-precision feedforward noise shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The upper plate of the first feedforward capacitor is connected to the upper plate of the first integration capacitor and the upper plate of the first cancellation capacitor through a noise shaping switch; the lower plate of the first feedforward capacitor is connected to the lower plate of the first integration capacitor, the lower plate of the first cancellation capacitor, and the first input end of the dynamic comparator module through a noise shaping switch.

3. The high-precision feedforward noise shaping successive approximation analog-to-digital converter according to claim 2, wherein, The upper plate of the second feedforward capacitor is connected to the upper plate of the second integration capacitor and the upper plate of the second cancellation capacitor through a noise shaping switch; the lower plate of the second feedforward capacitor is connected to the lower plate of the second integration capacitor, the lower plate of the second cancellation capacitor, and the second input end of the dynamic comparator module through a noise shaping switch.

4. The high-precision feedforward noise shaping successive approximation analog-to-digital converter according to claim 3, characterized in that, The lower plate of the first integration capacitor is connected to the common mode level through an error amplification switch; the lower plate of the second integration capacitor is connected to the common mode level through an error amplification switch.

5. The high-precision feedforward noise shaping successive approximation analog-to-digital converter according to claim 4, characterized in that, The first output end of the dynamic comparator module is connected to the upper plate of the first cancellation capacitor through a sampling noise cancellation switch; the first output end of the dynamic comparator module is connected to the upper plate of the first integration capacitor through an error amplification switch.

6. The high-precision feedforward noise shaping successive approximation analog-to-digital converter according to claim 5, characterized in that The second output end of the dynamic comparator module is connected to the upper plate of the second cancellation capacitor through a sampling noise cancellation switch; the second output end of the dynamic comparator module is connected to the upper plate of the second integration capacitor through an error amplification switch.

7. The high-precision feedforward noise shaping successive approximation analog-to-digital converter according to claim 6, characterized in that, The first output end of the dynamic amplifier module is connected to the lower plate of the second cancellation capacitor through a sampling noise cancellation switch; the second output end of the dynamic amplifier is connected to the lower plate of the first cancellation capacitor through a sampling noise cancellation switch.

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