Power management chip dynamic control method and system based on hybrid modulation

Abstract

The invention provides a power management chip dynamic control method and system based on hybrid modulation. According to the method, an instruction decoding unit is arranged in a chip to intercept an operation code sequence feature identifier, and a current detection unit is activated to collect a transient power consumption fluctuation curve of a power supply loop; the operation code identifiers and the power consumption curves are aligned and associated according to timestamps in a time sequence alignment module, and a load behavior feature library is constructed; the magnetic flux control current is adjusted through the driving circuit, so that the medium reaches the preset magnetic flux saturation before load transition; decomposing instruction stream fragments, performing waveform similarity matching on the instruction stream and the magnetic flux control current, and detecting a specific instruction combination mode; and writing a control parameter into the modulation logic unit based on the detection result and the magnetic flux saturation, and switching the working state combination of the step-down and step-up hybrid conversion mode. According to the invention, the transient response speed and the energy transmission efficiency of the power management chip in a video rendering burst load scene are improved.

Description

Technical Field

[0001] This application relates to the technical field of chip dynamic control, and particularly to a dynamic control method and system for a power management chip based on hybrid modulation. Background Art

[0002] When a mobile computing device executes a high-dynamic load task, the power management system needs to respond to the drastic power transition of the processor from the idle state to full-load operation within milliseconds. Such scenarios require the power chip to simultaneously meet three core requirements: accurately predicting the burst current demand triggered by the graphics processor instruction set; dynamically optimizing the transient energy transfer efficiency of the power conversion path; and maintaining the output voltage stable within a ±3% tolerance band to avoid rendering frame loss.

[0003] The current mainstream solution adopts an adaptive PID control architecture based on load current feedforward. By high-speed sampling the current change rate of the processor power supply circuit and combining with a pre-stored load-frequency response mapping table, it dynamically adjusts the pulse width modulation frequency of the switching power supply. This architecture triggers a multi-level compensation mechanism when detecting that the current rising edge exceeds the threshold: first, it predicts the future power consumption trend based on the historical load curve, then it corrects the output duty cycle of the PID controller by dynamically scaling the proportional coefficient, and finally, it optimizes and reduces the switching loss by using the conduction timing of the synchronous rectifier tube in the buck topology.

[0004] The response delay of this architecture is limited by the current sampling frequency and the PID calculation period. In the microsecond-level load switching scenario where the vertex shader and texture sampler in video rendering work alternately, there will still be an instantaneous drop in the output voltage. The fundamental defect is that the power path control is completely decoupled from the processor instruction set - the current feedforward signal only reflects the occurred load changes and cannot predict the calculation task sequence in the instruction pipeline, resulting in the lag of energy transfer optimization behind the actual load demand. At the same time, the fixed PID parameters cannot adapt to the non-linear load transition characteristics in the rendering pipeline, and the frequent duty cycle correction further exacerbates the switching loss of the power transistor, reducing the peak energy efficiency of the system. Summary of the Invention

[0005] This application provides a dynamic control method and system for a power management chip based on hybrid modulation to solve the problems of insufficient transient response speed and energy transfer efficiency in the prior art.

[0006] In the first aspect, this application provides a dynamic control method for a power management chip based on hybrid modulation, including: Synchronously intercepting the opcode sequence feature identifiers within a continuous time window in the processor instruction pipeline through the built-in instruction decoding unit of the chip, and parallelly activating the internal current detection unit of the chip to collect the transient power consumption fluctuation curve of the processor power supply circuit within the time window; In the timing alignment module of the chip configuration, align and associate the opcode sequence feature identifier with the transient power consumption fluctuation curve according to the timestamp, extract the recurring load change pattern feature group in the association result, and construct a load behavior feature library containing multi-level power consumption transition trajectories; According to the prediction pattern matching the current opcode segment in the load behavior feature library, adjust the magnetic flux control current flowing through the energy storage medium of the magnetically coupled double winding through the internal drive circuit of the chip, so that the energy storage medium enters the preset magnetic flux saturation before the load transition occurs; Decompose the instruction stream segment currently executed by the processor, perform waveform similarity matching on the instruction stream segment and the adjusted magnetic flux control current in the chip mode matching unit, and detect the specific instruction combination pattern triggered by the video rendering operation based on the matching result; Based on the detection result of the specific instruction combination pattern and the magnetic flux saturation of the energy storage medium, write control parameters to the chip modulation logic unit, and selectively switch the working state combination of the buck-boost hybrid energy conversion mode according to the control parameters.

[0007] Optionally, the adjusting the magnetic flux control current flowing through the energy storage medium of the magnetically coupled double winding through the internal drive circuit of the chip according to the prediction pattern matching the current opcode segment in the load behavior feature library, so that the energy storage medium enters the preset magnetic flux saturation before the load transition occurs, includes: Extract the prediction pattern matching the current opcode segment from the load behavior feature library, and analyze the prediction pattern to obtain the magnetic flux saturation target value, the minimum current duration required to reach the magnetic flux saturation target value, and the starting time point when the expected load transition occurs; Query the magnetic circuit characteristic mapping table pre-stored in the non-volatile unit of the chip, and output the corresponding DC bias current value and current ramp rate parameter through the magnetic circuit characteristic mapping table according to the magnetic flux saturation target value and the temperature parameter of the energy storage medium; Calculate the current regulation start time based on the starting time point and the minimum current duration, and trigger a stepped current output sequence controlled by the current ramp rate parameter at the current regulation start time through the programmable delay unit of the internal drive circuit of the chip; Apply the stepped current output sequence to the main magnetic circuit control end of the magnetically coupled double winding, monitor the differential value of the induced voltage at the main magnetic circuit control end according to the DC bias current value, and when the monitored value is stable within the preset threshold range, determine that the energy storage medium reaches the target magnetic flux saturation.

[0008] Optionally, for the instruction stream segment currently executed by the decomposition processor, in the chip mode matching unit, the instruction stream segment is subjected to waveform similarity matching with the adjusted flux control current, and based on the matching result, a specific instruction combination pattern triggered by a video rendering operation is detected, including: Intercept the instruction stream segment currently executed by the processor in a fixed time window, identify the distribution positions and execution timing relationships of the graphics processing dedicated operation codes in the instruction stream segment, and generate an instruction event pulse sequence waveform according to the distribution positions and execution timing relationships, where the vertex shader start operation code is marked as a positive pulse and the texture sampling operation code is marked as a negative pulse; Synchronously obtain the actual adjustment waveform of the adjusted flux control current within the fixed time window, and extract the turning point positions and turning directions in the actual adjustment waveform that exceed the preset change rate threshold; Match the instruction event pulse sequence waveform with the turning point positions and turning directions on the time axis, and determine that the match is successful when the time deviation between the vertex shader start pulse and the positive pulse turning point during the matching process is less than the set threshold; When the number of successful matches reaches two consecutive video rendering frame cycles, confirm that a specific instruction combination pattern triggered by the alternation of vertex shader intensive calculation and texture sampling is detected.

[0009] Optionally, based on the detection result of the specific instruction combination pattern and the flux saturation of the energy storage medium, write control parameters to the chip modulation logic unit, and selectively switch the working state combination of the buck-boost hybrid energy conversion mode according to the control parameters, including: Analyze the alternating time characteristics of the vertex shader intensive calculation stage and the texture sampling stage in the specific instruction combination pattern, and generate a mode switching timing parameter set in combination with the flux saturation value; According to the instruction density level of the vertex shader intensive calculation stage and the flux saturation value, calculate the minimum voltage gain coefficient and the maximum switching frequency threshold required for the boost mode; Based on the storage access frequency and the flux saturation decay rate of the texture sampling stage, limit the duty cycle adjustment range and the synchronous rectification trigger condition of the buck mode; Write a comprehensive control parameter package to the chip modulation logic unit, and complete the calculation process of the minimum voltage gain coefficient and the maximum switching frequency threshold through the comprehensive control parameter package during the vertex shader intensive calculation stage, and at the same time switch to the limiting process of the buck mode during the texture sampling stage.

[0010] Optionally, in the timing alignment module configured in the chip, the opcode sequence feature identifier is aligned and associated with the transient power consumption fluctuation curve according to timestamps, and a feature group of recurring load change patterns in the association result is extracted to construct a load behavior feature library including multi-level power consumption transition trajectories, including: Mark the corresponding timestamp for the opcode sequence feature identifier at each acquisition moment, and synchronously mark the same timestamp for the sampling points of the transient power consumption fluctuation curve; Based on the corresponding timestamp and the same timestamp, continuously intercepted time periods are generated according to the video rendering instruction cycle to generate association segments including opcode fragment combinations and the power consumption change profiles within their corresponding time periods; Compare the association segments within multiple consecutive video rendering instruction cycles. When the same opcode fragment combination is detected to repeat during the comparison, extract the feature group of the load change pattern corresponding to the repeatedly occurring opcode fragment combination; Divide the multi-level power consumption transition trajectories according to the amplitude values of the transition point sequences, and bind and store the opcode fragment combinations and the multi-level power consumption transition trajectories into a load behavior feature library with a multi-level index structure.

[0011] Optionally, intercept the instruction stream fragment currently executed by the processor according to a fixed time window, identify the distribution positions and execution timing relationships of the graphics processing dedicated opcodes in the instruction stream fragment, and generate an instruction event pulse sequence waveform according to the distribution positions and execution timing relationships, where the vertex shader start opcode is marked as a positive pulse and the texture sampling opcode is marked as a negative pulse, including: Set a fixed time window synchronized with the graphics processor instruction cycle to capture the instruction stream fragment executed by the processor within the fixed time window; Identify the first occurrence position of the vertex shader start opcode and the continuous distribution coordinates of the texture sampling opcode in the instruction stream fragment through a hardware decoding unit, and record the time interval sequence between the opcodes to characterize the execution timing relationship; Generate a baseline level at the starting point of the fixed time window, and generate a positive rectangular pulse when the first occurrence position is detected, where the pulse width is determined by the time interval sequence; Generate a negative rectangular pulse at the occurrence position of the continuous distribution coordinates. The starting moment of the negative rectangular pulse is dynamically offset according to the execution timing relationship. The pulse amplitude is proportional to the number of sampling times. The baseline level is maintained during the period without opcodes, and the positive rectangular pulse and the negative rectangular pulse form an instruction event pulse sequence waveform.

[0012] Optionally, calculate the current regulation start time based on the start time point and the minimum current duration, and trigger a stepped current output sequence controlled by the current ramp rate parameter at the current regulation start time through a programmable delay unit of the internal drive circuit of the chip, including: Taking the start time point as a reference, offset forward by the minimum current duration and superimpose a protection time margin to calculate the current regulation start time; Set a countdown trigger signal for the current regulation start time in the programmable delay unit, and synchronously load the current ramp rate parameter to the stepped waveform generator; When the countdown trigger signal reaches zero, generate a stepped current output sequence through the stepped waveform generator according to the current ramp rate parameter; Output the stepped current output sequence to the main magnetic circuit control terminal through the power amplification stage of the drive circuit, and inject a transient voltage suppression pulse when switching each step.

[0013] In a second aspect, the present application provides a dynamic control system for a power management chip based on hybrid modulation, including: An interception module for synchronously intercepting the opcode sequence feature identifier in the continuous time window of the processor instruction pipeline through the built-in instruction decoding unit of the chip, and parallelly activating the internal current detection unit of the chip to collect the transient power consumption fluctuation curve of the processor power supply circuit within the time window; A construction module for aligning and associating the opcode sequence feature identifier with the transient power consumption fluctuation curve according to the time stamp in the timing alignment module configured in the chip, extracting the load change pattern feature group that repeatedly appears in the association result, and constructing a load behavior feature library including multi-level power consumption transition trajectories; An adjustment module for adjusting the magnetic flux control current flowing through the energy storage medium of the magnetically coupled double winding through the internal drive circuit of the chip according to the prediction pattern matching the current opcode segment in the load behavior feature library, so that the energy storage medium enters a preset magnetic flux saturation before the load transition occurs; A matching module for decomposing the instruction stream segment currently executed by the processor, performing waveform similarity matching between the instruction stream segment and the adjusted magnetic flux control current in the chip mode matching unit, and detecting a specific instruction combination pattern triggered by video rendering operations based on the matching result; A switching module for writing control parameters to the chip modulation logic unit based on the detection result of the specific instruction combination pattern and the magnetic flux saturation of the energy storage medium, and selectively switching the working state combination of the buck-boost hybrid energy conversion mode according to the control parameters.

[0014] In a third aspect, the present application provides a computing device, including a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component to implement a dynamic control method for a power management chip based on hybrid modulation as described in the first aspect above.

[0015] In a fourth aspect, the present application provides a computer storage medium storing a computer program, which when executed by a computer, implements a dynamic control method for a power management chip based on hybrid modulation as described in the first aspect.

[0016] In the present application, an instruction decoding unit built into the chip synchronously intercepts the opcode sequence feature identifiers within a continuous time window in the processor instruction pipeline, and parallelly activates an internal current detection unit of the chip to collect the transient power consumption fluctuation curve of the processor power supply loop within the time window; in a timing alignment module configured in the chip, the opcode sequence feature identifiers are aligned and associated with the transient power consumption fluctuation curve according to timestamps, and a load change pattern feature group that repeatedly appears in the association result is extracted to construct a load behavior feature library containing multi-level power consumption transition trajectories; according to the prediction pattern matching the current opcode segment in the load behavior feature library, the magnetic flux control current flowing through the energy storage medium of the magnetically coupled double winding is adjusted through an internal drive circuit of the chip, so that the energy storage medium enters a preset magnetic flux saturation before the load transition occurs; the instruction stream segment currently executed by the processor is decomposed, and the waveform similarity between the instruction stream segment and the adjusted magnetic flux control current is matched in a chip pattern matching unit, and a specific instruction combination pattern triggered by a video rendering operation is detected based on the matching result; based on the detection result of the specific instruction combination pattern and the magnetic flux saturation of the energy storage medium, control parameters are written into a chip modulation logic unit, and the working state combination of the buck-boost hybrid energy conversion mode is selectively switched according to the control parameters.

[0017] The technical solution of the present application has the following beneficial effects: It realizes the millisecond-level spatio-temporal synchronization of the processor instruction characteristics and the physical state of the power supply loop, and establishes the raw data basis for load behavior analysis; extracts the multi-level power consumption transition trajectory pattern unique to the video rendering scene to form the decision basis for predicting sudden loads; dynamically optimizes the magnetic flux saturation of the magnetically coupled double-winding energy storage medium according to the instruction characteristic prediction result to improve the transient energy transmission ability; accurately identifies the switching timing of the rendering pipeline stage through the timing characteristic matching of the vertex shading / texture sampling instruction stream and the magnetic flux control current; couples the instruction pattern and the magnetic circuit state parameters, adapts to the buck-boost conversion mode combination, and optimizes the energy efficiency ratio in different rendering stages.

[0018] Further, extract the prediction pattern that matches the current opcode from the load behavior feature library, and parse out the target value of the magnetic flux saturation, the minimum current duration, and the starting time point of the load transition; query the magnetic circuit characteristic mapping table to output the temperature-compensated DC bias current value and the ramp rate parameter; calculate the stepped current sequence triggered at the starting moment based on the time point; apply it to the magnetic circuit control terminal and verify that the magnetic flux saturation meets the standard through the differential value of the induced voltage. Implement preventive closed-loop control of the magnetic coupling power path, enabling the energy storage medium to accurately enter the target magnetic flux state before the occurrence of video rendering burst loads, suppressing transient voltage drops, and reducing switching losses simultaneously.

[0019] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1 The flowchart shows a dynamic control method for a power management chip based on hybrid modulation provided by the present application; Figure 2 The structural schematic diagram shows a dynamic control system for a power management chip based on hybrid modulation provided by the present application; Figure 3 The structural schematic diagram shows a computing device provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0023] In some processes described in the specification and claims of the present application and the above-mentioned drawings, there are multiple operations that appear in a specific order. However, it should be clearly understood that these operations may not be executed in the order in which they appear in this article or may be executed in parallel. The serial numbers of the operations, such as 101, 102, etc., are only used to distinguish different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions such as "first" and "second" in this article are used to distinguish different messages, devices, modules, etc., and do not represent a sequence, nor do they limit that "first" and "second" are of different types.

[0024] Although existing power management solutions adopt a load current feedforward and adaptive PID control architecture, their inherent defect lies in the complete decoupling of power path regulation and the processor instruction set. The current sampling signal can only capture the load changes that have occurred and cannot predict the sequence of computational tasks about to be triggered in the instruction pipeline, such as the microsecond-level switching from vertex shaders to texture sampling in video rendering, resulting in the optimization of energy transfer always lagging behind the actual demand. At the same time, the PID control with fixed parameters is difficult to adapt to the non-linear transition characteristics of the rendering pipeline, and the frequent duty cycle correction exacerbates the switching loss, causing the core pain points of instantaneous voltage drop and insufficient peak energy efficiency at the output voltage.

[0025] In view of the above defects, the present invention proposes a dynamic control method for a power management chip based on the coordination of instruction flow characteristics and magnetic circuit states. The core lies in establishing a four-dimensional closed loop of the processor instruction set - power consumption characteristics - magnetic coupling power path - modulation strategy. By decoding the opcode sequence of the graphics processor and synchronously correlating the transient power consumption waveform, a load behavior feature library dedicated to the video rendering scenario is constructed; using this library to predict the load transition point and dynamically adjust the magnetic flux saturation of the magnetic coupling double-winding medium, so that the energy transfer path enters the optimized state before the occurrence of sudden loads; finally, the buck-boost mode switching is accurately triggered through the waveform matching of the instruction flow and the magnetic flux current. This method identifies the computational task sequence in advance through opcode characteristics, advancing the response; the dynamic adjustment of magnetic flux saturation improves the transient energy transfer efficiency; based on the vertex / texture instruction combination mode switching conversion strategy, voltage fluctuations are suppressed. Fundamentally solve the problems of voltage drop and energy efficiency decline caused by instruction decoupling in the prior art, and ensure the power quality and system stability in high-dynamic load scenarios.

[0026] The technical solution of this application is applicable to the sudden load scenarios of laptop computer CPUs / GPUs.

[0027] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of this application.

[0028] Figure 1 For the embodiments of this application, a flowchart of a dynamic control method for a power management chip based on hybrid modulation is provided, as Figure 1 shown. The method includes: 101. Synchronously intercept the opcode sequence feature identifier within a continuous time window in the processor instruction pipeline through the chip-built instruction decoding unit, and parallelly activate the chip internal current detection unit to collect the transient power consumption fluctuation curve of the processor power supply circuit within the time window; In the above solution, the time window is a fixed-duration segment synchronized with the graphics processor's rendering cycle, serving as a spatio-temporal unit for intercepting instruction streams and power consumption data. The opcode sequence feature identifier is a set of codes obtained by compressing the features of consecutive opcodes in the instruction pipeline. By extracting the type, order, and interval information of video rendering-specific instructions, an 8-bit feature code is generated, reflecting the instruction combination pattern. The transient power consumption fluctuation curve is the current-time change trajectory obtained at a sampling rate of 20 million times per second on the processor's power supply loop, capturing microsecond-level current jumps triggered by instruction execution.

[0029] In the embodiments of this application, first, the instruction decoding unit built into the chip automatically starts a fixed-length time window when detecting a screen refresh signal (such as the rising edge of the vertical synchronization signal). This window is synchronized with the rendering cycle of the graphics processor and is used to capture the instruction sequence and power consumption data simultaneously. For example, when the screen refresh signal is triggered, the decoding unit immediately starts continuously reading the instructions in the processor instruction pipeline at a cycle of 2 microseconds.

[0030] Second, within the time window, the decoding unit scans the instruction stream, identifies the types of instructions specific to video rendering (such as the start instruction for starting to draw a graph or the sampling instruction for processing textures), and compresses the type, order, and interval information of these consecutive instructions into a short 8-bit binary code according to preset rules, called the feature identifier. For example, a start draw instruction may be mapped to binary '01', and a texture sampling instruction may be mapped to '10', thereby generating a feature code reflecting the instruction combination pattern.

[0031] Next, the system simultaneously activates the current detection unit to collect the current values on the processor's power supply line at a sampling rate of 20 million times per second within the same time window, converts these analog current changes into digital waveforms, and particularly captures transient events with significant current fluctuations (i.e., microsecond-level jumps where the current change rate exceeds 10 amperes per second). For example, when a texture sampling instruction is executed, it may cause the current to drop by 5 amperes within 100 nanoseconds. Here, the change rate needs to be calculated: 100 nanoseconds is equal to 0.1 microseconds, so the change rate is 5 amperes divided by 0.1 microseconds, which is 50 amperes per second. This exceeds the threshold of 10 amperes per second and is thus recorded as a timestamped transient power consumption fluctuation curve.

[0032] Finally, the system aligns the feature identifier and the corresponding power consumption curve according to the timestamp accurate to nanoseconds, and writes them into adjacent storage areas in the memory, forming a data packet associating instructions with power consumption, ensuring that subsequent modules can access them synchronously. For example, the feature identifier is stored at memory addresses 0x2000 to 0x2001, while the power consumption curve is stored at 0x2002 to 0x2020. In this way, when the analysis module is called, it can directly associate the instruction features with the power consumption changes. The whole process is closely linked from signal triggering to data storage, achieving efficient synchronization. 102. Align and associate the opcode sequence feature identifier with the transient power consumption fluctuation curve according to the timestamp in the timing alignment module of the chip configuration, extract the feature group of load change patterns that repeatedly appear in the association result, and construct a load behavior feature library containing multi-level power consumption transition trajectories; Optionally, step 102 may specifically include: 1021. Mark the corresponding timestamp for the opcode sequence feature identifier at each acquisition moment, and synchronously mark the same timestamp for the sampling points of the transient power consumption fluctuation curve; 1022. Based on the corresponding timestamp and the same timestamp, intercept consecutive time periods according to the video rendering instruction cycle to generate an association segment containing the opcode fragment combination and the power consumption change profile within its corresponding time period; 1023. Compare the association segments within consecutive video rendering instruction cycles. When the same opcode fragment combination is detected to repeatedly appear during the comparison process, extract the feature group of load change patterns corresponding to the repeatedly appearing opcode fragment combination; 1024. Divide the multi-level power consumption transition trajectories according to the amplitude values of the transition point sequences, and bind and store the opcode fragment combination and the multi-level power consumption transition trajectories into a load behavior feature library with a multi-level index structure.

[0033] In the above solution, the timing alignment module is an internal hardware unit of the chip, which realizes the accurate matching of the opcode identifier and the power consumption curve timestamp through a nanosecond-level clock counter. The feature group of load change patterns is a set composed of repeatedly appearing opcode combinations and the power consumption transition events triggered by them, reflecting the periodic load law of the video rendering scenario. The multi-level power consumption transition trajectory is a power consumption mutation path divided by amplitude, storing the binding relationship between the opcode combination and the transition feature. The opcode fragment combination is an ordered set of video rendering-specific instruction sequences within a fixed time period. The power consumption change profile is the morphological feature of the current value changing with time within the associated time period, including the rising slope, peak position, and falling rate. The transition point sequence is a set of mutation points exceeding the set change rate threshold in the profile sorted by time, indicating the load state switch. The multi-level index structure is a storage architecture stratified by transition amplitude, supporting fast retrieval of trajectories through opcode combinations.

[0034] In the embodiments of this application, when the chip captures the opcode feature identifier (i.e., the mnemonic code representing a specific combination of graphic instructions) and the transient power consumption fluctuation curve (i.e., the record of the rapid change in the processor's power consumption), the primary task of the timing alignment module is to assign them time tags accurate to one billionth of a second (nanoseconds), ensuring that each point on the identifier and the power consumption curve strictly corresponds in time; for example, when the system recognizes an opcode combination representing "start drawing a graphic" (such as internal code 0xC1), it will record the current timestamp (such as "125 nanoseconds") at the same instant, freeze and record the current value at this moment (such as 28.6 amperes), and assign it the exact same "125 nanoseconds" time tag.

[0035] Next, based on the natural rhythm of the screen refresh (such as one cycle every 16.7 milliseconds), the system cuts the instruction identifiers and power consumption data with timestamps into consecutive segments. Each segment contains a complete sequence of instruction combinations within a period of time (such as a set of actions like "start drawing, process texture, generate pixel points") and the complete shape of the power consumption change within this period of time (i.e., the power consumption change profile).

[0036] Subsequently, the system continuously observes multiple screen refresh cycles (such as three consecutive cycles), and looks for the same instruction combinations that repeat in these segments; whenever it finds that the exact same instruction combination repeats in multiple cycles, the system will check the power consumption change profile corresponding to this instruction combination, find the points where the current undergoes a sharp mutation (i.e., the transition points where the current change speed exceeds 10 amperes per second), and record the time and the magnitude of the current value at which these mutation points occur; for example, if in three consecutive refresh cycles, a sudden sharp increase in current exceeding 25 amperes always occurs in an extremely short moment after 3.5 milliseconds (such as 100 nanoseconds later), the system will extract this sequence of time points (such as [3.5001 milliseconds, 3.5001 milliseconds, 3.5001 milliseconds]) and the corresponding sequence of current values (such as [28 amperes, 27.9 amperes, 28.2 amperes]).

[0037] Finally, the system will classify according to the range (amplitude) of these mutant point current values (for example, a mutation less than 10 amperes is counted as level 1, 10 to 30 amperes is counted as level 2, and greater than 30 amperes is counted as level 3), and then bind this recurring instruction combination with the power consumption mutation trajectory of the corresponding level it triggers (for example, an amplitude of about 25 amperes belongs to the level 2 trajectory) and store it in an organized feature database; this database is like a multi-level directory and can conveniently find the corresponding power consumption mutation level through the instruction combination; for example, after binding the instruction combination "[0xC1,0xD8]" (representing a specific graphics processing instruction sequence) with the level 2 power consumption mutation trajectory and storing it in the level 2 area of the database (such as address 0x5000 - 0x501F), the system can later know that when executing this set of instructions, the power consumption usually undergoes a medium-strength mutation.

[0038] The overall solution of step 102 above realizes the precise spatio-temporal association of instruction features and power consumption data through the timestamp synchronization mechanism, extracts key transition features in the repetitive load pattern based on the video rendering frame period, and constructs a hierarchical index feature library with scene adaptability. This solution breaks through the limitation of the decoupling of instructions and power consumption in traditional power control, establishes a prediction model from the processor opcode to the energy transfer characteristics, provides a high-precision decision basis for optimizing the magnetic circuit state in advance, and significantly improves the dynamic response ability in the sudden load scenario.

[0039] 103. According to the prediction pattern matching the current opcode segment in the load behavior feature library, adjust the magnetic flux control current of the energy storage medium flowing through the magnetically coupled double winding through the internal drive circuit of the chip, so that the energy storage medium enters the preset magnetic flux saturation before the load transition occurs; Optionally, step 103 may specifically include the following steps: 1031. Extract the prediction pattern matching the current opcode segment from the load behavior feature library, and parse the prediction pattern to obtain the magnetic flux saturation target value, the minimum current duration required to reach the magnetic flux saturation target value, and the starting time point when the expected load transition occurs; 1032. Query the magnetic circuit characteristic mapping table pre-stored in the non-volatile unit of the chip, and output the corresponding DC bias current value and current ramp rate parameter through the magnetic circuit characteristic mapping table according to the magnetic flux saturation target value and the temperature parameter of the energy storage medium; 1033. Calculate the current regulation start time based on the starting time point and the minimum current duration, and trigger a stepped current output sequence controlled by the current ramp rate parameter at the current regulation start time through the programmable delay unit of the internal drive circuit of the chip; Among them, step 1033 may specifically include the following process: taking the starting time point as a reference, offsetting forward by the minimum current duration and superimposing a protection time margin to calculate the current regulation start time; setting a countdown trigger signal for the current regulation start time in the programmable delay unit, and synchronously loading the current ramp rate parameter to the stepped waveform generator; when the countdown trigger signal reaches zero, generating a stepped current output sequence by the stepped waveform generator according to the current ramp rate parameter; outputting the stepped current output sequence to the main magnetic circuit control terminal through the power amplification stage of the drive circuit, and injecting a transient voltage suppression pulse when switching each step.

[0040] 1034. Apply the stepped current output sequence to the main magnetic circuit control terminal of the magnetically coupled double winding, monitor the differential value of the induced voltage at the main magnetic circuit control terminal according to the DC bias current value, and when the monitored value is stable within the preset threshold range, determine that the energy storage medium reaches the target magnetic flux saturation.

[0041] In the above solution, the prediction mode is a set of magnetic circuit control parameters associated with the opcode segment retrieved from the load behavior feature library, including the target magnetic state and time constraints. The target value of magnetic flux saturation is the proportion of the magnetic flux in the magnetically coupled double winding medium relative to the maximum capacity, which determines the transient energy transfer ability. The stepped current output sequence is a current output waveform that gradually increases in amplitude at fixed time intervals and is used for the progressive magnetization of the magnetic circuit. The magnetic circuit characteristic mapping table is a two-dimensional look-up table storing the correspondence between magnetic flux saturation and current parameters at different temperatures, calibrated through experiments. The programmable delay unit is an internally configurable timer in the chip, supporting the generation of trigger signals with nanosecond-level precision. The differential value of the induced voltage is the rate of change of the voltage across the magnetically coupled winding, which is a physical quantity reflecting the magnetic flux accumulation speed.

[0042] In the embodiments of the present application, first, when the chip needs to handle an upcoming drastic change in load (load transition), it utilizes a library storing historical experience (load behavior feature library) to predict and prepare in advance. The specific process is as follows: First, the chip checks the currently running instruction combination fragment (such as a combination named "vertex shader opcode 0xC1" and a combination named "texture sampling code 0xD8"), just like using a specific key to look up a matching record in the experience library. After finding the matching record, the chip interprets three key pieces of information from it: The first is the target magnetic flux saturation (that is, the "filled" degree that the energy storage medium is expected to reach, for example, the record shows that it needs to reach 85% saturation, numerically represented as 0x55), the second is the shortest power-on time required to reach this saturation (for example, the record shows that it needs to be powered on continuously for at least 200 microseconds, numerically represented as 0x00C8), and the third is the starting time point at which the drastic change in load is predicted to occur (for example, it is predicted to occur after 300 microseconds, numerically represented as 0x0000012C).

[0043] Next, the chip combines the current temperature situation (for example, the value read from the internal temperature sensor of the chip is 65°C, numerically represented as 0x41), and splices this temperature value with the just obtained target saturation value (85%) into a query code (0x55 + 0x41 = 0x5541). The chip uses this query code to query a pre-stored internal look-up table (magnetic circuit characteristic mapping table) that records the current parameters required at different saturations and temperatures. Through this query, the chip can obtain two specific parameters: one is the required DC current reference value (DC bias current value), and the other is the speed at which the current needs to rise (current climb rate parameter).

[0044] Then, the chip needs to calculate when to start adjusting the current to ensure that the energy storage medium just reaches the target saturation before the predicted load change occurs. The calculation method is as follows: Subtract the shortest time required to reach saturation (200 microseconds) from the start time point of the predicted load change (300 microseconds), and then subtract an additional reserved safety buffer time (such as 20 microseconds). This gives the absolute time point at which the current regulation must start (calculation example: 300 microseconds - 200 microseconds - 20 microseconds = 80 microseconds). A programmable timer (programmable delay unit) inside the chip will be set to send a start signal at this calculated time point (80 microseconds later). When this timer counts down to zero, it will trigger a current waveform generator (step waveform generator) to generate a step-by-step increasing current output sequence according to the previously looked-up current rise speed parameter (for example, this sequence may contain 5 steps, with the current increasing by 0.7 amperes per step and each step lasting for 2 microseconds). At the same time, to reduce interference during current switching, a short suppression pulse (transient voltage suppression pulse) will be applied additionally each time the current step jumps. This current step sequence will be applied to the control coil of the energy storage medium (the main magnetic path control end of the magnetically coupled double winding).

[0045] Finally, to confirm whether the energy storage medium has truly reached the target saturation, the chip continuously monitors the rate of change of the induced voltage across the control coil (the derivative of the induced voltage). When the monitored voltage change rate becomes very small and stabilizes within a preset small fluctuation range (for example, for three consecutive measurements, each separated by 150 nanoseconds, and the voltage change rate remains within plus or minus 5 millivolts per second), the chip determines that the energy storage medium has successfully reached the preset target magnetic flux saturation and is ready to handle the upcoming load transition.

[0046] The overall solution of step 103 above realizes the advanced closed-loop regulation of the state of the energy storage medium through the precise mapping from instruction characteristics to magnetic circuit parameters and temperature adaptive compensation. Combining the accurately timed step-by-step magnetization and physical quantity feedback verification, it breaks through the limitation of the traditional power management's ex-post response to load mutations, significantly enhances the timeliness and stability of energy transmission in burst load scenarios such as video rendering, and provides a reliable guarantee for the hybrid modulation strategy.

[0047] 104. Decompose the instruction stream segment currently executed by the processor, perform waveform similarity matching between the instruction stream segment and the adjusted magnetic flux control current in the chip mode matching unit, and detect a specific instruction combination pattern triggered by video rendering operations based on the matching result; Optionally, step 104 may specifically include the following steps: 1041. Intercept the instruction stream segment currently executed by the processor according to a fixed time window, identify the distribution positions and execution timing relationships of the graphics processing specific operation codes in the instruction stream segment, and generate an instruction event pulse sequence waveform according to the distribution positions and execution timing relationships, where the vertex shader start operation code is marked as a positive pulse and the texture sampling operation code is marked as a negative pulse; Specifically, step 1041 may include the following processes: Set a fixed time window synchronized with the graphics processor instruction cycle, and capture the instruction stream segment executed by the processor within the fixed time window; Identify the first occurrence position of the vertex shader start operation code and the continuous distribution coordinates of the texture sampling operation code in the instruction stream segment through a hardware decoding unit, and record the time interval sequence between the operation codes to characterize the execution timing relationship; Generate a baseline level at the starting point of the fixed time window, generate a positive rectangular pulse when the first occurrence position is detected, where the pulse width is determined by the time interval sequence; Generate a negative rectangular pulse at the occurrence position of the continuous distribution coordinates, and the starting moment of the negative rectangular pulse is dynamically offset according to the execution timing relationship, and the pulse amplitude is proportional to the number of sampling times. Maintain the baseline level during the period without operation codes, and form an instruction event pulse sequence waveform with the positive rectangular pulse and the negative rectangular pulse.

[0048] 1042. Synchronously obtain the actual adjustment waveform of the adjusted flux control current within the fixed time window, and extract the turning point positions and turning directions in the actual adjustment waveform that exceed the preset change rate threshold; 1043. Match the instruction event pulse sequence waveform with the turning point positions and turning directions on the time axis, and determine that the matching is successful when the time deviation between the vertex shader start pulse and the positive pulse turning point during the matching process is less than the set threshold; 1044. When the number of successful matches reaches two consecutive video rendering frame cycles, confirm that a specific instruction combination pattern triggered alternately by vertex shader intensive calculation and texture sampling is detected.

[0049] In the above solution, the instruction event pulse sequence waveform is to convert the graphics processing operation code into a voltage pulse signal with timing characteristics, which is a dynamic waveform reflecting the instruction execution order. The turning point positions and turning directions are the space-time coordinates of the mutation points in the current waveform where the change rate exceeds the set threshold, which mark the direction of the magnetic circuit state switch. The positive direction is for magnetization acceleration, and the negative direction is for demagnetization start. The fixed time window is an acquisition unit locked with the GPU rendering clock, ensuring the unity of the space-time reference of the instruction and current data. The change rate threshold is the threshold value for determining the current mutation, filtering out the interference of the normal fluctuation of the magnetic circuit.

[0050] In the embodiments of the present application, first, through step 1041, a fixed time interval is set to capture the instruction stream segment being executed by the processor, just like intercepting a small segment of code execution record; then, among these segments, the positions and sequences of special instruction types related to graphics processing are identified. For example, when an instruction starting a vertex shader is detected, it is marked as a voltage signal with an upward jump, and when an instruction for texture sampling is detected, it is marked as a voltage signal with a downward jump. And the widths of these signals are determined according to the time intervals between instructions, finally forming a voltage waveform reflecting the dynamic changes of the instructions, which is similar to a sequence of high and low pulses on a timeline; for example, within a 2 - microsecond time window, the system scans three vertex instructions and five texture instructions. According to the time points when the instructions appear, the first vertex instruction generates a +3V pulse at 0.1 microseconds, and the width is based on the instruction execution cycle, such as 0.5 microseconds. At the same time, each texture instruction immediately generates a -2V pulse with a width of 50 nanoseconds, and the other idle times remain at 0V, thus synthesizing a regular pulse curve.

[0051] Next, through step 1042, the actual change waveform of the adjusted flux control current within the same time interval is obtained simultaneously, which is like measuring the fluctuations of the current; analyze the current waveform, calculate the change speed of adjacent sampling points by dividing the current difference between two consecutive points by the time interval, and find the position points where the change speed exceeds the preset limit value. These points are the turning points. An upward change direction is positive, indicating that the current increases rapidly, and a downward change direction is negative, indicating that the current decreases rapidly; for example, using a high - precision sampler to sample the current value every 50 nanoseconds, 40 data points are obtained within a 2 - microsecond window. After calculating the change rate, two turning points are found: the first point has a change rate of +20A / microsecond at 0.3 microseconds, exceeding the 15A / microsecond threshold, and is marked as a positive turning point; the second point has a change rate of -18A / microsecond at 1.5 microseconds and is marked as a negative turning point.

[0052] Then, through step 1043, the generated instruction pulse waveform is aligned and matched with the current turning points on the time axis. Emphasis is placed on checking whether the pulse points of the vertex instructions occur at close time points to the positive turning points of the current. If the time deviation between the two is less than the set tolerance value, it is determined that a single match is successful; for example, on the time axis, taking the rising edge of the first vertex pulse as the reference zero point, for example, the vertex pulse is at 0.1 microseconds, and the closest positive turning point of the current is at 0.3 microseconds. The calculated time difference is 0.2 microseconds, but the system only tolerates a difference ≤100 nanoseconds to judge success, so this time it does not match; in another example, if the pulse is at 0.4 microseconds and the turning point is at 0.35 microseconds, the difference is 50 nanoseconds, less than 100 nanoseconds, then a match flag is generated; for the entire time window, the matching status of all vertex pulses is verified one by one, and all must match to confirm the overall match.

[0053] Finally, the number of successful matches is counted through step 1044. According to the continuous requirement of the video rendering cycle, only when the number of successful matches reaches a certain amount within the set frame cycle, the pattern of alternating vertex shading and texture sampling instructions is confirmed to be detected. For example, in 60Hz video rendering, each frame cycle is 16.7 milliseconds, and it is divided into 8 detection windows internally. At least 15 successful matches need to be accumulated in a total of 33.4 milliseconds for two consecutive frames to trigger confirmation. The specific calculation is as follows: there are 16 windows in two frames, and the actual number of successful matches is 16, exceeding the threshold of 15, then mark that this pattern is detected.

[0054] The overall solution of step 104 above dynamically correlates the spatio-temporal characteristics of the instruction stream and the magnetic circuit current change to accurately identify the alternating pattern of computing-storage load unique to the video rendering scenario. This solution breaks through the limitation of decoupling software instructions and hardware states in traditional power control, establishes a collaborative perception mechanism from processor operations to energy transfer behaviors, provides a highly reliable decision basis for the dynamic switching of hybrid modulation strategies, and significantly improves the energy efficiency adaptation accuracy and system stability in burst load scenarios.

[0055] 105. Write control parameters to the chip modulation logic unit based on the detection result of the specific instruction combination pattern and the magnetic flux saturation of the energy storage medium, and selectively switch the working state combination of the buck-boost hybrid energy conversion mode according to the control parameters.

[0056] Optionally, step 105 may specifically include the following steps: 1051. Analyze the alternating time characteristics of the vertex shading intensive calculation stage and the texture sampling stage in the specific instruction combination pattern, and generate a pattern switching timing parameter set in combination with the magnetic flux saturation value; 1052. Calculate the minimum voltage gain coefficient and the maximum switching frequency threshold required for the boost mode according to the instruction density level of the vertex shading intensive calculation stage and the magnetic flux saturation value; 1053. Based on the storage access frequency and the magnetic flux saturation decay rate of the texture sampling stage, limit the duty cycle adjustment range and the synchronous rectification trigger condition of the buck mode; 1054. Write a comprehensive control parameter package to the chip modulation logic unit, and complete the calculation process of the minimum voltage gain coefficient and the maximum switching frequency threshold through the comprehensive control parameter package in the vertex shading intensive calculation stage, and at the same time switch to the limiting process of the buck mode in the texture sampling stage.

[0057] In the above solution, the mode switching timing parameter set is a set that includes time constraints such as boost / buck mode activation time window and transition protection interval, and is dynamically generated by instruction phase characteristics and flux states. The minimum voltage gain coefficient is the amplification multiple of the output voltage relative to the input voltage in the boost mode, and is dynamically adjusted according to the calculated load demand. The synchronous rectification trigger condition is the determination rule for controlling the conduction of the body diode in the buck mode to prevent the inductor current from flowing back. The instruction density level is the load intensity level (low / medium / high) divided by the number of vertex opcodes appearing per unit time. The magnetic flux saturation attenuation rate is the percentage decrease of the magnetic flux per unit time, reflecting the energy release speed. The integrated control parameter package is a data structure integrating timing / electrical / protection parameters, and supports direct loading by hardware registers.

[0058] In the embodiments of the present application, first, through 1051, analyze the time characteristics of different stages in the detected specific instruction pattern, such as the start and end time points of vertex intensive calculation and texture sampling, and calculate the time interval difference between them. At the same time, combine the magnetic flux saturation of the energy storage medium to generate a time parameter group for controlling the power supply mode switch. For example, when it is found that the vertex calculation stage starts at 200 microseconds, the texture sampling stage starts at 390 microseconds, and the interval between the two stages is 190 microseconds; at this time, if the magnetic flux saturation reaches 85%, exceeding the 80% threshold, the system will extend the end time of the vertex stage by 10 microseconds to end at 400 microseconds, and set a 20-microsecond protection buffer period, and finally output the complete time control parameters: boost mode time window 200 - 400 microseconds, buck mode time window 420 - 510 microseconds, mode switch buffer period 20 microseconds, 400 - 420 microseconds. Subsequently, through 1052, according to the instruction density of the vertex calculation stage, that is, the frequency of instructions appearing per unit time and the current magnetic flux saturation, calculate the minimum voltage boost multiple required for the boost mode, that is, the lowest multiple by which the output voltage is amplified compared to the input voltage, and the highest operating frequency limit of the switching circuit. For example, 9 instructions are detected per microsecond in the vertex calculation stage, which belongs to the high-density level, and the corresponding voltage gain coefficient is 1.28 according to the preset rule, that is, the voltage needs to be boosted by 28%; at the same time, the current magnetic flux saturation is 85%, the base frequency is 1 MHz, and the unit adjustment amount is 0.1 MHz / %, calculate the maximum switching frequency threshold: 1 MHz + (85 - 80) × 0.1 = 1.5 MHz, to ensure that the power supply operates at a safe frequency. At the same time, through 1053, for the texture sampling stage, count its memory access frequency, that is, the number of times of accessing the memory per unit time, and combine the magnetic flux saturation drop rate to determine the switching time ratio range of the buck mode and the special conditions for preventing current reflux. For example, the memory is accessed 12 times per second in the sampling stage, then the lower limit of the switching time ratio is 12 × 2% = 24%; at the same time, it is detected that the magnetic flux drops at a rate of 5% / second, exceeding the 4% / second threshold, and the access frequency meets the standard, and set the synchronous rectification trigger condition as "only allowed to conduct when the inductor current returns to zero" to avoid current backflow damaging the circuit. Finally, through 1054, integrate and package all the foregoing parameters and write them into the chip power control unit to achieve automatic switching of the power supply mode according to the instruction stage. For example, package the time window parameters, voltage gain 1.28, frequency upper limit 1.5 MHz, switching time ratio 24%, current zero-crossing trigger condition, etc. into a 32-byte data packet; write it into the power control register address 0x5000 at high speed through the internal bus. When the processor starts vertex calculation, the boost mode is automatically enabled, running at 1.28 times the voltage and not exceeding 1.5 MHz frequency. When switching to texture sampling, it automatically switches to the buck mode, the switching conduction time is not less than 24%, and the protection mechanism is activated when the current returns to zero.

[0059] The following is a complete embodiment for steps 101 to 105: When the graphics processing unit (GPU) of a laptop computer performs high-load tasks such as rendering 4K videos, the chip executes a set of intelligent power management processes to smoothly handle the drastic fluctuations in current.

[0060] The whole process starts with the monitoring of the current work of the GPU: when the start signal of the screen refresh (rising edge of the vertical synchronization signal) arrives, the chip starts a very short 2-microsecond timing window to "capture" the instructions that the GPU is processing at this moment. For example, at the time point of 3.5 milliseconds, it recognizes a key instruction of "drawing the shape of an object" (vertex shader opcode 0xC1) and generates a specific identification code 0x5A for this instruction combination. At the same time, the ammeter inside the chip (measuring the main power supply line using a tiny 50-milliohm resistor) captures that the current surges from 12.8 amperes to 41.3 amperes within an extremely short time, with a change speed exceeding 30 million amperes per second, and the chip records the waveform of this drastic current jump.

[0061] Next is to establish an experience library: The chip marks the recognized instruction code 0x5A and the monitored peak current of 41.3 amperes with the same time stamp (3,500,000 nanoseconds). It retrieves the data for three consecutive video frame periods (approximately the time period from 3.5 milliseconds to 5.0 milliseconds) for analysis and discovers a pattern: every time the specific instruction code 0x5A appears, only 100 nanoseconds later, the current will surely increase drastically by more than 25 amperes, with an amplitude between 25 and 40 amperes. Then, the chip stores this experience rule of "when seeing the instruction code 0x5A, there will be a large current demand 100 nanoseconds later", together with the amplitude information of the current change, into its "behavior feature library".

[0062] The third step is prediction and advance preparation: When the chip sees that specific 0x5A instruction code again in the current instruction stream, it immediately retrieves the corresponding empirical data from the "behavior feature library": The internal energy storage material needs to reach an "fully charged" state of 85% in advance (saturation 85%). To reach this state, it requires a continuous power supply for at least 180 microseconds (minimum current time 180 μs), and it is predicted that this high current demand will occur 200 microseconds later (expected transition point TS = 200 μs). Considering the current chip temperature is 70 °C, it queries an internal stored look-up table (magnetic circuit mapping table) and obtains two key parameters: A reference current of 3.8 amperes needs to be provided (bias current 3.8 A), and the rate of increase of the current needs to be set at 800,000 amperes per second (ramp rate 0.8 A / μs). The chip calculates the optimal timing to start adjusting the current: The predicted high current demand point (200 microseconds later) minus the minimum time required for preparation (180 microseconds), and then minus the reserved 20 microseconds of safety buffer time. The result is that it must start immediately (0 microseconds later). Then, the current generator inside the chip is immediately triggered to generate a current that increases step by step like a staircase: Starting from 1.9 amperes, each step increases by 0.8 amperes (because the rate is 0.8 A / μs), so the second step is 2.7 amperes (1.9 + 0.8), the third step is 3.5 amperes (2.7 + 0.8), the fourth step is 4.3 amperes (3.5 + 0.8), and the fifth step reaches 5.1 amperes (4.3 + 0.8). The chip continuously monitors the change rate of the voltage across the energy storage material coil. When it is found that this change rate becomes very slow and stabilizes within a tiny range of plus or minus 4 millivolts per second, it is confirmed that the energy storage material has successfully reached the preset 85% "fully charged" state.

[0063] The fourth step is to verify the prediction model: In a later time period (10.0 milliseconds to 12.0 milliseconds), the chip decomposes the instruction stream and identifies that the "draw shape" instruction (0xC1) generates a +3V control pulse at 10.2 milliseconds, and the "apply texture" instruction (0xD8) generates a -2V pulse at 11.1 milliseconds. At the same time, it captures that the current controlling the energy storage material has a sharp upward turn at 10.2001 milliseconds (slope +28 A / μs, increasing 28 million amperes per second), and a sharp downward turn at 11.1003 milliseconds (slope -19 A / μs, decreasing 19 million amperes per second). The chip checks the time matching: The predicted "draw shape" pulse is at 10.2000 milliseconds, and the actual current turn is at 10.2001 milliseconds, with a difference of only 100 nanoseconds, meeting the error standard set by the chip (≤100 ns). By continuously analyzing multiple video frame cycles (total duration 33.4 milliseconds), the success rate of the high degree of temporal coincidence between such instruction pulses and sharp current turns reaches 94%, thus confirming that the prediction established by the chip before that the alternating execution of the "draw shape" and "apply texture" instructions will trigger a specific current pattern is reliable.

[0064] Finally, it is to dynamically optimize the power supply: The chip analyzes in detail the "draw shape" stage (occurring from 200 microseconds to 380 microseconds after the screen refresh signal): The instructions are very dense during this period (processing 9 million instructions per second), and the energy storage material remains at 87% "fully charged" state. The chip calculates that in this stage, the voltage gain needs to be increased by 26% (boost gain 1.26), but the frequency of the power switch is restricted not to exceed 620,000 times per second (switching frequency limit 620 kHz). In the subsequent "apply texture" stage (from 380 microseconds to 500 microseconds after the refresh signal): The access to the memory is very frequent (14 million times per second), and the "fully charged" degree of the energy storage material decreases at a rate of 5.3% per second (magnetic flux decay rate 5.3% / μs). Therefore, the chip sets that the minimum proportion of power output in this stage cannot be lower than 28% (duty cycle lower limit 28%), and requires that the power supply state must be switched at the instant when the current is zero (synchronous rectification condition "current zero crossing"). The chip packs all these optimized parameters (such as boost time period: 200 - 380 μs, buck time period: 380 - 500 μs, as well as specific gain values, frequency upper limit, minimum output proportion, synchronous switching flag), and at the precise moment of 200 microseconds after the screen refresh signal, sends them to the control module responsible for power regulation. In this way, in the "draw shape" stage, the power system stabilizes in the voltage boost mode and operates at a fixed frequency of 620,000 times per second; in the "apply texture" stage, it automatically switches to the voltage reduction mode and intelligently adjusts the proportion of power output between 28% and 80% according to the actual demand. This dynamic adjustment mechanism ensures that the power supply of the GPU is both efficient and stable during high-intensity rendering.

[0065] Through the deep coordination of instruction features and magnetic circuit states, this application realizes the preventive dynamic regulation of the power management chip in the video rendering burst load scenario. It breaks through the limitation of the traditional solution's passive response to the occurred load changes and establishes a closed-loop control chain from processor opcode parsing to energy transfer path optimization: based on instruction-level load prediction, it optimizes the state of the magnetic coupling medium in advance, accurately identifies the rendering pipeline stage through instruction-current waveform matching, and finally realizes the dynamic adaptation of the hybrid modulation strategy and computing tasks. This solution significantly improves the transient response speed and energy transfer efficiency, effectively suppresses voltage fluctuations, and ensures system stability and energy efficiency balance in high-dynamic load scenarios.

[0066] Figure 2 The following is a schematic structural diagram of a dynamic control system for a power management chip based on hybrid modulation provided by an embodiment of this application. As Figure 2 shown, the system includes: An intercept module 31, configured to synchronously intercept the opcode sequence feature identifiers in a continuous time window in the processor instruction pipeline through the chip's built-in instruction decoding unit, and parallelly activate the chip's internal current detection unit to collect the transient power consumption fluctuation curve of the processor power supply circuit within the time window; A construction module 32, configured to align and associate the opcode sequence feature identifier and the transient power consumption fluctuation curve in the chip's configured timing alignment module according to timestamps, extract the load change pattern feature group that repeatedly appears in the association result, and construct a load behavior feature library including multi-level power consumption jump trajectories; An adjustment module 33, configured to adjust the magnetic flux control current of the energy storage medium flowing through the magnetic coupling double winding through the chip's internal drive circuit according to the prediction pattern matching the current opcode segment in the load behavior feature library, so that the energy storage medium enters a preset magnetic flux saturation before the load transition occurs; A matching module 34, configured to decompose the instruction stream segment currently executed by the processor, perform waveform similarity matching between the instruction stream segment and the adjusted magnetic flux control current in the chip's pattern matching unit, and detect a specific instruction combination pattern triggered by video rendering operations based on the matching result; A switching module 35, configured to write control parameters to the chip modulation logic unit based on the detection result of the specific instruction combination pattern and the magnetic flux saturation of the energy storage medium, and selectively switch the working state combination of the buck-boost hybrid energy conversion mode according to the control parameters.

[0067] Figure 2 The described dynamic control system for a power management chip based on hybrid modulation can execute Figure 1For a dynamic control method of a power management chip based on hybrid modulation described in the illustrated embodiment, its implementation principle and technical effects will not be elaborated further. For each module and unit in the dynamic control system of a power management chip based on hybrid modulation in the above embodiment, the specific manner of performing operations has been described in detail in the embodiment related to this method, and will not be elaborated here.

[0068] In a possible design, Figure 2 A dynamic control system of a power management chip based on hybrid modulation in the illustrated embodiment can be implemented as a computing device, such as Figure 3 as shown, this computing device may include a storage component 41 and a processing component 42; The storage component 41 stores one or more computer instructions, and among them, the one or more computer instructions are called and executed by the processing component 42.

[0069] The processing component 42 is used for the Figure 1 dynamic control method of a power management chip based on hybrid modulation in the above

[0070] embodiment. Among them, the processing component 42 may include one or more processors to execute computer instructions to complete all or part of the steps in the above method. Of course, the processing component may also be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components for executing the above method.

[0071] The storage component 41 is configured to store various types of data to support operations on the terminal. The storage component can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0072] Of course, the computing device will necessarily also include other components, such as input / output interfaces, display components, communication components, etc.

[0073] The input / output interface provides an interface between the processing component and the peripheral interface module, and the above peripheral interface module may be an output device, an input device, etc.

[0074] The communication component is configured to facilitate communication between the computing device and other devices in a wired or wireless manner, etc.

[0075] Among them, the computing device can be a physical device or an elastic computing host provided by a cloud computing platform. In this case, the computing device can refer to a cloud server. The above processing components, storage components, etc. can be basic server resources rented or purchased from a cloud computing platform.

[0076] The embodiments of the present application also provide a computer storage medium storing a computer program, and when the computer program is executed by a computer, it can implement the above Figure 1 A dynamic control method for a power management chip based on hybrid modulation shown in the embodiments.

[0077] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0078] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. That is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative effort.

[0079] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the present application.

Claims

1. A dynamic control method for a power management chip based on hybrid modulation, characterized in that: include: The chip's built-in instruction decoding unit synchronously intercepts the opcode sequence feature identifier within a continuous time window in the processor's instruction pipeline, and simultaneously activates the chip's internal current detection unit to collect the transient power consumption fluctuation curve of the processor's power supply circuit within the time window; In a timing alignment module configured in the chip, the opcode sequence feature identifier is associated with the transient power consumption fluctuation curve according to timestamp alignment, a load change pattern feature group that appears repeatedly in the association result is extracted, and a load behavior feature library containing multi-level power consumption transition trajectories is constructed; According to the prediction pattern matching the current operation code fragment in the load behavior feature library, the magnetic flux control current flowing through the energy storage medium of the magnetically coupled dual winding is adjusted by the chip internal drive circuit so that the energy storage medium reaches a preset magnetic flux saturation before the load transition occurs; Decomposing an instruction stream segment currently executed by the processor, performing waveform similarity matching between the instruction stream segment and the adjusted magnetic flux control current in a chip pattern matching unit, and detecting a specific instruction combination pattern triggered by a video rendering operation based on the matching results; Based on the detection result of the specific instruction combination mode and the magnetic flux saturation of the energy storage medium, control parameters are written to the chip modulation logic unit, and the working state combination of the buck and boost hybrid energy conversion mode is selectively switched according to the control parameters.

2. The method according to claim 1, characterized in that The method comprises: adjusting the magnetic flux control current flowing through the energy storage medium of the magnetically coupled dual-winding by the internal driving circuit of the chip according to the prediction pattern matching the current operation code segment in the load behavior feature library, so that the energy storage medium reaches a preset magnetic flux saturation before the load transition occurs. Extracting a prediction pattern matching the current operation code segment from the load behavior feature library, parsing the prediction pattern to obtain a magnetic flux saturation target value, a minimum current duration required to achieve the magnetic flux saturation target value, and a start time point at which a load transition is expected to occur; querying a magnetic circuit characteristic mapping table pre-stored in a non-volatile unit of the chip, and outputting a corresponding DC bias current value and current ramp rate parameter through the magnetic circuit characteristic mapping table according to the magnetic flux saturation target value and the temperature parameter of the energy storage medium; Calculating a current regulation start time based on the starting time point and the minimum current duration, and triggering a step-type current output sequence controlled by the current ramp rate parameter at the current regulation start time through a programmable delay unit of an internal chip driving circuit; The stepped current output sequence is applied to the main magnetic circuit control end of the magnetically coupled dual winding, and the induced voltage differential value of the main magnetic circuit control end is monitored according to the DC bias current value. When the monitored value is stable within a preset threshold range, it is determined that the energy storage medium has reached the target magnetic flux saturation.

3. The method according to claim 1, characterized in that The processor decomposes an instruction stream segment currently executed by the processor, performs waveform similarity matching between the instruction stream segment and the adjusted magnetic flux control current in a chip pattern matching unit, and detects a specific instruction combination pattern triggered by a video rendering operation based on the matching result, including: intercepting an instruction stream segment currently being executed by the processor according to a fixed time window, identifying the distribution position and execution timing relationship of graphics processing-specific opcodes in the instruction stream segment, and generating an instruction event pulse train waveform based on the distribution position and execution timing relationship, wherein the vertex shader activation opcode is marked as a positive pulse and the texture sampling opcode is marked as a negative pulse; Synchronously acquiring an actual regulation waveform of the flux control current after regulation within the fixed time window, and extracting a turning point position and a turning direction exceeding a preset rate of change threshold in the actual regulation waveform; Matching the command event pulse sequence waveform with the turning point position and turning direction on the time axis, and determining that the match is successful when the time deviation between the vertex shader start pulse and the positive pulse turning point during the matching process is less than a set threshold; When the number of successful matches reaches two consecutive video rendering frame cycles, it is confirmed that a specific instruction combination pattern triggered by the alternation of vertex shading intensive calculations and texture sampling is detected.

4. The method according to claim 1, wherein The detection result of the specific instruction combination mode and the magnetic flux saturation of the energy storage medium are used to write control parameters to the chip modulation logic unit, and the working state combination of the step-down and step-up hybrid energy conversion modes is selectively switched according to the control parameters, including: Analyze the alternating time characteristics of the vertex shading intensive calculation phase and the texture sampling phase in the specific instruction combination mode, and combine the magnetic flux saturation value to generate a mode switching timing parameter set; Calculating a minimum voltage gain coefficient and a maximum switching frequency threshold required for a boost mode according to the instruction density level of the vertex shading intensive calculation phase and the magnetic flux saturation value; Based on the memory access frequency and the magnetic flux saturation decay rate in the texture sampling phase, the duty cycle adjustment range and the synchronous rectification triggering condition of the buck mode are limited; A comprehensive control parameter package is written to the chip modulation logic unit, and the calculation process of the minimum voltage gain coefficient and the maximum switching frequency threshold is completed through the comprehensive control parameter package in the vertex shading intensive calculation stage, while the limitation process of switching to the buck mode in the texture sampling stage is completed.

5. The method according to claim 1, wherein The timing alignment module configured in the chip aligns and associates the operation code sequence feature identifier with the transient power consumption fluctuation curve according to the timestamp, extracts the load change pattern feature group that appears repeatedly in the association result, and constructs a load behavior feature library containing multi-level power consumption transition trajectories, including: Marking a corresponding timestamp for the operation code sequence feature identifier at each acquisition moment, and synchronously marking the same timestamp for the sampling points of the transient power consumption fluctuation curve; Based on the corresponding timestamp and the same timestamp, intercepting continuous time periods according to video rendering instruction cycles to generate associated segments including opcode segment combinations and power consumption change profiles within corresponding time periods; Comparing the associated segments in a plurality of consecutive video rendering instruction cycles, and when the same opcode segment combination is detected to be repeated during the comparison process, extracting a load change pattern feature group corresponding to the repeated opcode segment combination; The multi-level power consumption transition trajectory is divided according to the amplitude value of the transition point sequence, and the operation code segment combination and the multi-level power consumption transition trajectory are bound and stored in a load behavior feature library with a multi-level index structure.

6. The method according to claim 3, characterized in that The method includes intercepting an instruction stream segment currently executed by the processor according to a fixed time window, identifying the distribution position and execution timing relationship of graphics processing-specific opcodes in the instruction stream segment, and generating an instruction event pulse sequence waveform based on the distribution position and execution timing relationship, wherein the vertex shader activation opcode is marked as a positive pulse and the texture sampling opcode is marked as a negative pulse, including: Setting a fixed time window synchronized with a graphics processor instruction cycle, and capturing instruction stream segments executed by the processor within the fixed time window; Identifying, by a hardware decoding unit, the first occurrence position of a vertex shader activation opcode and the continuously distributed coordinates of texture sampling opcodes in the instruction stream fragment, and recording a time interval sequence between the opcodes to characterize an execution timing relationship; generating a baseline level at a starting point of the fixed time window and generating a positive rectangular pulse when the first occurrence position is detected, wherein the pulse width is determined by the time interval sequence; A negative rectangular pulse is generated at the appearance position of the continuous distribution coordinates, the starting time of the negative rectangular pulse is dynamically offset according to the execution timing relationship, the pulse amplitude is proportional to the number of sampling times, the baseline level is maintained during the period without operation code, and the positive rectangular pulse and the negative rectangular pulse constitute an instruction event pulse sequence waveform.

7. The method according to claim 2, characterized in that The step of calculating the current regulation start time based on the starting time point and the minimum current duration, and triggering the stepped current output sequence controlled by the current ramp rate parameter at the current regulation start time through a programmable delay unit of an internal chip driving circuit, includes: Taking the starting time point as a reference, the minimum current duration is shifted forward and a protection time margin is added to calculate the current regulation start time; Setting the countdown trigger signal for the current regulation start-up moment in the programmable delay unit, and synchronously loading the current climbing rate parameter to the step waveform generator; When the countdown trigger signal returns to zero, a step current output sequence is generated by the step waveform generator according to the current climbing rate parameter; The step-type current output sequence is output to the main magnetic circuit control end through the power amplifier stage of the driving circuit, and a transient voltage suppression pulse is injected when each step is switched.

8. A power management chip dynamic control system based on hybrid modulation, characterized in that: include: An interception module is used to synchronously intercept the opcode sequence feature identifier within a continuous time window in the processor instruction pipeline through the chip's built-in instruction decoding unit, and in parallel activate the chip's internal current detection unit to collect the transient power consumption fluctuation curve of the processor power supply circuit within the time window; A construction module is used to align and associate the operation code sequence feature identifier with the transient power consumption fluctuation curve according to timestamps in a timing alignment module configured by the chip, extract the load change pattern feature group that repeatedly appears in the association result, and construct a load behavior feature library containing multi-level power consumption transition trajectories; a regulating module, configured to regulate, based on a prediction pattern in the load behavior feature library that matches the current operation code segment, the magnetic flux control current flowing through the energy storage medium of the magnetically coupled dual windings through an internal chip driving circuit, so that the energy storage medium reaches a preset magnetic flux saturation before a load transition occurs; a matching module configured to decompose instruction stream segments currently executed by the processor, perform waveform similarity matching between the instruction stream segments and the adjusted flux control current in a chip pattern matching unit, and detect specific instruction combination patterns triggered by video rendering operations based on the matching results; A switching module is used to write control parameters to the chip modulation logic unit based on the detection results of the specific instruction combination mode and the magnetic flux saturation of the energy storage medium, and selectively switch the working state combination of the buck and boost hybrid energy conversion modes according to the control parameters.

9. A computing device, characterized in that It includes a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component to implement a dynamic control method for a power management chip based on hybrid modulation as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that A computer program is stored, and when the computer program is executed by a computer, a dynamic control method for a power management chip based on hybrid modulation according to any one of claims 1 to 7 is implemented.

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