ECC verification single-bit error correction system in DDR

Abstract

The invention relates to memory error correction, in particular to an ECC check single-bit error correction system in a DDR (Double Data Rate), which comprises a DRAM (Dynamic Random Access Memory) scanner, periodically performs address read traversal operation on a DDR particle DRAM, timely finds a single-bit error of data in the DDR particle DRAM by inquiring an ECC check state in a DDR controller DDRC, and performs correction processing on the single-bit error, so that the error correction efficiency is improved. The error is prevented from being evolved into an uncorrectable multi-bit error; the DDR controller DDRC is used for converting the AXI interface signal into a corresponding DFI interface signal, outputting the DFI interface signal to a DDR physical layer DDR PHY, carrying out ECC verification on read-write data, and storing an ECC verification result to a register, so that a DRAM scanner inquires an ECC verification state; according to the technical scheme, the defects that in the prior art, the processing speed is low, data errors are not found in time, and more CPU resources are occupied can be effectively overcome.

Description

Technical Field

[0001] The present invention relates to memory error correction, and in particular to an ECC check single-bit error correction system in DDR. Background Art

[0002] For the data in DDR particle DRAM, due to the influence of some environmental factors, such as temperature changes, voltage fluctuations, electromagnetic interference, etc., some data bits may be flipped, thereby destroying the accuracy and integrity of the data and causing data errors.

[0003] For the data bit flip problem in DDR DRAM, ECC is currently a relatively effective detection method. Hamming code is a type of ECC check code. Because of its ability to correct single-bit errors and detect double-bit errors, it is widely used to ensure data accuracy and integrity.

[0004] In existing technology, ECC checking of data in DDR DRAM is primarily implemented through software. This involves using software to generate an ECC check code for write data, writing both the write data and the corresponding ECC check code into the DDR DRAM, and then performing ECC decoding and bit error handling on the read data. While this approach implements ECC checking of data in DDR DRAM, it suffers from slow processing speeds, delayed detection of data errors, and high CPU resource consumption. Summary of the Invention

[0005] (1) Technical problems solved

[0006] In view of the above shortcomings of the prior art, the present invention provides an ECC single-bit error correction system in DDR, which can effectively overcome the shortcomings of the prior art such as slow processing speed, untimely data error detection, and high CPU resource consumption.

[0007] (2) Technical solution

[0008] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0009] A DDR ECC single-bit error correction system includes a DRAM scanner, an AXI port arbiter PA, a DDR controller DDRC, a DDR physical layer DDR PHY and a DDR particle strip DIMM;

[0010] The DRAM scanner periodically reads and traverses the addresses of the DDR DRAM. It promptly detects single-bit errors in the data in the DDR DRAM by querying the ECC check status in the DDR controller DDRC, and corrects the single-bit errors to prevent them from becoming uncorrectable multi-bit errors.

[0011] The AXI port arbiter PA arbitrates multiple AXI input ports according to their priorities and selects the AXI input port with the highest priority to output to the DDR controller DDRC.

[0012] The DDR controller DDRC converts the AXI interface signal into the corresponding DFI interface signal and outputs it to the DDR physical layer DDRPHY. It also performs ECC check on the read and write data and stores the ECC check result in the register for the DRAM scanner to query the ECC check status.

[0013] Preferably, the DRAM scanner includes two bus interfaces, an AXI interface and an APB interface;

[0014] AXI interface, sends read and write commands to the AXI port arbiter PA;

[0015] The APB interface reads the status information of the ECC check error stored in the register of the DDR controller DDRC, so as to timely detect the single-bit error of the data in the DDR particle DRAM and correct the single-bit error.

[0016] Preferably, the AXI port arbiter PA includes a data selector Mux1;

[0017] The data selector Mux1 arbitrates the DRAM scanner AXI input port and other AXI input ports according to the priority, and selects the AXI input port with the highest priority and a valid command to output to the DDR controller DDRC at the same time.

[0018] Preferably, the data selector Mux1 includes n+1 AXI input ports, one of which is a DRAM scanner AXI input port fixed for use by the DRAM scanner and has the highest priority, and the other n AXI input ports are used by the CPU or DMA according to actual needs;

[0019] Since the DRAM scanner AXI input port has the highest priority, when the DRAM scanner sends a read or write command, the AXI port arbiter PA will promptly transmit the read or write command to the DDR controller DDRC, allowing the DRAM scanner to traverse the DDR particle DRAM address more quickly and quickly correct single-bit errors.

[0020] Preferably, the DDR controller DDRC includes:

[0021] The controller generates a command Cmd, an address Addr, and write data Wr_data, and receives read data Rd_data_out, a read address Rd_addr_out, and a read data completion enable signal Rddata_last_en;

[0022] The write data ECC processing module generates and processes the ECC check code for the write data Wr_data sent by the controller, and sends the write data Wrdata and the corresponding write data ECC check code ECC_wrdata to the DDR physical layer DDR PHY;

[0023] Read data register, stores the read data Dfi_rddata returned by the DDR physical layer DDR PHY, and sends it to the read data ECC processing module;

[0024] Read data valid register, stores the read data valid value Dfi_rddata_valid returned by the DDR physical layer DDRPHY, and sends the last read data valid value Rddata_last_en of the burst transmission as the read data completion enable signal Rddata_last_en to the controller and read address FIFO;

[0025] Read address FIFO, stores the read address Rd_addr when the read command Rd_cmd is 1, and sends the read address Rd_addr_out when the ECC check error occurs to the controller when the read data completion enable signal Rddata_last_en is 1;

[0026] The read data ECC processing module performs ECC decoding on the read data Dfi_rddata and sends the correctable error flag corr_err, the uncorrectable error flag uncorr_err, the corrected read data Rd_data_out and the single-bit error signal 1bit_err to the controller.

[0027] Preferably, the controller has a group of registers for storing status information when an ECC check error occurs, including a correctable error flag corr_err register, an uncorrectable error flag uncorr_err register, a read data Rd_data_out register, a read address Rd_addr_out register, and an ECC single-bit error Ecc_1bit_err register, so as to query the ECC check status;

[0028] Among them, when the read data completion enable signal Rddata_last_en is 1, the correctable error flag corr_err register, the uncorrectable error flag uncorr_err register, the read data Rd_data_out register and the read address Rd_addr_out register update the values of the corresponding name signals input by the controller;

[0029] When the read data completion enable signal Rddata_last_en is 1 and the DDR controller DDRC is not in the read-modify-write command RMW period, the ECC single-bit error Ecc_1bit_err register stores the value of the single-bit error signal 1bit_err and is automatically cleared after the DRAM scanner reads the value in the ECC single-bit error Ecc_1bit_err register.

[0030] Preferably, the write data ECC processing module includes:

[0031] The data selector Mux2 selects the write data Wr_data output by the controller or the invalid data invalid as the write data Wrdata under the control of the write command Wrcmd output by the controller;

[0032] The ECC generator generates the corresponding ECC check code according to the write data Wr_data output by the controller through the Hamming code;

[0033] Inverter NOT1 inverts the ECC check code to help check whether the DDR DRAM is disconnected. When the write data Wrdata written to the DDR DRAM is all 0, the corresponding ECC check code should be all 0. After inversion, it is all 1. When reading the data in the DDR DRAM, if the read data Rddata and the corresponding read data ECC check code ECC_rddata are all 0, it is considered that the DDR DRAM is disconnected. At this time, the ECC decoder in the read data ECC processing module will have an ECC check error.

[0034] The data selector Mux3 selects the inverted ECC check code output by the inverter NOT1 or invalid data invalid as the write data ECC check code ECC_wrdata under the control of the write command Wrcmd output by the controller.

[0035] Preferably, the read data ECC processing module includes:

[0036] Inverter NOT2 inverts the read data ECC check code ECC_rddata in the read data register;

[0037] The ECC decoder decodes the inverted read data ECC check code ECC_rddata and the read data Rddata in the read data register through Hamming code, and sets the correctable error flag corr_err to 1 when a single-bit error occurs, and sends the corrected data corr_data to the data selector Mux4; and sets the uncorrectable error flag uncorr_err to 1 when a multi-bit error occurs;

[0038] AND gate AND1 receives the correctable error flag corr_err, the inverted value of the uncorrectable error flag uncorr_err and the read data completion enable signal Rddata_last_en, and generates a single-bit error signal 1bit_err;

[0039] The data selector Mux4 selects the corrected data corr_data output by the ECC decoder or the read data Rddata in the read data register as the corrected read data Rd_data_out under the control of the single-bit error signal 1bit_err.

[0040] Preferably, the DDR particle strip DIMM includes a plurality of DDR particle DRAMs, wherein one of the DDR particle DRAMs is used as an ECC DRAM for storing ECC data ECC DATA;

[0041] The DDR controller DDRC communicates with the DDR physical layer DDRPHY via the DFI bus, and the DDR physical layer DDRPHY communicates with the DDR particle DRAM via the command address CA bus and the data DATA bus;

[0042] The data transmitted by the data bus DATA includes normal data DATA and ECC data ECC DATA.

[0043] (3) Beneficial effects

[0044] Compared with the existing technology, the ECC check single-bit error correction system in DDR provided by the present invention realizes the ECC check single-bit error correction function of DDR, can quickly perform ECC check processing on read and write data through hardware DDRC, and timely detect data errors in DDR particle DRAM through software DRAM scanner and correct single-bit errors; at the same time, because ECC check is implemented through hardware, there is no need to occupy additional resources such as CPU, so that resource overhead is significantly reduced; in addition, periodic address traversal and data error processing in DDR particle DRAM are all implemented through software, which reduces the number of hardware logic units and optimizes the system hardware structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0046] Figure 1 A schematic diagram of the system of the present invention;

[0047] Figure 2 For the present invention Figure 1 Schematic diagram of the hardware structure of the DRAM scanner, AXI port arbiter PA and DDR controller DDRC;

[0048] Figure 3 This is a timing diagram of the periodic read command of the DRAM scanner in the present invention;

[0049] Figure 4 This is a command timing diagram of the DRAM scanner for non-single-bit errors in the present invention;

[0050] Figure 5 This is a command timing diagram of the DRAM scanner for single-bit errors in the present invention;

[0051] Figure 6 This is a timing diagram of single-bit error correction during ECC checking in the present invention. DETAILED DESCRIPTION

[0052] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0053] A single-bit ECC error correction system in DDR, such as Figure 1 and Figure 2 As shown, it includes a DRAM scanner, an AXI port arbiter PA, a DDR controller DDRC, a DDR physical layer DDR PHY and a DDR particle strip DIMM;

[0054] The DRAM scanner periodically reads and traverses the addresses of the DDR DRAM. It promptly detects single-bit errors in the data in the DDR DRAM by querying the ECC check status in the DDR controller DDRC, and corrects the single-bit errors to prevent them from becoming uncorrectable multi-bit errors.

[0055] The AXI port arbiter PA arbitrates multiple AXI input ports according to their priorities and selects the AXI input port with the highest priority to output to the DDR controller DDRC.

[0056] The DDR controller DDRC converts the AXI interface signal into the corresponding DFI interface signal and outputs it to the DDR physical layer DDRPHY. It also performs ECC check on the read and write data and stores the ECC check result in the register for the DRAM scanner to query the ECC check status.

[0057] In the technical solution of the present application, the DDR particle strip DIMM includes multiple DDR particle DRAMs, one of which is used as an ECC DRAM for storing ECC data ECC DATA;

[0058] The DDR controller DDRC communicates with the DDR physical layer DDR PHY through the DFI bus, and the DDR physical layer DDR PHY communicates with the DDR DRAM through the command address CA bus and the data DATA bus.

[0059] The data transmitted by the data bus DATA includes normal data DATA and ECC data ECC DATA.

[0060] ①The DRAM scanner includes two bus interfaces, AXI interface and APB interface;

[0061] AXI interface, sends read and write commands to the AXI port arbiter PA;

[0062] The APB interface reads the status information of the ECC check error stored in the register of the DDR controller DDRC, so as to timely detect the single-bit error of the data in the DDR particle DRAM and correct the single-bit error.

[0063] ②AXI port arbiter PA includes data selector Mux1;

[0064] The data selector Mux1 arbitrates the DRAM scanner AXI input port and other AXI input ports according to the priority, and selects the AXI input port with the highest priority and a valid command to output to the DDR controller DDRC at the same time.

[0065] Specifically, the data selector Mux1 includes n+1 AXI input ports, one of which is a DRAM scanner AXI input port that is fixed for use by the DRAM scanner and has the highest priority, and the other n AXI input ports are used by the CPU or DMA according to actual needs;

[0066] Since the DRAM scanner AXI input port has the highest priority, when the DRAM scanner sends a read or write command, the AXI port arbiter PA will promptly transmit the read or write command to the DDR controller DDRC, allowing the DRAM scanner to traverse the DDR particle DRAM address more quickly and quickly correct single-bit errors.

[0067] DDR controller DDRC includes:

[0068] The controller generates a command Cmd, an address Addr, and write data Wr_data, and receives read data Rd_data_out, a read address Rd_addr_out, and a read data completion enable signal Rddata_last_en;

[0069] The write data ECC processing module generates and processes the ECC check code for the write data Wr_data sent by the controller, and sends the write data Wrdata and the corresponding write data ECC check code ECC_wrdata to the DDR physical layer DDR PHY;

[0070] Read data register, stores the read data Dfi_rddata returned by the DDR physical layer DDR PHY, and sends it to the read data ECC processing module;

[0071] Read data valid register, stores the read data valid value Dfi_rddata_valid returned by the DDR physical layer DDRPHY, and sends the last read data valid value Rddata_last_en of the burst transmission as the read data completion enable signal Rddata_last_en to the controller and read address FIFO;

[0072] Read address FIFO, stores the read address Rd_addr when the read command Rd_cmd is 1, and sends the read address Rd_addr_out when the ECC check error occurs to the controller when the read data completion enable signal Rddata_last_en is 1;

[0073] The read data ECC processing module performs ECC decoding on the read data Dfi_rddata and sends the correctable error flag corr_err, the uncorrectable error flag uncorr_err, the corrected read data Rd_data_out and the single-bit error signal 1bit_err to the controller.

[0074] 1) The controller has a set of registers for storing status information when an ECC check error occurs, including the correctable error flag corr_err register, the uncorrectable error flag uncorr_err register, the read data Rd_data_out register, the read address Rd_addr_out register, and the ECC single-bit error Ecc_1bit_err register, to query the ECC check status;

[0075] Among them, when the read data completion enable signal Rddata_last_en is 1, the correctable error flag corr_err register, the uncorrectable error flag uncorr_err register, the read data Rd_data_out register and the read address Rd_addr_out register update the values of the corresponding name signals input by the controller;

[0076] When the read data completion enable signal Rddata_last_en is 1 and the DDR controller DDRC is not in the read-modify-write command RMW period, the ECC single-bit error Ecc_1bit_err register stores the value of the single-bit error signal 1bit_err and is automatically cleared after the DRAM scanner reads the value in the ECC single-bit error Ecc_1bit_err register.

[0077] 2) Write data ECC processing module includes:

[0078] The data selector Mux2 selects the write data Wr_data output by the controller or the invalid data invalid as the write data Wrdata under the control of the write command Wrcmd output by the controller;

[0079] The ECC generator generates the corresponding ECC check code according to the write data Wr_data output by the controller through the Hamming code;

[0080] Inverter NOT1 inverts the ECC check code to help check whether the DDR DRAM is disconnected. When the write data Wrdata written to the DDR DRAM is all 0, the corresponding ECC check code should be all 0. After inversion, it is all 1. When reading the data in the DDR DRAM, if the read data Rddata and the corresponding read data ECC check code ECC_rddata are all 0, it is considered that the DDR DRAM is disconnected. At this time, the ECC decoder in the read data ECC processing module will have an ECC check error.

[0081] The data selector Mux3 selects the inverted ECC check code output by the inverter NOT1 or invalid data invalid as the write data ECC check code ECC_wrdata under the control of the write command Wrcmd output by the controller.

[0082] 3) Read data ECC processing module includes:

[0083] Inverter NOT2 inverts the read data ECC check code ECC_rddata in the read data register;

[0084] The ECC decoder decodes the inverted read data ECC check code ECC_rddata and the read data Rddata in the read data register through Hamming code, and sets the correctable error flag corr_err to 1 when a single-bit error occurs, and sends the corrected data corr_data to the data selector Mux4; and sets the uncorrectable error flag uncorr_err to 1 when a multi-bit error occurs;

[0085] AND gate AND1 receives the correctable error flag corr_err, the inverted value of the uncorrectable error flag uncorr_err and the read data completion enable signal Rddata_last_en, and generates a single-bit error signal 1bit_err;

[0086] The data selector Mux4 selects the corrected data corr_data output by the ECC decoder or the read data Rddata in the read data register as the corrected read data Rd_data_out under the control of the single-bit error signal 1bit_err.

[0087] The technical solution of the present application implements fast ECC check processing and ECC check status storage of read and write data through hardware DDRC, and implements periodic read traversal of DDR particle DRAM through software DRAM scanner. After each read data is returned, the DRAM scanner queries the ECC single-bit error Ecc_1bit_err register of DDRC through the APB interface to determine whether single-bit error correction is required for the current read data, thereby enabling timely correction of single-bit errors in DDR particle DRAM to prevent them from evolving into uncorrectable multi-bit errors.

[0088] The DRAM scanner's periodic read command timing is as follows: Figure 3As shown, the duration Tcycle between time t1 and time t1' is the time it takes for the DRAM scanner to traverse the DDR particle DRAM address once. The user needs to configure this duration based on the data flipping characteristics of the DDR particle DRAM. According to the number N of DDR particle DRAM addresses, the DRAM scanner sends a read command every time interval Tint, where Tint = Tcycle / N, thereby realizing the DRAM scanner's periodic traversal of the DDR particle DRAM address.

[0089] For the Tint duration, the DRAM scanner command timing and the timing of ECC single-bit error correction are as follows: Figures 4 to 6 As shown in Figure 2. At time t1, the DRAM scanner sends a read command RDn with address n. After the Txr time, at time t3, the corresponding read data Rd datan is returned. Figure 6 As shown, Txr = T1 + T2 + T3 + RL + T4 + BL + T5, where T1 is the delay time of the command from the DRAM scanner to the DDRC; T2 is the delay time of the command from the DDRC to the DFI; T3 is the delay time of the command from the DFI to the DRAM; RL is the time from the DRAM receiving the read command to the sending of the read data; BL is the time of one burst of read and write data; T4 is the delay time of the read data from the DRAM to the DFI; T5 is the delay time of the read data from the DFI to the DRAM scanner;

[0090] exist Figure 6 At time t6, the read data is ECC-checked within the DDRC. If a single-bit error occurs, the value of the ECC single-bit error Ecc_1bit_err register is set to 1. Otherwise, the value of the ECC single-bit error Ecc_1bit_err register remains unchanged.

[0091] At time t3, the DRAM scanner sends a read request to the ECC single-bit error Ecc_1bit_err register through the APB interface. After time Tpr, at time t4, the value of the ECC single-bit error Ecc_1bit_err register is returned to the DRAM scanner through the APB interface. The ECC single-bit error Ecc_1bit_err register is automatically cleared after receiving the read request.

[0092] At time t4, if the register value read by the DRAM scanner is 0, the DRAM scanner will not perform any processing and will remain idle until time t2. Figure 4 As shown; at time t4, if the register value read by the DRAM scanner is 1, the DRAM scanner sends a write command MASKWRn with a mask function at address n, as shown Figure 5 and Figure 6As shown in FIG, after the command is transmitted to the DDRC, a read-modify-write command RMW is generated according to the DDR protocol. That is, the DDRC first sends a read command of address n, and waits for the read data datan to be returned to the DDRC. The DDRC then sends a write command of address n. The write data corresponding to the write command is the previous read data datan. The write data is written into the DRAM until time t5.

[0093] The duration between time t4 and time t5 is Txmw, such as Figure 6 As shown, Txmw = T1 + T2*2 + T3*2 + RL + T4 + BL*2 + WL, where WL is the time from when the DRAM receives the write command to when it sends the write data;

[0094] The time interval between the DDRC controller sending a read command RDn and sending a write command WRn is Trmw, where Trmw = T2 + T3 + RL + T4 + BL, which is the RMW duration of the DDRC read, modify, and write command. During the Trmw duration, the DDRC cannot send other valid commands. At time t7, regardless of the value of the single-bit error signal 1bit_err, the value of the ECC single-bit error Ecc_1bit_err register remains unchanged.

[0095] After time t5, the DRAM scanner does not perform any processing and remains idle until time t2. Figure 5 As shown;

[0096] At time t2, the DRAM scanner sends the next read command with address n+1, and the subsequent command timing repeats Figure 4 or Figure 5 .

[0097] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A single-bit error correction system for ECC in DDR, characterized by: Includes DRAM scanner, AXI port arbiter PA, DDR controller DDRC, DDR physical layer DDR PHY and DDR particle strip DIMM; The DRAM scanner periodically reads and traverses the addresses of the DDR DRAM. It promptly detects single-bit errors in the data in the DDR DRAM by querying the ECC check status in the DDR controller DDRC, and corrects the single-bit errors to prevent them from becoming uncorrectable multi-bit errors. The AXI port arbiter PA arbitrates multiple AXI input ports according to their priorities and selects the AXI input port with the highest priority to output to the DDR controller DDRC. The DDR controller DDRC converts the AXI interface signal into the corresponding DFI interface signal and outputs it to the DDR physical layer DDR PHY. It also performs ECC check on the read and write data and stores the ECC check result in the register for the DRAM scanner to query the ECC check status.

2. The ECC single-bit error correction system in DDR according to claim 1, characterized in that: The DRAM scanner includes two bus interfaces, an AXI interface and an APB interface; AXI interface, sends read and write commands to the AXI port arbiter PA; The APB interface reads the status information of the ECC check error stored in the register of the DDR controller DDRC, so as to timely detect the single-bit error of the data in the DDR particle DRAM and correct the single-bit error.

3. The ECC single-bit error correction system in DDR according to claim 1, characterized in that: The AXI port arbiter PA includes a data selector Mux1; The data selector Mux1 arbitrates the DRAM scanner AXI input port and other AXI input ports according to the priority, and selects the AXI input port with the highest priority and a valid command to output to the DDR controller DDRC at the same time.

4. The ECC single-bit error correction system in DDR according to claim 3, characterized in that: The data selector Mux1 includes n+1 AXI input ports, one of which is a DRAM scanner AXI input port fixed for use by the DRAM scanner and has the highest priority, and the other n AXI input ports are used by the CPU or DMA according to actual needs; Since the DRAM scanner AXI input port has the highest priority, when the DRAM scanner sends a read or write command, the AXI port arbiter PA will promptly transmit the read or write command to the DDR controller DDRC, allowing the DRAM scanner to traverse the DDR particle DRAM address more quickly and quickly correct single-bit errors.

5. The ECC single-bit error correction system in DDR according to claim 1, characterized in that: The DDR controller DDRC includes: The controller generates a command Cmd, an address Addr, and write data Wr_data, and receives read data Rd_data_out, a read address Rd_addr_out, and a read data completion enable signal Rddata_last_en; The write data ECC processing module generates and processes the ECC check code for the write data Wr_data sent by the controller, and sends the write data Wrdata and the corresponding write data ECC check code ECC_wrdata to the DDR physical layer DDR PHY; Read data register, stores the read data Dfi_rddata returned by the DDR physical layer DDR PHY, and sends it to the read data ECC processing module; Read data valid register, stores the read data valid value Dfi_rddata_valid returned by the DDR physical layer DDRPHY, and sends the last read data valid value Rddata_last_en of the burst transmission as the read data completion enable signal Rddata_last_en to the controller and read address FIFO; Read address FIFO, stores the read address Rd_addr when the read command Rd_cmd is 1, and sends the read address Rd_addr_out when the ECC check error occurs to the controller when the read data completion enable signal Rddata_last_en is 1; The read data ECC processing module performs ECC decoding on the read data Dfi_rddata and sends the correctable error flag corr_err, the uncorrectable error flag uncorr_err, the corrected read data Rd_data_out and the single-bit error signal 1bit_err to the controller.

6. The ECC single-bit error correction system in DDR according to claim 5, characterized in that: The controller has a group of registers for storing status information when an ECC check error occurs, including a correctable error flag corr_err register, an uncorrectable error flag uncorr_err register, a read data Rd_data_out register, a read address Rd_addr_out register, and an ECC single-bit error Ecc_1bit_err register, so as to query the ECC check status; Among them, when the read data completion enable signal Rddata_last_en is 1, the correctable error flag corr_err register, the uncorrectable error flag uncorr_err register, the read data Rd_data_out register and the read address Rd_addr_out register update the values of the corresponding name signals input by the controller; When the read data completion enable signal Rddata_last_en is 1 and the DDR controller DDRC is not in the read-modify-write command RMW period, the ECC single-bit error Ecc_1bit_err register stores the value of the single-bit error signal 1bit_err and is automatically cleared after the DRAM scanner reads the value in the ECC single-bit error Ecc_1bit_err register.

7. The ECC single-bit error correction system in DDR according to claim 5, characterized in that: The write data ECC processing module includes: The data selector Mux2 selects the write data Wr_data output by the controller or the invalid data invalid as the write data Wrdata under the control of the write command Wrcmd output by the controller; The ECC generator generates the corresponding ECC check code according to the write data Wr_data output by the controller through the Hamming code; Inverter NOT1 inverts the ECC check code to help check whether the DDR DRAM is disconnected. When the write data Wrdata written to the DDR DRAM is all 0, the corresponding ECC check code should be all 0. After inversion, it is all 1. When reading the data in the DDR DRAM, if the read data Rddata and the corresponding read data ECC check code ECC_rddata are all 0, it is considered that the DDR DRAM is disconnected. At this time, the ECC decoder in the read data ECC processing module will have an ECC check error. The data selector Mux3 selects the inverted ECC check code output by the inverter NOT1 or invalid data invalid as the write data ECC check code ECC_wrdata under the control of the write command Wrcmd output by the controller.

8. The ECC single-bit error correction system in DDR according to claim 5, characterized in that: The read data ECC processing module includes: Inverter NOT2 inverts the read data ECC check code ECC_rddata in the read data register; The ECC decoder decodes the inverted read data ECC check code ECC_rddata and the read data Rddata in the read data register through Hamming code, and sets the correctable error flag corr_err to 1 when a single-bit error occurs, and sends the corrected data corr_data to the data selector Mux4; and sets the uncorrectable error flag uncorr_err to 1 when a multi-bit error occurs; AND gate AND1 receives the correctable error flag corr_err, the inverted value of the uncorrectable error flag uncorr_err and the read data completion enable signal Rddata_last_en, and generates a single-bit error signal 1bit_err; The data selector Mux4 selects the corrected data corr_data output by the ECC decoder or the read data Rddata in the read data register as the corrected read data Rd_data_out under the control of the single-bit error signal 1bit_err.

9. The ECC single-bit error correction system in DDR according to any one of claims 1 to 8, characterized in that: The DDR particle strip DIMM includes a plurality of DDR particle DRAMs, wherein one DDR particle DRAM is used as an ECC DRAM for storing ECC data ECC DATA; The DDR controller DDRC communicates with the DDR physical layer DDRPHY via the DFI bus, and the DDR physical layer DDRPHY communicates with the DDR particle DRAM via the command address CA bus and the data DATA bus; The data transmitted by the data bus DATA includes normal data DATA and ECC data ECC DATA.

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