Clock tree delay matching method and device, equipment and storage medium

Abstract

The invention relates to the field of FPGA (field programmable gate array) technology, and discloses a clock tree delay matching method, device and equipment and a storage medium, the method is applied to an FPGA system comprising a main clock tree and a copy path, and the programmable bit setting of a clock tree architecture and a clock switching center of the copy path is consistent with that of the main clock tree. Comprising the following steps: dynamically synchronizing SWH configuration of a main clock tree and a copy path by constructing the copy path which has the same clock tree architecture as the main clock tree and has a programmable bit of a clock switching center, so that the transmission delay of the copy path is matched with the delay change of the main clock tree in real time; a feedback clock signal generated by the copy path is compared with a reference clock signal in phase, a delay line is controlled by adjusting the voltage of the main clock tree, and automatic delay alignment of the main clock tree and the data path is achieved. Through cooperative configuration of a copy path and a main clock tree, the problem of phase mismatching of a clock signal and a data path caused by application configuration difference in a traditional FPGA is solved.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to a clock tree delay matching method, device, equipment and storage medium. Background Art

[0002] In FPGAs (Field-Programmable Gate Arrays), the signal distribution of the clock tree directly impacts the chip's timing performance and reliability. Traditional FPGA clock tree designs typically rely on fixed feedback mechanisms (such as delay-locked loops (DLLs) and voltage-controlled delay lines (VCDLs)) to align the phases of clock and data signals. However, because the FPGA's clock tree topology dynamically changes with the configuration of different applications, fixed feedback circuits are unable to adapt to this variability. This results in mismatches between the propagation delay of the main clock tree and the delay of the feedback path, causing clock-data skew and, in turn, timing violations (such as setup / hold time conflicts).

[0003] Therefore, there is an urgent need for a delay matching method that can dynamically adapt to changes in FPGA clock tree configuration to address the limitations of the traditional fixed feedback mechanism. Summary of the Invention

[0004] In view of this, the present invention provides a clock tree delay matching method, apparatus, device and storage medium to address the limitations of the traditional fixed feedback mechanism. The technical solution is as follows.

[0005] In a first aspect, the present invention provides a clock tree delay matching method, which is applied to an FPGA system including a main clock tree and a replica path, wherein the clock tree architecture and the programmable bit settings of the clock switching center of the replica path are consistent with those of the main clock tree, and the method comprises:

[0006] In response to a configuration update of a clock switching center programmable bit of the primary clock tree, adjusting the clock switching center programmable bit of the replica path to cause a propagation delay of the replica path to match that of the primary clock tree;

[0007] generating a feedback clock signal corresponding to the propagation delay of the main clock tree through the replica path;

[0008] The feedback clock signal is compared with the reference clock signal in phase, and the transmission delay of the voltage-controlled delay line of the master clock tree is adjusted according to the comparison result to match the delay of the master clock tree with that of the data path.

[0009] The clock tree delay matching method provided by the present invention constructs a replica path with the same clock tree architecture and clock switch hub (SWH) programmable bit configuration as the main clock tree. When the SWH configuration of the main clock tree is updated, the SWH programmable bits of the replica path are synchronously adjusted, so that the transmission delay of the replica path tracks the dynamic changes of the main clock tree in real time. The phase comparison result of the feedback clock signal generated by the replica path and the reference clock signal is automatically adjusted to adjust the transmission delay of the voltage-controlled delay line (VCDL) of the main clock tree, thereby directly eliminating the phase deviation between the main clock tree and the data path. Through the coordinated dynamic configuration of the replica path and the main clock tree, this method realizes automatic matching of the FPGA clock tree delay, solves the clock-data signal skew problem caused by the traditional fixed feedback mechanism that cannot adapt to the changes in the main clock tree topology, and significantly improves the timing consistency and reliability of the FPGA system.

[0010] In an optional implementation, the clock tree architecture of the main clock tree and the replica path is an H-type structure, which includes a central switching node and symmetrically distributed hierarchical wiring.

[0011] The clock tree delay matching method provided by the present invention adopts an H-shaped clock tree architecture for the master clock tree and the replica path, which includes a central switching node and symmetrically distributed hierarchical wiring. By adopting the H-shaped clock tree architecture and utilizing the structural characteristics of its central switching node and symmetrical hierarchical wiring, the wiring delay distribution of the master clock tree and the replica path is geometrically symmetrical, thereby reducing delay deviation caused by differences in wiring paths. The symmetrical layout of the H-shaped structure ensures that the delay change trends of the master path and the replica path are consistent under the same SWH configuration, further improving the accuracy of delay matching between the two.

[0012] In an optional embodiment, the method further includes:

[0013] When the programmable bit of the clock switching center of the main clock tree is updated, the programmable bit of the clock switching center of the replica path is synchronously updated within a set clock cycle.

[0014] The clock tree delay matching method provided by this invention synchronizes the programmable bits of the SWH of the replica path within a set clock cycle when the programmable bits of the SWH of the master clock tree are updated. By setting a synchronous update period, the SWH configuration of the replica path keeps pace with dynamic changes in the master clock tree, avoiding feedback clock signal distortion caused by configuration update delays. This mechanism enables the replica path to track dynamic configuration changes of the master path in real time, thereby maintaining delay matching accuracy between the master and replica paths.

[0015] In an optional implementation, adjusting a programmable bit of a clock switching center of a replica path includes:

[0016] The configuration file of the FPGA system is loaded to update the programmable bit of the clock switching center of the replication path. The configuration file includes a mapping relationship table between the main clock tree and the clock switching center of the replication path.

[0017] The clock tree delay matching method provided by this invention updates the SWH programmable bits of the replica path by loading an FPGA configuration file. The configuration file contains a SWH mapping table for the primary and replica paths. This SWH mapping table in the configuration file ensures that the configuration update logic of the primary and replica paths is completely consistent, avoiding human programming errors. This automated mapping ensures configuration synchronization between the primary and replica paths, thereby improving the reliability and repeatability of delay matching.

[0018] In an optional embodiment, the method further includes:

[0019] When it is detected that the timing deviation between the main clock tree and the data path exceeds a preset threshold or a reconfiguration instruction is received, a configuration file is loaded to update the programmable bit of the clock switching center of the replica path.

[0020] The clock tree delay matching method provided by this invention triggers a SWH update for the replica path when the timing deviation between the primary and data paths exceeds a threshold or when a reconfiguration instruction is received. By proactively detecting timing deviations or responding to external instructions, the delay matching mechanism is triggered on demand, avoiding unnecessary configuration updates. This mechanism reduces the dynamic power consumption of the FPGA system while ensuring delay matching accuracy and enhancing its adaptability to sudden configuration changes.

[0021] In an optional implementation, performing a phase comparison between the feedback clock signal and the reference clock, and adjusting a transmission delay of a voltage-controlled delay line of the master clock tree according to the comparison result, includes:

[0022] Inputting the feedback clock signal into the feedback input terminal of the phase comparator and inputting the reference clock signal into the reference input terminal of the phase comparator to obtain the phase difference between the feedback clock signal and the reference clock; the phase comparator is a phase-locked loop or a delay-locked loop;

[0023] generating an error control signal according to the phase difference;

[0024] The propagation delay of the voltage-controlled delay line of the master clock tree is adjusted by the error control signal.

[0025] The clock tree delay matching method provided by this invention uses a phase comparator, a phase-locked loop (PLL) or delay-locked loop (DLL), to generate an error control signal based on the phase difference to adjust the VCDL delay of the master clock tree. The optional PLL or DLL scheme provides a flexible phase comparison mechanism to meet the clock accuracy and response speed requirements of different application scenarios. PLLs are suitable for precise locking of high-frequency clocks, while DLLs offer lower power consumption in low-frequency scenarios. The combination of the two expands the applicability of the method.

[0026] In summary, the clock tree delay matching method provided by the present invention provides a structural consistency basis for the delay synchronization matching of the replica path and the main path by constructing a replica path with the same H-type clock tree architecture as the main clock tree, and utilizing the geometric characteristics of its central switching node and symmetrical hierarchical wiring; on this basis, the SWH programmable bit configuration of the main path and the replica path is dynamically synchronized and updated, and by loading a configuration file containing the master-replica SWH mapping relationship table, the configuration logic of the two is forced to be completely associated, ensuring that the transmission delay of the replica path tracks the dynamic changes of the main path in real time; further combined with the timing deviation threshold detection or external instruction trigger mechanism, the configuration update is triggered only when necessary, avoiding redundant operations and reducing power consumption, and the optional PLL / DLL phase comparator flexibly selects high-frequency locking or low-power adjustment mode according to the application scenario requirements to form a closed-loop feedback control. The above technical features, through a layer-by-layer progressive design that ensures architectural symmetry, dynamic configuration synchronization, on-demand triggered updates, and feedback mode adaptation, enable the replication path to accurately reproduce the delay characteristics of the main clock tree, and then automatically adjust the VCDL transmission delay of the main path through phase comparison results, ultimately achieving adaptive delay matching between the main clock tree and the data path. This systematically solves the clock-data skew problem caused by the fixed feedback mechanism of the traditional FPGA clock tree that cannot adapt to dynamic configuration, significantly improving timing reliability, energy efficiency, and applicability in multiple scenarios.

[0027] In a second aspect, the present invention provides a clock tree delay matching device, which is applied to an FPGA system including a main clock tree and a replica path, wherein the clock tree architecture and the programmable bit setting of the clock switching center of the replica path are consistent with those of the main clock tree, and the device includes:

[0028] an update module, configured to adjust the clock switching center programmable bits of the replica path in response to a configuration update of the clock switching center programmable bits of the master clock tree so that a transmission delay of the replica path matches that of the master clock tree;

[0029] a generation module, configured to generate a feedback clock signal corresponding to a transmission delay of a main clock tree through a replication path;

[0030] The adjustment module is used to compare the phase of the feedback clock signal with the reference clock signal, and adjust the transmission delay of the voltage-controlled delay line of the main clock tree according to the comparison result to match the delay of the main clock tree with that of the data path.

[0031] In an optional embodiment, the adjustment module is specifically configured to:

[0032] Inputting the feedback clock signal into the feedback input terminal of the phase comparator and inputting the reference clock signal into the reference input terminal of the phase comparator to obtain the phase difference between the feedback clock signal and the reference clock; the phase comparator is a phase-locked loop or a delay-locked loop;

[0033] generating an error control signal according to the phase difference;

[0034] The propagation delay of the voltage-controlled delay line of the master clock tree is adjusted by the error control signal.

[0035] In an optional embodiment, the device further comprises:

[0036] The synchronous updating module is configured to synchronously update the programmable bit of the clock switching center of the replica path within a set clock cycle when the programmable bit of the clock switching center of the master clock tree is updated.

[0037] In an optional implementation, the generating module is specifically configured to:

[0038] The configuration file of the FPGA system is loaded to update the programmable bit of the clock switching center of the replication path, wherein the configuration file includes a mapping relationship table between the main clock tree and the clock switching center of the replication path.

[0039] In an optional implementation, the update module is further configured to:

[0040] When it is detected that the timing deviation between the main clock tree and the data path exceeds a preset threshold or a reconfiguration instruction is received, the configuration file is loaded to update the clock switching center programmable bit of the replica path.

[0041] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the clock tree delay matching method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0042] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the clock tree delay matching method of the first aspect or any corresponding embodiment thereof.

[0043] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, where the computer instructions are used to enable a computer to execute the clock tree delay matching method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 is a schematic diagram of a traditional clock tree matching method according to an embodiment of the present invention;

[0046] Figure 2 is a flow chart of a clock tree delay matching method according to an embodiment of the present invention;

[0047] Figure 3 is a schematic diagram of an FPGA clock tree delay matching method according to an embodiment of the present invention;

[0048] Figure 4 is a schematic diagram of a replication path according to an embodiment of the present invention;

[0049] Figure 5 is a schematic diagram of an H-type clock tree in an FPGA according to an embodiment of the present invention;

[0050] Figure 6 is a structural block diagram of a clock tree delay matching device according to an embodiment of the present invention;

[0051] Figure 7 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0053] In the field of FPGA (Field Programmable Gate Array) technology, the signal distribution of the clock tree is the core link that affects the timing performance and reliability of the chip. Traditional clock tree design often uses the feedback mechanism of delay locked loop (DLL) and voltage controlled delay line (VCDL), such as Figure 1 As shown in the figure, phase alignment is used to reduce the skew of the clock signal and data path. Data / clock mismatch at the final flip-flop may cause data / clock skew and is not suitable for FPGA applications. For example, the DLL controls the phase difference between the feedback clock and the reference clock within a single clock cycle by adjusting the delay of the VCDL, thereby ensuring timing convergence. This method performs well in scenarios with fixed clock topology, but the dynamic programmable nature of FPGAs causes its clock tree path to change significantly with different application configurations (such as switching clock network levels or routing paths). In this case, the feedback path of the traditional fixed architecture cannot synchronously adapt to the dynamic configuration of the main clock tree, resulting in a mismatch between the feedback delay and the actual delay of the main path, causing the accumulation of clock-data phase deviation, and ultimately causing timing violations (such as setup / hold time conflicts).

[0054] Existing technologies are limited in two key areas. First, the DLL's feedback path typically utilizes a different hardware architecture or routing scheme than the main clock tree, making its delay characteristics unable to track the dynamic changes of the main path in real time. For example, when the main clock tree adjusts its routing due to programmable bit updates in the SWH (clock switching hub), the delay of the fixed feedback path remains based on the initial configuration, resulting in distorted phase comparison results. Second, the diverse topologies of FPGA clock trees (e.g., global H-shaped clock trees and local tree structures) require architecturally compatible feedback mechanisms. However, traditional solutions, relying on fixed feedback circuits (e.g., a single ring VCDL), struggle to adapt to the delay matching requirements of diverse clock tree configurations. In particular, in multi-layered, highly symmetrical H-shaped clock trees, asymmetric feedback paths introduce additional routing deviations, exacerbating clock skew.

[0055] In response to the above problems, there is an urgent need in this field for a delay matching mechanism that can dynamically adapt to changes in the FPGA clock tree configuration. Existing attempts at improvement (such as segmented DLLs or programmable feedback paths) have partially improved flexibility, but still have defects such as configuration update lags, high dependence on manual calibration, or surges in power consumption. For example, segmented DLLs require manual division of delay line intervals and cannot be dynamically linked with the SWH programmable bits of the main clock tree; and although the programmable feedback path supports hardware reconstruction, it lacks a collaborative configuration mechanism with the main path, resulting in low calibration efficiency. These defects seriously restrict the timing reliability and dynamic adaptability of FPGAs in scenarios such as high-performance computing and real-time signal processing.

[0056] Therefore, an embodiment of the present invention provides a clock tree delay matching method, which is applied to an FPGA system including a main clock tree and a replica path. The clock tree architecture and the programmable bit setting of the clock switching center of the replica path are consistent with those of the main clock tree. The process of the method is as follows: Figure 2 As shown, the following steps are included:

[0057] S201 : In response to a configuration update of a clock switching center programmable bit of a primary clock tree, adjust a clock switching center programmable bit of a replica path to make a transmission delay of the replica path match that of the primary clock tree.

[0058] Specifically, the trigger condition is a configuration update of the programmable bits in the clock switch hub (SWH) of the primary clock tree. The SWH settings of the replica path must match those of the primary clock tree, so the adjustment operation forces synchronization of the two configurations. By synchronizing the SWH configuration, the replica path's delay characteristics, such as physical routing levels and switch nodes, remain consistent with those of the primary path.

[0059] S202 : Generate a feedback clock signal corresponding to the transmission delay of the main clock tree through the replication path.

[0060] Specifically, the replica path's architecture is consistent with the primary clock tree, and the feedback clock signal it generates necessarily reflects the primary path's actual delay. Because the replica path's SWH configuration is synchronized with the primary path, its delay characteristics completely mimic those of the primary path, so the feedback clock signal carries the primary path's actual delay information.

[0061] S203 : performing a phase comparison between the feedback clock signal and the reference clock signal, and adjusting the transmission delay of the voltage-controlled delay line of the master clock tree according to the comparison result, so as to match the delay of the master clock tree with that of the data path.

[0062] Specifically, by comparing the phase difference between the feedback clock signal and the reference clock signal (usually the system master clock or an external reference clock), an error control signal is generated. This signal is used to dynamically adjust the transmission delay of the VCDL in the master clock tree, ultimately achieving delay alignment between the master clock tree and the data path. Through a closed-loop feedback mechanism, the dynamic delay fluctuations of the master clock tree are compensated in real time to within the timing window of the data path. This solves the timing mismatch problem caused by traditional open-loop control (such as fixed delay lines) that cannot adapt to FPGA configuration changes, significantly improving the system's timing convergence capability.

[0063] In the clock tree delay matching method of this embodiment, the clock tree architecture of the main clock tree and the replica path is an H-type structure, and the H-type structure includes a central switching node and symmetrically distributed hierarchical wiring. The H-type clock tree is a topological structure with a central switching node (i.e., the central hub for clock signal distribution) and symmetrical hierarchical wiring (wire branches that are symmetrical left and right or up and down). For example, the clock signal starts from the central node and extends symmetrically to the left and right sides to the clock drive units at all levels. The main path and the replica path use the same H-type architecture to ensure that the wiring paths of the two are completely consistent in geometric distribution, hierarchical depth and node position. Symmetrical wiring reduces the additional delay deviation caused by the physical layout differences between the main path and the replica path, so that the transmission delay change trends of the two are consistent, thereby improving the matching accuracy.

[0064] Optionally, the clock tree delay matching method of this embodiment also includes: when the programmable bit of the clock switching center of the main clock tree is updated, the programmable bit of the clock switching center of the replica path is synchronously updated within the set clock cycle. Specifically, the SWH configuration of the main path changes (such as the user modifies the clock network hierarchy or the tool automatically optimizes the wiring). The SWH of the replica path must complete the synchronous update within a preset clock cycle (for example, 1-10 clock cycles) to ensure the dynamic consistency of the configurations of the two. By limiting the time window for synchronous updates, feedback signal distortion caused by configuration lag in the replica path is avoided, and the real-time delay matching of the main path and the replica path is maintained. Fast synchronization reduces the risk of phase difference accumulation introduced by configuration update delays, ensuring the stability of closed-loop control.

[0065] Optionally, in the above step 201, adjusting the programmable bit of the clock switching center of the copy path includes: loading the configuration file of the FPGA system to update the programmable bit of the clock switching center of the copy path, and the configuration file includes a mapping relationship table between the main clock tree and the clock switching center of the copy path. The binary or text file generated by the FPGA development tool contains the SWH configuration parameters of the main path and its correspondence with the copy path. The mapping rules of each SWH programmable bit of the main path (such as the clock switching node number, the routing level selection bit) and the corresponding bit of the copy path are clarified. By loading the configuration file, the SWH update of the copy path is automatically completed to avoid configuration errors caused by manual intervention. The mapping relationship table forces the SWH bits of the main path and the copy path to correspond one to one to ensure that the configuration logic of the two is completely synchronized.

[0066] Optionally, the clock tree delay matching method of this embodiment further includes: loading a configuration file to update the programmable bits of the clock switching center of the replica path when the timing deviation between the master clock tree and the data path exceeds a preset threshold or a reconfiguration instruction is received. Receiving a reconfiguration instruction from a user or upper-layer system (such as an FPGA dynamic reconfiguration command), and detecting the phase deviation between the master clock tree and the data path (e.g., insufficient setup time margin) in real time using a timing analysis tool or hardware monitoring circuit.

[0067] Optionally, in the above step 203, the feedback clock signal is phase-compared with the reference clock, and the transmission delay of the voltage-controlled delay line of the main clock tree is adjusted according to the comparison result, including: inputting the feedback clock signal into the feedback input end of the phase comparator, and inputting the reference clock signal into the reference input end of the phase comparator to obtain the phase difference between the feedback clock signal and the reference clock; the phase comparator is a phase-locked loop or a delay-locked loop; generating an error control signal according to the phase difference; and adjusting the transmission delay of the voltage-controlled delay line of the main clock tree through the error control signal.

[0068] In the above steps, the phase comparator is a phase-locked loop (PLL) or delay-locked loop (DLL), which generates an error signal based on the phase difference to adjust the VCDL delay of the main path. PLL is suitable for precise phase locking of high-frequency clock signals, adjusting the frequency and phase through a voltage-controlled oscillator (VCO). DLL is suitable for low-frequency scenarios, directly aligning the clock edge by adjusting the delay of the VCDL, and has low power consumption. Two optional solutions, PLL and DLL, are provided to adapt to different application scenarios (such as high-frequency computing and low-power sensing). PLL provides higher accuracy at high frequencies, while DLL reduces power consumption at low frequencies, enhancing the versatility of the method.

[0069] In summary, the clock tree delay matching method provided by the embodiment of the present invention provides a structural consistency basis for delay synchronization matching between the replica path and the main path by constructing a replica path with the same H-type clock tree architecture as the main clock tree, and utilizing the geometric characteristics of its central switch node and symmetrical hierarchical wiring. On this basis, the SWH programmable bit configuration of the main path and the replica path is dynamically synchronized and updated. By loading a configuration file containing a master-replica SWH mapping relationship table, the configuration logic of the two is forced to be completely associated, ensuring that the transmission delay of the replica path tracks the dynamic changes of the main path in real time. Further, combined with the timing deviation threshold detection or external instruction trigger mechanism, the configuration update is triggered only when necessary, avoiding redundant operations and reducing power consumption. The optional PLL / DLL phase comparator flexibly selects high-frequency locking or low-power adjustment mode according to the application scenario requirements to form a closed-loop feedback control. The above technical features, through a layer-by-layer progressive design that ensures architectural symmetry, dynamic configuration synchronization, on-demand triggered updates, and feedback mode adaptation, enable the replication path to accurately reproduce the delay characteristics of the main clock tree, and then automatically adjust the VCDL transmission delay of the main path through phase comparison results, ultimately achieving adaptive delay matching between the main clock tree and the data path. This systematically solves the clock-data skew problem caused by the fixed feedback mechanism of the traditional FPGA clock tree that cannot adapt to dynamic configuration, significantly improving timing reliability, energy efficiency, and applicability in multiple scenarios.

[0070] For example, the clock tree delay matching method provided by the above embodiment will be described below through a specific example. The FPGA clock tree delay matching method proposed in this example is as follows: Figure 3 As shown, in the FPGA, replica delay blocks are automatically programmed on the clock tree feedback path to match the phase between the clock input and the DLL feedback clock.

[0071] Specifically, a replica path is added in the FPGA that uses the same clock switch hub (SWH) settings as the main clock tree, such as Figure 4As shown in Figure 2. This replica path is designed to mimic the delay characteristics of the primary clock path. This allows delay variations in the primary clock path (due to different FPGA configurations and applications) to be automatically reflected in the replica path. Because the replica path tracks the delay of the primary clock path, it automatically adjusts to accommodate these variations, minimizing skew between data and the final clock signal. This allows the clock tree to dynamically adapt to different configurations and applications without manual recalibration, thereby improving FPGA performance in a wide range of scenarios.

[0072] Figure 4 In this example, the replica path uses the same SWH programmable bits to track the delay of the primary clock tree. T2 matches the delay of T1 using the same SWH programmable bits, minimizing clock and data skew. The replica feedback path uses the same clock tree architecture as the primary clock tree and has the same software-programmable bits. In FPGA applications, the SWH of the primary clock tree may be changed, and the replica feedback path can use the same SWH programmable bits to track the delay of the primary clock tree, minimizing skew between data and the final clock. This setup provides flexibility and automatically tracks clock tree delays.

[0073] The clock tree architecture of the main clock tree and the replica path is an H-type structure, which contains a central switching node and symmetrically distributed hierarchical wiring. A typical H-type clock tree in an FPGA is as follows: Figure 5 As shown in the figure, to achieve low clock skew, a CLK SWH (Clock Switching Hub) is used to program, route, and distribute the clock tree. T1 is the delay of the H-type clock tree, and T2 is the delay of the replica clock tree fed back to the PLL. T2 matches the delay of T1 through the same SWH programmable bits, minimizing skew between the clock input and feedback clocks.

[0074] This example uses a replica feedback path to track the delay of the master clock tree using the same SWH programmable bits, minimizing skew between data and the final clock. This setup provides flexibility and automatically tracks clock tree delays. It addresses key shortcomings of traditional clock tree design and provides reliability and adaptability for evolving FPGA technology, enhancing FPGA flexibility and performance by ensuring more reliable and adaptable clock distribution.

[0075] This embodiment also provides a clock tree delay matching device for implementing the above-mentioned embodiments and preferred implementations. Details already described will not be repeated. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0076] This embodiment provides a clock tree delay matching device, which is applied to an FPGA system including a main clock tree and a replica path. The clock tree architecture and the programmable bit setting of the clock switching center of the replica path are consistent with those of the main clock tree. Figure 6 As shown, the device includes:

[0077] An updating module 601 is configured to adjust the clock switching center programmable bits of the replica path in response to a configuration update of the clock switching center programmable bits of the master clock tree, so that the transmission delay of the replica path matches that of the master clock tree;

[0078] A generating module 602 is configured to generate a feedback clock signal corresponding to a transmission delay of a primary clock tree through a replica path;

[0079] The adjustment module 603 is configured to compare the phases of the feedback clock signal and the reference clock signal, and adjust the transmission delay of the voltage-controlled delay line of the master clock tree according to the comparison result to match the delay of the master clock tree with that of the data path.

[0080] In an optional implementation, the adjustment module 603 is specifically configured to:

[0081] Inputting the feedback clock signal into the feedback input terminal of the phase comparator and inputting the reference clock signal into the reference input terminal of the phase comparator to obtain the phase difference between the feedback clock signal and the reference clock; the phase comparator is a phase-locked loop or a delay-locked loop;

[0082] generating an error control signal according to the phase difference;

[0083] The propagation delay of the voltage-controlled delay line of the master clock tree is adjusted by the error control signal.

[0084] In an optional embodiment, the device further comprises:

[0085] The synchronous updating module 604 is configured to synchronously update the programmable bit of the clock switching center of the replica path within a set clock cycle when the programmable bit of the clock switching center of the master clock tree is updated.

[0086] In an optional implementation, the generating module 602 is specifically configured to:

[0087] The configuration file of the FPGA system is loaded to update the programmable bit of the clock switching center of the replication path, wherein the configuration file includes a mapping relationship table between the main clock tree and the clock switching center of the replication path.

[0088] In an optional implementation, the update module 601 is further configured to:

[0089] When it is detected that the timing deviation between the main clock tree and the data path exceeds a preset threshold or a reconfiguration instruction is received, the configuration file is loaded to update the clock switching center programmable bit of the replica path.

[0090] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0091] The clock tree delay matching device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0092] The embodiment of the present invention also provides a computer device having the above Figure 6 The clock tree delay matching device is shown.

[0093] See also Figure 7 , Figure 7 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 7 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0094] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0095] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0096] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0097] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0098] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0099] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0100] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0101] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A clock tree delay matching method, characterized in that: The method is applied to an FPGA system including a main clock tree and a replica path, wherein the clock tree architecture and the programmable bit settings of the clock switching center of the replica path are consistent with those of the main clock tree, and the method includes: In response to a configuration update of a clock switching center programmable bit of a master clock tree, adjusting a clock switching center programmable bit of the replica path so that a transmission delay of the replica path matches that of the master clock tree; generating a feedback clock signal corresponding to the transmission delay of the main clock tree through the replica path; A phase comparison is performed between the feedback clock signal and the reference clock signal, and a transmission delay of a voltage-controlled delay line of the master clock tree is adjusted according to the comparison result, so that the delay of the master clock tree matches that of the data path.

2. The method according to claim 1, characterized in that The clock tree architecture of the main clock tree and the replica path is an H-type structure, and the H-type structure includes a central switching node and symmetrically distributed hierarchical wiring.

3. The method according to claim 2, characterized in that The method further comprises: When the clock switching center programmable bit of the master clock tree is updated, the clock switching center programmable bit of the replica path is synchronously updated within a set clock cycle.

4. The method according to claim 3, characterized in that The adjusting the clock switching center programmable bit of the replica path includes: The configuration file of the FPGA system is loaded to update the programmable bit of the clock switching center of the replication path, wherein the configuration file includes a mapping relationship table between the main clock tree and the clock switching center of the replication path.

5. The method according to claim 4, characterized in that The method further comprises: When it is detected that the timing deviation between the main clock tree and the data path exceeds a preset threshold or a reconfiguration instruction is received, the configuration file is loaded to update the clock switching center programmable bit of the replica path.

6. The method according to claim 3, characterized in that The step of comparing the phase of the feedback clock signal with the reference clock and adjusting the transmission delay of the voltage-controlled delay line of the master clock tree according to the comparison result includes: Inputting the feedback clock signal into a feedback input terminal of a phase comparator, and inputting the reference clock signal into a reference input terminal of the phase comparator, to obtain a phase difference between the feedback clock signal and the reference clock; the phase comparator is a phase-locked loop or a delay-locked loop; generating an error control signal according to the phase difference; The transmission delay of the voltage-controlled delay line of the master clock tree is adjusted by the error control signal.

7. A clock tree delay matching device, characterized in that: The device is applied to an FPGA system including a main clock tree and a replica path, wherein the clock tree architecture and the programmable bit setting of the clock switching center of the replica path are consistent with those of the main clock tree, and the device includes: an update module, configured to adjust the clock switching center programmable bits of the replica path in response to a configuration update of the clock switching center programmable bits of the master clock tree, so that a transmission delay of the replica path matches that of the master clock tree; a generating module, configured to generate a feedback clock signal corresponding to a transmission delay of the main clock tree through the replica path; The adjustment module is used to compare the phase of the feedback clock signal with the reference clock signal, and adjust the transmission delay of the voltage-controlled delay line of the master clock tree according to the comparison result to match the delay of the master clock tree with that of the data path.

8. The device according to claim 7, characterized in that The adjustment module is specifically used to: Inputting the feedback clock signal into a feedback input terminal of a phase comparator, and inputting the reference clock signal into a reference input terminal of the phase comparator, to obtain a phase difference between the feedback clock signal and the reference clock; the phase comparator is a phase-locked loop or a delay-locked loop; generating an error control signal according to the phase difference; The transmission delay of the voltage-controlled delay line of the master clock tree is adjusted by the error control signal.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the clock tree delay matching method according to any one of claims 1 to 6 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the clock tree delay matching method according to any one of claims 1 to 6.

Images