Active capacitive shielding for programmable logic arrays

Abstract

The invention relates to active capacitive shielding for programmable logic arrays. According to various embodiments of the present disclosure, a programmable logic array circuit is provided. In some embodiments, a programmable logic array circuit includes an AND plane including a plurality of sets of product term bands, an OR plane including a plurality of output lines, a first plurality of dynamic drive shield lines in the AND plane, and a second plurality of dynamic drive shield lines in the OR plane. Each of the plurality of sets of product term bands is only adjacent to a corresponding line of the first plurality of dynamically driven shielded lines. Each of the plurality of output lines is only adjacent to a corresponding line of the second plurality of dynamic drive shield lines.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to programmable logic arrays, and more particularly, to capacitive shielding for programmable logic arrays. Background Art

[0002] Programmable logic arrays (PLAs) are an area-efficient way to implement complex combinational functions. When associated with registers, PLAs form fast, area-efficient finite state machines. A typical PLA consists of an AND plane followed by an OR plane. The AND plane generates product terms (the AND of a subset of inputs). The OR plane generates outputs from the OR of specific product terms. Each output is the sum of a specific set of ANDs of specific inputs.

[0003] The AND and OR planes use dynamic domino logic. The AND plane (actually using NAND gates) is decoded when the input is valid and stable, its output is inverted when the NAND function is valid and stable, and the OR plane is decoded when the inverted output of the NAND gate is valid and stable. The AND clock (usually denoted as "CKA") drives the decoding of the AND gate, and the OR clock (usually denoted as "CKO") drives the decoding of the OR gate.

[0004] The dense metal interconnects within the AND and OR planes (including the encoding of the AND and OR planes and the output lines of the OR plane) generate parasitic capacitive coupling that can cause PLA dynamic operation to malfunction. If a product term in the AND plane is decoded, then the product term line will drop from the drive voltage Vdd (e.g., 3VDC) to 0 volts (V). Due to capacitive coupling, a drop from Vdd to 0V in a decoded line tends to cause (one or more) adjacent lines to also drop to 0V, which may cause (one or more) adjacent lines to erroneously appear decoded. Similarly, if a line is decoded in the OR plane and drops from Vdd to 0V, then parasitic capacitive coupling will tend to cause (one or more) adjacent lines to also drop to 0V, which may cause (one or more) adjacent lines to erroneously appear decoded.

[0005] One approach that has been used to prevent this problem due to capacitive coupling is to place a passive shield between each line in the AND plane and between each line and each output in the OR plane. In this approach, each product term line and each output has shielding on both sides. A drawback of using this approach to prevent capacitive coupling is that the amount of area occupied by the shield increases the size of the PLA or reduces the number of inputs, product terms, and outputs that can be accommodated within the same area.

[0006] Applicants have identified many technical challenges and difficulties associated with providing capacitive shielding for PLA. Through applied effort, ingenuity, and innovation, Applicants have solved the problems associated with providing capacitive shielding for PLA by developing the solutions embodied in the present disclosure, which will be described in detail below. Summary of the Invention

[0007] Various embodiments described herein relate to circuits, integrated circuits, methods, apparatus, and systems for providing capacitive shielding for programmable logic arrays.

[0008] According to various embodiments of the present disclosure, a programmable logic array circuit is provided. In some embodiments, the programmable logic array circuit includes: an AND plane including multiple groups of product term bands, an OR plane including multiple output lines, a first plurality of dynamically driven shield lines in the AND plane, and a second plurality of dynamically driven shield lines in the OR plane. Each of the multiple groups of product term bands is adjacent to only one corresponding line in the first plurality of dynamically driven shield lines. Each of the multiple output lines is adjacent to only one corresponding line in the second plurality of dynamically driven shield lines. In response to the voltage on one or more of the multiple groups of product term bands dropping from a driving voltage to zero volts, the voltage on one or more of the first plurality of dynamically driven shield lines is driven from zero volts to a driving voltage. In response to the voltage on one or more of the multiple output lines dropping from the driving voltage to zero volts, the voltage on one or more of the second plurality of dynamically driven shield lines is driven from zero volts to a driving voltage.

[0009] In some embodiments, the voltage on all of the first plurality of dynamically driven shield lines is driven from zero volts to the driven voltage in response to the voltage on one or more of the plurality of sets of product term bands dropping from the driven voltage to zero volts, and the voltage on all of the second plurality of dynamically driven shield lines is driven from zero volts to the driven voltage in response to one or more of the voltages on the plurality of output lines dropping from the driven voltage to zero volts.

[0010] In some embodiments, in response to the voltage on one or more of the multiple sets of product term bands dropping from the driving voltage to zero volts, the voltage on a corresponding one of the first plurality of dynamically driven shield lines is driven from zero volts to the driving voltage, and in response to the voltage on one or more of the multiple output lines dropping from the driving voltage to zero volts, the voltage on a corresponding one of the second plurality of dynamically driven shield lines is driven from zero volts to the driving voltage.

[0011] In some embodiments, the programmable logic array circuit further includes an AND plane clock and an OR plane clock. A voltage on one or more of the first plurality of dynamic drive shield lines is driven from zero volts to a driving voltage by the AND plane clock, and a voltage on one or more of the second plurality of dynamic drive shield lines is driven from zero volts to a driving voltage by the OR plane clock.

[0012] In some embodiments, the programmable logic array circuit further includes first and second inverters connected in series between the AND plane clock and one or more of a first plurality of dynamic drive shield lines driven from zero volts to a drive voltage to introduce a phase shift between the AND plane clock and a voltage on one or more of the first plurality of dynamic drive shield lines, and third and fourth inverters connected in series between the OR plane clock and one or more of a second plurality of dynamic drive shield lines driven from zero volts to the drive voltage to introduce a phase shift between the OR plane clock and the voltage on one or more of the second plurality of dynamic drive shield lines.

[0013] In some embodiments, the length of each of the first plurality of dynamically driven shield lines is substantially equal to the length of a corresponding one of the plurality of sets of product term bands, and the length of each of the second plurality of dynamically driven shield lines is substantially equal to the length of a corresponding one of the plurality of output lines.

[0014] In some embodiments, the length of each of the first plurality of dynamically driven shield lines is less than half the length of a corresponding one of the plurality of sets of product term bands, and the length of each of the second plurality of dynamically driven shield lines is less than half the length of a corresponding one of the plurality of output lines.

[0015] According to various embodiments of the present disclosure, a method for providing capacitive shielding for a programmable logic array (PLA) circuit is provided. In some embodiments, the method includes positioning each of a plurality of product-term strips of an AND plane of the PLA circuit adjacent to only one corresponding line of a first plurality of dynamically driven shield lines, positioning each of a plurality of output lines of an OR plane of the PLA circuit adjacent to only one corresponding line of a second plurality of dynamically driven shield lines, driving a voltage on one or more of the first plurality of dynamically driven shield lines from zero volts to a driven voltage in response to a voltage on one or more of the plurality of product-term strips dropping from a driven voltage to zero volts, and driving a voltage on one or more of the second plurality of dynamically driven shield lines from zero volts to a driven voltage in response to a voltage on one or more of the plurality of output lines dropping from the driven voltage to zero volts.

[0016] According to various embodiments of the present disclosure, an integrated circuit is provided. In some embodiments, the integrated circuit includes a first plurality of signal lines and a first plurality of dynamically driven shield lines. Each of the first plurality of signal lines is adjacent to only one corresponding line in the first plurality of dynamically driven shield lines. In response to a voltage on one or more of the first plurality of signal lines dropping from a driving voltage to zero volts, a voltage on one or more of the first plurality of dynamically driven shield lines is driven from zero volts to a driving voltage.

[0017] The above summary of the invention is provided only for the purpose of summarizing some example embodiments to provide a basic understanding of some aspects of the present disclosure. Therefore, it should be understood that the above embodiments are merely examples and should not be interpreted as narrowing the scope or spirit of the present disclosure in any way. It should also be understood that in addition to those embodiments summarized here, the scope of the present disclosure includes many potential embodiments, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The description of the illustrative embodiments may be read in conjunction with the accompanying drawings. It should be understood that for simplicity and clarity of illustration, the elements illustrated in the drawings are not necessarily drawn to scale unless otherwise described. For example, the dimensions of some elements may be exaggerated relative to other elements unless otherwise described. Embodiments incorporating the teachings of the present disclosure are shown and described with respect to the drawings presented herein, in which:

[0019] Figure 1 A block diagram illustrating an example programmable logic array according to some embodiments of the present disclosure;

[0020] Figure 2A and 2B illustrates example active shield configurations for an example AND plane and an example OR plane, respectively, of an example programmable logic array according to some embodiments of the present disclosure;

[0021] Figure 3 illustrates example product terms or output lines and active shield voltages of an example programmable logic array according to some embodiments of the present disclosure;

[0022] Figure 4 illustrates example clock and active shield voltages for an example programmable logic array according to some embodiments of the present disclosure;

[0023] Figure 5 illustrates example clock and active shield voltages for example programmable logic arrays according to some alternative embodiments of the present disclosure; and

[0024] Figure 6 Example active shield configurations for example programmable logic arrays according to some alternative embodiments of the present disclosure are described. DETAILED DESCRIPTION

[0025] Some embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, which illustrate some, but not all, embodiments of the present disclosure. Indeed, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like numbers refer to like elements throughout.

[0026] As used herein, terms such as "front," "back," and "top" are used for explanation purposes in the examples provided below to describe the relative positions of certain components or component parts. In addition, based on this disclosure, it will be apparent to one of ordinary skill in the art that the terms "substantially" and "approximately" indicate that the referenced element or associated description is accurate within applicable engineering tolerances.

[0027] As used herein, the term "comprising" means including, but not limited to, and should be interpreted in the manner in which it is commonly used in a patent context. The use of broader terms such as comprises, includes, and having should be understood as support for narrower terms such as consisting of, consisting essentially of, and consisting substantially of.

[0028] The phrases "in one embodiment," "according to one embodiment," etc. generally mean that the particular feature, structure, or characteristic following the phrase can be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, such phrases are not necessarily referring to the same embodiment).

[0029] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0030] If the specification states that a component or feature "may, can," "could, should," "would," "preferably," "likely," "typically," "optionally," "for example," "often," or "might" (or other such language) be included or have a characteristic, then the specific component or feature is not required to be included or have that characteristic. Such components or features may optionally be included in some embodiments, or may be excluded.

[0031] Various embodiments of the present disclosure overcome the aforementioned technical challenges and difficulties and provide various technical improvements and advantages based on, for example, but not limited to, providing example circuits, integrated circuits, methods, devices, and systems for providing capacitive shielding of PLA.

[0032] Various embodiments of the present disclosure provide a PLA circuit, integrated circuit, and method in which the product terms in the AND plane and the output lines in the OR plane have capacitive shielding on only one side, thereby significantly reducing the number of capacitive shields and, therefore, the area used, compared to the above-described methods. (e.g., Figure 2AAs will be seen and described below, each product term comprises a set of separate but linearly arranged conductors (called "strips"), each strip shunting one or more transistors. Figure 2B As will be seen, and described below, each output line comprises a single straight conductor. The product term strips and groups of output lines are collectively referred to herein as signal lines. Having capacitive shielding on only one side of each group of product term strips in the AND plane and output lines in the OR plane (rather than on both sides as in the above approach) would theoretically restore some of the undesirable capacitive coupling that was prevented using the above approach. However, in various embodiments of the present disclosure, this effect is mitigated by using active shielding (also referred to as "dynamically driven shielding") instead of passive shielding.

[0033] In various embodiments, the active shield is dynamically driven from 0V to Vdd at the same time (or slightly after) one or more decode lines are driven from Vdd to 0V. Due to capacitive coupling with nearby decode lines that are dropping from Vdd to 0V, the tendency of the undecoded lines to drop from Vdd is mitigated by the capacitive coupling of the undecoded lines with the active shield that is driven in the opposite direction at the same time (or nearly the same time). In various embodiments, the signal driving the active shield in the AND plane has a similar phase and amplitude to the AND clock signal CKA, and the signal driving the active shield in the OR plane has a similar phase and amplitude to the OR clock signal CKO.

[0034] In various embodiments, all active shields are dynamically driven from 0 V to Vdd at the same time (or slightly after) one or more decode lines are driven from Vdd to 0 V. In various other embodiments, only the active shield adjacent to one of the decode lines is dynamically driven from 0 V to Vdd.

[0035] In various embodiments, the active shield in the AND plane is dynamically driven from 0V to Vdd by the AND plane clock. In various embodiments, the active shield in the OR plane is dynamically driven from 0V to Vdd by the OR plane clock.

[0036] In various embodiments, two inverters in series are positioned between the AND plane clock and one or more active shields in the AND plane to introduce a phase shift between the AND plane clock and the voltage on the active shields in the AND plane. In various embodiments, two inverters in series are positioned between the OR plane clock and one or more active shields in the OR plane to introduce a phase shift between the OR plane clock and the voltage on the active shields in the OR plane.

[0037] In various embodiments, the active shield in the AND plane is substantially the same length as the product term strip group, and the active shield in the OR plane is substantially the same length as the output line. In various other embodiments, the active shield in the AND plane is less than half the length of the product term strip group, and the active shield in the OR plane is less than half the length of the output line.

[0038] Figure 1 An example block diagram of an example programmable logic array according to some embodiments of the present disclosure is illustrated. Figure 1 As can be seen, the example PLA 100 includes an AND plane 102, an inverter block 104 including a plurality of inverters, and an OR plane 106. In the illustrated embodiment, the AND plane 102 receives a plurality of inputs IN1, IN2, ..., INn. n AND plane 102 is a clock input and a clock input CKA. Within AND plane 102 are multiple sets of product term straps and multiple active shields, as further described below. The outputs from the product term strap sets are input to inverter block 104, inverted, and then provided to OR plane 106. Inverter block 104 receives a clock input CKN. In the illustrated embodiment, OR plane 106 receives a clock input CKO and has multiple outputs OUT1, OUT2, ..., OUT n .

[0039] Now refer to Figure 2A , an example active shield configuration 200 of an example AND plane of an example programmable logic array is illustrated according to some embodiments of the present disclosure. Configuration 200 includes multiple sets of product term strips 202a-202j and multiple active shields 204a-204f. Figure 2A As can be seen, each group of product term strips 202a-202j is adjacent to another group of product term strips and one of the active shields 204a-204f. For example, group 202a is adjacent to active shield 204a and group 202b. Figure 2A In an exemplary embodiment, the active shield and the product term strip group have substantially the same length.

[0040] Because groups 202a-202j do not have shields on both sides as in the previously described approach, there is some capacitive coupling between adjacent strips within each pair of groups (i.e., between 202a and 202b, between 202c and 202d, and so on). As described above, this coupling is counteracted by the active shields on the opposite side of each affected group. For example, if group 202c is decoded and the voltage on its strip drops from Vdd to 0V, the voltage on the strip of adjacent group 202d will also drop due to capacitive coupling. However, in various embodiments of the present disclosure, at the same time or slightly after the voltage on the strip of group 202c drops from Vdd to 0V, the voltage on active shield 204c (as well as the voltages on some or all other active shields) is driven from 0V to Vdd, thereby preventing or at least reducing the voltage drop on the strip of group 202d (and any other undecoded product terms that might otherwise be affected by the adjacent decoded groups). In various embodiments of the present disclosure, the voltage drop on the strip of group 202d is reduced sufficiently to prevent line 202d from appearing to be decoded.

[0041] Now refer to Figure 2B , an example active shield configuration 220 of an example OR plane of an example programmable logic array is illustrated according to some embodiments of the present disclosure. Configuration 220 includes a plurality of outputs 222a-222j and a plurality of active shields 224a-224f. Figure 2B As can be seen, each output line 222a-222j is adjacent to another output line and an active shield 224a-224f. For example, output line 222a is adjacent to active shield 224a and output line 222b. Figure 2B In an exemplary embodiment, the active shield is substantially the same length as the output line.

[0042] Because output lines 222a-222j do not have shields on both sides as in the previously described approach, there is some capacitive coupling between each pair of output lines (i.e., between 222a and 222b, between 222c and 222d, and so on). As described above, this coupling is counteracted by the active shields on the opposite side of each affected output line. For example, if output line 222c is decoded and its voltage drops from Vdd to 0V, the voltage on adjacent output line 222d will also drop due to capacitive coupling. However, in various embodiments of the present disclosure, at the same time or slightly after the voltage on output line 222c drops from Vdd to 0V, the voltage on active shield 224c (and the voltages on some or all other active shields) is driven from 0V to Vdd, thereby preventing or at least reducing the voltage drop on output line 222d (and any other undecoded output lines that might otherwise be affected by adjacent decoded output lines). In various embodiments of the present disclosure, the voltage drop on output line 222d is reduced sufficiently to prevent output line 222d from appearing to be decoded.

[0043] Now refer to Figure 3 , illustrates example product terms or output lines and active shield voltages of example programmable logic arrays according to some embodiments of the present disclosure. Figure 3 In the example of FIG, curve 300 illustrates a voltage 302 on a decoded line (which may be a set of product term strips of an AND plane or an output line of an OR plane), such as line 202c in the example above; curve 310 illustrates a voltage 312 on an adjacent undecoded line (which may be a set of product term strips of an AND plane or an output line of an OR plane), such as line 202d in the example above; and curve 320 illustrates a voltage 322 on an active shield of an adjacent undecoded line, such as active shield 204c in the example above. Figure 3 As can be seen, the voltage 302 on the decoded line drops from Vdd to 0V. In response, the voltage 322 on the active shield is driven from 0V to Vdd, as can be seen by curve 320. Due to the capacitive coupling between the undecoded line and the active shield, the tendency of the voltage drop on the decoded line to cause a corresponding voltage drop on the undecoded line is offset by the voltage increase on the active shield and its tendency to cause a corresponding voltage increase on the undecoded line. Figure 3 As can be seen from the curve 310 of FIG. 3 , this cancellation limits the voltage drop on the undecoded line so that the undecoded line is not incorrectly determined to be decoded. In the illustrated embodiment, the voltage drop on the undecoded line is referred to as Vperturbation, and the resulting voltage on the undecoded line can be expressed as Vdd-Vperturbation. In various embodiments, as long as the resulting voltage on the undecoded line (Vdd-Vperturbation) is greater than the threshold of the output inverter on the undecoded line, the undecoded line will not be incorrectly determined to be decoded.

[0044] As described above, in various embodiments, the active shield in the AND plane is dynamically driven from 0V to Vdd by the AND plane clock, and / or the active shield in the OR plane is dynamically driven from 0V to Vdd by the OR plane clock. Figure 4 , illustrates example clock and active shield voltages for an example programmable logic array according to some embodiments of the present disclosure. Figure 4 In the example of FIG. 4 , a curve 400 illustrates the output voltage 402 of the AND plane clock CKA and / or the OR plane clock CKO. As described above, the AND clock drives the NAND gate decode of the AND plane when the input is valid and stable, and the OR clock drives the OR gate decode when the inverted output of the NAND gate is valid and stable. In either case (CKA drives the AND plane decode, or CKO drives the OR plane decode), the corresponding clock is provided as Figure 4 The decoder is driven by a short voltage (typically Vdd) as shown in curve 400 .

[0045] As described above, in various embodiments, the active shield in the AND plane is dynamically driven from 0V to Vdd by the AND plane clock, and / or the active shield in the OR plane is dynamically driven from 0V to Vdd by the OR plane clock. Figure 4 As can be seen in the curve 410 of FIG, the voltage 412 of the AND plane active shield and / or the OR plane active shield has the same or very similar phase and amplitude as the output voltage 402 of the AND plane clock CKA and / or the OR plane clock CKO. In various embodiments, there may be a slight delay between the output voltage 402 of the AND plane clock CKA and / or the OR plane clock CKO and the voltage 412 provided to the AND plane active shield and / or the OR plane active shield. In 0.6 μm EEPROM technology, this delay is approximately 1 nanosecond (ns).

[0046] As described above, in various embodiments, two inverters in series are positioned between the AND plane clock and one or more active shields in the AND plane to introduce a phase shift between the AND plane clock and the voltage on the active shield in the AND plane, and / or two inverters in series are positioned between the OR plane clock and one or more active shields in the OR plane to introduce a phase shift between the OR plane clock and the voltage on the active shield in the OR plane. Now referring to Figure 5 , illustrates example clock and active shield voltages for an example programmable logic array according to some alternative embodiments of the present disclosure. Figure 5 An example similar to Figure 4 , except that Figure 5 A phase shift is introduced in by adding two inverters in series between the clock and the active shield. Figure 5 In the example of FIG. 5 , curve 500 illustrates the output voltage 502 of the AND plane clock CKA and / or the OR plane clock CKO, while curve 510 illustrates the voltage 512 provided to the active shield. The phase shift between the clock voltage 502 and the active shield voltage 512 introduced by the two inverters is Figure 5 As can be clearly seen in the . In various embodiments, the active shield is most effective when it is raised at the same time that the product term strap or output line falls. The product term strap falls with a small delay after the CKA clock signal rises, while the output line falls with a small delay after the CKO clock signal rises. Therefore, it may be optimal to raise the AND plane shield with a small delay after the CKA clock signal rises, and to raise the OR plane shield with a small delay after the CKO clock signal rises. In various embodiments, two linked inverters provide this desired delay. In various embodiments, by sizing the transistors of each inverter, the delay can be adjusted to best accommodate the AND / OR plane switching delay relative to their respective clocks.

[0047] In various embodiments of the present disclosure, the active shield in the AND plane is approximately half or less than half the length of the product term strip group, and / or the active shield in the OR plane is approximately half or less than half the length of the output line. Figure 6 An example active shield configuration for an example OR plane of an example programmable logic array is illustrated, where the active shield is less than half the length of the output line and its position is staggered. (An example AND plane in such an embodiment would be similar to Figure 6 , but where the output lines 602a-602l are replaced by multiple sets of discrete product term straps.) By reducing the length of the active shield, the area used for the PLA is reduced even further than the example configuration of FIG. 2 , in which the active shield has approximately the same length as the product term straps and / or sets of output lines, while still canceling capacitive coupling sufficiently to prevent undecoded product terms and / or output lines from being incorrectly determined to be decoded.

[0048] Figure 6 The configuration 600 includes a plurality of output lines 602a-602l of the OR plane, and a plurality of active shields 604a-604g. Figure 6 As can be seen, each of the output lines 602a-602l is adjacent to another of the output lines on one side and is adjacent to an active shield 604a-604f that is slightly more than half the length of the other of the output lines and slightly less than half the length on the other side. For example, output line 602b is adjacent to output line 602a on one side and is adjacent to a portion of output line 602c and active shield 604b on the other side. Figure 6 As can be seen, the active shielding is staggered left and right in position.

[0049] exist Figure 6 In the illustrated embodiment, each undecoded output line is capacitively coupled to one full-length adjacent line and one partial (approximately half) length adjacent output line on the opposite side. However, the effect of each undecoded output line on its adjacent partial-length active shield is still sufficient to reduce the voltage drop sufficiently to prevent the undecoded output line from appearing decoded.

[0050] Each signal line of the PLA has three capacitive couplings: (1) to ground potential, due to the signal running on the substrate at ground, and due to the capacitance of all drains of all n-type transistors of the PLA connected to the signal line (called Cgnd); (2) to the set of other adjacent signal lines (potential perturbators) (called Csig_sig); and (3) to the adjacent shield (called Csig_shield). These couplings act as capacitive bridges. In the worst case, all other signal lines facing the undecoded signal line are decoded and drop from Vdd to 0V. The potential of the undecoded signal (perturbation) is determined as: Vperturbation = Vdd x (Csig_sig – Csig_shield) / (Csig_sig + Csig_shield + Cgnd). To prevent the undecoded line from being mistakenly interpreted as decoded, Vdd – Vperturbation should be greater than the threshold of the output inverter on the undecoded line.

[0051] For analysis Figure 6 For the purpose of this configuration, we will consider the active shield to be exactly half the length of the product term strip and / or output line group. Thus, each signal line is adjacent to 1.5 signal lines and 0.5 shield. In this regard, Csig_sig ~ 3x Csig_shield and Vperturbation ~ Vdd x 2x Csig_shield ~ (Vdd / 2) / (1+(Cgnd / (4xCsig_shield))4x Csig_shield+Cgnd), which can be rewritten as Vperturbation ~ (Vdd / 2) / (1+(Cgnd / (4xCsig_shield)) by dividing by 4x Csig_shield. Thus, in a circuit such as Figure 6 In the example configuration in , due to the influence of Cgnd, Vperturbation is worse than Vdd / 2 and therefore below the threshold where the signal line is incorrectly interpreted as being decoded.

[0052] In various embodiments of the present invention, all product term band groups and / or all output lines can be positioned with an active shield on one side and another line on the opposite side. In various alternative embodiments of the present invention, only some product term band groups and / or some output lines are positioned with an active shield on one side and another line on the opposite side, while other product term band groups and / or some output lines are positioned with passive shields on both sides.

[0053] in conclusion

[0054] Many modifications and other embodiments of the disclosure set forth herein will occur to those skilled in the art having the benefit of the teachings of the procedures in the foregoing description and the associated drawings. Although the drawings show only certain components of the apparatus and system described herein, it will be understood that various other components may be used in conjunction with the system. Therefore, it will be understood that the disclosure is not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. In addition, the steps in the above-described method do not necessarily occur in the order described in the drawings, and in some cases, one or more of the steps described may occur substantially simultaneously, or may include additional steps. Although specific terms are employed herein, they are used in a general and descriptive sense only and not for purposes of limitation.

[0055] Although various embodiments according to the principles disclosed herein have been shown and described above, those skilled in the art may modify them without departing from the spirit and teachings of the present disclosure. The embodiments described herein are merely representative and are not intended to be limiting. Many variations, combinations, and modifications are possible and are within the scope of the present disclosure. The disclosed embodiments primarily relate to programmable logic arrays, however, those skilled in the art will recognize that such principles can be applied to any device in which it is desired to offset capacitive coupling. Alternative embodiments resulting from combining, integrating, and / or omitting features of (one or more) embodiments are also within the scope of the present disclosure. Therefore, the scope of protection is not limited by the description set forth above.

[0056] Additionally, section headings are used herein to provide organizational cues or to conform to the recommendations under 37 CFR 1.77. Such headings shall not limit or characterize the disclosure set forth in any claims that may arise from this disclosure.

[0057] While the detailed description has described certain embodiments of the present disclosure, the appended claims are intended to cover other embodiments of the present disclosure that differ from the described embodiments according to various modifications and improvements. For example, the appended claims may cover any form of integrated circuit having one or more programmable logic arrays, such as, but not limited to, standalone EEPROM memories containing PLAs and / or any other circuits using PLAs, such as microcontrollers and microprocessors.

[0058] In the appended claims, unless the specific terms "means" or "step" are used in a given claim, it is not intended that the claim be interpreted under 35 USC 112, paragraph 6.

Claims

1. A programmable logic array circuit, comprising: AND plane, including multiple sets of product term bands; OR plane, including multiple output lines; a first plurality of dynamically driven shield lines in the AND plane; as well as a second plurality of dynamically driven shield lines in the OR plane; wherein each of the plurality of sets of product term bands is adjacent to only one corresponding one of the first plurality of dynamically driven shield lines; wherein each of the plurality of output lines is adjacent to only one corresponding dynamically driven shield line of the second plurality of dynamically driven shield lines; wherein, in response to the voltage on one or more of the plurality of sets of product term bands dropping from a driving voltage to zero volts, the voltage on one or more of the first plurality of dynamically driven shield lines is driven from zero volts to the driving voltage; and wherein, in response to the voltage on one or more of the plurality of output lines dropping from the driving voltage to zero volts, the voltage on one or more of the second plurality of dynamically driven shield lines is driven from zero volts to the driving voltage.

2. The programmable logic array circuit according to claim 1, wherein: in response to a voltage on one or more of the plurality of sets of product term bands dropping from the drive voltage to zero volts, the voltage on all of the first plurality of dynamically driven shield lines being driven from zero volts to the drive voltage; and Wherein, in response to the voltage on one or more of the plurality of output lines dropping from the driving voltage to zero volts, the voltage on all of the second plurality of dynamically driven shield lines is driven from zero volts to the driving voltage.

3. The programmable logic array circuit according to claim 1 , wherein: in response to a voltage on one or more of the plurality of sets of product term bands dropping from the drive voltage to zero volts, a voltage on corresponding ones of the first plurality of dynamically driven shield lines being driven from zero volts to the drive voltage; and Wherein, in response to the voltage on one or more of the plurality of output lines dropping from the driving voltage to zero volts, the voltage on corresponding dynamic drive shield lines in the second plurality of dynamic drive shield lines is driven from zero volts to the driving voltage.

4. The programmable logic array circuit according to claim 1 , further comprising: AND flat clock; as well as OR flat clock; wherein the voltage on one or more of the first plurality of dynamic drive shield lines is driven from zero volts to the drive voltage by the AND plane clock, and Wherein the voltage on one or more of the second plurality of dynamic drive shield lines is driven from zero volts to the drive voltage by the OR planar clock.

5. The programmable logic array circuit according to claim 4 , further comprising: a first inverter and a second inverter connected in series between the AND planar clock and the one or more of the first plurality of dynamic drive shield lines driven from zero volts to the drive voltage to introduce a phase shift between the AND planar clock and the voltage on one or more of the first plurality of dynamic drive shield lines; as well as A third inverter and a fourth inverter are connected in series between the OR planar clock and one or more of the second plurality of dynamic drive shield lines driven from zero volts to the drive voltage to introduce a phase shift between the OR planar clock and the voltage on one or more of the second plurality of dynamic drive shield lines.

6. The programmable logic array circuit of claim 1 , wherein a length of each of the first plurality of dynamically driven shield lines is substantially equal to a length of a corresponding one of the plurality of sets of product term bands; and The length of each of the second plurality of dynamic drive shielding lines is substantially equal to the length of a corresponding one of the plurality of output lines.

7. The programmable logic array circuit of claim 1 , wherein a length of each of the first plurality of dynamically driven shield lines is less than half a length of a corresponding one of the plurality of sets of product term bands; and The length of each of the second plurality of dynamic drive shielding lines is less than half the length of a corresponding one of the plurality of output lines.

8. A method for providing capacitive shielding to a programmable logic array (PLA) circuit, the method comprising: positioning each of a plurality of sets of product term strips of an AND plane of the PLA circuit adjacent only to a corresponding one of a first plurality of dynamically driven shield lines; positioning each of a plurality of output lines of an OR plane of the PLA circuit adjacent only to a corresponding one of a second plurality of dynamically driven shield lines; driving the voltage on one or more of the first plurality of dynamically driven shield lines from zero volts to the drive voltage in response to the voltage on one or more of the plurality of sets of product term bands dropping from a drive voltage to zero volts; as well as In response to the voltage on one or more of the plurality of output lines dropping from the drive voltage to zero volts, the voltage on one or more of the second plurality of dynamically driven shield lines is driven from zero volts to the drive voltage.

9. The method according to claim 8, wherein in response to a voltage on one or more of the plurality of sets of product term bands dropping from the drive voltage to zero volts, the voltage on all of the first plurality of dynamically driven shield lines being driven from zero volts to the drive voltage; and Wherein, in response to the voltage on one or more of the plurality of output lines dropping from the driving voltage to zero volts, the voltage on all of the second plurality of dynamically driven shield lines is driven from zero volts to the driving voltage.

10. The method according to claim 8, wherein in response to a voltage on one or more of the plurality of sets of product term bands dropping from the drive voltage to zero volts, a voltage on corresponding ones of the first plurality of dynamically driven shield lines being driven from zero volts to the drive voltage; and Wherein, in response to the voltage on one or more of the plurality of output lines dropping from the driving voltage to zero volts, the voltage on corresponding dynamic drive shield lines in the second plurality of dynamic drive shield lines is driven from zero volts to the driving voltage.

11. The method of claim 8, wherein the voltage on one or more of the first plurality of dynamically driven shield lines is driven from zero volts to the drive voltage by an AND plane clock of the PLA circuit; and Wherein the voltage on one or more of the second plurality of dynamically driven shield lines is driven from zero volts to the drive voltage by an OR planar clock of the PLA circuit.

12. The method according to claim 11, further comprising: inserting a first inverter and a second inverter in series between the AND planar clock and the one or more of the first plurality of dynamic drive shield lines driven from zero volts to the drive voltage to introduce a phase shift between the AND planar clock and the voltage on one or more of the first plurality of dynamic drive shield lines; as well as A third inverter and a fourth inverter are inserted in series between the OR planar clock and the one or more of the second plurality of dynamic drive shield lines driven from zero volts to the drive voltage to introduce a phase shift between the OR planar clock and the voltage on one or more of the second plurality of dynamic drive shield lines.

13. The method of claim 8, wherein a length of each of the first plurality of dynamically driven shield lines is substantially equal to a length of a corresponding one of the plurality of sets of product term bands; and The length of each of the second plurality of dynamic drive shielding lines is substantially equal to the length of a corresponding one of the plurality of output lines.

14. The method of claim 8, wherein a length of each of the first plurality of dynamically driven shield lines is less than half a length of a corresponding one of the plurality of sets of product term bands; and The length of each of the second plurality of dynamic drive shielding lines is less than half the length of a corresponding one of the plurality of output lines.

15. An integrated circuit comprising: a first plurality of signal lines; as well as a first plurality of dynamically driven shield lines; wherein each of the first plurality of signal lines is adjacent to only a corresponding one of the first plurality of dynamically driven shield lines; and Wherein, in response to the voltage on one or more of the first plurality of signal lines dropping from a driving voltage to zero volts, the voltage on one or more of the first plurality of dynamic drive shield lines is driven from zero volts to the driving voltage.

16. The integrated circuit of claim 15, further comprising: a second plurality of signal lines; as well as a second plurality of dynamically driven shield lines; wherein each of the second plurality of signal lines is adjacent to only a corresponding one of the second plurality of dynamically driven shield lines; and Wherein, in response to the voltage on one or more of the second plurality of signal lines dropping from a driving voltage to zero volts, the voltage on one or more of the second plurality of dynamically driven shield lines is driven from zero volts to the driving voltage.

17. The integrated circuit of claim 16, wherein the integrated circuit comprises a programmable logic array (PLA) circuit; wherein the first plurality of signal lines comprises a plurality of sets of product term strips of an AND plane of the PLA circuit; and The second plurality of signal lines includes a plurality of output lines of an OR plane of the PLA circuit.

18. The integrated circuit of claim 17, wherein: in response to a voltage on one or more of the plurality of sets of product term bands dropping from the drive voltage to zero volts, the voltage on all of the first plurality of dynamically driven shield lines being driven from zero volts to the drive voltage; and Wherein, in response to the voltage on one or more of the plurality of output lines dropping from the driving voltage to zero volts, the voltage on all of the second plurality of dynamically driven shield lines is driven from zero volts to the driving voltage.

19. The integrated circuit of claim 17, wherein: in response to a voltage on one or more of the plurality of sets of product term bands dropping from the drive voltage to zero volts, a voltage on corresponding ones of the first plurality of dynamically driven shield lines being driven from zero volts to the drive voltage; and Wherein, in response to the voltage on one or more of the plurality of output lines dropping from the driving voltage to zero volts, the voltage on corresponding dynamic drive shield lines in the second plurality of dynamic drive shield lines is driven from zero volts to the driving voltage.

20. The integrated circuit of claim 17, further comprising: AND flat clock; as well as OR flat clock; wherein the voltage on one or more of the first plurality of dynamic drive shield lines is driven from zero volts to the drive voltage by the AND plane clock, and Wherein the voltage on one or more of the second plurality of dynamically driven shield lines is driven from zero volts to the drive voltage by the OR planar clock.

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