JFET device and preparation method thereof

Abstract

The invention provides a JFET (Junction Field Effect Transistor) device and a preparation method thereof. The JFET device comprises a substrate layer; the drift layer is positioned on one side of the substrate layer along the first direction; the first doped regions are spaced along the second direction, the conduction type of the first doped regions is opposite to that of the drift layer, and the first doped regions and the surface of one side, facing the substrate layer, of the drift layer are spaced along the first direction; the gate doped region is positioned on one side, deviating from the substrate layer, of the first doped region along the first direction; the source regions are located between the adjacent first doped regions; the pinch-off regions are positioned between the adjacent first doped regions and between the substrate layer and the source region; wherein the size of the first doped region in the first direction is 0.8-4 microns; wherein the second direction intersects with the first direction.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a JFET device and a preparation method thereof. Background Art

[0002] A junction field-effect transistor (JFET) is a three-terminal active device with amplification capabilities. Two highly doped P regions are fabricated on the same N-type semiconductor and connected together. The resulting electrode is called the gate (g). Two electrodes, called the drain (d) and source (s), extend from each end of the N-type semiconductor. Summary of the Invention

[0003] The technical problem to be solved by the present invention is how to reduce the leakage of JFET devices, reduce the process steps, and improve the reliability.

[0004] In order to solve the above technical problems, the present invention provides a JFET device, comprising: a substrate layer; a drift layer located on one side of the substrate layer along a first direction; a plurality of first doped regions spaced apart along a second direction, the conductivity type of the first doped regions being opposite to the conductivity type of the drift layer, and the first doped regions being spaced apart from a surface of the drift layer facing the substrate layer along the first direction; a gate doped region located on a side of the first doped region facing away from the substrate layer along the first direction; a source region located between adjacent first doped regions; a pinch-off region located between adjacent first doped regions and between the substrate layer and the source region; wherein a size of the first doped region in the first direction is 0.8 microns to 4 microns; and wherein the second direction intersects with the first direction.

[0005] Optionally, the first doping region is an ion implantation region.

[0006] Optionally, it also includes: a second doping region, the second doping region penetrates the first doping region and the pinch-off region in the second direction, the conductivity type of the second doping region is opposite to the conductivity type of the first doping region, and the doping concentration of the second doping region is greater than the doping concentration of the drift layer; the first doping region is divided into a first sub-doping region and a second sub-doping region by the second doping region, the first sub-doping region and the second sub-doping region are located on both sides of the second doping region along the first direction and are connected to the second doping region.

[0007] Optionally, a size of the second doping region in the first direction is 0.2 micrometers to 1 micrometer.

[0008] Optionally, the source region and the second doping region are spaced apart in the first direction.

[0009] Optionally, it also includes: a second doping region, which is located between adjacent first doping regions; the conductivity type of the second doping region is opposite to the conductivity type of the first doping region, and the doping concentration of the second doping region is greater than the doping concentration of the drift layer; wherein the second doping region is located on the side of the source region facing the substrate layer and is connected to the source region; the surface of the side of the second doping region facing the substrate layer is away from the substrate layer relative to the surface of the side of the first doping region facing the substrate layer.

[0010] Optionally, the second doped region protrudes toward the first doped region in the second direction.

[0011] Optionally, the second doping region is located between adjacent first doping regions.

[0012] Optionally, the second doped region is located between the source region and the drift layer in the first direction.

[0013] Optionally, a size of the second doping region in the first direction is 0.3 microns to 1.5 microns.

[0014] Optionally, the second doping region is located between a portion of adjacent first doping regions, and the second doping region is not located between another portion of adjacent first doping regions.

[0015] Optionally, the second doping region is located in a portion of the drift layer between adjacent first doping regions.

[0016] Optionally, a size of the second doping region in the first direction is 0.3 microns to 2.5 microns.

[0017] Optionally, the doping concentration of the first doping region is greater than or equal to the doping concentration of the second doping region.

[0018] Optionally, the doping concentration of the second doping region is 1.2 to 10 times the doping concentration of the drift layer.

[0019] The present application also provides a method for preparing a JFET device, comprising: forming a drift layer on one side of a substrate layer along a first direction; forming a plurality of first doped regions spaced apart in a second direction in the drift layer; wherein the conductivity type of the first doped region is opposite to the conductivity type of the drift layer, and the first doped region is spaced apart from a surface of the drift layer facing the substrate layer along the first direction; forming a gate doped region, wherein the gate doped region is located on a side of the first doped region away from the substrate layer along the first direction; forming a source region, wherein the source region is located between adjacent first doped regions; a pinch-off region is provided between adjacent first doped regions and between the substrate layer and the source region; wherein a size of the first doped region in the first direction is 0.8 micrometers to 4 micrometers; and wherein the second direction intersects with the first direction.

[0020] Optionally, it also includes: forming a second doping region, the second doping region penetrates the first doping region and the pinch-off region in the second direction, the conductivity type of the second doping region is opposite to the conductivity type of the first doping region, and the doping concentration of the second doping region is greater than the doping concentration of the drift layer; the first doping region is divided into a first sub-doping region and a second sub-doping region by the second doping region, the first sub-doping region and the second sub-doping region are located on both sides of the second doping region along the first direction and are connected to the second doping region.

[0021] Optionally, the source region and the second doping region are spaced apart in the first direction.

[0022] Optionally, it also includes: forming a second doping region, the second doping region is located between adjacent first doping regions; the conductivity type of the second doping region is opposite to the conductivity type of the first doping region, and the doping concentration of the second doping region is greater than the doping concentration of the drift layer; wherein the second doping region is located on the side of the source region facing the substrate layer and is connected to the source region; the surface of the side of the second doping region facing the substrate layer is away from the substrate layer relative to the surface of the side of the first doping region facing the substrate layer.

[0023] Optionally, forming the first doping region and the gate doping region includes: forming a plurality of initial first doping regions spaced apart in the second direction in the drift layer through an ion implantation process; forming a gate doping region, wherein the initial first doping region of the gate doping region along the first direction toward the substrate layer side serves as the first doping region.

[0024] Optionally, the ion implantation process for forming the initial first doping region includes a first sub-ion implantation and / or a second sub-ion implantation; wherein, the implantation direction of the first sub-ion implantation is along the first crystal direction of the drift layer, and the implantation direction of the second sub-ion implantation is along the second crystal direction of the drift layer; the first crystal direction is the crystal direction with the highest linear arrangement density of atoms in the drift layer; the linear arrangement density of atoms in the drift layer along the second crystal direction is 40%-70% of the linear arrangement density of atoms in the drift layer along the first crystal direction; and the angle between the second crystal direction and the first crystal direction is greater than zero.

[0025] Optionally, the step of forming the second doping region includes: before forming the initial first doping region, epitaxially forming an initial second doping region on a side of the drift layer away from the substrate layer; in the process of forming the initial first doping region, an ion implantation process implants ions into part of the drift layer and part of the initial second doping region, and neutralizes part of the initial second doping region, and the initial second doping region between adjacent initial first doping regions in the second direction forms the second doping region; wherein, the second doping region protrudes toward the first doping region in the second direction.

[0026] Optionally, the second doping region is formed between a portion of adjacent first doping regions.

[0027] The technical solution of the present invention has the following technical effects:

[0028] In the JFET device provided by the technical solution of the present invention, the size of the first doped region in the first direction is 0.8 to 4 microns. This allows a greater distance in the first direction between the surface of the first doped region facing the substrate layer and the surface of the source region facing the substrate layer. Consequently, when the device is turned off, the depletion layer formed by the first doped region and the pinch-off region can be pinched off at a location away from the source region, thereby reducing leakage. Because the first doped region has a larger size in the first direction, the depletion layer formed by the first doped region and the pinch-off region has a larger size in the first direction when the device is turned off, thereby improving the pinch-off effect and further reducing leakage.

[0029] Furthermore, the first doping region is an ion implantation region, so a trenching process is not required to form the first doping region, which reduces the complexity of the process and improves the reliability of the first doping region. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of a JFET device in the related art;

[0032] Figure 2 Schematic diagram of a JFET device in one embodiment of the present application;

[0033] Figure 3 is a schematic diagram of a JFET device in another embodiment of the present application;

[0034] Figure 4 is a schematic diagram of a JFET device in another embodiment of the present application;

[0035] Figure 5 is a schematic diagram of a JFET device in another embodiment of the present application;

[0036] Figures 6 to 9 Schematic diagram of the fabrication process of a JFET device in another embodiment of the present application;

[0037] Figures 10 to 13 Schematic diagram of the fabrication process of a JFET device in another embodiment of the present application;

[0038] Figures 14 to 17 Schematic diagram of the fabrication process of a JFET device in another embodiment of the present application;

[0039] Figures 18 to 21 Schematic diagram of the structure of the preparation process of a JFET device in another embodiment of the present application. DETAILED DESCRIPTION

[0040] A JFET device of related technology, refer to Figure 1 , comprising: a substrate layer 150; a drift layer 100 located on one side of the substrate layer 150 along a first direction; a drain electrode 160 located on a side of the substrate layer 150 facing away from the drift layer 100; a plurality of trenches spaced apart along a second direction, the trenches extending from a surface of the drift layer 100 facing away from the substrate layer 150 along the first direction into a portion of the drift layer 100; a source region 140; a source electrode 180; a first doped region 110 in the drift layer 110 located at the bottom of the trenches; a pinch-off region 130 located between adjacent trenches and between adjacent first doped regions 110; a gate doped region 120; and a gate electrode 170. Both the first doped region 110 and the gate doped region 120 are spaced apart from the source region 140 in the first direction. The distance between the surface of the first doped region 110 facing the substrate layer 150 and the surface of the source region 140 facing the substrate layer 150 in the first direction is relatively large, thereby improving the ability of the pinch-off region 130 to pinch off current during shutdown. The second direction is perpendicular to the first direction.

[0041] A first doped region 110 is formed in the drift layer 100 at the bottom of the trench by an ion implantation process. Since the first doped region 110 is formed on the basis of the trench formation, the distance in the first direction between the surface of the first doped region 110 facing the substrate layer 150 and the surface of the source region 140 facing the substrate layer 150 is relatively large.

[0042] However, the thickness of the first doped region 110 in the first direction is relatively small. Therefore, the pinch-off region 130, which is higher than the first doped region 110 in the first direction, is difficult to deplete with the first doped region 110. Therefore, the pinch-off capability needs to be further improved. The trenching process is relatively complex and the inner walls of the trench are prone to defects, which reduces the reliability of the first doped region 110.

[0043] On this basis, the present application provides a JFET device and a preparation method thereof, which reduces leakage, reduces process steps, and improves reliability.

[0044] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0045] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0046] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components; wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0047] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0048] An embodiment of the present application provides a JFET device, referring to Figure 2 ,include:

[0049] substrate layer 250;

[0050] a drift layer 200 located on one side of the substrate layer 250 along the first direction;

[0051] a plurality of first doped regions 210 spaced apart along a second direction, wherein the conductivity type of the first doped regions 210 is opposite to that of the drift layer 200 , and the first doped regions 210 are spaced apart from a surface of the drift layer 200 facing the substrate layer 250 along the first direction;

[0052] a gate doping region 220 , located on a side of the first doping region 210 away from the substrate layer 250 along the first direction;

[0053] a source region 240 located between adjacent first doping regions 210 ;

[0054] a pinch-off region 230 , located between adjacent first doping regions 210 and between the substrate layer 250 and the source region 240 ;

[0055] The size of the first doping region 210 in the first direction is 0.8 micrometers to 4 micrometers; for example, the size of the first doping region 210 in the first direction is 0.8 micrometers, 1 micrometer, 1.4 micrometers, 1.6 micrometers, 2 micrometers, 3 micrometers or 4 micrometers.

[0056] The second direction intersects the first direction. For example, the second direction is perpendicular to the first direction.

[0057] In this embodiment, the size of the first doped region 210 in the first direction is 0.8 to 4 microns. This allows for a greater distance in the first direction between the surface of the first doped region 210 facing the substrate layer 250 and the surface of the source region 240 facing the substrate layer 250. Consequently, during shutdown, the depletion layer formed by the first doped region 210 and the pinch-off region can be pinched off at a location away from the source region 240, thereby reducing leakage. Because the first doped region 210 is larger in the first direction, the depletion layer formed by the first doped region 210 and the pinch-off region 230 is larger in the first direction during shutdown, thereby enhancing the pinch-off effect and further reducing leakage.

[0058] In this embodiment, the conductivity type of the first doping region 210 is opposite to the conductivity type of the drift layer 200 . For example, when the conductivity type of the drift layer 200 is N-type, the conductivity type of the first doping region 210 is P-type.

[0059] In this embodiment, the source region 240 extends from a surface of the drift layer 200 facing away from the substrate layer 250 along a first direction to a portion of the drift layer 200 between adjacent first doping regions 210 .

[0060] Furthermore, the first doping region 210 is an ion implantation region, so a trenching process is not required to form the first doping region 210 , which reduces the complexity of the process and improves the reliability of the first doping region 210 .

[0061] In this embodiment, the conductivity type of the substrate layer 250 is the same as that of the source region 240 and the drift layer 200 . The doping concentration of the source region 240 is greater than that of the drift layer 200 .

[0062] The first direction is perpendicular to the surface of the substrate layer 250 .

[0063] In this embodiment, the doping concentration of the drift layer 200 is lower than the doping concentration of the substrate layer 250. In one embodiment, the drift layer 210 is made of silicon carbide doped with N-type conductive ions, which may be phosphorus ions or nitrogen ions.

[0064] In this embodiment, the JFET device further includes a drain electrode 330 located on a side of the substrate layer 250 facing away from the drift layer 200. The material of the drain electrode 330 includes metal or alloy.

[0065] In this embodiment, the conductivity type of the first doping region 210 is opposite to the conductivity type of the drift layer 200 . For example, when the conductivity type of the first doping region 210 is P-type, the conductivity type of the drift layer 200 is N-type.

[0066] In this embodiment, the conductivity type of the gate doping region 220 is the same as the conductivity type of the first doping region 210. For example, the conductivity type of the first doping region 210 is P-type, and the conductivity type of the gate doping region 220 is P-type. The doping concentration of the gate doping region 220 is greater than the doping concentration of the first doping region 210.

[0067] In this embodiment, the depth of the gate doping region 220 in the first direction is smaller than the depth of the first doping region 210 in the first direction.

[0068] In this embodiment, the gate doping region 220 and the source region 240 have overlapping projections in the second direction and are in contact with each other.

[0069] In this embodiment, the JFET device further includes a source electrode 320 and a gate electrode 310. The source electrode 320 is located on a surface of the source region 240 that faces away from the substrate layer 250 along the first direction. The gate electrode 310 is located on a surface of the gate doped region 220 that faces away from the substrate layer 250 along the first direction. The source electrode 320 is made of a metal or an alloy. The gate electrode 310 is made of a metal or an alloy. The source electrode 320 and the gate electrode 310 are spaced apart in the second direction.

[0070] In this embodiment, the source electrode 320 is used to apply a first potential Source, and the gate electrode 310 is used to apply a second potential Gate.

[0071] In this embodiment, when the JFET device is in the off state, the second potential applied to the gate electrode 310 is a negative potential, so that the PN junction formed by the first doped region 210 and the pinch-off region 230 is reverse biased, the doping concentration of the first doped region 210 is greater than the doping concentration of the pinch-off region 230, and the depletion layer mainly expands in the pinch-off region 230.

[0072] Another embodiment of the present application further provides a JFET device. The difference between this embodiment and the previous embodiment is that, Figure 3 The JFET device also includes a second doping region 260, which penetrates the first doping region 210 and the pinch-off region 230 in the second direction. The conductivity type of the second doping region 260 is opposite to that of the first doping region 210, and the doping concentration of the second doping region 260 is greater than the doping concentration of the drift layer 200; the first doping region 210 is divided into a first sub-doping region and a second sub-doping region by the second doping region 260, and the first sub-doping region and the second sub-doping region are located on both sides of the second doping region 260 along the first direction and are connected to the second doping region 260.

[0073] The conductivity type of the second doping region 260 is opposite to the conductivity type of the first doping region 210 . For example, when the conductivity type of the first doping region 210 is P-type, the conductivity type of the second doping region 260 is N-type.

[0074] Figure 3 In the embodiment, due to the provision of the second doped region 260, the doping concentration of the second doped region 260 is greater than the doping concentration of the drift layer 200. When the JFET device is turned on, the second doped region 260 reduces the resistance of the current conduction path from the source region 240 to the drain electrode 330. Furthermore, when the JFET device is turned on, the provision of the second doped region 260 can also affect the depletion boundaries of the first doped region 210 and the pinch-off region 230, thereby increasing the extent of the depletion region in the first doped region 210 and reducing the extent of the depletion region in the pinch-off region 230 and the second doped region 260. This increases the width of the conduction path from the source region to the drain electrode 330, thereby reducing resistance.

[0075] The doping concentration of the second doping region 260 is much lower than the doping concentration of the source region 240 .

[0076] refer to Figure 3 The doping concentration of the second doping region 260 is 1.2 to 10 times, for example, 1.2 times, 3 times, 5 times, 8 times, or 10 times, the doping concentration of the drift layer 200 .

[0077] refer to Figure 3 The source region 240 and the second doping region 260 are spaced apart in the first direction.

[0078] If the size of the second doping region 260 in the first direction is too small, the degree of reducing the resistance of the current conduction path from the source region 240 to the drain electrode 330 is limited; if the size of the second doping region 260 in the first direction is too large, it is not conducive to improving the pinch-off performance of the JFET device when the JFET device is in the off state. In one embodiment, referring to Figure 3 The size of the second doping region 260 in the first direction is 0.2 micrometers to 1 micrometer, for example, 0.2 micrometers, 0.3 micrometers, 0.5 micrometers, 0.8 micrometers or 1 micrometer.

[0079] refer to Figure 3 The doping concentration of the first doping region 210 is greater than or equal to the doping concentration of the second doping region 260. This makes it easy for the second doping region 260 between adjacent first doping regions 210 to be depleted when the JFET device is in the off state, and the depletion layer can cover the second doping region 260 between adjacent first doping regions 210, making the JFET device easy to pinch off.

[0080] In one embodiment, the doping concentration of the first doping region 210 is 2E16atom / com 3 -7E16atom / com.

[0081] about Figure 3 Zhongyu Figure 2 The same contents will not be described in detail.

[0082] Another embodiment of the present application further provides a JFET device. The difference between this embodiment and the previous embodiment is that, Figure 4The JFET device further includes a second doped region 260, which is located between adjacent first doped regions 210. The second doped region 260 is located in a portion of the drift layer 200 between adjacent first doped regions 260. The conductivity type of the second doped region 260 is opposite to that of the first doped region 210, and the doping concentration of the second doped region 260 is greater than the doping concentration of the drift layer 200. The second doped region 260 is located on the side of the source region 240 facing the substrate layer 250 and is connected to the source region 240. The surface of the second doped region 260 facing the substrate layer 250 is farther away from the substrate layer 250 than the surface of the first doped region 210 facing the substrate layer 250. The second doped region 260 can reduce the on-resistance of the JFET device.

[0083] In this embodiment, the source region 240 extends from a surface of the drift layer 200 facing away from the substrate layer 250 along the first direction to a portion of the drift layer 200 between adjacent first doping regions 210. The second doping region 260 and the first doping region 210 have overlapping projections in the second direction.

[0084] refer to Figure 4 A second doping region 260 is located between a portion of adjacent first doping regions 210, while no second doping region is located between another portion of adjacent first doping regions 210. The presence of the second doping region 260 between a portion of adjacent first doping regions 210 reduces on-resistance. The absence of the second doping region between another portion of adjacent first doping regions 210 allows the pinch-off region between the other portion of adjacent first doping regions 210 to achieve a better pinch-off effect during shutdown.

[0085] If the size of the second doped region 260 in the first direction is too small, the degree to which the resistance of the current conduction path from the source region 240 to the drain electrode 330 is reduced is limited. If the size of the second doped region 260 in the first direction is too large, the pinch-off performance of the JFET device is not improved when the JFET device is in the off state. In one embodiment, the size of the second doped region 260 in the first direction is 0.3 microns to 2.5 microns, for example, 0.3 microns, 0.5 microns, 1 micron, 2 microns, or 2.5 microns.

[0086] In one embodiment, the doping concentration of the second doping region 260 is much lower than the doping concentration of the source region 240 .

[0087] In one embodiment, the doping concentration of the second doping region 260 is 1.2 to 10 times, for example, 1.2 times, 3 times, 5 times, 8 times, or 10 times, the doping concentration of the drift layer 200 .

[0088] In one embodiment, the doping concentration of the first doping region 210 is greater than or equal to the doping concentration of the second doping region 260. This makes it easier for the second doping region 260 between adjacent first doping regions 210 to be depleted when the JFET device is in the off state, making the JFET device easier to pinch off.

[0089] In one embodiment, the doping concentration of the first doping region 210 is 2E16atom / com 3 -7E16atom / com.

[0090] about Figure 4 Zhongyu Figure 2 The same contents will not be described in detail.

[0091] Another embodiment of the present application further provides a JFET device, the JFET device of the present application and Figure 2 The difference between JFET devices is: Figure 5 The JFET device further includes a second doped region 260, which is located between adjacent first doped regions 210. The conductivity type of the second doped region 260 is opposite to that of the first doped region 210, and the doping concentration of the second doped region 260 is greater than the doping concentration of the drift layer 200. The second doped region 260 is located on the side of the source region 240 facing the substrate layer 250 and is connected to the source region 240. The surface of the second doped region 260 facing the substrate layer 250 is farther away from the substrate layer 250 than the surface of the first doped region 210 facing the substrate layer 250. The second doped region 260 can reduce the on-resistance of the JFET device.

[0092] refer to Figure 5 The second doped region 260 protrudes in the second direction toward the first doped region 210. When the JFET device is turned on, the conductive path from the source region 240 to the drain electrode 330 is wider along the second direction at the location of the second doped region 260, thereby reducing the on-resistance. Preferably, a second doped region 260 is provided between adjacent first doped regions 210.

[0093] In one embodiment, the second doping region 260 is located between the source region 240 and the drift layer 200 in the first direction. The second doping region 260 and the first doping region 210 have overlapping projections in the second direction.

[0094] If the size of the second doped region 260 in the first direction is too small, the degree to which the resistance of the current conduction path from the source region 240 to the drain electrode 330 is reduced is limited. If the size of the second doped region 260 in the first direction is too large, the pinch-off performance of the JFET device is not improved when the JFET device is in the off state. In one embodiment, the size of the second doped region 260 in the first direction is 0.3 microns to 1.5 microns, for example, 0.3 microns, 0.5 microns, 1 micron, or 1.5 microns.

[0095] In one embodiment, the doping concentration of the second doping region 260 is much lower than the doping concentration of the source region 240 .

[0096] In one embodiment, the doping concentration of the second doping region 260 is 1.2 to 10 times, for example, 1.2 times, 3 times, 5 times, 8 times, or 10 times, the doping concentration of the drift layer 200 .

[0097] In one embodiment, the doping concentration of the first doping region 210 is greater than or equal to the doping concentration of the second doping region 260. This makes it easier for the second doping region 260 between adjacent first doping regions 210 to be depleted when the JFET device is in the off state, making the JFET device easier to pinch off.

[0098] In one embodiment, the doping concentration of the first doping region 210 is 2E16atom / com 3 -7E16atom / com.

[0099] about Figure 5 Zhongyu Figure 2 The same contents will not be described in detail.

[0100] Another embodiment of the present application also provides a method for preparing a JFET device, comprising: forming a drift layer on one side of a substrate layer along a first direction; forming a plurality of first doped regions spaced apart in a second direction in the drift layer; wherein the conductivity type of the first doped region is opposite to the conductivity type of the drift layer, and the first doped region is spaced apart from a surface of the drift layer facing the substrate layer along the first direction; forming a gate doped region, wherein the gate doped region is located on a side of the first doped region away from the substrate layer along the first direction; forming a source region, wherein the source region is located between adjacent first doped regions; a pinch-off region is provided between adjacent first doped regions and between the substrate layer and the source region; wherein a size of the first doped region in the first direction is 0.8 microns to 4 microns; wherein the second direction intersects with the first direction.

[0101] refer to Figures 6 to 9 A structural schematic diagram of a method for preparing a JFET device.

[0102] refer to Figure 6 , a drift layer 200 is formed on one side of the substrate layer 250 along the first direction.

[0103] The doping concentration of the drift layer 200 is lower than the doping concentration of the substrate layer 250 .

[0104] The process of forming the drift layer 200 includes an epitaxial growth process.

[0105] The description of the drift layer 200 and the substrate layer 250 refers to the description of the aforementioned embodiment and will not be repeated in detail.

[0106] refer to Figure 7 A plurality of initial first doping regions 2100 spaced apart in the second direction are formed in the drift layer 200 by ion implantation. The initial first doping regions 2100 are spaced apart from a surface of the drift layer 200 facing the substrate layer 250 along the first direction.

[0107] In this embodiment, the initial first doped region 2100 extends from a surface of the drift layer 200 facing away from the substrate layer 250 along a first direction into a portion of the drift layer 200 .

[0108] The conductivity type of the initial first doping region 2100 is opposite to that of the drift layer 200 .

[0109] The process of forming the initial first doping region 2100 includes an ion implantation process. A trenching process is not required to form the initial first doping region 2100 , which reduces the complexity of the process and improves the reliability of the initial first doping region 2100 .

[0110] In one embodiment, the ion implantation process for forming the initial first doped region 2100 includes a first sub-ion implantation and / or a second sub-ion implantation. The first sub-ion implantation is performed along a first crystal direction of the drift layer 200, and the second sub-ion implantation is performed along a second crystal direction of the drift layer 200. The first crystal direction is the crystal direction with the highest linear density of atoms in the drift layer 200. The linear density of atoms in the drift layer 200 along the second crystal direction is 40% to 70% of the linear density of atoms in the drift layer 200 along the first crystal direction. The angle between the second crystal direction and the first crystal direction is greater than zero.

[0111] The first sub-ion injection and the second sub-ion injection can be injected through the gaps inside the lattice of the drift layer 200. The ion injection has less scattering, which can increase the injection depth while reducing the injection energy, and reduce the injection damage, so that the initial first doped region 2100 has a larger thickness in the first direction.

[0112] In one embodiment, the drift layer 200 is made of SiC. In other embodiments, the drift layer 200 may be made of other materials.

[0113] In one embodiment, the drift layer 200 is made of 4H—SiC, the first crystal orientation is <0001>, and the second crystal orientation is <11-23>.

[0114] In one embodiment, in the first sub-ion injection, the incident ions are subjected to the blocking barrier height of the atoms arranged along the first crystal direction in the drift layer 200; in the second sub-ion injection, the incident ions are subjected to the blocking barrier height of the atoms arranged along the second crystal direction in the drift layer 200; wherein the blocking barrier height in the second sub-ion injection is 35%-65% of the blocking barrier height in the first sub-ion injection.

[0115] A pinch-off region 230 is defined between adjacent initial first doping regions 2100 .

[0116] refer to Figure 8 , forming a source region 240; and forming a gate doping region 220.

[0117] The process of forming the source region 240 includes an ion implantation process. The process of forming the gate doping region 220 includes an ion implantation process.

[0118] The initial first doping region 2100 of the gate doping region 220 facing the substrate layer 250 along the first direction serves as the first doping region 210. The gate doping region 220 is located on the side of the first doping region 210 facing away from the substrate layer 250 along the first direction. The source region 240 is located between adjacent first doping regions 210.

[0119] In this embodiment, the source region 240 extends from a surface of the drift layer 200 facing away from the substrate layer 250 along a first direction to a portion of the drift layer 200 between adjacent first doping regions 210 .

[0120] The gate doping region 220 has the same conductivity type as the first doping region 210. For example, the first doping region 210 has a P-type conductivity, and the gate doping region 220 has a P-type conductivity. The gate doping region 220 has a greater doping concentration than the first doping region 210.

[0121] In this embodiment, the gate doping region 220 and the source region 240 have overlapping projections in the second direction and are in contact with each other.

[0122] There is no limitation on the order of forming the source region 240 and the gate doping region 220 .

[0123] refer to Figure 9, forming a source electrode 320 and a gate electrode 310, the source electrode 320 is located on the side surface of the source region 240 away from the substrate layer 250 along the first direction, and the gate electrode 310 is located on the side surface of the gate doping region 220 away from the substrate layer 250 along the first direction; forming a drain electrode 330, the drain electrode 330 is located on the side of the substrate layer 250 away from the drift layer 200.

[0124] The source electrode 320 and the gate electrode 310 are spaced apart from each other in the second direction.

[0125] Figures 10 to 13 Schematic diagram of the structure of the preparation process of a JFET device in another embodiment of the present application.

[0126] refer to Figure 10 , a drift layer 200 is formed on one side of the substrate layer 250 along the first direction.

[0127] The description of this step refers to the description of the above embodiment.

[0128] refer to Figure 11 A plurality of initial first doping regions 2100 spaced apart in the second direction are formed in the drift layer 200 by ion implantation. The initial first doping regions 2100 are spaced apart from a surface of the drift layer 200 facing the substrate layer 250 along the first direction.

[0129] In this embodiment, the initial first doped region 2100 extends from a surface of the drift layer 200 facing away from the substrate layer 250 along a first direction into a portion of the drift layer 200 .

[0130] The conductivity type of the initial first doping region 2100 is opposite to that of the drift layer 200 .

[0131] The process of forming the initial first doping region 2100 includes an ion implantation process. The initial first doping region 2100 does not require a trenching process, which reduces the complexity of the process and improves the reliability of the initial first doping region 2100. The description of this step is similar to that of the previous embodiment.

[0132] A pinch-off region 230 is defined between adjacent initial first doping regions 2100 .

[0133] refer to Figure 12 , forming a second doping region 260, the second doping region 260 penetrates the initial first doping region 2100 and the pinch-off region 230 in the second direction, the conductivity type of the second doping region 260 is opposite to the conductivity type of the initial first doping region 2100, and the doping concentration of the second doping region 260 is greater than the doping concentration of the drift layer 200.

[0134] The second doping region 260 is formed by an ion implantation process.

[0135] In one embodiment, the doping concentration of the second doping region 260 is 1.2 to 10 times, for example, 1.2 times, 3 times, 5 times, 8 times, or 10 times, the doping concentration of the drift layer 200 .

[0136] In one embodiment, the size of the second doping region 260 in the first direction is 0.2 micrometers to 1 micrometer, for example, 0.2 micrometers, 0.5 micrometers, 0.8 micrometers, or 1 micrometer.

[0137] The description of the second doping region 260 in this embodiment is as follows Figure 3 Detailed description of the second doped region 260 in FIG.

[0138] refer to Figure 13 , forming a source region 240; and forming a gate doping region 220.

[0139] The process of forming the source region 240 includes an ion implantation process. The process of forming the gate doping region 220 includes an ion implantation process.

[0140] The initial first doping region 2100 of the gate doping region 220 facing the substrate layer 250 along the first direction serves as the first doping region 210. The gate doping region 220 is located on the side of the first doping region 210 facing away from the substrate layer 250 along the first direction. The source region 240 is located between adjacent first doping regions 210.

[0141] The gate doping region 220 has the same conductivity type as the first doping region 210. For example, the first doping region 210 has a P-type conductivity, and the gate doping region 220 has a P-type conductivity. The gate doping region 220 has a greater doping concentration than the first doping region 210.

[0142] In this embodiment, the source region 240 extends from a surface of the drift layer 200 facing away from the substrate layer 250 along a first direction to a portion of the drift layer 200 between adjacent first doping regions 210 .

[0143] The source region 240 and the second doping region 260 are spaced apart from each other in the first direction.

[0144] The doping concentration of the second doping region 260 is much lower than the doping concentration of the source region 240 .

[0145] The first doping region 210 is divided into a first sub-doping region and a second sub-doping region by the second doping region 260 . The first sub-doping region and the second sub-doping region are located on both sides of the second doping region 260 along the first direction and connected to the second doping region 260 .

[0146] In one embodiment, the doping concentration of the first doping region 210 is greater than or equal to the doping concentration of the second doping region 260 .

[0147] In this embodiment, the gate doping region 220 and the source region 240 have overlapping projections in the second direction and are in contact with each other.

[0148] There is no limitation on the order of forming the source region 240 and the gate doping region 220 .

[0149] refer to Figure 13 , forming a source electrode 320 and a gate electrode 310, the source electrode 320 is located on the side surface of the source region 240 away from the substrate layer 250 along the first direction, and the gate electrode 310 is located on the side surface of the gate doping region 220 away from the substrate layer 250 along the first direction; forming a drain electrode 330, the drain electrode 330 is located on the side of the substrate layer 250 away from the drift layer 200.

[0150] The source electrode 320 and the gate electrode 310 are spaced apart from each other in the second direction.

[0151] Figures 14 to 17 Schematic diagram of the structure of the preparation process of a JFET device in another embodiment of the present application.

[0152] refer to Figure 14 , a drift layer 200 is formed on one side of the substrate layer 250 along the first direction.

[0153] The description of this step refers to the description of the above embodiment.

[0154] refer to Figure 15 A plurality of initial first doping regions 2100 spaced apart in the second direction are formed in the drift layer 200 by ion implantation. The initial first doping regions 2100 are spaced apart from a surface of the drift layer 200 facing the substrate layer 250 along the first direction.

[0155] In this embodiment, the initial first doped region 2100 extends from a surface of the drift layer 200 facing away from the substrate layer 250 along a first direction into a portion of the drift layer 200 .

[0156] The conductivity type of the initial first doping region 2100 is opposite to that of the drift layer 200 .

[0157] The process of forming the initial first doping region 2100 includes an ion implantation process. The initial first doping region 2100 does not require a trenching process, which reduces the complexity of the process and improves the reliability of the initial first doping region 2100. The description of this step is similar to that of the previous embodiment.

[0158] There is a pinch-off region 230 between adjacent initial first doping regions 2100. Figure 16 , forming a second doping region 260; forming a source region 240; and forming a gate doping region 220.

[0159] The process for forming the source region 240 includes an ion implantation process. The process for forming the second doped region 260 includes an ion implantation process. The process for forming the gate doped region 220 includes an ion implantation process. The order of forming the source region 240 and the gate doped region 220 is not limited.

[0160] The initial first doping region 2100 of the gate doping region 220 facing the substrate layer 250 along the first direction serves as the first doping region 210. The gate doping region 220 is located on the side of the first doping region 210 facing away from the substrate layer 250 along the first direction. The source region 240 is located between adjacent first doping regions 210.

[0161] The gate doping region 220 has the same conductivity type as the first doping region 210. For example, the first doping region 210 has a P-type conductivity, and the gate doping region 220 has a P-type conductivity. The gate doping region 220 has a greater doping concentration than the first doping region 210.

[0162] The second doping region 260 is located between adjacent first doping regions 210. The second doping region 260 is located in a portion of the drift layer 200 between adjacent first doping regions 210. The conductivity type of the second doping region 260 is opposite to that of the first doping region 210, and the doping concentration of the second doping region 260 is greater than the doping concentration of the drift layer 200. The second doping region 260 is located on a side of the source region 240 facing the substrate layer 250 and is connected to the source region 240. The surface of the second doping region 260 facing the substrate layer 250 is further away from the substrate layer 250 than the surface of the first doping region 210 facing the substrate layer 250.

[0163] The source region 240 extends from a surface of the drift layer 200 facing away from the substrate layer 250 along a first direction to a portion of the drift layer 200 between adjacent first doping regions 210 .

[0164] In one embodiment, the second doping region 260 is formed between a portion of adjacent first doping regions 210 , and no second doping region is formed between another portion of adjacent first doping regions 210 .

[0165] In one embodiment, the size of the second doping region 260 in the first direction is 0.3 micrometers to 2.5 micrometers, such as 0.3 micrometers, 0.5 micrometers, 1 micrometer, 2 micrometers, or 2.5 micrometers.

[0166] In one embodiment, the doping concentration of the second doping region 260 is much lower than the doping concentration of the source region 240 .

[0167] In one embodiment, the doping concentration of the second doping region 260 is 1.2 to 10 times, for example, 1.2 times, 3 times, 5 times, 8 times, or 10 times, the doping concentration of the drift layer 200 .

[0168] In one embodiment, the doping concentration of the first doping region 210 is greater than or equal to the doping concentration of the second doping region 260 .

[0169] In this embodiment, the gate doping region 220 and the source region 240 have overlapping projections in the second direction and are in contact with each other.

[0170] refer to Figure 17 , forming a source electrode 320 and a gate electrode 310, the source electrode 320 is located on the side surface of the source region 240 away from the substrate layer 250 along the first direction, and the gate electrode 310 is located on the side surface of the gate doping region 220 away from the substrate layer 250 along the first direction; forming a drain electrode 330, the drain electrode 330 is located on the side of the substrate layer 250 away from the drift layer 200.

[0171] The source electrode 320 and the gate electrode 310 are spaced apart from each other in the second direction.

[0172] Figures 18 to 21 Schematic diagram of the structure of the preparation process of a JFET device in another embodiment of the present application.

[0173] refer to Figure 18 , a drift layer 200 is formed on one side of the substrate layer 250 along the first direction.

[0174] The description of this step refers to the description of the above embodiment.

[0175] refer to Figure 19 An initial second doped region 2600 is epitaxially formed on a side of the drift layer 200 away from the substrate layer 250 .

[0176] The process of forming the initial second doping region 2600 is an epitaxial growth process.

[0177] The doping concentration of the initial second doping region 2600 is greater than the doping concentration of the drift layer 200 , and the conductivity type of the initial second doping region 2600 is the same as that of the drift layer 200 .

[0178] refer to Figure 20 , a plurality of initial first doping regions spaced apart in the second direction are formed in the drift layer 200 by an ion implantation process; in the process of forming the initial first doping regions, the ion implantation process implants ions into part of the drift layer 200 and part of the initial second doping region 2600, and neutralizes part of the initial second doping region 2600, and the initial second doping regions 2600 between adjacent initial first doping regions in the second direction form second doping regions 260.

[0179] refer to Figure 20 , forming a source region 240; and forming a gate doping region 220.

[0180] The process of forming the source region 240 includes an ion implantation process. The process of forming the gate doping region 220 includes an ion implantation process. The order of forming the source region 240 and forming the gate doping region 220 is not limited.

[0181] The initial first doping region 2100 of the gate doping region 220 facing the substrate layer 250 along the first direction serves as the first doping region 210. The gate doping region 220 is located on the side of the first doping region 210 facing away from the substrate layer 250 along the first direction. The source region 240 is located between adjacent first doping regions 210.

[0182] The gate doping region 220 has the same conductivity type as the first doping region 210. For example, the first doping region 210 has a P-type conductivity, and the gate doping region 220 has a P-type conductivity. The gate doping region 220 has a greater doping concentration than the first doping region 210.

[0183] The second doping region 260 is located between adjacent first doping regions 210. The conductivity type of the second doping region 260 is opposite to that of the first doping region 210, and the doping concentration of the second doping region 260 is greater than the doping concentration of the drift layer 200. The second doping region 260 is located on the side of the source region 240 facing the substrate layer 250 and is connected to the source region 240. The surface of the second doping region 260 facing the substrate layer 250 is farther away from the substrate layer 250 than the surface of the first doping region 210 facing the substrate layer 250. The second doping region 260 protrudes toward the first doping region 210 in the second direction.

[0184] The second doping region 260 is located between the source region 240 and the drift layer 200 in the first direction.

[0185] In one embodiment, the size of the second doping region 260 in the first direction is 0.3 micrometers to 1 micrometer, for example, 0.5 micrometers, 1 micrometer, 1.5 micrometers, or 2 micrometers.

[0186] In one embodiment, the doping concentration of the second doping region 260 is 1.2 to 10 times, for example, 1.2 times, 3 times, 5 times, 8 times, or 10 times, the doping concentration of the drift layer 200 .

[0187] In one embodiment, the doping concentration of the first doping region 210 is greater than or equal to the doping concentration of the second doping region 260 .

[0188] In one embodiment, the doping concentration of the second doping region 260 is much lower than the doping concentration of the source region 240 .

[0189] In this embodiment, the gate doping region 220 and the source region 240 have overlapping projections in the second direction and are in contact with each other.

[0190] refer to Figure 21 , forming a source electrode 320 and a gate electrode 310, the source electrode 320 is located on the side surface of the source region 240 away from the substrate layer 250 along the first direction, and the gate electrode 310 is located on the side surface of the gate doping region 220 away from the substrate layer 250 along the first direction; forming a drain electrode 330, the drain electrode 330 is located on the side of the substrate layer 250 away from the drift layer 200.

[0191] The source electrode 320 and the gate electrode 310 are spaced apart from each other in the second direction.

[0192] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A JFET device, characterized in that: include: substrate layer; a drift layer located on one side of the substrate layer along the first direction; a plurality of first doped regions spaced apart along a second direction, wherein the conductivity type of the first doped regions is opposite to the conductivity type of the drift layer, and the first doped regions are spaced apart from a surface of the drift layer facing the substrate layer along the first direction; a gate doping region, located on a side of the first doping region away from the substrate layer along the first direction; a source region, located between adjacent first doping regions; a pinch-off region, located between adjacent first doping regions and between the substrate layer and the source region; Wherein, the size of the first doping region in the first direction is 0.8 micrometers to 4 micrometers; The second direction intersects with the first direction.

2. The JFET device according to claim 1, wherein: The first doping region is an ion implantation region.

3. The JFET device according to claim 1, wherein: Also includes: a second doping region, the second doping region penetrating the first doping region and the pinch-off region in a second direction, the conductivity type of the second doping region being opposite to that of the first doping region, and the doping concentration of the second doping region being greater than the doping concentration of the drift layer; the first doping region being divided by the second doping region into a first sub-doping region and a second sub-doping region, the first sub-doping region and the second sub-doping region being located on both sides of the second doping region along the first direction and connected to the second doping region; Preferably, the size of the second doping region in the first direction is 0.2 micrometers to 1 micrometer; Preferably, the source region and the second doping region are spaced apart in the first direction.

4. The JFET device according to claim 1, wherein: Also includes: A second doping region, wherein the second doping region is located between adjacent first doping regions; the conductivity type of the second doping region is opposite to the conductivity type of the first doping region, and the doping concentration of the second doping region is greater than the doping concentration of the drift layer; wherein the second doping region is located on a side of the source region facing the substrate layer and is connected to the source region; a surface of the second doping region facing the substrate layer is farther away from the substrate layer than a surface of the first doping region facing the substrate layer.

5. The JFET device according to claim 4, characterized in that The second doping region protrudes toward the first doping region in the second direction; Preferably, the second doping region is located between adjacent first doping regions; Preferably, the second doped region is located between the source region and the drift layer in the first direction; Preferably, a size of the second doping region in the first direction is 0.3 microns to 1.5 microns.

6. The JFET device according to claim 4, wherein: The second doping region is located between a portion of adjacent first doping regions, and the second doping region is not located between another portion of adjacent first doping regions; Preferably, the second doping region is located in a portion of the drift layer between adjacent first doping regions; Preferably, a size of the second doping region in the first direction is 0.3 micrometers to 2.5 micrometers.

7. The JFET device according to any one of claims 4 to 6, characterized in that: The doping concentration of the first doping region is greater than or equal to the doping concentration of the second doping region; Preferably, the doping concentration of the second doping region is 1.2 to 10 times the doping concentration of the drift layer.

8. A method for preparing a JFET device, characterized in that: include: forming a drift layer on one side of the substrate layer along a first direction; forming a plurality of first doped regions spaced apart in a second direction in the drift layer; wherein the conductivity type of the first doped regions is opposite to that of the drift layer, and the first doped regions are spaced apart from a surface of the drift layer facing the substrate layer along the first direction; forming a gate doping region, wherein the gate doping region is located on a side of the first doping region away from the substrate layer along the first direction; forming a source region, wherein the source region is located between adjacent first doping regions; and a pinch-off region is provided between adjacent first doping regions and between the substrate layer and the source region; Wherein, the size of the first doping region in the first direction is 0.8 micrometers to 4 micrometers; The second direction intersects with the first direction.

9. The method for preparing a JFET device according to claim 8, wherein: Also includes: forming a second doping region, the second doping region penetrating the first doping region and the pinch-off region in a second direction, the conductivity type of the second doping region being opposite to that of the first doping region, and the doping concentration of the second doping region being greater than the doping concentration of the drift layer; the first doping region being divided by the second doping region into a first sub-doping region and a second sub-doping region, the first sub-doping region and the second sub-doping region being located on both sides of the second doping region along the first direction and connected to the second doping region; Preferably, the source region and the second doping region are spaced apart in the first direction.

10. The method for preparing a JFET device according to claim 8, wherein: Also includes: A second doping region is formed, wherein the second doping region is located between adjacent first doping regions; the conductivity type of the second doping region is opposite to the conductivity type of the first doping region, and the doping concentration of the second doping region is greater than the doping concentration of the drift layer; wherein the second doping region is located on a side of the source region facing the substrate layer and is connected to the source region; a surface of the second doping region facing the substrate layer is farther away from the substrate layer than a surface of the first doping region facing the substrate layer.

11. The method for preparing a JFET device according to claim 10, wherein: The forming of the first doping region and the gate doping region includes: forming a plurality of initial first doping regions spaced apart in the second direction in the drift layer by an ion implantation process; forming a gate doping region, wherein the gate doping region is the initial first doping region on a side of the substrate layer along the first direction as the first doping region; Preferably, the ion implantation process for forming the initial first doping region includes a first sub-ion implantation and / or a second sub-ion implantation; wherein, the implantation direction of the first sub-ion implantation is along the first crystal direction of the drift layer, and the implantation direction of the second sub-ion implantation is along the second crystal direction of the drift layer; the first crystal direction is the crystal direction with the highest linear arrangement density of atoms in the drift layer; the linear arrangement density of atoms in the drift layer along the second crystal direction is 40%-70% of the linear arrangement density of atoms in the drift layer along the first crystal direction; and the angle between the second crystal direction and the first crystal direction is greater than zero.

12. The method for preparing a JFET device according to claim 11, wherein: The step of forming the second doping region includes: before forming the initial first doping region, epitaxially forming an initial second doping region on a side of the drift layer facing away from the substrate layer; during the process of forming the initial first doping region, an ion implantation process is used to implant ions into a portion of the drift layer and a portion of the initial second doping region, and neutralize a portion of the initial second doping region, so that the initial second doping region between adjacent initial first doping regions in the second direction forms the second doping region; Wherein, the second doping region protrudes toward the first doping region in a second direction.

13. The method for preparing a JFET device according to claim 10, wherein: The second doping region is formed between a portion of adjacent first doping regions.

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