A super-junction power MOSFET structure with optimized linear output and its preparation method

Abstract

The present invention provides a super-junction power MOSFET structure with optimized linear output and a preparation method thereof, which are used to solve the technical problem that the output signal of the traditional SJMOS device structure is distorted or generates unnecessary harmonics, resulting in the inability of the power management system to output stably. The present invention provides multiple pillar regions within the silicon drift region, and is provided with a guard ring and a surface guard ring on the outside thereof; the width and doping concentration of the pillar regions and the guard rings are both distributed in a gradient decreasing from top to bottom; the upper surfaces of the multiple pillar regions are sequentially provided with a shield region and a base region from bottom to top, and the shield region is wider than the base region; JFET regions are provided on both sides of the shield region and the base region, and the doping concentration of the shield region and the JFET region is distributed in an inverse gradient, and the corresponding depth of the doping peak concentration is located at the bottom of the base region; the doping concentration of the shield region is higher than that of the base region, and the doping concentration of the JFET region is higher than that of the silicon drift region; the base region is provided with a source region and a source electrode contact region, and the source electrode is conductively connected to the source electrode contact region.

Description

Technical Field

[0001] The present invention relates to a power semiconductor, and in particular to a super junction power MOSFET structure with optimized linear output and a preparation method thereof. Background Art

[0002] Power metal-oxide semiconductor field-effect transistors (Power MOSFETs), also known as power MOSFETs, are the primary power switches used in today's power electronics applications, widely used in automotive, industrial, lighting, and computer applications. Power MOSFETs are typically used for switching at a given frequency. Previously, their linear operation was limited to a few applications, such as audio amplifiers and linear DC-DC converters. Currently, linear operation is also widely used in many other applications, including low-voltage and high-voltage devices, such as electronic loads, industrial applications with slow switching speeds using high-voltage and ultra-high-voltage devices (up to 1000V), and fan controllers in automotive applications.

[0003] Modern power MOS tubes are constantly developing and have broken through the "Si limit" for R by introducing compensation structures. ON and V BD The super junction MOSFET (SuperJunctionMOSFET, SJMOS) is one of the typical representative structures. The multiple epitaxial super junction is achieved by ion implantation in the silicon epitaxial layer and repeated multiple times, and finally the pillar structure is introduced under the base area. The pillar columnar structure and the SJMOS form a super junction in the drift area, and the charge compensation effect of the pillar structure on the drift area is used to increase the doping concentration of the drift area as much as possible. Through the appropriate pillar / drift junction doping concentration and structural size design, the high V DS In the voltage blocking state, the space charge regions of the PN junctions formed by adjacent pillars / drifts are overlapped and connected, forming a uniform space charge region in the entire lateral drift region to bear high withstand voltage and achieve low R DS(ON) and high V BD .

[0004] However, the traditional SJMOS device structure does not pay attention to the linearity of the output current relative to the input gate-source voltage during linear application of the device, that is, the problem of transconductance stability, which leads to output signal distortion or the generation of unnecessary harmonics, which is not conducive to the stable output of the power management system. Summary of the Invention

[0005] The purpose of the present invention is to solve the technical problem that the traditional SJMOS device structure does not pay attention to the linearity of the output current relative to the input gate-source voltage when the device is used linearly, resulting in output signal distortion or generation of unnecessary harmonics, which is not conducive to the stable output of the power management system, and to provide a super junction power MOSFET structure with optimized linear output and a preparation method thereof.

[0006] In order to achieve the above objectives, the technical solutions of the present invention are:

[0007] A super-junction power MOSFET structure with optimized linear output, which is special in that it includes a silicon substrate, a silicon drift region located on the upper surface of the silicon substrate, and a drain electrode located on the lower surface of the silicon substrate;

[0008] The silicon drift region is provided with a plurality of columnar pillar regions for forming an active region, and a guard ring is provided outside the plurality of pillar regions for forming a terminal region; the width of the pillar regions and the guard rings are both distributed in a gradient decreasing distribution from top to bottom; the doping concentration of the pillar regions and the guard rings are both distributed in a gradient decreasing distribution from top to bottom; the Pillar regions and the guard rings introduce a variable width structure and a gradient doping distribution, so that the device has a current path with a more uniform width in the longitudinal direction when in the on state, thereby reducing the on-state resistance and suppressing current concentration;

[0009] The upper surfaces of the plurality of pillar regions are sequentially provided with Shield regions and Base regions from bottom to top, and the width of the Shield region is greater than that of the Base region; JFET regions are provided on both sides of the Shield region and the Base region, and two adjacent JFET regions are connected as one; the doping concentrations of the Shield region and the JFET region are both distributed in an inverse gradient, and the corresponding depth of the doping peak concentration is located at the bottom of the Base region; the doping concentration of the Shield region is higher than the doping concentration of the Base region, and the doping concentration of the JFET region is higher than the doping concentration of the silicon Drift region; preferably, the doping concentration range of the Base region is 5E16~5E17, the peak doping concentration range of the Shield region is 5E17~5E18, and the peak doping concentration range of the JFET region is 2E17~5E18.

[0010] A surface guard ring is provided on the upper surface of the guard ring; the upper surfaces of the surface guard ring, the JFET region and the base region are all flush with the upper surface of the silicon drift region;

[0011] The Source region and the source electrode contact region are sequentially arranged in the Base region from the outside to the inside; the upper surfaces of the Source region and the source electrode contact region are flush with the upper surface of the JFET region;

[0012] A field oxide layer is provided on the upper surface of the surface protection ring, and the field oxide layer is in contact with the upper surface of the JFET region; a gate oxide layer, a gate electrode and an injection shielding oxide layer are provided on the upper surface of the JFET region from bottom to top, and the gate oxide layer is in contact with the upper surface of the Base region; a dielectric layer is provided on the upper surfaces of the field oxide layer and the shielding oxide layer, and the dielectric layer extends to the Source region; a source electrode is provided on the dielectric layer, and the source electrode is conductively connected to the source electrode contact region.

[0013] Furthermore, the doping concentrations of the Shield region, JFET region, Base region, and silicon Drift region meet the following requirements:

[0014] When the bias voltage applied to the drain electrode is insufficient to cause the PN junction space charge region formed by the pillar region and the silicon drift region to overlap, the PN junction formed by the shield region and the JFET region on both sides of the MOS structure unit is reverse biased and overlaps to form a potential barrier, which is used to shield the area below the gate oxide layer and reduce the voltage borne by the base region;

[0015] When the MOS structure is in the on state with the gate electrode biased, a potential barrier is formed between the Shield region and the JFET region due to the overlap of the space charge region, which shields the area above the Base region, so that the MOS structure channel can withstand higher V DS The voltage can avoid premature channel pinch-off and maintain the linear output characteristics of the drain-source current in a larger voltage range.

[0016] Furthermore, the doping concentration range of the Pillar region and the guard ring decreases gradually from 2E17 to 2E18 at the top to 1E17 to 1E18 at the bottom.

[0017] Furthermore, the width of the Pillar region decreases linearly from 2 to 2.5 um at the top to 1 to 1.5 um at the bottom, and the distance between adjacent Pillar regions increases linearly from 2 to 1.5 um at the top to 3 to 2.5 um at the bottom.

[0018] Furthermore, the dielectric layer includes a USG layer and a BPSG layer located on the upper surface of the USG layer;

[0019] A passivation structure is provided on the upper surface of the source electrode.

[0020] Furthermore, the silicon substrate, silicon drift region, JFET region and source region are N-type; the pillar region, surface guard ring, shield region and base region are P-type;

[0021] Alternatively, the silicon substrate, silicon drift region, JFET region and source region are of P type; the pillar region, surface guard ring, shield region and base region are of N type.

[0022] Based on the above-mentioned super-junction power MOSFET structure with optimized linear output, the present invention further provides a method for preparing the super-junction power MOSFET structure with optimized linear output, which is special in that it includes the following steps:

[0023] 1] Select a silicon substrate, deposit an epitaxial layer on the silicon substrate as the first layer structure of the drift region, and perform a first type of ion implantation on the first layer structure of the drift region;

[0024] 2] Performing a photolithography process on the first layer structure of the drift area to define the first layer cylindrical guard ring area and the first layer cylindrical Pillar area, and performing a second type of ion implantation on the guard ring area and the Pillar area to form the first layer structure of the guard ring and the first layer structure of the Pillar area;

[0025] 3] On the drift region first layer structure formed with the guard ring first layer structure and the pillar region first layer structure, an epitaxial layer is deposited again as the drift region second layer structure;

[0026] 4] Repeat the same process in steps 2] to 3] 4 to 6 times on each layer of the Drift region structure, and finally form a silicon Drift region, a columnar structured guard ring, and a Pillar region; wherein, when defining each layer of the columnar guard ring region and each layer of the columnar Pillar region, their widths are gradually increased, and in the second type ion process implantation of each layer of the columnar guard ring region and each layer of the columnar Pillar region, the second type ion implantation dose is gradually increased, so that the width and doping concentration of the pillar region and the guard ring are distributed in a gradient increasing direction from the silicon substrate side toward the JFET region; then, a surface guard ring region is defined on the upper surface of the silicon Drift by a photolithography process, and the surface guard ring region is implanted with the second type ion to form a surface guard ring;

[0027] 5] Thermally grow an oxide layer on the surface of the silicon drift region that forms the surface guard ring, and form a field oxide layer and an active region outside the field oxide layer through a photolithography process; thermally grow an oxide layer on the surface of the active region, and perform a first type of ion implantation on the active region to form a JFET region, so that the doping concentration in the JFET region has an inverse gradient distribution; then remove the oxide layer on the surface of the active region;

[0028] 6] On the upper surface of the wafer where the field oxide layer and the JFET region are formed, a thermal oxide layer growth, polysilicon deposition, and oxide layer deposition process are sequentially performed, and a corresponding gate oxide layer, gate electrode, implantation mask oxide layer, and gate implantation window are formed by photolithography; a second type of ion implantation is performed in the shield region through the gate implantation window;

[0029] 7] Anneal the second type of ions injected into the Shield region to form the Shield region, so that the doping concentration in the Shield region is distributed in an inverse gradient; then, implant the second type of ions into the Base region through the gate injection window;

[0030] 8] Anneal the second type of ions implanted in the Base region to form the Base region; define the Source region in the gate implantation window through a photolithography process, and implant the first type of ions into the Source region;

[0031] 9] Anneal the first type of ions implanted into the Source region to form a Source region;

[0032] 10] After forming the Source region, a dielectric layer is deposited on the upper surface of the wafer, and then metal electrode contact holes are formed on the dielectric layer through photolithography and etching processes;

[0033] 11] Performing a second type of ion implantation on the source electrode contact region through the metal electrode contact hole, followed by annealing to form the source electrode contact region;

[0034] 12] Depositing a metal layer on the upper surface of the wafer where the active electrode contact area is formed, and patterning the metal layer through photolithography and etching processes to form a source electrode;

[0035] 13] A metal layer is evaporated on the lower surface of the silicon substrate to form a drain electrode, completing the preparation of a super-junction power MOSFET structure with optimized linear output.

[0036] Furthermore, step a] is further included between step 12 and step 13;

[0037] a] Deposit a passivation layer on the source electrode and form a passivation structure through photolithography and etching processes.

[0038] Furthermore, the silicon substrate is N-type, the first type of ions are N-type, and the second type of ions are P-type;

[0039] Alternatively, the silicon substrate is of P type, the first type ions are of P type, and the second type ions are of N type.

[0040] Furthermore, in step 1], the silicon substrate is N-type, and the deposition thickness of the epitaxial layer is 10-20 μm;

[0041] The first type of ions are arsenic ions, with an implantation energy of 50 KeV to 90 KeV and a dose of 8.0E12 to 2.4E13;

[0042] In step 2], the second type of ions are boron ions, the implantation energy is 40KeV to 70KeV, and the implantation dose is 8.0E12 to 2.4E13;

[0043] In step 3], the epitaxial layer is deposited to a thickness of 5 to 7 μm;

[0044] In step 4], the second type of ions are boron ions, the implantation energy is 30KeV to 50KeV, and the implantation dose is 8.0E12 to 2.4E13;

[0045] In step 5, the growth temperature of the thermally grown oxide layer on the surface of the silicon drift forming the surface protection ring is 1100℃ and the thickness is The growth temperature of the thermally grown oxide layer on the active area is 1150℃ and the thickness is

[0046] The first type of ions are arsenic ions, with an implantation energy of 100 KeV to 150 KeV and an implantation dose of 1.5E13 to 3.5E13;

[0047] In step 6, the temperature of the thermally grown oxide layer is 1050°C and the thickness is The thickness of polysilicon deposition is The thickness of the implanted shielding oxide layer is The second type of ions is boron ions, with an implantation energy of 100-150 KeV and an implantation dose of 8E13-1E14;

[0048] In step 7, the annealing temperature of the shield area is 1100-1150°C, and the annealing time is 90-120 minutes. The second type is boron ions, with an implantation energy of 40-50 KeV and an implantation dose of 3E13-5E13.

[0049] In step 8], the annealing temperature of the base region is 1100-1150°C, and the annealing time is 90-120 min. The first type of ions is arsenic ions, and the implantation energy is 40-60 KeV, and the implantation dose is 8E15-1.2E16.

[0050] In step 9], the annealing temperature is 950-1000° C. and the annealing time is 90-120 min;

[0051] In step 11, the second type of ions is boron ions, the implantation energy is 60-80 KeV, the implantation dose is 3E14-5E14; the annealing temperature is 900-1000°C, and the annealing time is 20-30 min.

[0052] In step 12], the metal layer is deposited to a thickness of 4 to 6 μm.

[0053] The beneficial effects of the present invention compared to the prior art are:

[0054] 1. The present invention provides a super junction power MOSFET structure with optimized linear output. Compared with the traditional SJMOS structure, the present invention introduces a Shield region with an inverse gradient doping distribution below the Base region, and the concentration and width are greater than the Base region. At the same time, the JFET region also presents an inverse gradient doping distribution, so that the Shield region and the JFET region can form a narrow JFET region structure at the doping peak depth; the introduction of the high-concentration Shield region and the narrow JFET region structure enables the MOS cell structure to withstand low V DS When the voltage is high, the PN junction space charge regions of the Shield region and the JFET region on both sides overlap to form a potential barrier, which has a shielding effect on the Base region. On the one hand, it can reduce the voltage drop borne by the Base region and reduce the channel length of the MOS structure. In the short channel device, it helps to suppress the occurrence of punch-through breakdown and obtain a smaller channel resistance. On the other hand, it can effectively reduce the reverse transfer capacitance of the device and improve the high-frequency characteristics and switching loss of the device.

[0055] 2. The present invention provides a super junction power MOSFET structure with optimized linear output. By introducing a high-concentration Shield region and forming a narrow JFET region structure, the PN junction space charge region of the Shield region and the JFET region on both sides can be DS The voltage overlaps before it reaches the channel pinch-off voltage, which can shield the high V DS The voltage pinches off the channel, maintaining the linear output characteristics of the MOSFET in a larger voltage range, and on the other hand, it can suppress the short channel effect. DS Better maintain high output resistance under voltage.

[0056] 3. The present invention provides a super-junction power MOSFET structure with linear output characteristics. Due to the provision of a high-concentration JFET region, the increase in resistance caused by the narrow JFET region structure can be further compensated, so that the present invention has good resistance characteristics and reduces on-state power consumption.

[0057] 4. The present invention provides a super-junction power MOSFET structure with optimized linear output, in which the width and doping concentration of the pillar region are both gradiently distributed. Due to the lower impurity doping concentration in the silicon drift region, the longitudinal voltage drop of the device gradually decreases from the silicon substrate side to the device surface, and at the same time, the space charge region formed by the PN junction composed of the silicon drift and the pillar region on the substrate side is narrower; combined with the characteristic of the Pillar region structure that the width decreases from top to bottom, the current path width of the device is uniformly distributed in the longitudinal direction when the device is in the on state, which helps to reduce the resistance of the silicon drift region, reduce the on-state power consumption, and improve the current concentration of the device when operating at high current in linear applications.

[0058] 5. The present invention provides a method for preparing a super-junction power MOSFET structure with optimized linear output, which is simple, efficient and highly practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 A schematic structural diagram of an embodiment of a super-junction power MOSFET structure with optimized linear output according to the present invention;

[0060] Figure 2-1 Schematic diagram of step 1 of the preparation method according to an embodiment of the present invention;

[0061] Figure 2-2 Schematic diagram of step 2 of the preparation method according to an embodiment of the present invention;

[0062] Figure 2-3 Schematic diagram of step 3 of the preparation method according to an embodiment of the present invention;

[0063] Figure 2-4 Schematic diagram of step 4 of the preparation method according to an embodiment of the present invention;

[0064] Figure 2-5 Schematic diagram of step 5 of the preparation method according to an embodiment of the present invention;

[0065] Figure 2-6 Schematic diagram of step 6 of the preparation method according to an embodiment of the present invention;

[0066] Figure 2-7 Schematic diagram of step 7 of the preparation method according to an embodiment of the present invention;

[0067] Figure 2-8 Schematic diagram of step 8 of the preparation method according to an embodiment of the present invention;

[0068] Figure 2-9 Schematic diagram of step 9 of the preparation method according to an embodiment of the present invention;

[0069] Figure 2-10 Schematic diagram of step 10 of the preparation method according to an embodiment of the present invention;

[0070] Figure 2-11 Schematic diagram of step 11 of the preparation method according to an embodiment of the present invention;

[0071] Figure 2-12 Schematic diagram of step 12 of the preparation method according to an embodiment of the present invention;

[0072] Figure 2-13 Schematic diagram of step 13 of the preparation method according to an embodiment of the present invention;

[0073] Figure 2-14 Schematic diagram of step 14 of the preparation method according to an embodiment of the present invention;

[0074] Figure 3 This is a diagram of the gradient-increasing doping distribution in the pillar region in an embodiment of the present invention.

[0075] The specific reference numerals are as follows:

[0076] 1-Silicon substrate; 2-Silicon Drift region, 2-1-Drift region first layer structure, 2-2-Drift region second layer structure; 3-pillar region, 3-1-Pillar region first layer structure; 4-guard ring, 4-1-guard ring first layer structure; 41-surface guard ring; 5-field oxide layer; 6-JFET region; 7-gate oxide layer; 8-gate electrode; 9-injection shielding oxide layer; 10-Shield region; 11-Base region; 12-Source region; 13-USG layer; 14-BPSG layer; 15-source electrode contact region; 16-source electrode; 17-passivation structure; 18-drain electrode. DETAILED DESCRIPTION

[0077] In order to make the advantages and features of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0078] like Figure 1As shown, a superjunction power MOSFET structure with optimized linear output comprises a silicon substrate 1, a silicon drift region 2 located on the upper surface of the silicon substrate 1, and a drain electrode 18 located on the lower surface of the silicon substrate 1. Multiple pillar regions 3 are disposed within the silicon drift region 2 to form the active region. Guard rings 4 are disposed outside the pillar regions 3 to form the termination region. Specifically, the widths of the pillar regions 3 and guard rings 4 decrease in a gradient from top to bottom, and the doping concentrations of the pillar regions 3 and guard rings also decrease in a gradient from top to bottom. The pillar regions and guard rings incorporate a variable-width structure and gradient doping profile to provide a more uniform current path in the longitudinal direction when the device is in the on state, reducing on-state resistance and suppressing current concentration. Furthermore, shield regions 10 and base regions 11 are disposed sequentially on the upper surfaces of the multiple pillar regions 3, with the shield region 10 being wider than the base region 11. JFET regions 6 are disposed on both sides of the shield regions 10 and base regions 11. The doping concentrations of the Shield region 10 and the JFET region 6 are both inversely gradient distributed, and the corresponding depths of the doping peak concentrations are both located at the bottom of the Base region 11. The doping concentration of the Shield region 10 is higher than that of the Base region 11, and the doping concentration of the JFET region 6 is higher than that of the silicon Drift region 2. The structural design and doping concentration design of the JFET region 6, the Shield region 10, and the Base region 11 work together to suppress the high V DS voltage pinches off the channel, and the lower V DSIt has a shielding effect on the Base region under voltage. A surface protection ring 41 is provided on the upper surface of the protection ring 4. The upper surfaces of the surface protection ring 41, the JFET region 6 and the Base region 11 are all flush with the upper surface of the silicon Drift region 2. The Source region 12 and the source electrode contact region 15 are sequentially provided in the Base region 11 from the outside to the inside. The upper surfaces of the Source region 12 and the source electrode contact region 15 are all flush with the upper surface of the JFET region 6. A field oxide layer 5 is provided on the upper surface of the surface protection ring 41, and the field oxide layer 5 is in contact with the upper surface of the JFET region 6; a gate oxide layer 7, a gate electrode 8 and an injection shielding oxide layer 9 are sequentially provided on the upper surface of the JFET region 6 from bottom to top, and the gate oxide layer 7 is in contact with the upper surface of the Base region 11. A dielectric layer is provided on the upper surface of the field oxide layer 5 and the shielding oxide layer 9, and the dielectric layer extends to the Source region 12; the integrated dielectric layer in this embodiment includes a USG layer 13 and a BPSG layer 14 located on the upper surface of the USG layer 13. In other embodiments of the present invention, other forms of dielectric layers may also be used. A source electrode 16 is provided on the BPSG layer 14, and the source electrode 16 is connected to the source electrode contact region 15. In this embodiment, a passivation structure 17 is provided on the upper surface of the source electrode 16.

[0079] In this embodiment, the silicon substrate 1, silicon drift region 2, JFET region 6, and source region 12 are N-type, while the pillar region 3, surface guard ring 41, shield region 10, and base region 11 are P-type. In other embodiments of the present invention, when the silicon substrate 1, silicon drift region 2, JFET region 6, and source region 12 are P-type, the pillar region 3, surface guard ring 41, shield region 10, and base region 11 are N-type accordingly. Preferably, the doping concentration of the pillar region 3 and the guard ring 4 is the same, decreasing gradually from 2E17-2E18 at the top to 1E17-1E18 at the bottom. The width of the pillar region 3 decreases linearly from 2-2.5um at the top to 1-1.5um at the bottom, and the spacing between adjacent pillar regions 3 increases linearly from 2-1.5um at the top to 3-2.5um at the bottom. The implanted ions in the base region 11 are boron ions, and their doping concentration ranges from 5E16 to 5E17. The implanted ions in the shield region 10 are boron ions, and their doping peak concentration ranges from 5E17 to 5E18. The implanted ions in the JFET region 6 are arsenic ions, and their doping peak concentration ranges from 2E17 to 5E18.

[0080] Operating Principle: When no bias is applied to gate electrode 8 and a high positive bias is applied to drain electrode 18, the operating principle of the present invention's optimized linear output superjunction power MOSFET structure is similar to that of a conventional SJMOS. The PN junction space charge regions formed by the pillar regions 3 and silicon drift regions 2 of adjacent MOS structural units overlap, forming a uniform spatial electric field across the entire silicon drift region 2, which supports high voltage. However, when the bias applied to the drain electrode 18 is low and insufficient to cause the PN junction space charge region formed by the pillar region 3 and the silicon drift region 2 to overlap, the Shield region 10 and the JFET region 6 of the present invention form a narrow JFET region structure at the doping peak depth. The high concentration of the Shield region 10 and the introduction of the narrow JFET region structure will cause the PN junction formed by the Shield region 10 on both sides of the MOS structure unit and the JFET region 6 directly below the gate electrode 8 to be reverse biased and overlapped under the condition of low or insufficient bias of the drain electrode 18, so that this region can still form a potential barrier when the bias of the drain electrode 18 is low. The formed potential barrier will shield the area below the gate oxide layer 7, thereby reducing the voltage borne by the Base region 11. This effect can reduce the channel length of the MOS structure while avoiding the problem of low V DS Punch-through breakdown of the base space charge region occurs under bias, thereby obtaining a smaller channel length and reducing channel resistance in the MOS structure.

[0081] Due to the precise definition of the doping concentration and size of the Shield region 10 and the JFET region 6 in the present invention, when the MOS structure is in the on state with a bias applied to the gate electrode 8, the Shield region 10 and the PN junction space charge region of the JFET region 6 overlap to form a potential barrier, shielding the area above the Base region 11. This shielding has the following effects: 1. It reduces the voltage drop in the Base region; 2. It reduces the PN junction space charge region of the Shield region and the JFET region on both sides at V DS The voltage overlaps before it reaches the channel pinch-off voltage, causing the MOS structure channel to withstand higher V DSFirst, it can avoid premature channel pinch-off when the voltage is low, and maintain the linear output characteristics of the drain-source current in a larger voltage range; second, it can make the channel modulation effect of the MOS structure small enough at high electric fields, and maintain the high output resistance in its linear region; third, it can help achieve a smaller channel length and a higher transconductance, and reduce the switching loss of the device. On the other hand, the high-concentration JFET region 6 set in the present invention can further compensate for the increase in resistance caused by the narrow JFET region structure, so that the present invention has good resistance characteristics and reduces on-state power consumption. At the same time, the present invention introduces a decreasing distribution of width from top to bottom and a decreasing distribution of doping concentration from top to bottom in the pillar region 3. Due to the lower impurity doping concentration of the silicon drift region 2, the longitudinal voltage drop of the device gradually decreases from the side of the silicon substrate 1 to the device surface. By introducing a decreasing distribution of impurity doping concentration in pillar region 3 from top to bottom, the space charge region formed on the substrate side by the PN junction formed by the silicon drift region 2 and the pillar region 3 is narrower. At the same time, combined with the characteristic that the width of the pillar region 3 decreases from top to bottom, the current path width of the device is uniformly distributed in the longitudinal direction when the device is in the on state. This helps to reduce the resistance of the silicon drift region 2, lower the on-state power consumption, and improve the current concentration of the device when operating at high current in linear applications.

[0082] Based on the above embodiments, the present invention further provides a method for preparing a super junction power MOSFET structure with optimized linear output, which specifically includes the following steps:

[0083] 1] If Figure 2-1 As shown, an N+ type silicon substrate 1 is selected, an N-type epitaxial layer is deposited on the N+ type silicon substrate 1 as the first layer structure 2-1 of the N-type drift region, and arsenic ions are implanted into the first layer structure 2-1 of the N-type drift region; wherein the deposition thickness of the N-type epitaxial layer is 10-20 μm; the arsenic ion implantation energy is 50 KeV to 90 KeV, and the dose is 8.0E12 to 2.4E13;

[0084] 2] If Figure 2-2 As shown, a photolithography process is performed on the first layer structure 2-1 of the N-type Drift region to define a first layer columnar guard ring region and a first layer columnar Pillar region, and boron ions are implanted into the guard ring region and the Pillar region to form a P-type guard ring first layer structure 4-1 and a P-type Pillar region first layer structure 3-1; wherein the boron ion implantation energy is 40KeV to 70KeV, and the implantation dose is 8.0E12 to 2.4E13;

[0085] 3] If Figure 2-3As shown, on the N-type Drift region first layer structure 2-1 on which the P-type guard ring first layer structure 4-1 and the P-type Pillar region first layer structure 3-1 are formed, an N-type epitaxial layer is deposited again as the N-type Drift region second layer structure 2-2, with a deposition thickness of 5 to 7 μm.

[0086] 4] If Figure 2-4 As shown, the same process in steps 2] to 3] is repeated 4 to 6 times on each layer of the N-type Drift region structure to form an N-type silicon Drift region 2, a P-type guard ring 4 of a columnar structure, and a P-type Pillar region 3; wherein, when defining each layer of the columnar guard ring region and each layer of the columnar Pillar region, their widths are gradually increased so that the widths of each layer of the guard ring region and each layer of the Pillar region are distributed in a gradient increasing manner from the silicon substrate 1 side to the JFET region 6; and in the second type ion process implantation of each layer of the columnar guard ring region and each layer of the columnar Pillar region, the second type ion implantation dose is gradually increased so that the doping concentrations of the pillar region 3 and the guard ring 4 are distributed in a gradient increasing manner from the silicon substrate 1 side to the JFET region 6. The specific gradient doping distribution is as follows: Figure 3 As shown; a surface guard ring region is defined on the upper surface of the N-type silicon Drift region 2 by a photolithography process, and boron ions are implanted into the surface guard ring region to form a P-type surface guard ring 41; wherein the boron ion implantation energy is 30KeV to 50KeV, and the implantation dose is 8.0E12 to 2.4E13;

[0087] 5】As Figure 2-5 As shown, an oxide layer is thermally grown on the upper surface of the N-type silicon Drift region 2 forming the P-type surface protection ring 41. The growth temperature is 1100°C and the thickness is The field oxide layer 5 and the active area outside the field oxide layer 5 are formed by photolithography; an oxide layer is thermally grown on the upper surface of the active area at a growth temperature of 1150°C and a thickness of Arsenic ions are implanted into the active region to form an N+ type JFET region 6, so that the doping concentration in the JFET region 6 is distributed in an inverse gradient; the oxide layer on the surface of the active region is then removed; wherein the arsenic ion implantation energy is 100KeV to 150KeV, and the implantation dose is 1.5E13 to 3.5E13;

[0088] 6】As Figure 2-6 As shown, on the upper surface of the wafer with the field oxide layer 5 and the N+ type JFET region 6, thermal growth oxide layer, polysilicon deposition and oxide layer deposition processes are sequentially performed, and the corresponding gate oxide layer 7, gate electrode 8, injection mask oxide layer 9 and gate injection window are formed by photolithography process; wherein, the temperature of the thermal growth oxide layer is 1050℃ and the thickness is The thickness of polysilicon deposition is The thickness of the implanted shielding oxide layer is Perform boron ion implantation in the P+ shield region through the gate implantation window, with an implantation energy of 100-150 KeV and an implantation dose of 8E13-1E14;

[0089] 7】As Figure 2-7 As shown, the boron ions implanted into the P+ shield region are annealed to form a P+ shield region 10, so that the doping concentration in the P+ shield region 10 is distributed in an inverse gradient. The annealing temperature is 1100-1150° C., and the annealing time is 90-120 min. Subsequently, boron ions are implanted into the P-type base region through the gate implantation window. The implantation energy is 40-50 KeV, and the implantation dose is 3E13-5E13.

[0090] 8】As Figure 2-8 As shown, the boron ions implanted into the P-type base region are annealed to form a P-type base region 11. The annealing temperature is 1100-1150° C. and the annealing time is 90-120 min. An N+ type source region is defined in the gate implantation window through a photolithography process, and arsenic ions are implanted into the N+ type source region. The implantation energy is 40-60 KeV and the implantation dose is 8E15-1.2E16.

[0091] 9】As Figure 2-9 As shown, the arsenic ions implanted into the N+ type Source region are annealed to form an N+ type Source region 12. The annealing temperature is 950-1000° C. and the annealing time is 90-120 min.

[0092] 10】As Figure 2-10 As shown, after forming the N+ type Source region 12, a USG layer 13 (undoped silicon oxide glass) and a BPSG layer 14 (borosilicate glass) are sequentially deposited on the upper surface of the wafer as dielectric layers. A dielectric layer is deposited, and then a metal electrode contact hole is formed on the dielectric layer by photolithography. The deposition thickness of the USG layer 13 is The deposition thickness of the BPSG layer 14 is

[0093] 11】As Figure 2-11 As shown, a BF2 injection process is performed in the source electrode contact region through the metal electrode contact hole, and annealing is performed after the injection to form the source electrode contact region 15. The injection energy is 60 to 80 KeV, the injection dose is 3E14 to 5E14, the annealing temperature is 900 to 1000° C., and the annealing time is 20 to 30 minutes.

[0094] 12】As Figure 2-12As shown, an AlSiCu metal layer with a thickness of 4 to 6 μm is deposited on the upper surface of the wafer where the active electrode contact area 15 is formed, and the AlSiCu metal layer is patterned by a photolithography process to form a source electrode 16;

[0095] 13】As Figure 2-13 As shown, a passivation layer is deposited on the source electrode 16, and a passivation structure 17 is formed by photolithography and etching processes;

[0096] 14】As Figure 2-14 As shown, a Ti / Ni / Ag metal layer is evaporated on the lower surface of the silicon substrate 1 to form a drain electrode (18), thereby completing the preparation of a super junction power MOSFET structure with optimized linear output.

[0097] In other embodiments of the present invention, when preparing a super-junction power MOSFET structure, when the silicon substrate 1 is P-type, the type of doping ions required to be implanted in each step will also change, forming a corresponding P-type silicon Drift region 2, N-type pillar region 3, N-type guard ring 4, N-type surface guard ring 41, P-type JFET region 6, N-type Shield region 10, N-type Base region 11 and P-type Source region 12.

[0098] The present invention provides a super-junction power MOSFET structure with optimized linear output, which can be used in applications such as linear amplifiers / voltage regulators, plug-in circuits, battery charging / motor speed regulation, and intelligent switches, meeting the application requirements of various types of power management chips for high-performance, high-reliability linear power MOSFET devices.

[0099] It is worth noting that in the present invention, Drift region refers to the drift region, Base region refers to the base region, Source region refers to the source region, Shield region refers to the shield region, and Pillar region refers to the pillar region. The above description is only used to illustrate the technical solution of the present invention, not to limit it. For ordinary professionals in this field, it is possible to modify the specific technical solutions described in the above embodiments, or to replace some of the technical features therein with equivalents. Such modifications or replacements do not cause the essence of the corresponding technical solution to deviate from the scope of the technical solution protected by the present invention.

Claims

1. A super-junction power MOSFET structure with optimized linear output, characterized by: It comprises a silicon substrate (1), a silicon drift region (2) located on the upper surface of the silicon substrate (1), and a drain electrode (18) located on the lower surface of the silicon substrate (1); A plurality of columnar pillar regions (3) are provided in the silicon drift region (2) for forming an active region, and a guard ring (4) is provided outside the plurality of pillar regions (3) for forming a terminal region; the widths of the pillar regions (3) and the guard ring (4) are both distributed in a gradient decreasing manner from top to bottom; the doping concentrations of the pillar regions (3) and the guard ring (4) are both distributed in a gradient decreasing manner from top to bottom; Shield regions (10) and base regions (11) are sequentially arranged on the upper surfaces of the plurality of pillar regions (3) from bottom to top, the width of the shield region (10) being greater than the width of the base region (11); JFET regions (6) are arranged on both sides of the shield region (10) and the base region (11); the doping concentrations of the shield region (10) and the JFET region (6) are both distributed in an inverse gradient, and the corresponding depth of the doping peak concentration is both located at the bottom of the base region (11); the doping concentration of the shield region (10) is higher than the doping concentration of the base region (11), and the doping concentration of the JFET region (6) is higher than the doping concentration of the silicon drift region (2); The upper surface of the protection ring (4) is provided with a surface protection ring (41); the upper surfaces of the surface protection ring (41), the JFET region (6) and the base region (11) are all flush with the upper surface of the silicon drift region (2); The base region (11) is provided with a source region (12) and a source electrode contact region (15) in sequence from the outside to the inside; the upper surfaces of the source region (12) and the source electrode contact region (15) are flush with the upper surface of the JFET region (6); The upper surface of the surface protection ring (41) is provided with a field oxide layer (5), and the field oxide layer (5) is in contact with the upper surface of the JFET region (6); the upper surface of the JFET region (6) is provided with a gate oxide layer (7), a gate electrode (8), and an injection shielding oxide layer (9) in sequence from bottom to top, and the gate oxide layer (7) is in contact with the upper surface of the Base region (11); the upper surfaces of the field oxide layer (5) and the shielding oxide layer (9) are provided with a dielectric layer, and the dielectric layer extends to the Source region (12); a source electrode (16) is provided on the dielectric layer, and the source electrode (16) is conductively connected to the source electrode contact region (15).

2. The super junction power MOSFET structure with optimized linear output according to claim 1, characterized in that: The doping concentrations of the Shield region (10), the JFET region (6), the Base region (11) and the silicon Drift region (2) meet the following requirements: When the bias voltage applied to the drain electrode (18) is insufficient to cause the PN junction space charge region formed by the pillar region (3) and the silicon drift region (2) to overlap, the PN junction formed by the shield region (10) and the JFET region (6) on both sides of the MOS structure unit is reverse biased and overlaps to form a potential barrier, which is used to shield the area below the gate oxide layer (7) and reduce the voltage borne by the base region (11); When the MOS structure is in an on-state with a bias applied to the gate electrode (8), a potential barrier is formed between the Shield region (10) and the JFET region (6) due to the overlap of the space charge region, thereby forming a shielding effect on the area above the Base region (11), thereby preventing the MOS structure channel from being pinched off prematurely and maintaining the linear output characteristics of the drain-source current within a larger voltage range.

3. The super junction power MOSFET structure with optimized linear output according to claim 1, characterized in that: The doping concentration range of the Pillar region (3) and the guard ring (4) decreases gradually from 2E17 to 2E18 at the top to 1E17 to 1E18 at the bottom.

4. The super junction power MOSFET structure with optimized linear output according to claim 3, characterized in that: The width of the Pillar region (3) decreases linearly from 2 to 2.5 μm at the top to 1 to 1.5 μm at the bottom, and the distance between adjacent Pillar regions (3) increases linearly from 2 to 1.5 μm at the top to 3 to 2.5 μm at the bottom.

5. A super junction power MOSFET structure with optimized linear output according to any one of claims 1 to 4, characterized in that: The dielectric layer includes a USG layer (13) and a BPSG layer (14) located on the upper surface of the USG layer (13); A passivation structure (17) is provided on the upper surface of the source electrode (16).

6. The super junction power MOSFET structure with optimized linear output according to claim 5, characterized in that: The silicon substrate (1), silicon drift region (2), JFET region (6) and source region (12) are of N-type; the pillar region (3), surface protection ring (41), shield region (10) and base region (11) are of P-type; Alternatively, the silicon substrate (1), silicon drift region (2), JFET region (6) and source region (12) are of P type; and the pillar region (3), surface protection ring (41), shield region (10) and base region (11) are of N type.

7. A method for preparing a super junction power MOSFET structure with optimized linear output according to any one of claims 1 to 6, characterized in that: The following steps are involved: 1] Selecting a silicon substrate (1), depositing an epitaxial layer on the silicon substrate (1) as a first layer structure (2-1) of the drift region, and performing a first type of ion implantation on the first layer structure (2-1) of the drift region; 2] Performing a photolithography process on the first layer structure (2-1) of the drift region to define a first layer cylindrical guard ring region and a first layer cylindrical Pillar region, and performing a second type of ion implantation on the guard ring region and the Pillar region to form a first layer structure (4-1) of the guard ring and a first layer structure (3-1) of the Pillar region; 3] On the drift region first layer structure (2-1) on which the guard ring first layer structure (4-1) and the pillar region first layer structure (3-1) are formed, an epitaxial layer is deposited again as the drift region second layer structure (2-2); 4] Repeat the same process in steps 2] to 3] 4 to 6 times on each layer of the Drift region structure to form a silicon Drift region (2), a columnar structured protection ring (4), and a Pillar region (3); wherein, when defining each layer of the columnar protection ring region and each layer of the columnar Pillar region, their widths are gradually increased, and in the second type ion process implantation of each layer of the columnar protection ring region and each layer of the columnar Pillar region, the second type ion implantation dose is gradually increased; then, a surface protection ring region is defined on the upper surface of the silicon Drift (2) by a photolithography process, and the surface protection ring region is implanted with the second type ions to form a surface protection ring (41); 5] Thermally growing an oxide layer on the upper surface of the silicon drift region (2) forming the surface protection ring (41), forming a field oxide layer (5) and an active region outside the field oxide layer (5) through a photolithography process; thermally growing an oxide layer on the upper surface of the active region, and performing a first type of ion implantation on the active region to form a JFET region (6), so that the doping concentration in the JFET region (6) is distributed in an inverse gradient; and then removing the oxide layer on the surface of the active region; 6] On the upper surface of the wafer on which the field oxide layer (5) and the JFET region (6) are formed, thermal oxide layer growth, polysilicon deposition and oxide layer deposition processes are sequentially performed, and a corresponding gate oxide layer (7), a gate electrode (8), an implantation mask oxide layer (9) and a gate implantation window are formed by a photolithography process; and a second type of ion implantation is performed in the shield region through the gate implantation window; 7] Annealing the second type of ions injected into the Shield region to form a Shield region (10), so that the doping concentration in the Shield region (10) is distributed in an inverse gradient; and then injecting the second type of ions into the Base region through the gate injection window; 8] Annealing the second type of ions injected into the base region to form a base region (11); defining a source region in the gate injection window through a photolithography process, and injecting the first type of ions into the source region; 9] Annealing the first type of ions implanted into the Source region to form a Source region (12); 10] After forming the Source region (12), a dielectric layer is deposited on the upper surface of the wafer, and then a metal electrode contact hole is formed on the dielectric layer by photolithography and etching processes; 11] Performing a second type of ion implantation in the source electrode contact region through the metal electrode contact hole, and performing annealing after the implantation to form a source electrode contact region (15); 12] depositing a metal layer on the upper surface of the wafer where the active electrode contact region (15) is formed, and patterning the metal layer through photolithography and etching processes to form a source electrode (16); 13] A metal layer is evaporated on the lower surface of the silicon substrate (1) to form a drain electrode (18), thereby completing the preparation of a super-junction power MOSFET structure with optimized linear output.

8. The method for preparing a super junction power MOSFET structure with optimized linear output according to claim 7, characterized in that: Also included between step 12 and step 13 is step a]; a] Depositing a passivation layer on the source electrode (16), and forming a passivation structure (17) through photolithography and etching processes.

9. The method for preparing a super junction power MOSFET structure with optimized linear output according to claim 8, characterized in that: The silicon substrate (1) is N-type, the first type of ions are N-type, and the second type of ions are P-type; Alternatively, the silicon substrate (1) is of P type, the first type of ions are of P type, and the second type of ions are of N type.

10. The method for preparing a super junction power MOSFET structure with optimized linear output according to any one of claims 7 to 9, characterized in that: In step 1], the silicon substrate (1) is N-type, and the deposition thickness of the epitaxial layer is 10-20 μm; The first type of ions are arsenic ions, with an implantation energy of 50 KeV to 90 KeV and a dose of 8.0E12 to 2.4E13; In step 2], the second type of ions are boron ions, the implantation energy is 40KeV to 70KeV, and the implantation dose is 8.0E12 to 2.4E13; In step 3], the epitaxial layer is deposited to a thickness of 5 to 7 μm; In step 4], the second type of ions are boron ions, the implantation energy is 30KeV to 50KeV, and the implantation dose is 8.0E12 to 2.4E13; In step 5], the growth temperature of the thermally grown oxide layer on the surface of the silicon Drift (2) forming the surface protection ring (41) is 1100°C and the thickness is The growth temperature of the thermally grown oxide layer on the active area is 1150℃ and the thickness is The first type of ions are arsenic ions, with an implantation energy of 100 KeV to 150 KeV and an implantation dose of 1.5E13 to 3.5E13; In step 6, the temperature of the thermally grown oxide layer is 1050°C and the thickness is The thickness of polysilicon deposition is The thickness of the implanted shielding oxide layer is The second type of ions is boron ions, with an implantation energy of 100-150 KeV and an implantation dose of 8E13-1E14; In step 7, the annealing temperature of the shield area is 1100-1150°C, and the annealing time is 90-120 minutes. The second type is boron ions, with an implantation energy of 40-50 KeV and an implantation dose of 3E13-5E13. In step 8], the annealing temperature of the base region is 1100-1150°C, and the annealing time is 90-120 min. The first type of ions is arsenic ions, and the implantation energy is 40-60 KeV, and the implantation dose is 8E15-1.2E16. In step 9], the annealing temperature is 950-1000° C. and the annealing time is 90-120 min; In step 11, the second type of ions is boron ions, the implantation energy is 60-80 KeV, the implantation dose is 3E14-5E14; the annealing temperature is 900-1000°C, and the annealing time is 20-30 min. In step 12], the metal layer is deposited to a thickness of 4 to 6 μm.

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