Power mosfet with variable transparency edge ring formed by deep self-aligned implantation

Abstract

To provide a method for forming an edge ring that at least partially surrounds an active area of an electronic device by obtaining an edge ring implant in a self-aligned manner.SOLUTION: A method includes disposing an N-type semiconductor body 50 having a lattice structure with spatial symmetry, forming damaged regions 80a to 80c in the semiconductor body having an amorphous lattice structure or a lattice structure without spatial symmetry, and forming a P-type edge termination region 68 in the semiconductor body, and the forming of the P-type edge termination region includes performing a channeling implant of a P-type doping species in the damaged region and in portions of the semiconductor body adjacent to each side of the damaged region.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to Italian Patent Application No. 102024000005770, filed March 14, 2024, and entitled "MOSFET DI POTENZA PROVVISTO DI ANELLO DI BORDO A TRASPARENZA VARIABILE FORMATO MEDIANTE UN IMPIANTO AUTOALLINEATO AD ELEVATA PROFONDITA," which is incorporated herein by reference to the fullest extent permitted by law.

[0002] The present disclosure relates to electronic devices and methods for fabricating the same, and more particularly to a method for forming an edge ring that at least partially surrounds an active area of ​​an electronic device by utilizing intentionally damaged regions to obtain an edge ring implant in a self-aligned manner. [Background technology]

[0003] Ion implantation is nowadays an established technique for introducing dopants into silicon carbide, SiC, since dopant diffusion is not an applicable technique due to the low diffusivity of SiC compared to other semiconductor materials (e.g., silicon), and epitaxial growth may not be a useful alternative, especially for locally confined volumes.

[0004] As is known, the crystalline structure of SiC influences the depth distribution obtained during implantation. Indeed, so-called channeling can significantly increase the penetration depth of ions into crystalline materials relative to amorphous targets. This phenomenon can occur when the direction of the impinging ion beam is approximately parallel to the major crystal axes or planes. In these directions, the reduction in energy loss per ion path length is smaller, and therefore the ions travel deeper into the target.

[0005] To theoretically explain the probability of channeling, the concept of "critical channeling angle" has been introduced. In this case, the critical angle is considered as the maximum angle between the axial row of atoms and the incident beam at which ions are still guided along that axis. To investigate and predict the channeling phenomenon during ion implantation, different software exists today for Monte Carlo simulations in crystalline targets, for example using the binary collision approximation (MC-BCA).

[0006] Channeling is often an undesirable effect, and SiC wafers are typically tilted in a random, non-channeling direction to minimize channeling effects during implantation. A roughly Gaussian doping profile with respect to depth is thus obtained, the depth being determined by the energy, the ions used, and the target atomic structure. On the other hand, if the implantation is performed along the crystallographic axis, a completely different profile is obtained, with the ions following the crystallographic direction at depth into the target. It has been demonstrated that in SiC, the deepest channeled ions can penetrate many times beyond the range of action expected for a corresponding random implant.

[0007] It is known to use implantation hard masks, for example of silicon oxide (SiO2), configured to locally shield the SiC wafer during the implantation step in order to form locally confined implantation regions. However, the applicant has verified that the use of a hard mask of the aforementioned type can cause flatness problems of the layer to which the mask is applied after removing the same mask, due to lattice stress effects created on the SiC substrate by the presence of this hard mask.

[0008] Furthermore, the use of such a hard mask limits the mutual spatial distance between adjacent implants, as is the case with, for example, variable transparency type edge termination rings. Figure 1 illustrates an electronic device provided with this type of edge termination ring, according to an embodiment that is not necessarily prior art.

[0009] Referring to Figure 1, a portion of a chip containing an electronic device 1, such as a power MOSFET, is illustrated limited to its edge region surrounding an active area. The chip portion in Figure 1 is illustrated in a three-axis Cartesian reference system with mutually orthogonal axes X, Y, and Z. Electronic device 1 includes a semiconductor body 10 made of SiC having a first conductivity type (N-type) and defined along axis Z by opposing front and rear surfaces 10a, 10b, with a side surface 10c connecting front surface 10a to rear surface 10b along axis Z; a body region 14 having a second conductivity type (P-type) opposite to the first conductivity type (N-type) and extending within semiconductor body 10; a source region 17 within body region 14; a first edge termination region 16 having a second conductivity type (P-type) that is in electrical contact with body region 14 and extends facing front surface 10a; and a second edge termination region 16 having a second conductivity type (P-type) that is higher than the doping value of body region 14 and lower than the doping value of first edge termination region 16. The electronic device 1 includes a second edge termination region 18 (the aforementioned variable transparency ring) having a low doping value, a dielectric layer 20 on the front surface 10a, a conductive layer 22 on the dielectric layer 20 and forming an edge field plate of the electronic device 1, and a first metallization 24a in electrical contact with the conductive layer 22 and a second metallization 24b in electrical contact with the first edge termination region 16 and the source 17, where the first metallization 24a and the second metallization 24b apply a predetermined bias voltage (typically in a voltage range of 10-20 V) between the first metallization 24a and the second metallization 24b. Figure 1 further illustrates a channel stop region 19, which extends laterally relative to the second edge termination region 18, specifically between the second edge termination region 18 and the side surface 10c. The channel stop region 19 functions to form an equipotential ring.

[0010] Second edge termination region 18 is formed by implanting a doping species having a second conductivity and extends along axis Z to a depth of several micrometers, e.g., up to 5 μm, into semiconductor body 10. Second edge termination region 18 includes a plurality of implanted subregions 18′ that extend in turn along axis X and are separated from one another by respective portions of semiconductor body 10. Each implanted subregion 18′ may have an extension along axis X that is different from that of the other implanted subregions 18′, and in particular, may have an extension that decreases from first edge termination region 16 toward channel stop region 19.

[0011] First edge termination region 16 and second edge termination region 18 function to prevent or reduce the generation of electric fields of values ​​that could damage electronic device 1. In particular, applicants have demonstrated that edge termination regions of the type illustrated in Figure 1 are intended to improve the distribution of electric fields in devices with voltage ratings up to 3300V, distributing the electric field lines in the edge region below the critical breakdown value of the semiconductor material used.

[0012] Formation of second edge termination region 18 particularly contemplates the use of a high-energy, high-dose channeled deep ion implant to reach a desired depth while locally inverting the conductivity of semiconductor body 10 (from N-type to P-type) until the desired doping value of implanted subregions 18′ is achieved. Formation of second edge termination region 18, as noted, contemplates the use of a hard mask for deep implantation of dopants having the second conductivity (P) to a depth of up to 5 μm along axis Z. However, as noted, this type of hard mask limits the minimum separation dimension along axis X between implanted subregions 18′, particularly limiting the mutual distance between subregions 18′ to a value greater than 1 μm.

[0013] Therefore, a need is felt to overcome the drawbacks discussed above, particularly with respect to the formation of second edge termination region 18. Summary of the Invention

[0014] This object is achieved by an electronic device and a method for manufacturing the same as defined in the appended claims.

[0015] Embodiments provide an electronic device comprising: a semiconductor body having a first conductivity and a first doping value and provided with a front surface, the semiconductor body being made of a material having a lattice structure with spatial symmetry; an active area configured to accommodate, in use, a conductive channel of the electronic device; an edge region surrounding the active area and structurally continuous with the active area, the edge region having, at least in part, a second conductivity opposite the first conductivity, the edge region originating from the front surface and extending into the semiconductor body, the edge region comprising at least first and second subregions having the second conductivity separated from each other by a portion of the semiconductor body having the first conductivity; and a damaged region facing the front surface, the damaged region having an amorphous lattice structure or a lattice structure without spatial symmetry, the damaged region extending into a portion of the semiconductor body between the first and second subregions.

[0016] One embodiment provides a method comprising: disposing a semiconductor body having a first conductivity and a first doping value and having a front surface, the semiconductor body having an active area made of a material having a lattice structure with spatial symmetry and configured to accommodate, in use, a conductive channel of an electronic device, and an edge region surrounding the active area and structurally continuous with the active area, forming a damaged region in a portion of the front surface, the damaged region having an amorphous lattice structure or a lattice structure without spatial symmetry, and forming a first edge termination region in the semiconductor body starting from the front surface, the first edge termination region having a second conductivity opposite to the first conductivity, the forming of the first edge termination region comprising performing a channeling implant of a doping species having the second conductivity in the damaged region and in portions of the semiconductor body adjacent on either side of the damaged region. [Brief explanation of the drawings]

[0017] For a better understanding of the present disclosure, reference is made to the accompanying drawings. [Figure 1] An electronic device according to an embodiment not subject to the present disclosure is illustrated in cross-sectional view limited to an edge region of the electronic device. [Figure 2] 1 illustrates, in a top view, a die including an active area and edge regions of an electronic device according to one aspect of the present disclosure. [Figure 3] 2 illustrates, in cross-sectional view, the electronic device housed by the die of FIG. 2, limited to the edge region, along scribe line III-III of FIG. [Figure 4] The steps of the method for manufacturing the electronic device of FIG. 3 are illustrated by a flow diagram. [Figure 5] 4 illustrates in cross-section an electronic device according to a further embodiment based on the embodiment of FIG. 3, limited to an edge region. DETAILED DESCRIPTION OF THE INVENTION

[0018] Preferred embodiments of the present disclosure are described below by way of non-limiting examples.

[0019] 2, a die or chip 30, or a portion thereof, is illustrated in a Cartesian three-axis reference system with orthogonal axes X, Y, and Z. The die 30 is obtained after a step of dicing a semiconductor wafer, not illustrated. The die 30 is shown in plan view on the plane XY.

[0020] Die 30 includes an outer periphery 32 that physically defines die 30. Die 30 houses at least one electronic device 40, such as a MOSFET, specifically a power MOSFET, and more specifically a vertical conduction MOSFET, as partially illustrated in Figure 3. In the following description, the terms "electronic device" and "MOSFET" are used interchangeably and without loss of generality.

[0021] Die 30 includes at least two functional regions: an active area 34, which typically extends across a central portion of die 30, and an edge or peripheral region 36, which completely surrounds active area 34. The edge region actually extends between active area 34 and outer edge 32, and is bounded on its outer side by outer edge 32. Active area 34 includes a conductive channel region in use of MOSFET 40. Instead, edge region 36 is a region that does not have a conductive channel in use. Edge region 36 includes functional elements to reduce or prevent crowding of electric field lines outside of the active area, such as, for example, one or more edge termination regions, also known as guard rings, as better described and illustrated with reference to FIG. 3 .

[0022] Figure 3 is a cross-sectional view in plane XZ of a portion of die 30 along scribe line III-III of Figure 2. The dashed lines in Figure 3 that distinguish between active area 34 and edge region 36 should be understood to be qualitative.

[0023] FIG. 2 illustrates only some elements of FIG. 3, ie, FIG. 3 is more detailed than FIG.

[0024] MOSFET 40 includes a semiconductor body 50 of silicon carbide (SiC), particularly of the 4H-SiC polytype. Alternatively, semiconductor body 50 may be 3C-SiC or 6H-SiC or other SiC polytypes.

[0025] Generally, the semiconductor body 50 is made of a material having a crystal structure or lattice configured to allow ion implantation by utilizing a channeled implantation technique (known as channeling). Such a crystal lattice can be described by a periodic distribution of groups of atoms (or ions / molecules). Ideally, considering a crystal that extends infinitely in spatial coordinates, the periodicity results in translational invariance (or translational symmetry). Thus, the entire crystal is generated by the periodic repetition of a basic unit, called a unit cell, which may contain groups of atoms and / or ions and / or molecules. Translational symmetry means that a general point belonging to a basic cell has a one-to-one correspondence with a point of a basic cell obtained by a suitable translation from the first one.

[0026] The semiconductor body 50 has a first conductivity type (e.g., N-type) and a 1.10 15 ~1·10 20 atoms / cm 3 In one embodiment, semiconductor body 50 comprises a substrate having a drift layer (not illustrated in detail in the figures) formed thereon (e.g., epitaxially grown). In this case, the substrate may have a doping of, for example, 1·10 18 ~1·10 20 atoms / cm 3 The drift layer has a doping of, for example, 1·10 15 ~1·10 17 atoms / cm 3 The drift layer has a thickness comprised, for example, between 3 and 100 μm (boundaries included).

[0027] The semiconductor body 50 is defined above by a front surface 50a and below by a rear surface 50b, which are opposite each other along the direction of the axis Z. The side surfaces 50c laterally define the die 30 and extend along the axis Z between the front surface 50a and the rear surface 50b, connecting the front surface 50a and the rear surface 50b to each other.

[0028] At the front surface 50a there is a body region 51 having a second conductivity type (P type) opposite to the first conductivity type. A source region 52 extends into the body region 51 at the front surface 50a. A drain region 54 extends to the rear surface 50b. A gate region 56 extends, in a manner known per se, on the front surface 50a and comprises a gate dielectric 56a and a gate conductive region 56b on the gate dielectric 56a.

[0029] 3 illustrates a single body region 51, a single source region 52, and a single gate region 56 for ease of representation. However, it will be apparent that MOSFET 40 may comprise any number of body 51, source 52, and gate regions 56. In particular, the illustrated body 51, source 52, and gate regions 56 extend proximate to the edges of active area 34.

[0030] MOSFET 40 also includes a first edge termination region 58 in semiconductor body 50, implanted into and facing front surface 50a. First edge termination region 58 has a second conductivity type and a higher doping (P+) than body region 51. First edge termination region 58 includes an end portion (or end region) 58' that extends into edge region 36 (and optionally partially into active area 34), such that first edge termination region 58 is in direct electrical contact with body region 51. First edge termination region 58 functions to shield structures of the device extending over edge termination region 58 (particularly portion 62a of conductive layer 62, described below) from high electric fields when biased to body and source voltages. Source region 52 may be omitted in body region 51, which is in direct electrical contact with first edge termination region 58, as illustrated in FIG. 3 .

[0031] A field dielectric layer ("field oxide") 60 extends over first edge termination region 58 (over front surface 50a), and a conductive layer 62 (e.g., made of metal or N-type doped polysilicon) extends over dielectric layer 60. Layer 62 is configured to distribute a gate bias to the device (gate conductive region 56b is electrically connected to layer 62).

[0032] Conductive layer 62 includes a first portion 62a that extends over first edge termination region 58 and is electrically isolated from first edge termination region 58 by a dielectric or oxide (e.g., SiO2) layer, and a second portion 62b that extends over dielectric layer 60. First portion 62a and second portion 62b are structurally and electrically continuous with each other. Second portion 62b couples the gate potential to edge termination region 36 and thus forms an edge field plate for MOSFET 40.

[0033] Conductive layer 62 is electrically connected to gate conductive region 56b (in a manner not illustrated) and is formed during the same step of forming gate conductive region 56b. Passivation layer 64 extends over conductive layer 62 to protect and insulate conductive layer 62. Passivation layer 64 is interrupted where metallization 63 is in electrical contact with conductive layer 62.

[0034] 2 and 3 , MOSFET 40 includes second edge termination region 68 (or second edge ring 68) having a second conductivity type (P-type) and a doping value that is lower than the doping value of first edge termination region 58 (or first edge ring 58). Second edge termination region 68 extends at an end portion (or “end region”) 58″ of first edge termination region 58 opposite end portion 58′ that extends into body region 51. Thus, second edge termination region 68 extends as an extension of, and is in direct electrical contact with, first edge termination region 58. Second edge termination region 68 functions to distribute or thin the electric field lines of potential so as to avoid thickening of the electric field lines on the radius of curvature of first edge termination region 58, similar to that described with reference to FIG. 1 , thereby maximizing the value of the edge breakdown voltage.

[0035] 3 further illustrates an optional channel stop region 90 extending laterally relative to second edge termination region 68 and facing front surface 50a. Channel stop region 90 specifically extends between second edge termination region 68 and side surface 50c of die 30. Channel stop region 90 is formed by implantation of a doping species having a first conductivity type (e.g., N-type obtained by doping with phosphorus), with a dopant dose of 1·10 19 ~5·10 20 atoms / cm 3 The channel stop region 90 functions to form an equipotential ring with the drain on the die edge.

[0036] The doping density of the first edge termination region 58 is 1·10 18 ~1·10 20 atoms / cm 3 The doping density of the second edge termination region 68 is on the order of 1·10 16 ~1·10 18 atoms / cm 3 That's about it.

[0037] The thickness of first edge termination region 58 along direction Z starting from front surface 50a is comprised for example between 0.3 and 1 μm (inclusive). The thickness of second edge termination region 68 along direction Z starting from front surface 50a is comprised for example between 0.5 and 5 μm (inclusive), in particular between 1 and 5 μm (inclusive).

[0038] 2 and 3, second edge termination region 68 comprises a plurality of subregions 68a-68d (generally designated by reference numeral 68) separated from one another by respective portions 69a-69c (having a first conductivity, here N-type) of semiconductor body 50 and extending (in the representation of FIG. 3) along axis X. In a non-limiting manner of the present disclosure, each subregion 68a-68d has an extension along axis X that is different from that of the other subregions 68a-68d, specifically, an extension that decreases from first edge termination region 58 toward channel stop region 90.

[0039] It can be seen from the plan view of Figure 2 that the sub-regions 68a-68d surround the active area, in particular completely surround it, and therefore what is represented in Figure 3 (limited to the shape and extension of the sub-regions 68a-68d along axis X) applies equally to a cross section taken along axis Y.

[0040] Although FIG. 3 illustrates four sub-regions 68a-68d, this representation should not be construed as limiting the present disclosure, as the number of sub-regions 68a-68d can be selected in the design step as needed, and can be, for example, two or more (e.g., two to six).

[0041] Subregion 68a is in direct electrical communication with first edge termination region 58; i.e., end portion 58" of first edge termination region 58 extends into subregion 68a. Subregion 68b extends laterally relative to subregion 68a and is separated from subregion 68a by portion 69a of semiconductor body 50. The distance along axis X between subregions 68a and 68b is equal to or less than 1 μm, for example, between 0.25 and 1 μm. Similarly, subregion 68c extends laterally relative to subregion 68b. Subregion 68c extends laterally relative to subregion 68c and is separated from subregion 68b by portion 69c of semiconductor body 50. The distance along axis X between subregion 68b and subregion 68c is equal to or less than 1 μm, for example, 0.25 to 1 μm. Similarly, subregion 68d extends laterally relative to subregion 68c and is separated from subregion 68c by portion 69c of semiconductor body 50. The distance along axis X between subregion 68c and subregion 68d is equal to or less than 1 μm, for example, 0.25 to 1 μm.

[0042] The aforementioned distances along axis X between subregions 68a-68d can be equal to one another or can be different from one another. Design requirements determined by the net epitaxial concentration may assume values ​​for the distances along axis X between subregions 68a-68d that are greater than 1 μm, for example, up to 3 μm.

[0043] The sub-regions 68a to 68d all face the front surface 50a and end within the semiconductor body 50 without reaching the rear surface 50b.

[0044] According to one aspect of the present disclosure, each damaged region 80a-80c extends between sub-regions 68a-68d, and the damaged regions 80a-80c face the front surface 50a and terminate within the semiconductor body 50 at respective portions 69a-69c.

[0045] 2, it should be noted that damaged regions 80a-80c also extend to completely or partially surround active area 34. The representation of damaged regions 80a-80c in FIG. 3 pertains to a cross section taken along axis X of FIG. 2, but applies equally to a cross section taken along axis Y of FIG. 2.

[0046] In particular, damaged region 80a extends into portion 69a between subregions 68a and 68b and is adjacent to subregions 68a and 68b. Damaged region 80b extends into portion 69b between subregions 68b and 68c and is adjacent to subregions 68b and 68c. Damaged region 80c extends into portion 69c between subregions 68c and 68d and is adjacent to subregions 68c and 68d.

[0047] Applicant has demonstrated that the channeling effect can be altered by intentionally damaging regions at the front surface 50a of semiconductor body 50, i.e., the regions where the channeling implantation to form subregions 68a-68b occurs. Thus, damaged regions 80a-80c are obtained by intentionally damaging semiconductor body 50 only in those portions of semiconductor body 50, or only in portions 69a-69c, where it is desired to form damaged regions 80a-80c, e.g., by ion implantation of non-reactive or non-doping species. The ion implantation is such that it causes damage to the crystal lattice of semiconductor body 50 without locally altering the conductive properties of semiconductor body 50. Suitable species for this purpose include, for example, ions of Si, Ar, Ge, and He.

[0048] If present, the damaged regions 80a-80c alter or suppress channeling effects during the formation of the second edge termination region 68, giving the second edge termination region 68 the shape illustrated in FIG. 3 and described above (i.e., forming a series of subregions 68a-68d that are physically separated from one another).

[0049] The damaged regions 80a-80c start at the front surface 50a in the semiconductor body 50 and extend to a maximum depth comprised between, for example, 0.1 and 0.6 μm (including boundaries). In one embodiment, the thickness of the damaged regions 80a-80c is uniform, and in a further embodiment, the thickness of the damaged regions 80a-80c is not uniform but varies between a maximum value of 0.6 μm and a minimum value of 0.1 μm.

[0050] FIG. 4 illustrates, in a flow diagram, the steps in the manufacturing process for MOSFET 40, limited to those elements useful for understanding the present disclosure.

[0051] 4, once semiconductor body 50 is deposited or formed, and prior to the formation of layers 60 and 62 described above, an implantation mask (step S2), for example made of photoresist or a dielectric material, is formed on front surface 50a. This implantation mask is patterned to cover front surface 50a except for areas 69a-69c where it is desired to form damaged regions 80a-80c, thus leaving the excluded areas unmasked.

[0052] Then, in step S3, damaged regions 80a-80c are formed using an implant mask, as described above. Note that because the depth of these regions (less than 1 micrometer) does not require high implant energies, the formation of this implant mask does not unduly restrict the minimum dimension along axis X of damaged regions 80a-80c, and therefore it is possible to use a masking material that allows for good definition to be obtained (unlike the hard masks used for deep implants of several micrometers, as described with reference to FIG. 1).

[0053] To complete the formation of the damaged regions 80a to 80c, the formation of the damaged regions 80a to 80c is performed in 10 13 atoms / cm 2 This involves using an implantation dose greater than 80 kJ / cm and sufficient energy to shift atoms from their crystalline structure throughout the required depth (e.g., energies in the range 30-300 keV, inclusive). The damage-introducing implant is not performed under channeling conditions, and annealing of the wafer during the process is avoided to remove the induced damage. According to a further embodiment, the damaged regions 80 a-c are formed by one or more steps of etching the front surface 50 a of the semiconductor body 50, e.g., an RIE (Reactive Ion Etching) process having physical etching properties (ion bombardment), to mask areas of the semiconductor body 50 that will not be subjected to the intentional damaging process.

[0054] Next, in step S4, second edge termination region 68 is formed. This step involves forming a hard mask (e.g., one or more native oxide layers or one or more intentionally added oxide layers) on surface 50a laterally relative to (i.e., surrounding) the series of damaged regions 80a-80c. The hard mask of step S4 covers surface 50a except for the portions of surface 50a corresponding to damaged regions 80a-80c (i.e., portions 69a-69c) and except for the portions of surface 50a where it is desired to form subregions 68a-68d. In other words, forming the mask of step S4 envisions forming this mask some distance away from damaged regions 80a and 80c, which are the outermost damaged regions of the series of damaged regions 80a-80c, with all other damaged regions (here, 80b) falling between such outer damaged regions 80a, 80c. The distance between the mask and the outer damage regions 80a, 80c is selected in the design step based on the desired extension along X for the corresponding subregions 68a and 68d, which are also the outermost subregions of the series of subregions 68a-68d (all other subregions 68b, 68c are included between these outer subregions 68a and 68d).

[0055] Then, in step S5, the method proceeds with a channeling implant of a doping species having a second conductivity at the front surface 50a to form a second edge termination region 68.

[0056] Following the described steps S1-S5, the structure of MOSFET 40 is completed with respect to edge region 36 by the formation of a field dielectric layer ("field oxide") 60, a conductive layer 62, metallization 63, and a passivation layer 64.

[0057] Referring to step S5, channeled implantation occurs when the ion beam during implantation is aligned with the channeling direction. For example, for SiC, this is the 000-1 or 11-23 direction. Typically, substrates are cut from ingots grown in the 000-1 direction, and for substrates with a diameter of 150 mm or 200 mm, the surface is sloped by 4° (when dicing wafers). This entails that to implant with channeling on 000-1 wafers, the ion beam needs to be tilted by 4° during implantation, and for 11-23 wafers, by 13° or 21°.

[0058] As a result of the two possible damage steps mentioned above, semiconductor body 50 does not have the same lattice structure in damaged regions 80a-80c as semiconductor body 50 extending laterally to damaged regions 80a-80c. In particular, when semiconductor body 50 is intentionally damaged, it has an amorphous structure or a disordered crystalline structure or a lattice structure without spatial symmetry in the unintentionally damaged portions of semiconductor body 50. Channeling effects are altered by the presence of damaged regions 80a-80c and by the presence of a masking surface layer disposed on front surface 50a of semiconductor body 50.

[0059] The advantages of the present disclosure are apparent from the foregoing discussion. In particular, according to the present disclosure, the use of a hard mask is not required in step S3 of Figure 4. Furthermore, forming the edge termination regions 58, 68 does not require the use of high-energy and high-dose ion implantation to reach the desired depth and conductivity.

[0060] Finally, it will be apparent that modifications and variations can be made to what has been described and illustrated herein without departing from the scope of the present disclosure, as defined in the appended claims.

[0061] For example, the present disclosure applies to electronic devices other than vertical channel MOSFETs, such as horizontal channel MOSFETs, trench FETs, diodes, thyristors, MESFETs, MISFETs, IGBTs, and the like.

[0062] Additionally, semiconductor body 50 can be a material other than SiC, such as, for example, GaN.

[0063] Furthermore, semiconductor body 50 may comprise a substrate of semiconductor material (such as SiC, GaN, etc.) and optionally one or more epitaxial surface layers grown on the substrate.

[0064] 3 and 5, i.e., the body region in direct electrical connection with first edge termination region 58, does not contain source region 52. Indeed, in this embodiment, the illustrated body region 51 extends to the border with edge region 36, i.e., near an area of ​​device 40 that is not designed to participate in electrical conduction, and the absence of a source region prevents the flow of charge carriers (conduction current) toward edge region 36.

[0065] Additionally, as mentioned above, second edge termination region 68 may comprise only two subregions, e.g., only subregions 68a and 68b, in which case there is only one damaged region (damaged region 80a) extending between subregions 68a and 68b.

[0066] MOSFET 40 (or other devices fabricated according to the present disclosure) may also optionally include a current spreading layer (CSL) 70 facing front surface 50a and extending into semiconductor body 50. See FIG. 5, where elements corresponding to those in FIG. 3 are identified with the same reference numerals and will not be further described. CSL 70 extends from front surface 50a to a maximum thickness T 100 of 0.3 to 2 μm along axis Z. CSL_MAXGenerally, CSL 70 has a depth equal to that of body 51 or extends below body 51 by a maximum value of 1 μm. In one embodiment, the maximum depth reached by CSL 70 is greater than the maximum depth reached by body region 51. Thus, in this case, body region 51 is completely contained within CSL 70. CSL 70 forms a concentrated layer that functions to improve the value of on-resistance (known as Ron) of MOSFET 40. The doping of CSL 70 is greater than the doping of semiconductor body 50. CSL 70 may have a doping of, for example, 10 μm. 17 atoms / cm 3 CSL 70 may have a doping that is about 2 to 20 times the doping of the portion of semiconductor body 50 that contains it. CSL 70 may have a uniform or non-uniform thickness along axis Z, beginning at front surface 50a. In particular, CSL 70 may have a maximum thickness in active area 34 (which serves to reduce Ron) and a thinner thickness in a portion of second edge termination region 68. CSL 70 may be formed using channeled ion implantation.

Claims

1. 1. An electronic device comprising: a semiconductor body having a first conductivity and a first doping value and provided with a front surface, the semiconductor body being made of a material having a lattice structure with spatial symmetry; an active area configured, in use, to accommodate a conductive channel of said electronic device; an edge region surrounding the active area and structurally continuous with the active area, at least in part: a first edge termination region having a second conductivity type opposite to the first conductivity type, starting from the front surface and extending into the semiconductor body, the first edge termination region comprising at least first and second subregions having the second conductivity type separated from each other by a portion of the semiconductor body having the first conductivity type; an edge region containing a damaged region extending into the portion of the semiconductor body between the first subregion and the second subregion and facing the front surface, the damaged region having an amorphous lattice structure or a lattice structure without spatial symmetry; and An electronic device comprising:

2. 2. The electronic device of claim 1, wherein the first sub-region and the second sub-region of the first edge termination region start from the front surface and extend along a first direction perpendicular to the front surface to a respective maximum depth comprised between 1 and 5 μm, the maximum depths of the first sub-region and the second sub-region being equal to one another.

3. 3. The electronic device of claim 2, wherein the first sub-region and the second sub-region of the first edge termination region have respective extensions that differ from one another along a second direction that is orthogonal to the first direction.

4. 10. The electronic device of claim 1, wherein the first sub-region and the second sub-region of the first edge termination region have uniform doping values ​​relative to one another.

5. 10. The electronic device of claim 1 , wherein the active area comprises a body region having the second conductivity type, the first sub-region of the first edge termination region being electrically connected to the body region and having a doping greater than a respective doping of the body region.

6. 6. The electronic device of claim 5, further comprising a second edge termination region having the second conductivity type and extending between the first sub-region of the first edge termination region and the body region, the first sub-region of the edge termination region and the second edge termination region being electrically contiguous with one another.

7. the second sub-region extends along a second direction to a distance from the body region that is greater than the corresponding distance between the first sub-region and the body region; 6. The electronic device of claim 5, wherein the second sub-regions have smaller extensions along the second direction than the corresponding extensions of the first sub-regions.

8. the second edge termination region has a doping greater than the doping of the first edge termination region and is in direct electrical contact with the body region; 7. The electronic device of claim 6, wherein the first sub-region of the first edge termination region is in direct electrical contact with the second edge termination region.

9. The electronic device of claim 1 , wherein the damaged region contains non-reactive or non-doping ionic species, such as, for example, Si, Ar, Ge, He, etc.

10. 2. The electronic device of claim 1, wherein the damaged region originates at the front surface and extends along a first direction into the semiconductor body to a maximum depth that is less than a maximum depth of the first edge termination region.

11. 11. The electronic device according to claim 10, wherein the depth of the damaged region is 0.1 to 0.6 μm.

12. 2. The electronic device of claim 1, wherein the semiconductor body is made of silicon carbide, which is 3C-SiC, 4H-SiC, or 6H-SiC.

13. 1. A method for manufacturing an electronic device, comprising: disposing a semiconductor body having a first conductivity and a first doping value and provided with a front surface, the semiconductor body being made of a material having a lattice structure with spatial symmetry, the semiconductor body having an active area configured to accommodate, in use, a conductive channel of the electronic device, and an edge region surrounding the active area and being structurally continuous with the active area; forming a damaged region on a portion of the front surface, the damaged region having an amorphous lattice structure or a lattice structure without spatial symmetry; and forming a first edge termination region in the semiconductor body starting from the front surface, the first edge termination region having a second conductivity type opposite to the first conductivity type; forming a first edge termination region, the first edge termination region including performing a channeling implant of a doping species having the second conductivity in the damaged region and in portions of the semiconductor body adjacent to both sides of the damaged region; A method comprising:

14. 14. The method of claim 13, wherein the channeling implant causes the formation of at least a first sub-region and a second sub-region having a second conductivity type separated from one another by the portion of the semiconductor body.

15. 15. The method of claim 14, wherein the first and second subregions start from the front surface and extend along a first direction perpendicular to the front surface to a respective maximum depth comprised between 1 and 5 μm, the maximum depths of the first and second subregions being equal to one another.

16. forming the damaged region includes performing an implantation of non-reactive or non-doping ionic species of Si, Ar, Ge, or He; The implantation energy is between 30 keV and 300 keV; The injection dose is 10 １３ atoms / cm ２ The method of claim 13, wherein the amount is about 1000 ppm.

17. The method of claim 13 , wherein forming the damaged region comprises performing an etch.

18. The method of claim 13, wherein forming the damaged region comprises forming the damaged region having a maximum depth value comprised between 0.1 and 0.6 μm.

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