Triple-modular redundancy optimization system design method for FPGA (Field Programmable Gate Array) circuit

Abstract

The invention discloses a triple modular redundancy optimization system design method for an FPGA circuit. The method comprises the steps that a preset circuit netlist is analyzed and extracted to obtain netlist analysis information; executing circuit triple copy and voter insertion according to the netlist analysis information and triple modular redundancy strategy information; and outputting the triple modular redundancy circuit as a circuit network table format specified by a user. The method has the advantages of flexible and comprehensive functions and high efficiency, and can meet the circuit design requirements of users in the aspects of redundancy degree, design cycle and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a triple-module redundancy optimization system design method for FPGA circuits. Background Art

[0002] SRAM-based FPGAs, with their advantages of reprogrammability, low power consumption, and short development cycles, have been widely adopted since their introduction. However, with the widespread adoption of FPGAs, their susceptibility to radiation exposure has become increasingly prominent in space applications. The large number of high-energy particles in outer space can affect the functionality of SRAM-based FPGAs, generating soft errors that can lead to functional failures or hardware damage. Therefore, research on radiation mitigation strategies for SRAM-based FPGAs is crucial to extend the lifespan of these SRAM-based FPGAs for space applications.

[0003] Currently, implementing triple modular redundancy (TMR) through manual coding is a tedious, time-consuming, and error-prone process. This method is inefficient, has long design cycles, and severely impacts development progress. Existing commercial TMR tools offer limited strategies for implementing TMR. Local, distributed, and global TMR only offer a few preset module replication granularities. However, users are increasingly demanding the redundancy level and redundancy targets of circuit units in their designs. These commercial tools' strategies are unable to meet these increasingly complex TMR needs. Summary of the Invention

[0004] The technical problem solved by the present invention is: to overcome the shortcomings of the existing technology and provide a three-module redundancy optimization system design method for FPGA circuits, which has the advantages of flexible and comprehensive functions and high efficiency, and can meet the user's circuit design requirements in terms of redundancy level, design cycle, etc.

[0005] The object of the present invention is achieved through the following technical solution: a triple-module redundancy optimization system design method for FPGA circuits, comprising: parsing and extracting a preset circuit netlist to obtain netlist parsing information; performing circuit triplicate replication and voter insertion based on the netlist parsing information and triple-module redundancy strategy information; and outputting the triple-module redundancy circuit into a user-specified circuit netlist format.

[0006] In the above-mentioned triple-module redundancy optimization system design method for FPGA circuits, the circuit netlist is a Verilog structured netlist or an EDIF netlist.

[0007] In the above-mentioned triple-module redundancy optimization system design method for FPGA circuits, the netlist parsing information includes the modules, ports, components and connection information of the circuit.

[0008] In the above-mentioned triple-module redundancy optimization system design method for FPGA circuits, the triple-module redundancy strategies include: a feedback loop-based strategy, a fault injection-based strategy, an irradiation experiment-based strategy, a functional simulation-based strategy, and a machine learning-based strategy.

[0009] In the above-mentioned triple-module redundancy optimization system design method for FPGA circuits, the feedback loop-based strategy is: targeting the fault accumulation sensitive points in the circuit, searching for the register feedback loop in the circuit, and eliminating the accumulated faults by copying all the units in the loop and inserting a voter after the register in the loop.

[0010] In the above-mentioned triple-module redundancy optimization system design method for FPGA circuits, the fault injection-based strategy is: using fault injection to flip the configuration code bits of the user circuit bit by bit, check the circuit operation status, obtain the circuit-sensitive configuration code bits, and map them to circuit-sensitive units.

[0011] In the above-mentioned triple-module redundancy optimization system design method for FPGA circuits, the strategy based on irradiation experiments is: using heavy ions to conduct irradiation experiments on user circuits to observe whether data errors occur in the configuration memory and whether the functions of internal logic units are abnormal, so as to obtain the radiation-sensitive units of the circuit.

[0012] In the above-mentioned triple-module redundancy optimization system design method for FPGA circuits, the functional simulation-based strategy is: by inputting error stimulus into a specific signal line or module, performing functional simulation, observing whether the error will propagate and affect the final output of the circuit, and obtaining logic-sensitive units.

[0013] In the above-mentioned triple-module redundancy optimization system design method for FPGA circuits, the machine learning-based strategy is as follows: collecting circuit status data under different working conditions, performing preprocessing and feature extraction, using the divided training set to train the neural network model, using the trained model to predict new data, and determining sensitive units based on thresholds.

[0014] In the triple-module redundancy optimization system design method for the FPGA circuit, a voter is inserted to converge three output signals into a single input signal when a tripled circuit unit is connected to a non-tripled circuit unit.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The present invention reduces the threshold and difficulty for users to achieve high-quality triple-module redundant design, meets users' multi-faceted needs in terms of redundancy level, redundancy target, design cycle, etc., and improves the design efficiency of radiation-resistant triple-module redundant circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0018] Figure 1 This is a flow chart of a triple-module redundancy optimization system design method for FPGA circuits provided by an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the process of developing FPGA design using Vivado provided by an embodiment of the present invention;

[0020] Figure 3 It is a structural diagram after the design netlist is parsed according to an embodiment of the present invention;

[0021] Figure 4 This is a flow chart of developing FPGA TMR design using Vivado according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that, unless there is a conflict, the embodiments of the present disclosure and the features described in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0023] Figure 1 This is a flow chart of the triple-module redundancy optimization system design method for FPGA circuits provided by an embodiment of the present invention. Figure 1 As shown, the triple-module redundancy optimization system design method of the FPGA circuit includes:

[0024] Analyze and extract the preset circuit netlist to obtain netlist analysis information;

[0025] Based on the netlist analysis information and triple-module redundancy strategy information, circuit triplicate replication and voter insertion are performed;

[0026] Output the triple-module redundant circuit to the user-specified circuit netlist format.

[0027] The circuit netlist is a Verilog structural netlist or an EDIF netlist.

[0028] The three-module redundancy strategies include: feedback loop-based strategy, fault injection-based strategy, irradiation experiment-based strategy, functional simulation-based strategy, and machine learning-based strategy. Each strategy outputs a subset of user circuit units to be replicated.

[0029] The feedback loop-based strategy targets fault-accumulating points within the circuit, searches for register feedback loops within the circuit, replicates all cells within the loop, and inserts voters after the registers within the loop to eliminate accumulated faults. The fault injection-based strategy uses fault injection to flip the configuration code bits of the user circuit bit by bit, observes the circuit's operation, and obtains sensitive configuration code bits, which are then mapped to sensitive cells. The irradiation experiment-based strategy uses heavy ion irradiation to observe whether data errors occur in the configuration memory and whether internal logic cells malfunction, thereby identifying radiation-sensitive cells. The functional simulation-based strategy uses fault stimulation within specific signal lines or modules, performs functional simulation, and observes whether the error propagates and affects the circuit's final output, thereby identifying sensitive logic cells. The machine learning-based strategy collects circuit state data under different operating conditions, performs preprocessing and feature extraction, trains a neural network model using a partitioned training set, uses the trained model to predict new data, and identifies sensitive cells based on thresholds.

[0030] Netlist parsing information is module, port, component and connection information, including library, cell, instance, port, net and other attributes.

[0031] Specifically, the method includes: first reading in the circuit netlist and parsing it to extract the modules, ports, components and connection information of the circuit; specifying an appropriate three-module redundancy strategy based on actual design requirements such as resource overhead and timing constraints; performing circuit triplicate replication and voter insertion based on the netlist parsing information and the three-module strategy information; and outputting the three-module redundant circuit into a user-specified circuit netlist format.

[0032] The circuit netlist is a Verilog structured netlist or EDIF netlist, which is generated by the synthesis operation in the general FPGA development process. Taking Xilinx FPGA design tool Vivado as an example, the general FPGA development process is briefly described. Figure 2 As shown, it mainly includes the following processes:

[0033] (1) Design input: Create an FPGA project and add design source files, such as HDL (VHDL / Verilog) files, EDIF or NGC netlist files, schematics, IP core modules, etc.

[0034] (2) Synthesis: Synthesize all design source files to generate a design netlist with a specific structure, such as a Verilog structured netlist or an EDIF netlist;

[0035] (3) Implementation: Layout and routing of the design netlist, that is, rationally configuring the hardware and underlying units in the design netlist on the inherent hardware structure inside the FPGA chip and accurately connecting each component;

[0036] (4) Generate code stream: Use the code stream generation tool to convert the design file into a .bit format code stream file.

[0037] (5) Download programming: Download the code stream file to the FPGA chip.

[0038] The three-module redundancy strategies include: feedback loop-based strategy, fault injection-based strategy, irradiation experiment-based strategy, functional simulation-based strategy, and machine learning-based strategy. Each strategy outputs a subset of user circuit units to be replicated.

[0039] The feedback loop-based strategy targets the fault accumulation sensitive points in the circuit, searches for the register feedback loop in the circuit, and eliminates the accumulated faults by copying all the units in the loop and inserting voters after the registers in the loop.

[0040] The fault injection-based strategy uses fault injection to flip the configuration code bits of the user circuit bit by bit, check the circuit operation status, obtain the circuit sensitive configuration code bits, and map them to circuit sensitive units.

[0041] The strategy based on irradiation experiments is to use heavy ions to conduct irradiation experiments on user circuits to observe whether there are data errors in their configuration memory and whether there are abnormalities in the functions of internal logic units, so as to obtain the radiation-sensitive units of the circuit.

[0042] The strategy based on functional simulation is to input error stimulus into specific signal lines or modules, perform functional simulation, observe whether the error will propagate and affect the final output of the circuit, and obtain logic-sensitive units.

[0043] The machine learning-based strategy is to collect circuit status data under different working conditions, perform preprocessing and feature extraction, use the divided training set to train the neural network model, use the trained model to predict new data, and determine sensitive units based on thresholds.

[0044] Netlist parsing information includes the modules, ports, components and connection information of the user circuit, including attributes such as library, cell, instance, port, net, etc. Figure 3As shown in Figure 2, the triple-mode strategy information is a subset of user circuit cells to be replicated, obtained by analyzing the selected triple-mode redundancy strategy and the user netlist information. The voter is inserted to converge the three output signals into a single input signal when the tripled circuit cell is connected to the non-tripled circuit cell.

[0045] According to the extracted netlist parsing information and the subset of user circuit units to be copied, the insertion position of the voter in the circuit is analyzed, the actual circuit copying and voter insertion operations are performed, and finally the netlist design in TMR form is generated.

[0046] User-specified circuit netlist formats include Verilog structural netlist and EDIF netlist.

[0047] In summary, the complete triple-module redundancy implementation process of the present invention is as follows: Figure 4 shown.

[0048] This embodiment provides a method for automatically implementing a triple-module redundant circuit. It uses a Verilog or EDIF netlist file generated by an EDA synthesis tool as the design input and outputs a TMR circuit file in the same format for the user to implement subsequent general FPGA implementation processes, thereby improving the efficiency of the user's triple-module redundant circuit implementation.

[0049] This embodiment integrates multiple triple-mode redundancy strategies, including a feedback loop-based strategy, a fault injection-based strategy, an irradiation experiment-based strategy, a functional simulation-based strategy, and a machine learning-based strategy, providing a flexible and efficient triple-mode redundancy implementation solution to meet users' multi-faceted needs in terms of redundancy level, redundancy goals, design cycle, etc.

[0050] This embodiment reduces the threshold and difficulty for users to achieve high-quality triple-mode redundant design, meets users' multi-faceted needs in terms of redundancy level, redundancy goals, design cycle, etc., and improves the design efficiency of radiation-resistant triple-mode redundant circuits.

[0051] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.

Claims

1. A triple-module redundancy optimization system design method for FPGA circuits, characterized in that include: Analyze and extract the preset circuit netlist to obtain netlist analysis information; Based on the netlist analysis information and triple-module redundancy strategy information, circuit triplicate replication and voter insertion are performed; Output the triple-module redundant circuit to the user-specified circuit netlist format.

2. The triple modular redundancy optimization system design method for FPGA circuits according to claim 1, characterized in that: The circuit netlist is a Verilog structured netlist or an EDIF netlist.

3. The triple modular redundancy optimization system design method for FPGA circuits according to claim 1, characterized in that: The netlist parsing information includes modules, ports, components and connection information of the circuit.

4. The triple-module redundancy optimization system design method for FPGA circuits according to claim 1, wherein: The triple-module redundancy strategy includes: a strategy based on a feedback loop, a strategy based on a fault injection, a strategy based on an irradiation experiment, a strategy based on a functional simulation, and a strategy based on machine learning.

5. The triple modular redundancy optimization system design method for FPGA circuits according to claim 4, characterized in that: The feedback loop-based strategy is: targeting the fault accumulation sensitive points in the circuit, searching for the register feedback loop in the circuit, duplicating all units in the loop, and inserting voters after the registers in the loop to eliminate accumulated faults.

6. The triple modular redundancy optimization system design method for FPGA circuits according to claim 4, characterized in that: The fault injection-based strategy is: using fault injection to flip the configuration code bits of the user circuit bit by bit, check the circuit operation status, obtain circuit sensitive configuration code bits, and map them into circuit sensitive units.

7. The triple modular redundancy optimization system design method for FPGA circuits according to claim 4, characterized in that: The strategy based on irradiation experiment is: using heavy ions to perform irradiation experiments on user circuits to observe whether data errors occur in the configuration memory and whether the functions of internal logic units are abnormal, so as to obtain the radiation sensitive units of the circuit.

8. The triple-module redundancy optimization system design method for FPGA circuits according to claim 4, characterized in that: The functional simulation-based strategy is to input error stimulus into a specific signal line or module, perform functional simulation, observe whether the error will propagate and affect the final output of the circuit, and obtain logic-sensitive units.

9. The triple modular redundancy optimization system design method for FPGA circuits according to claim 4, characterized in that: The machine learning-based strategy is to collect circuit status data under different working conditions, perform preprocessing and feature extraction, use the divided training set to train the neural network model, use the trained model to predict new data, and determine sensitive units based on thresholds.

10. The triple modular redundancy optimization system design method for FPGA circuits according to claim 1, wherein: The voter is inserted to converge the three output signals into a single input signal when the tripled circuit cell is connected to the non-tripled circuit cell.

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