Test method and device of storage equipment, electronic equipment and storage medium

Abstract

The invention relates to the technical field of computer hardware testing, and discloses a testing method and device of storage equipment, electronic equipment and a storage medium, and the testing method comprises the steps that a write address control strategy is generated, and the write address control strategy is used for representing the write sequence of different addresses in the storage equipment; obtaining test data; and sequentially writing the test data into corresponding positions of the storage equipment according to a sequence defined by the write-in address control strategy. The technical problem of low reliability of the writing effect of the test storage device is solved, and the technical effect of improving the test accuracy of the storage device is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of computer hardware testing, and in particular to a storage device testing method, apparatus, electronic device, and storage medium. Background Art

[0002] When testing storage devices, data write operations are a key test item. Related technologies often use simple sequential writes (for example, starting from the starting address of the storage device and incrementing from the starting address to the ending address without skipping, writing data to each address) or random writes (writing to randomly selected addresses on the storage device). However, these test methods are significantly different from the data writing methods used in actual storage device applications. They cannot accurately assess the reliability of storage devices and cannot meet the needs of in-depth storage device testing and data integrity verification. Summary of the Invention

[0003] The present application provides a storage device testing method, apparatus, electronic device, and storage medium to at least solve the problem of low reliability of storage device writing effect testing in related technologies.

[0004] The present application provides a method for testing a storage device, comprising: generating a write address control strategy, the write address control strategy being used to indicate the write order of different addresses in the storage device; obtaining test data; and writing the test data into corresponding locations of the storage device in sequence according to the order defined by the write address control strategy.

[0005] The present application also provides a testing device for a storage device, comprising: an address control module for generating a write address control strategy, the write address control strategy being used to indicate the write order of different addresses in the storage device; a data generation module for obtaining test data; and a storage module for writing the test data into corresponding positions of the storage device in sequence according to the order defined by the write address control strategy.

[0006] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned storage device testing methods when executing the computer program.

[0007] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned storage device testing methods are implemented.

[0008] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned storage device testing methods when executed by a processor.

[0009] Through the present application, a software tool for storage device testing is provided, which includes three parts: an address control module, a data generation module and a storage module. When performing a write test on a storage device, the address control module can pre-generate a write address control strategy, and the write address control strategy is used to indicate the write order of different addresses in the storage device. In other words, the write address control strategy can customize which addresses are written first and which addresses are written later. The addresses written successively are not actually adjacent physical storage addresses. The addresses written successively can not only jump but also repeat, so that certain addresses are written multiple times. Afterwards, the data generation module obtains test data, and the test data is used to write to the corresponding storage address during the write test. Finally, through the storage module, the obtained test data is written into the customized storage address in sequence according to the write address control strategy, and the writing method is implemented by jumping or rereading. Therefore, the process of writing test data to the storage device imitates the rules of writing data to the storage device when the computer is actually in use, making the storage device testing method and the computer's actual data writing method more similar and consistent. It can test the performance and quality of certain specific locations of the storage medium in a targeted manner, significantly improve the reliability of storage device testing, and meet the needs of in-depth testing of storage devices and data integrity verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 A flowchart of a storage device testing method provided in an embodiment of the present application;

[0012] Figure 2 Another flowchart of a method for testing a storage device provided in an embodiment of the present application;

[0013] Figure 3 Another flowchart of a method for testing a storage device provided in an embodiment of the present application;

[0014] Figure 4 A schematic diagram of the storage module structure provided in an embodiment of the present application;

[0015] Figure 5 A schematic diagram of a flow chart of a storage device testing apparatus provided in an embodiment of the present application;

[0016] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0018] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0019] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0020] In the field of data storage technology, storage devices are continuously developing towards higher density and larger capacity. Storage density is an important metric for measuring the efficiency of a storage device or data structure, typically describing the amount of data that can be stored per unit space. For example, QLC NAND (Quad Level Cell NAND) storage devices are widely used in the market due to their high storage density and relatively low cost. However, as storage density increases, performance testing and data management of storage devices become more difficult, placing higher demands on test accuracy and data management effectiveness.

[0021] Currently, in the testing phase of storage devices, the test of data write operations is a key test item. Related technologies often use simple sequential write or random write methods during write tests. Simple sequential write refers to starting from the starting address of the storage device, and incrementing from the starting address to the end address in a non-jumping manner, and writing data to each address. For example, the storage device includes storage addresses h0 to h10. Simple sequential write means starting from h0, writing h0 first, then writing h1, then writing h2, and finally writing h10. Random write refers to randomly selecting addresses of the storage device for writing. For example, the storage device includes storage addresses h0 to h10. Random write means randomly selecting some addresses from addresses h0 to h10 and randomly sorting them, and then writing data to the randomly selected addresses.

[0022] From the perspective of the storage test methods commonly used in related technologies, simple sequential writing cannot simulate the complex address access patterns in actual applications. For example, in the actual application of a computer, the computer does not strictly write in sequence according to the serial number of the address. A general possible writing method is to write the first data to h2, the second data to h6, the third data to h0, and the fourth data to h2. It is not difficult to find that the actual data writing method of a computer has the phenomenon of address jumping and repeated address writing. If the storage device is tested only according to the simple sequential writing method, the fact that the storage device can ensure data integrity in the simple sequential writing scenario does not mean that the storage device can also ensure data integrity in actual application. Once the storage device is put into use, some data may not be fully and correctly written to the corresponding address due to the address jumping and repeated address writing method.

[0023] Random write testing methods make it difficult to specifically test the performance of specific address areas of a storage device. Because addresses are randomly selected for writing, it is impossible to test the logic of repeated writes to certain specific areas. It is also impossible to conduct targeted testing to determine the integrity of rewritten data. In terms of data management, existing technologies lack effective means to record and manage the number of writes and the order in which specific addresses are written. This cannot meet the needs of in-depth testing of storage devices and data integrity verification. Furthermore, returning storage devices to the factory for repair after a problem occurs significantly increases the time and financial costs of manufacturing products. Therefore, it is imperative to provide a more reliable storage device testing method.

[0024] An embodiment of the present application provides a method for testing a storage device, and the method is described in detail in conjunction with an execution flow of the method for testing a storage device.

[0025] In this embodiment, a method for testing a storage device is provided, such as Figure 1 As shown, the process includes the following steps:

[0026] Step S101 : generating a write address control strategy, where the write address control strategy is used to indicate the write order of different addresses in the storage device.

[0027] Specifically, in actual computer application scenarios, writing data to storage devices often involves address jumps and address re-reading and writing. Based on this, this embodiment aims to be close to the actual computer application scenarios, create and generate corresponding address control strategies, and thus represent the write order of different addresses in the storage device through the address control strategy.

[0028] For example, in an optional embodiment, the generated address control strategy may include: first performing a first write from address 'h0 to 'h4, then performing a first write at address 'h8, then performing a second write starting from address 'h0, and then alternating in a pattern of first writing to address 'h9, second writing to address 'h1, first writing to address 'hA, second writing to address 'h2, first writing to address 'hB, second writing to address 'h3, first writing to address 'hC, and second writing to address 'h4, while skipping invalid address ranges (addresses 'h5 to 'h7 and addresses 'hD to 'hF, etc. are invalid addresses), until ending at address 'h6cc. This embodiment is merely an example and is not limited thereto.

[0029] In an embodiment of the present invention, the storage device testing method may be implemented by a pre-developed testing software tool, wherein step S101 is executed by an address control module in the tool.

[0030] Step S102: Acquire test data.

[0031] Specifically, the test tool provided in this embodiment also includes a test data module for obtaining test data. Test data refers to data information used to write to each address of the storage device, so as to test whether the data written to each address can be written completely and accurately, so as to reflect the reliability of the storage device. In this embodiment, the form of the test data is not particularly limited, and can be text data or vector data such as pictures and videos. In this embodiment, the test data can be obtained by pre-saving the test software in the execution device or by sending data in real time from an external client device or server.

[0032] In some scenarios, if there is no requirement for repeatable testing of storage devices, the test data for each test can be different random data; if the test scenario requires repeatable testing of storage devices, the test data for each test can also be fixed data information.

[0033] Step S103 : writing the test data into corresponding locations of the storage device in sequence according to the order defined by the write address control policy.

[0034] Specifically, the test tool provided in this embodiment also includes a storage module for specifically executing the test steps and writing the test data to the address of the storage device. Through this application, the address control module has pre-generated a write address control strategy. The write address control strategy can customize which addresses are written first and which addresses are written later. The addresses written in sequence are not actually adjacent physical storage addresses. The addresses written in sequence can not only jump but also repeat, so that certain addresses are written multiple times. Through the storage module, the acquired test data is written to the customized storage address in sequence according to the write address control strategy, and the writing method is implemented by jumping or rereading. Therefore, the process of writing test data to the storage device imitates the law of writing data to the storage device when the computer is actually used, making the storage device test method and the computer's actual data writing method more similar and consistent, and can test the performance and quality of certain specific locations of the storage medium in a targeted manner, significantly improving the reliability of storage device testing, and meeting the needs of in-depth testing of storage devices and data integrity verification.

[0035] In some optional implementations, the above step S101 includes:

[0036] Step a1: Obtain a write address test case. The write address test case is a text used to record the write order of different addresses in the storage device.

[0037] Step a2: Divide the write address test case into several test phases.

[0038] Specifically, in an embodiment of the present invention, the address control module is mainly composed of three software units: a state machine, a counter, and a comparator. The state machine is used to control the different stages of address generation, and determines the address generation method and the write count mark according to the current state. In other words, the state machine acts as a "commander" to coordinate the counter to generate the logical address that the user needs to test. The counter is responsible for recording the current address value, thereby outputting the corresponding address to the storage module so that the storage module can be tested according to the address output by the counter. The comparator is used to determine whether the address output by the counter reaches a specific boundary value or an invalid address range, thereby performing a range validity check on the address. Only addresses that meet the range validity conditions will be output, otherwise the test will be rejected.

[0039] Furthermore, in an embodiment of the present invention, the testing process is further optimized, proposing a pipelined storage device write test method. Specifically, after each address is generated, data is immediately acquired and tested, rather than waiting until all addresses are generated before performing statistics and testing. This technical approach facilitates verification of the reliability of each data write test and facilitates accurate location of anomalies.

[0040] Among them, the test tool provided by the embodiment of the present invention first obtains a write address test case, and the write address test case is written by an experienced expert or automatically generated by a trained natural language model. The address test case is a text used to record the write order of different addresses in the storage device. For example, the test case exemplified in the above steps is: "First, perform the first write from address 'h0 to 'h4, then perform the first write at address 'h8, and then perform the second write starting from address 'h0, and then perform the first write at address 'h9, the second write at address 'h1, the first write at address 'hA, the second write at address 'h2, the first write at address 'hB, the second write at address 'h3, the first write at address 'hC, and the second write at address 'h4, while skipping the invalid address range (addresses 'h5 to 'h7 and addresses 'hD to 'hF, etc. are invalid addresses) until the end of address 'h6cc".

[0041] After obtaining the above test cases, the state machine divides the write address test cases into several test stages, so that in subsequent tests, the tests are performed stage by stage. In other words, the next stage test is performed only after the previous stage test is completed, so as to achieve the effect of pipeline write test.

[0042] For example, in an optional embodiment, the divided test phases may include: the first phase (first writing of 'h0 to 'h4), the second phase (first writing of 'h8), the third phase (second writing of 'h0), and the fourth phase (alternating writing of addresses such as 'h9).

[0043] Step a3: According to the test case of the current test phase, the address generator is controlled to generate the current address, and a write count mark is added to the current address, where the write count mark indicates the number of write tests the generated current address is used for.

[0044] Specifically, the test cases after the aforementioned steps are divided into stages are readable, textual cases, while the address control strategy executed by the storage module refers to control instructions, machine language that can be understood by the machine. To complete the conversion of test cases to control strategies, it is necessary to achieve it through the cooperation of a state machine and a counter. In an embodiment of the present invention, the state machine identifies the test cases of each stage, thereby controlling the counter to perform the work of locating the storage address and the number of writes, so as to convert the test cases of each stage into the form of storage address and write number marks. The storage module can perform the corresponding write test task by reading the storage address and write number marks.

[0045] For example, the state machine first runs the control logic of the initialization phase, that is, when the test software tool is started, the state machine enters the initial state, initializes the counter to 'h0 (the first address that needs to be written to the test), and marks the number of writes as the first write (used to indicate that 'h0 will perform the first write test).

[0046] Afterwards, if Figure 2 As shown, the state machine starts to run the control logic of the first stage (the first write of 'h0 to 'h4): the state machine controls the counter to increment from 'h0, and after each increment, the counter needs to output the current address and the first write mark until the counter reaches 'h4.

[0047] Among them, the current address (the current address refers to the address output by the counter at the current stage and current step, such as h0) and the first write mark output by the counter each time will directly reach the storage module, so that the storage module uses the current address (such as h0), the first write mark and the obtained test data to directly perform a write test on the current address (such as h0). The storage module does not wait for the subsequent address (such as h1) to be received before testing all received addresses uniformly (for example, it will not perform a write test on h0 and h1 at the same time). Therefore, if there is a write anomaly at the current address (such as h0), the address where the test problem occurs (such as h0) can be quickly and accurately located, improving the accuracy of anomaly location and the test accuracy.

[0048] Similarly, after the first stage test is completed, the state machine starts the second stage test (the first write of 'h8). In other words, when the counter reaches 'h4, the state machine switches to the special address processing state, sets the counter directly to 'h8, and outputs the 'h8 address and the first write mark.

[0049] Similarly, after the second stage test is completed, the state machine starts the third stage test (the second write of 'h0): after completing the write of 'h8, the state machine switches to the second write start state, resets the counter to 'h0, and marks the write count as the second write and outputs it.

[0050] Similarly, after the third phase of testing is complete, the state machine begins the fourth phase of testing, the alternating write phase: the state machine enters the alternating write state, and the counter begins incrementing from 'h9. Addresses greater than 'h9 (such as 'h9, 'hA, 'hB, etc.) are marked as the first write. Addresses that have already been written to for the first time (such as 'h1, 'h2, 'h3, 'h4, etc.) are marked as the second write when their turn comes. When the counter reaches 'h6cc, the state machine ends the entire address generation process.

[0051] Step a4, verify the validity of the current address range;

[0052] Step a5: When the verification passes, the current address and the write count mark are output, so that the current address and the write count mark are used as the write address control strategy in the current test phase.

[0053] Specifically, when the counter outputs each address of each test stage in the aforementioned step, taking the current address of the current stage to be tested as an example, it is necessary to use a comparator to check whether the value of the counter enters an invalid address range (such as addresses such as 'h5-'h7 and 'hD-'hF). If it enters the invalid range, these addresses are skipped and continue to increment to the next valid address. If it does not enter the invalid range, the current address and the number of write times are normally output to the storage module to ensure that it is within the valid range, thereby improving the accuracy of the storage device test.

[0054] When the storage module receives the current address and the write count mark, it directly executes the operation of writing the test data to the current address, and can determine whether the current address test is completed through the write count mark information. If the current address test is completed, the user can be directly notified to perform subsequent equipment reliability analysis and data reading work, thereby improving test flexibility and test efficiency and reducing the time consumed by the test cycle.

[0055] In addition, in some optional implementations, a dynamic test case adjustment mechanism is also provided. At the beginning of the test, the write address control strategy is generated based on static test cases and cannot be adjusted according to real-time feedback during the test. The embodiment of the present invention introduces a real-time performance monitoring module (for example, monitoring the response time and error rate of each storage address writing data), performs write monitoring on each storage address, and uploads the real-time monitored data to the artificial intelligence big model. The write order and frequency are dynamically optimized by the artificial intelligence big model to optimize new test cases during the test process, thereby dynamically adjusting the write address control strategy according to the new test cases. For example, if certain address areas are frequently written with errors, the number of repeated writes in the area is automatically increased. Through this technical means, the pertinence and efficiency of the test are further improved, and potential problems are discovered earlier.

[0056] In some optional implementations, the above step S102 includes:

[0057] Step b1, obtaining a fixed random seed;

[0058] Step b2, generating random data based on a fixed random seed;

[0059] Step b3: Process the random data into a data format that meets storage requirements to obtain test data.

[0060] Specifically, a random seed is a random number generated with a true random number (seed) as the initial condition. Generally, computer random numbers are pseudo-random numbers, which use a true random number (seed) as the initial condition and then use a specific algorithm to iterate and generate random numbers. The random seed is the initial value of the random number generator, which determines the starting point of the random process.

[0061] In an embodiment of the present invention, some repeated writing test scenarios often involve repeated testing, in which the same data needs to be written to verify the reliability of the storage device. Related technologies often open up a space in a computer storage medium and store fixed data in the space, and use the fixed data to perform write tests on the storage device. However, this method requires more computer storage resources, which is not conducive to the installation and maintenance of the test tool. Based on this, the data generation module provided in the embodiment of the present invention realizes lightweight data generation through a random number generator, a seed register and a data formatting unit.

[0062] Among them, the seed register is used to store some fixed random seeds, such as Figure 3 As shown, during the initialization phase, a fixed seed value is loaded into the seed register when the system starts up, and the random number generator is initialized based on this seed. The random number generator uses the fixed random number seed to generate a corresponding pseudo-random number sequence, ensuring that the random number sequence generated each time the system runs is repeatable. Simultaneously, the data formatting unit adjusts the generated random number sequence to the data length and format required by the storage module. For example, if the storage module requires 8 bits of data to be written each time, the data formatting unit will truncate or expand the generated random number to 8 bits. Finally, the data generation module passes the formatted data to the storage module and prepares to receive information from the address control module for the next time to generate new data.

[0063] Through the technical means provided by the embodiments of the present invention, the data generation module uses a fixed seed to initialize the random number generator. As long as the seed is the same, a completely consistent random data sequence is generated each time the system is run, ensuring the repeatability of test data and facilitating comparative analysis of test results. Not only can the same data be generated for repeatable testing, but because the number of fixed random seeds is small and the space occupied is small, it can also effectively reduce the waste of computer storage resources and improve their utilization compared to solutions that store fixed data.

[0064] In some optional implementations, the above step b2 includes:

[0065] Step b21, judging whether the current address is being written to for the first time based on the current address and the write count mark;

[0066] Step b22: when the current address is being written to for the first time, randomly extract a portion of the first target seed from the fixed random seed, and generate random data based on the first target seed;

[0067] Step b23, when the current address is not the first time to be written to the test, determining the second target seed used by the current address during the first test;

[0068] Step b24: extracting a second target seed from the fixed random seed, and generating random data based on the second target seed.

[0069] Specifically, in an embodiment of the present invention, the storage address and write count mark generated each time by the address control module in each stage will be passed to the data generation module. The data generation module makes a judgment based on the received storage address and write count mark to determine whether the current address is the first time to be written to. If the current address is the first time to be written to, the data generation module randomly extracts part of the first target seed from the fixed random seed, and generates random data as test data based on the first target seed, thereby enriching the data type. If the current address is not the first time to be written to, the data generation module searches for the second target seed used when the current address was first written to, and extracts the second target seed from the fixed random seed, thereby generating the same data as the first write test as test data to meet the conditions for repeated testing.

[0070] Through the technical means provided by the embodiments of the present invention, repeated data can be freely selected according to whether the current test scenario is repeated, further improving the flexibility of the test.

[0071] In some optional implementations, the above step S103 includes:

[0072] Step c1: determining a target physical storage location corresponding to the current address in the storage device.

[0073] Step c2: Calculate the verification information of the test data.

[0074] Step c3: writing the verification information and test data into the target physical storage location.

[0075] Step c4: store the test data in a temporary buffer area.

[0076] Step c5, record the number of write times of the current address.

[0077] Step c6: Import the storage addresses whose write times reach the preset threshold into the test completion list.

[0078] Specifically, after the address control module determines the current address and the write count mark, and the data generation module generates the corresponding test data, the corresponding storage test task is executed through the storage module.

[0079] In this embodiment, the storage module is the core part of the entire test tool responsible for actual data storage and data management. Figure 4 As shown in FIG, it is mainly composed of a storage array, a write count record table, a data check unit, a cache area and an address mapping table.

[0080] The storage array refers to the actual physical space of the storage device, which is used to manage the actual physical addresses of the stored data. The write count record table is used to record the number of write tests performed on each storage address. The data verification unit is used to calculate the verification information of the test data so that the correctness of the data write can be judged by the verification information when the data is subsequently read. The temporary cache area is used to manage areas such as memory and cache where data is stored electrically. The cache area stores a small amount of data, but has high data reading efficiency. When repeated data is written, the data written for the first time can be placed in the temporary cache area for quick call during subsequent reuse. The address mapping table is used to map the logical address generated by the address control module to the actual physical address in the storage array.

[0081] During the initialization phase, the storage module will initialize all storage cells in the storage array to default values (usually all 0s) to ensure that the storage array is in a clean initial state and is ready for subsequent data writing. In addition, the storage module creates and initializes a write count record table during the initialization phase. This table is used to record the number of writes to each valid address. Each item in the table corresponds to a storage address, and the initial value is set to 0, indicating that no write operation has been performed. During the initialization phase, the storage module clears the cache area so that its initial state is empty. The cache area is used to temporarily store data that may be accessed again in the near future to improve the efficiency of data reading and writing. During the initialization phase, the storage module will establish an address mapping table to map logical addresses to physical addresses in the storage array to ensure that data can be accurately stored in the corresponding location.

[0082] Then, during the data write phase, the storage module receives the test data to be written from the data generation module and obtains the corresponding address and write count information from the address control module. The address mapping table then converts the received current address (which is a logical address) into a physical address in the storage array, determining the target physical storage location where the data is actually to be stored.

[0083] Before writing data into the storage array, the data verification unit generates verification information for the data, for example, using a cyclic redundancy check (CRC) algorithm to generate a CRC code. This embodiment is merely an example and is not intended to be limiting. Other verification methods can also be used to generate unique verification information. The generated verification information is stored with the data to facilitate subsequent data integrity checks.

[0084] According to the converted physical address, the storage module writes the test data and verification information together to the corresponding position of the storage array. At the same time, the write count corresponding to the address in the write count record table is updated. If it is the first write, the write count is increased by 1; if it is the second write, the write count is also increased by 1, and it is checked whether the write count of the address reaches the preset number threshold (for example, 2 times). If the preset number threshold is reached, the address is marked as an address that has been written and recorded in the test completion list, indicating that the address can be subsequently read or analyzed without waiting for the write test of other addresses to be completed, thereby improving the test efficiency and reducing the test cycle time.

[0085] In addition, the written data is stored in a temporary cache area at the same time for possible subsequent quick access. In this embodiment, if the cache area is full, the least recently used data in the cache area is replaced according to the cache replacement policy.

[0086] In some optional implementations, the address mapping table is also regularly managed. For example, these addresses can be marked as objects for further verification or other operations. Simultaneously, the list can be cleaned up and no longer needed records can be deleted to save storage space and improve search efficiency. Furthermore, the temporary cache area is regularly managed to update the data in the cache to ensure that the data in the cache is the latest and most commonly used. The size of the cache area is adjusted based on system usage to balance the cache hit rate and storage space usage. Furthermore, regular maintenance operations are performed on the storage array, such as checking the status of the storage cells and performing error correction, to ensure the reliability and stability of the storage array.

[0087] In some optional implementations, the storage device testing method provided by the present invention further includes:

[0088] Step d1, receiving the target address of the data to be read;

[0089] Step d2, searching the temporary buffer area for the target data stored corresponding to the target address;

[0090] Step d3: If the temporary buffer area includes the target data, the target data is read from the temporary buffer area and the test ends;

[0091] Step d4: if the temporary buffer does not include the target data, then reading the target data and target verification information corresponding to the target data from the physical storage location corresponding to the target address;

[0092] Step d5, re-verify based on the target data to obtain verification information;

[0093] Step d6: Determine the reliability of the storage device by judging the consistency between the verification check information and the target check information.

[0094] Specifically, the storage device testing method provided by an embodiment of the present invention also includes a data reading test. At the beginning of the test, the storage module receives the target address of the data to be read by the user. The storage module first searches the temporary cache area for the target data corresponding to the address. If the target data exists in the temporary cache area (i.e., a cache hit occurs), the data is read directly from the cache area, which can significantly improve the data reading speed. If the required target data is not found in the temporary cache area (i.e., a cache miss), the physical location of the target address in the storage array is found according to the address mapping table, and the target data and corresponding target verification information are read from the storage array.

[0095] After reading the data, the data verification unit recalculates the verification information for the read target data, obtains verification information, and compares the verification information with the stored target verification information. If the two are consistent, it indicates that no errors occurred during the storage and reading process of the target data and it can be used normally. If they are inconsistent, it indicates that the target data may have been damaged and appropriate error handling measures must be taken, such as data recovery or error message prompts. The technical solution provided by the embodiments of the present invention can accurately perform reliability analysis on the data write test, thereby further improving the reliability of the data write test.

[0096] The technical solution provided by the present invention has the following advantages:

[0097] 1. The address control module of the present invention can configure extremely complex address write sequences. Rather than being fixed to a single write pattern, this address control module offers significant flexibility and customizability. Rules such as address range, write sequence, and write count can be easily adjusted based on the characteristics of different storage devices and specific testing requirements. This precise address sequence control can closely simulate the complex address access patterns of storage devices in real-world applications, making test results more realistic and improving test accuracy and reliability.

[0098] 2. The data generation module uses a fixed seed to initialize the random number generator. Each time the system runs, as long as the seed is the same, it can generate a completely consistent random data sequence. This feature ensures the repeatability of the test.

[0099] 3. The present invention divides the system into three core modules: an address control module, a data generation module, and a storage module. Each module has a clear division of labor and close collaboration. The address control module is responsible for generating accurate address and write count information, the data generation module generates appropriate data based on this information, and the storage module accurately writes data to the specified address and effectively manages it. The modular design not only improves the system's maintainability and scalability, but also implements a pipelined testing method, enabling individual exception analysis of each address's write test, further enhancing the performance and flexibility of the entire system.

[0100] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0101] The embodiment of the present application also provides a testing device for a storage device, such as Figure 5 Shown, including:

[0102] An address control module 501 is used to generate a write address control strategy, which is used to indicate the write order of different addresses in the storage device;

[0103] Data generation module 502, used to obtain test data;

[0104] The storage module 503 is configured to write the test data into corresponding locations of the storage device in sequence according to the order defined by the write address control policy.

[0105] In some optional implementations, the address control module 501 includes:

[0106] A use case acquisition unit, used to acquire a write address test case, where the write address test case is a text used to record the write order of different addresses in the storage device;

[0107] A phase division unit, used for dividing the write address test case into several test phases;

[0108] An address generation unit is used to control the address generator to generate a current address according to the test case of the current test phase, and to add a write count mark to the current address, where the write count mark indicates the number of write tests performed on the generated current address;

[0109] Verification unit, used to verify the validity of the current address range;

[0110] The output unit is used to output the current address and the write count mark when the verification is passed, so that the current address and the write count mark are used as the write address control strategy in the current test phase.

[0111] In some optional implementations, the data generation module 502 includes:

[0112] A seed acquisition unit, used to obtain a fixed random seed;

[0113] A data generation unit, configured to generate random data based on a fixed random seed;

[0114] The formatting processing unit is used to process random data into a data format that meets storage requirements to obtain test data.

[0115] In some optional implementations, the data generating unit includes:

[0116] A judging unit, configured to judge whether the current address is being written to for the first time according to the current address and the write count mark;

[0117] a random generation unit, configured to randomly extract a portion of a first target seed from a fixed random seed and generate random data based on the first target seed when a write test is performed on a current address for the first time;

[0118] a fixed seed obtaining unit, configured to determine a second target seed used by the current address during the first test when the current address is not subjected to the write test for the first time;

[0119] The fixed generation unit is configured to extract a second target seed from the fixed random seed and generate random data based on the second target seed.

[0120] In some optional implementations, the storage module 503 includes:

[0121] A mapping unit, configured to determine a target physical storage location corresponding to a current address in a storage device;

[0122] A verification unit, used to calculate verification information of test data;

[0123] a storage unit, configured to write the verification information and the test data into a target physical storage location;

[0124] The cache unit is used to store test data in a temporary cache area.

[0125] The times recording unit is used to record the times of writing to the current address;

[0126] The completion unit is used to import the storage addresses whose write times reach a preset threshold into the test completion list.

[0127] For descriptions of features in the embodiments corresponding to the storage device testing apparatus, reference may be made to the relevant descriptions of the embodiments corresponding to the storage device testing method, which will not be detailed here.

[0128] The embodiment of the present application also provides an electronic device, such as Figure 6 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any of the above-mentioned storage device testing method embodiments.

[0129] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned storage device testing method embodiments when running.

[0130] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0131] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned storage device test embodiments are implemented.

[0132] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned storage device test embodiments are implemented.

[0133] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0134] The above is a detailed introduction to the testing method, apparatus, electronic device and storage medium of a storage device provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for testing a storage device, characterized in that: include: Generate a write address control strategy, wherein the write address control strategy is used to indicate the write order of different addresses in the storage device; Get test data; The test data are sequentially written into corresponding locations of the storage device according to the order defined by the write address control strategy.

2. The method according to claim 1, characterized in that The generating of the write address control strategy includes: Obtaining a write address test case, wherein the write address test case is a text for recording a write sequence of different addresses in a storage device; Dividing the write address test case into several test phases; According to the test case of the current test phase, the address generator is controlled to generate a current address, and a write count mark is added to the current address, where the write count mark indicates the number of write tests performed on the generated current address; Verify the scope validity of the current address; When the verification passes, the current address and the write count mark are output, so that the current address and the write count mark serve as the write address control strategy of the current test phase.

3. The method according to claim 2, characterized in that The obtaining of test data includes: Get a fixed random seed; generating random data based on the fixed random seed; The random data is processed into a data format that meets storage requirements to obtain the test data.

4. The method according to claim 3, characterized in that Generating random data based on the fixed random seed includes: Determine whether the current address is being written to for the first time according to the current address and the write count mark; When the current address is subjected to a write test for the first time, randomly extracting a portion of a first target seed from the fixed random seed, and generating the random data based on the first target seed; When the current address is not subjected to a write test for the first time, determining a second target seed used by the current address during the first test; The second target seed is extracted from the fixed random seed, and the random data is generated based on the second target seed.

5. The method according to claim 2, characterized in that Writing the test data into corresponding locations of the storage device in sequence according to the order defined by the write address control strategy includes: Determining a target physical storage location corresponding to the current address in the storage device; Calculating verification information of the test data; Writing the verification information and the test data into the target physical storage location; The test data is stored in a temporary buffer area.

6. The method according to claim 5, characterized in that The method further comprises: Recording the number of writes to the current address; The storage addresses whose write times reach the preset threshold are imported into the test completion list.

7. The method according to claim 5, characterized in that The method further comprises: Receive the target address of the data to be read; Searching the temporary buffer area for target data stored corresponding to the target address; If the temporary buffer area includes the target data, reading the target data from the temporary buffer area and ending the test; If the temporary buffer area does not include the target data, reading the target data and target verification information corresponding to the target data from a physical storage location corresponding to the target address; Re-verify based on the target data to obtain verification information; The reliability of the storage device is determined by judging the consistency between the verification check information and the target check information.

8. A storage device testing device, characterized in that: include: An address control module, configured to generate a write address control strategy, wherein the write address control strategy is used to indicate a write order of different addresses in the storage device; Data generation module, used to obtain test data; The storage module is used to write the test data into corresponding positions of the storage device in sequence according to the order defined by the write address control strategy.

9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the storage device testing method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the storage device testing method according to any one of claims 1 to 7 are implemented.

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