Wafer-level gallium arsenide chip heat dissipation packaging structure and packaging method

Abstract

The present invention discloses a wafer-level gallium arsenide chip heat dissipation packaging structure and packaging method. In this packaging structure, the main chip and the gallium arsenide chip are interconnected in a planar manner through a redistribution layer. The back of the gallium arsenide chip is coated with high thermal conductivity / high thermal conductivity heat dissipation glue / or affixed with a high thermal conductivity DAF film and adhered to the high thermal conductivity wafer above to form a high-density interconnected reconstruction chip. The reconstruction chip is interconnected with the substrate through metal bumps. A heat dissipation cover is provided on the top of the substrate and the reconstruction chip, or a heat dissipation ring is attached to the substrate and a heat dissipation fin is provided on the top of the reconstruction chip, so that the heat dissipation cover or heat dissipation fin is directly bonded and contacted with the high thermal conductivity wafer. The gallium arsenide chip conducts internal heat away through the high thermal conductivity wafer, the heat dissipation cover or the heat dissipation fin. Compared with the traditional gallium arsenide chip embedded packaging structure, the present application reduces the amount of plastic packaging material and the thickness of the plastic packaging is thinner, which can reduce warping. In terms of the packaging method, it can reduce the processing difficulty and significantly improve the thermal conductivity effect.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly to a heat dissipation packaging structure and a packaging method for a wafer-level gallium arsenide chip. Background Art

[0002] Gallium arsenide (GaAs) is an important semiconductor material. Semiconductor devices made with GaAs exhibit advantages such as high frequency, high- and low-temperature performance, low noise, and strong radiation resistance. While GaAs possesses many advantages among semiconductor materials, transistors made with it have poor thermal conductivity, making them unsuitable for high-power devices. Furthermore, GaAs decomposes at high temperatures, requiring high production technology.

[0003] In specific applications, it was found that due to the limitations of wafer processing, the incoming material thickness of GaAs chips is generally thin, at 100μm. When multiple chips are packaged together in a fan-out package, such as the ewlb-M package (dry film fan-out package structure), the package thickness is relatively thick. The GaAs chip is embedded in a compound (a semiconductor material composed of two or more elements), which causes heat accumulation and poor heat dissipation efficiency, affecting the chip's performance. In addition, because the chip is thin, the silicon content is low, and the mass of the plastic packaging compound increases, resulting in excessive wafer warping and difficult processing. Summary of the Invention

[0004] To solve the above problems, the present invention provides a wafer-level GaAs chip heat dissipation packaging structure and packaging method. A wafer with a high thermal conductivity material is mounted on the back of the GaAs chip to transfer the heat of the chip to the top, solving the heat accumulation problem and reducing wafer warping, thereby reducing processing difficulty.

[0005] According to one aspect of the present invention, a wafer-level GaAs chip heat dissipation packaging structure is provided, comprising a main chip, a GaAs chip, a high-thermal-conductivity wafer, and a redistribution layer. The main chip and the GaAs chip are located on the same side of the redistribution layer, and the main chip and the GaAs chip are interconnected in a planar manner through the redistribution layer. The high-thermal-conductivity wafer is attached to the top of the GaAs chip using high-thermal-conductivity silver glue / high-thermal-conductivity heat-dissipating glue / or high-thermal-conductivity DAF film. The main chip, GaAs chip, and high-thermal-conductivity wafer are encapsulated to form a plastic layer. The back of the high-thermal-conductivity wafer is exposed to the surface of the plastic layer, and the other side of the redistribution layer is provided with metal bumps. Thus, in this packaging structure, the main chip and the GaAs chip are interconnected in a planar manner through the redistribution layer. A high-thermal-conductivity wafer made of high-thermal-conductivity material is attached to the back of the GaAs chip to conduct heat, and then plastic-encapsulated to form a high-density interconnected reconstructed chip. Compared to traditional GaAs chip embedded packaging structures, this structure reduces the amount of plastic encapsulation material and the thickness of the plastic encapsulation, thereby reducing warping, lowering processing difficulty, improving thermal conductivity, and avoiding heat accumulation.

[0006] Preferably, in some embodiments, the package structure further includes a substrate and a heat dissipation cover. The redistribution layer is flip-chip mounted on the substrate via metal bumps. The heat dissipation cover comprises a top cover and surrounding dams. The top cover is attached to the plastic encapsulation layer and is in direct contact with the high-thermal-conductivity chip. The dams are attached to the substrate. The back of the substrate is implanted with solder balls and mounted with components. Thus, the reconstructed chip is soldered to the substrate via the metal bumps, and the heat dissipation cover is placed on top of the substrate and the reconstructed chip to enhance heat dissipation.

[0007] Preferably, in some embodiments, the package structure further includes a substrate, a heat sink ring, and heat sink fins. The redistribution layer is flip-chip mounted on the substrate via metal bumps, the heat sink ring is mounted on the substrate, the back of the substrate is soldered with solder balls and components are mounted, the heat sink fins are mounted on the plastic layer, and the heat sink fins are in direct contact with the high-thermal-conductivity chip. Thus, the reconstructed chip is soldered to the substrate via metal bumps, the heat sink ring is mounted on the substrate, and the heat sink fins are mounted on top of the reconstructed chip to enhance heat dissipation.

[0008] Preferably, the main chip is a main chip SOC grain, and the high thermal conductivity chip is a silicon chip.

[0009] According to another aspect of the present invention, a packaging method is provided for preparing the above-mentioned wafer-level gallium arsenide chip heat dissipation packaging structure, the method comprising:

[0010] Provide temporary carrier board, temporary bonding film, main chip, GaAs chip and high thermal conductivity wafer;

[0011] Adopt film lamination technology to stick temporary bonding film on temporary carrier;

[0012] Flip the main chip onto the temporary bonding film; Flip the gallium arsenide chip onto the temporary bonding film;

[0013] The high thermal conductivity wafer is mounted on top of the GaAs chip using a face-up process;

[0014] The main chip, gallium arsenide chip and high thermal conductivity wafer on the temporary bonding film are encapsulated and coated by wafer-level plastic encapsulation process to form a plastic encapsulation layer;

[0015] The temporary carrier and the temporary bonding film are separated from the bottom of the wafer using a debonding process, and the wafer is turned upside down.

[0016] The redistribution layer is processed on the wafer using photolithography and electroplating processes, and metal bumps are made on top of the redistribution layer using ball implantation or electroplating processes;

[0017] A laminating process is used to apply a grinding film to the redistribution layer side of the wafer, and a lapping process is used to thin the back of the wafer so that the back of the high thermal conductivity chip is exposed to the plastic sealing layer;

[0018] The wafer is cut into individual reconstructed chips using a dicing process.

[0019] Furthermore, before mounting the high thermal conductivity chip, a dispensing process or a printing process is used to coat high thermal conductivity silver glue and / or high thermal conductivity heat dissipation glue on the top of the gallium arsenide chip, and then a positive mounting process is used to mount the high thermal conductivity chip on the top of the gallium arsenide chip, and the high thermal conductivity silver glue and / or high thermal conductivity heat dissipation glue is cured through a curing process.

[0020] Furthermore, the method further comprises:

[0021] Provide scribing film with high thermal conductivity DAF film and high thermal conductivity wafers. Through the film lamination process, the scribing film with high thermal conductivity DAF film is attached to the back of the high thermal conductivity wafer. Through the scribing process, the high thermal conductivity wafer is cut into single high thermal conductivity wafers with high thermal conductivity DAF film.

[0022] The high thermal conductivity chip with high thermal conductivity DAF film is mounted on the top of the gallium arsenide chip using a positive mounting process, and the high thermal conductivity DAF film is solidified through a curing process.

[0023] Furthermore, the method further comprises:

[0024] Provide substrates, components, and heat dissipation covers;

[0025] The reconstructed chip is flipped onto the substrate using a flip-chip process, and components are mounted on the substrate;

[0026] The metal bumps between the redistribution layer and the substrate are covered and protected using the bottom filling process;

[0027] Mounting a heat dissipation cover, wherein the heat dissipation cover has a top cover and cofferdams around it, the top cover is mounted on the plastic packaging layer and is in direct contact with the high thermal conductivity chip, and the cofferdams are mounted on the substrate;

[0028] The ball planting process and surface mounting process are used to plant solder balls and mount components on the back of the substrate.

[0029] Furthermore, the method further comprises:

[0030] Provide substrates, components, heat sink rings, and heat sink fins;

[0031] The reconstructed chip is flipped onto the substrate using a flip-chip process, and components are mounted on the substrate;

[0032] The metal bumps between the redistribution layer and the substrate are covered and protected using the bottom filling process;

[0033] Mounting a heat sink ring on the substrate;

[0034] Use ball planting technology and surface mounting technology to plant solder balls and mount components on the back of the substrate;

[0035] The heat sink fins are mounted on the plastic packaging layer, and the heat sink fins are in direct contact with the high thermal conductivity chip.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention realizes planar interconnection between the main chip and the gallium arsenide chip through a redistribution layer, and the back of the gallium arsenide chip is coated with high thermal conductivity / high thermal conductivity heat dissipation glue / or affixed with a high thermal conductivity DAF film to adhere to the high thermal conductivity chip above to conduct heat, thereby forming a high-density interconnected reconstruction chip. The reconstruction chip is interconnected with the substrate through metal bumps, and a heat dissipation cover is provided on the top of the substrate and the reconstruction chip, or a heat dissipation ring is mounted on the substrate and a heat dissipation fin is provided on the top of the reconstruction chip, so that the heat dissipation cover or heat dissipation fin is directly bonded and contacted with the high thermal conductivity chip. The gallium arsenide chip conducts internal heat away through the high thermal conductivity chip, the heat dissipation cover or the heat dissipation fin, thereby enhancing heat dissipation. Compared with the traditional gallium arsenide chip embedded packaging structure, the packaging structure provided by the present application reduces the amount of plastic packaging material and the thickness of the plastic packaging is thinner, which can reduce warping. In terms of the packaging method, it can reduce the difficulty of processing, and the thermal conductivity effect is significantly improved, effectively avoiding the problem of heat accumulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a schematic structural diagram of an embodiment of a reconfigurable chip;

[0038] Figure 2 This is a schematic diagram of a pre-process for manufacturing a reconstructable chip according to an embodiment;

[0039] Figure 3 This is a schematic diagram of a subsequent manufacturing process of a reconstructed chip according to an embodiment;

[0040] Figure 4 middle Figure 4 A is the dot coating process, Figure 4 B is a schematic diagram of applying high thermal conductivity silver glue or high thermal conductivity heat dissipation glue to the GaAs chip through the printing process;

[0041] Figure 5 is a schematic diagram of a process for manufacturing a high thermal conductivity wafer with a high thermal conductivity DAF film in another embodiment;

[0042] Figure 6 is a schematic diagram of a pre-process of manufacturing a reconstructed chip according to another embodiment;

[0043] Figure 7 is a schematic diagram of a subsequent manufacturing process of a reconstructed chip according to another embodiment;

[0044] Figure 8 This is a schematic structural diagram of an embodiment of a wafer-level gallium arsenide chip heat dissipation packaging structure;

[0045] Figure 9 yes Figure 8 Schematic diagram of the production process of the package structure;

[0046] Figure 10 It is a structural schematic diagram of another embodiment of a wafer-level gallium arsenide chip heat dissipation packaging structure;

[0047] Figure 11 yes Figure 10 Schematic diagram of the production process of the packaging structure.

[0048] Figure numerals: main chip-1; gallium arsenide chip-2; high thermal conductivity chip-3; high thermal conductivity chip wafer-30; high thermal conductivity silver glue-31; high thermal conductivity heat dissipation glue-32; high thermal conductivity DAF film-33; plastic sealing layer-4; redistribution layer-5; metal bumps-51; substrate-6; solder balls-61; components-62; heat dissipation cover-7; top cover-71; cofferdam-72; heat dissipation ring-8; heat dissipation fins-9; UF glue-11; heat dissipation glue-12; grinding film-13; temporary carrier-100; temporary bonding film-101. DETAILED DESCRIPTION

[0049] The present invention will be further described below in conjunction with specific embodiments.

[0050] The invention discloses a wafer-level gallium arsenide chip heat dissipation packaging structure and a packaging method.

[0051] like Figure 1 As shown, the wafer-level GaAs chip heat dissipation packaging structure includes a main chip 1, a GaAs chip 2, a high thermal conductivity chip 3 and a redistribution layer 5. The main chip 1 and the GaAs chip 2 are located on the same side of the redistribution layer 5. The main chip 1 and the GaAs chip 2 are planarly interconnected through the redistribution layer 5. The high thermal conductivity chip 3 is attached to the top of the GaAs chip 2 through high thermal conductivity silver glue / or high thermal conductivity heat dissipation glue / or high thermal conductivity DAF film. The main chip 1, GaAs chip 2 and high thermal conductivity chip 3 above the redistribution layer 5 are encapsulated with plastic packaging material to form a plastic packaging layer 4. The back of the high thermal conductivity chip 3 is exposed to the surface of the plastic packaging layer 4, and metal bumps 51 are processed on the other side of the redistribution layer 5.

[0052] Combine Figure 2 and Figure 3 , specifically describing a packaging method for the above-mentioned packaging structure, wherein a high thermal conductivity silver glue or a high thermal conductivity heat dissipation glue is used to connect the gallium arsenide chip 2 and the high thermal conductivity wafer 3, including the following steps:

[0053] S01A: Prepare a temporary carrier 100, a temporary bonding film 101, a main chip 1, a GaAs chip 2, and a high thermal conductivity wafer 3. Use a film lamination technique to attach a temporary bonding film 101, such as a thermal release film, to the temporary carrier 100.

[0054] S02A: Using a flip-chip process, the main chip 1 is mounted on the temporary bonding film 101. In this embodiment, the main chip 1 is a main chip SOC die.

[0055] S03A: Using a flip-chip process, the secondary GaAs chip 2 is mounted on the temporary bonding film 101 .

[0056] S04A: Use a dot coating process or a printing process to apply a high thermal conductivity silver glue 31 or a high thermal conductivity heat dissipation glue 32 on the top of the GaAs chip 2, such as Figure 4 shown.

[0057] S05A: Using a top-mount process, a high-thermal-conductivity chip 3 is mounted on top of the gallium arsenide chip 2. In this embodiment, a silicon chip is used for the high-thermal-conductivity chip 3. The high-thermal-conductivity silver glue 31 or the high-thermal-conductivity heat-dissipating glue 32 is cured through a curing process.

[0058] S06A: The wafer is encapsulated by using a wafer-level encapsulation process. Specifically, the main chip 1 , the gallium arsenide chip 2 and the high thermal conductivity wafer 3 on the temporary bonding film 101 are encapsulated to form a encapsulation layer 4 .

[0059] S07A: Using a debonding process, the temporary carrier 100 and the temporary bonding film 101 are separated from the bottom of the wafer, and the wafer is turned upside down.

[0060] S08A: Processing organic RDL (ReDistribution Layer) on wafers using photolithography and electroplating processes.

[0061] S09A: A metal bump 51 is formed on the top of the redistribution layer 5 by using a ball planting process or an electroplating process.

[0062] S10A: Prepare a polishing film 13 and adhere the polishing film 13 to the surface of the wafer where the redistribution layer 5 is located using a film lamination process.

[0063] S11A: The back of the wafer is thinned by a grinding process to expose the back of the chip. The back of the high thermal conductivity chip 3 needs to be exposed to the surface of the plastic packaging layer 4.

[0064] S12A: The wafer is cut into individual reconstructed chips using a dicing process.

[0065] Combine Figure 5 、 Figure 6 and Figure 7 , specifically describing another packaging method of the above packaging structure, in which a high thermal conductivity DAF film 33 is used to connect the gallium arsenide chip 2 and the high thermal conductivity wafer 3, comprising the following steps:

[0066] The high thermal conductivity wafer 3 with the high thermal conductivity DAF film 33 is mounted on the top of the gallium arsenide chip 2 using a face-up process, and then cured through a curing process.

[0067] S01B: Prepare a high thermal conductivity wafer 30 and a dicing film with a high thermal conductivity DAF film 33. Thin the high thermal conductivity wafer 30 to a required thickness through a lapping process.

[0068] S02B: Through the film lamination process, a dicing film with a high thermal conductivity DAF film 33 is attached to the back side of the high thermal conductivity wafer 30 .

[0069] S03B: Through a scribing process, the high thermal conductivity wafer 30 is cut into individual high thermal conductivity wafers 3 with high thermal conductivity DAF films 33 for standby use.

[0070] S04B: Prepare a temporary carrier 100, a temporary bonding film 101, a main chip 1, and a GaAs chip 2. Adopt a film bonding technology to bond the temporary bonding film 101, such as a thermal peeling film, to the temporary carrier 100.

[0071] S05B: Using a flip-chip process, the main chip 1 is mounted on the temporary bonding film 101. In this embodiment, the main chip 1 is a main chip SOC die.

[0072] S06B: Using a flip-chip process, the secondary GaAs chip 2 is mounted on the temporary bonding film 101 .

[0073] S07B: Using a top-mounting process, the high thermal conductivity wafer 3 with the high thermal conductivity DAF film 33 prepared in step S03B is mounted on top of the GaAs chip 2. The high thermal conductivity DAF film 33 is solidified through a solidification process.

[0074] S08B: The wafer is encapsulated by using a wafer-level encapsulation process. Specifically, the main chip 1 , the gallium arsenide chip 2 and the high thermal conductivity wafer 3 on the temporary bonding film 101 are encapsulated to form a encapsulation layer 4 .

[0075] S09B: Using a debonding process, the temporary carrier 100 and the temporary bonding film 101 are separated from the bottom of the wafer, and the wafer is turned upside down.

[0076] S10B: Using photolithography and electroplating processes, organic RDL (ReDistribution Layer, redistribution layer 5) is processed on the wafer.

[0077] S11B: metal bumps 51 are manufactured on the top of the redistribution layer 5 by using a ball planting process or an electroplating process.

[0078] S12B: Prepare a grinding film 13 and adhere the grinding film 13 to the surface of the wafer where the redistribution layer 5 is located using a film lamination process.

[0079] S13B: The back of the wafer is thinned by a grinding process to expose the back of the chip. The back of the high thermal conductivity chip 3 needs to be exposed to the surface of the plastic packaging layer 4.

[0080] S14B: The wafer is cut into individual reconstructed chips using a dicing process.

[0081] The above-mentioned packaging structure is further packaged with the substrate 6 and the heat dissipation cover 7 to form a packaging structure: the above-mentioned reconstructed chip is flipped on the substrate 6, the redistribution layer 5 is soldered to the substrate 6 through the metal bumps 51, the components 62 are mounted on the front of the substrate 6, and the heat dissipation cover 7 is mounted using the top cover technology. Specifically, the heat dissipation cover 7 has a top cover 71 and cofferdams 72 on all sides. The top cover 71 is mounted on the plastic packaging layer 4, and the top cover 71 is in direct contact with the high thermal conductivity chip 3. The cofferdam 72 is mounted on the substrate 6. Solder balls 61 are planted on the back of the substrate 6 and components 62 are mounted.

[0082] The packaging method of the packaging structure specifically includes the following steps: Figure 8 and Figure 9 Explanation:

[0083] The substrate 6, components 62, and heat dissipation cover 7 are prepared.

[0084] Step A: Using a flip-chip process, the reconstructed chip is flip-chip mounted on the substrate 6 and reflow soldered.

[0085] Step B: Mount the components 62 on the substrate 6 using a surface mount process and perform reflow soldering.

[0086] Step C: Using the bottom filling process, filling with UF glue 11, the UF glue 11 covers and protects the metal bumps 51 between the redistribution layer 5 and the substrate 6, and surrounds the redistribution layer 5 and the lower part of the plastic packaging layer 4.

[0087] Step D: Use the cover process to mount the heat dissipation cover 7, the top cover 71 is mounted on the plastic packaging layer 4, and the top cover 71 is in direct contact with the high thermal conductivity chip 3, the cofferdam 72 is mounted on the substrate 6, and the plastic packaging layer 4 and the top cover 71, the substrate 6 and the cofferdam 72 are bonded by the heat dissipation glue 12.

[0088] Step E: solder balls 61 are planted on the back side of the substrate 6 using a ball planting process, and components 62 are mounted on the back side of the substrate 6 using a surface mounting process.

[0089] The above-mentioned packaging structure uses a heat dissipation cover 7. The packaging structure described below uses a heat dissipation ring 8 and heat dissipation fins 9. Specifically, the reconstructed chip prepared above is flipped onto a substrate 6. The redistribution layer 5 is soldered to the substrate 6 via metal bumps 51. Components 62 are mounted on the front of the substrate 6. The heat dissipation ring 8 is mounted on the substrate 6. The back of the substrate 6 is implanted with solder balls 61 and mounted with components 62. The heat dissipation fins 9 are mounted on the plastic layer 4, and the heat dissipation fins 9 are in direct contact with the high thermal conductivity chip 3.

[0090] The packaging method of the packaging structure specifically includes the following steps: Figure 10 and Figure 11 Explanation:

[0091] Prepare the substrate 6, components 62, heat sink ring 8, and heat sink fins 9.

[0092] Step H: Using a flip-chip process, flip-chip the reconstructed chip onto the substrate 6 and perform reflow soldering.

[0093] Step I: Surface mount technology is used to mount the components 62 on the substrate 6, and then reflow soldering is performed.

[0094] Step J: Using the bottom filling process, filling with UF glue 11, the UF glue 11 covers and protects the metal bumps 51 between the redistribution layer 5 and the substrate 6, and surrounds the redistribution layer 5 and the lower part of the plastic packaging layer 4.

[0095] Step K: Using a cover-up process, the heat dissipation ring 8 is mounted on the top of the substrate 6 using heat dissipation adhesive 12 .

[0096] Step L: solder balls 61 are planted on the back side of the substrate 6 using a ball planting process, and components 62 are mounted on the back side of the substrate 6 using a surface mounting process.

[0097] Step M: Using a mounting process, the heat dissipation fins 9 are mounted on the top of the reconstructed chip using a heat dissipation adhesive 12 , and the heat dissipation fins 9 are in direct contact with the high thermal conductivity chip 3 .

[0098] The present invention realizes planar interconnection between the main chip 1 and the gallium arsenide chip 2 through a redistribution layer 5. The back of the gallium arsenide chip 2 is coated with high thermal conductivity / high thermal conductivity heat dissipation glue 32 / or affixed with a high thermal conductivity DAF film 33 to adhere to the high thermal conductivity chip 3 above, conducting heat to form a high-density interconnected reconstruction chip. The reconstruction chip is welded and interconnected with the substrate 6 through metal bumps 51. A heat dissipation cover 7 is provided on the substrate 6 and the top of the reconstruction chip, or a heat dissipation ring 8 is mounted on the substrate 6 and a heat dissipation fin 9 is provided on the top of the reconstruction chip, so that the heat dissipation cover 7 or the heat dissipation fin 9 is directly bonded and contacted with the high thermal conductivity chip 3. The gallium arsenide chip 2 conducts internal heat away through the high thermal conductivity chip 3, the heat dissipation cover 7 or the heat dissipation fin 9, thereby enhancing heat dissipation, effectively avoiding heat accumulation problems, and significantly improving the thermal conductivity effect.

[0099] Compared with the traditional embedded packaging structure of gallium arsenide chip 2, the packaging structure provided by the present application reduces the amount of plastic packaging material and the thickness of the plastic packaging, which can reduce warping. In terms of the packaging method, the processing difficulty is greatly reduced and the yield rate is greatly improved.

[0100] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other variations and improvements can be made without departing from the creative concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A wafer-level gallium arsenide chip heat dissipation packaging structure, characterized in that: The invention comprises a main chip, a gallium arsenide chip, a high thermal conductivity wafer and a redistribution layer. The main chip and the gallium arsenide chip are arranged on the same side of the redistribution layer, and the main chip and the gallium arsenide chip are interconnected in a planar manner through the redistribution layer. The high thermal conductivity wafer is mounted on the top of the gallium arsenide chip through high thermal conductivity silver glue / high thermal conductivity heat dissipation glue / or high thermal conductivity DAF film. The main chip, gallium arsenide chip and high thermal conductivity wafer are plastic-sealed around to form a plastic sealing layer. The back side of the high thermal conductivity wafer is exposed to the surface of the plastic sealing layer. The other side of the redistribution layer is provided with metal bumps.

2. The packaging structure according to claim 1, wherein: It also includes a substrate and a heat dissipation cover. The redistribution layer is flip-chip mounted on the substrate through metal bumps. The heat dissipation cover has a top cover and cofferdams around it. The top cover is mounted on the plastic packaging layer and is in direct contact with the high thermal conductivity chip. The cofferdam is mounted on the substrate. The back of the substrate is planted with solder balls and components are mounted thereon.

3. The packaging structure according to claim 1, wherein: It also includes a substrate, a heat sink ring and heat sink fins. The redistribution layer is flip-chip mounted on the substrate through metal bumps, the heat sink ring is mounted on the substrate, the back of the substrate is planted with solder balls and components are mounted, the heat sink fins are mounted on the plastic packaging layer, and the heat sink fins are in direct contact with the high thermal conductivity chip.

4. The packaging structure according to claim 1, wherein: The main chip is a main chip SOC crystal grain, and the high thermal conductivity chip is a silicon chip.

5. A packaging method for a wafer-level gallium arsenide chip heat dissipation packaging structure, characterized in that: The method comprises: Provide temporary carrier board, temporary bonding film, main chip, GaAs chip and high thermal conductivity wafer; Adopt film lamination technology to stick temporary bonding film on temporary carrier; Flip the main chip onto the temporary bonding film; Flip the gallium arsenide chip onto the temporary bonding film; The high thermal conductivity wafer is mounted on top of the GaAs chip using a face-up process; The main chip, gallium arsenide chip and high thermal conductivity wafer on the temporary bonding film are encapsulated and coated by wafer-level plastic encapsulation process to form a plastic encapsulation layer; The temporary carrier and the temporary bonding film are separated from the bottom of the wafer using a debonding process, and the wafer is turned upside down. The redistribution layer is processed on the wafer using photolithography and electroplating processes, and metal bumps are made on top of the redistribution layer using ball implantation or electroplating processes; A laminating process is used to apply a grinding film to the redistribution layer side of the wafer, and a lapping process is used to thin the back of the wafer so that the back of the high thermal conductivity chip is exposed to the plastic sealing layer; The wafer is cut into individual reconstructed chips using a dicing process.

6. The packaging method according to claim 5, characterized in that: Before mounting the high thermal conductivity chip, a high thermal conductivity silver glue and / or a high thermal conductivity heat dissipation glue is coated on the top of the gallium arsenide chip using a dispensing process or a printing process. Then, the high thermal conductivity chip is mounted on the top of the gallium arsenide chip using a positive mounting process, and the high thermal conductivity silver glue and / or the high thermal conductivity heat dissipation glue is cured through a curing process.

7. The packaging method according to claim 5, characterized in that: The method further comprises: Provide scribing film with high thermal conductivity DAF film and high thermal conductivity wafers. Through the film lamination process, the scribing film with high thermal conductivity DAF film is attached to the back of the high thermal conductivity wafer. Through the scribing process, the high thermal conductivity wafer is cut into single high thermal conductivity wafers with high thermal conductivity DAF film. The high thermal conductivity chip with high thermal conductivity DAF film is mounted on the top of the gallium arsenide chip using a positive mounting process, and the high thermal conductivity DAF film is solidified through a curing process.

8. The packaging method according to claim 6 or 7, characterized in that: The method further comprises: Provide substrates, components, and heat dissipation covers; The reconstructed chip is flipped onto the substrate using a flip-chip process, and components are mounted on the substrate; The metal bumps between the redistribution layer and the substrate are covered and protected using the bottom filling process; Mounting a heat dissipation cover, wherein the heat dissipation cover has a top cover and surrounding dams, wherein the top cover is mounted on the plastic packaging layer and is in direct contact with the high thermal conductivity chip, and the cofferdams are mounted on the substrate; The ball planting process and surface mounting process are used to plant solder balls and mount components on the back of the substrate.

9. The packaging method according to claim 6 or 7, characterized in that: The method further comprises: Provide substrates, components, heat sink rings, and heat sink fins; The reconstructed chip is flipped onto the substrate using a flip-chip process, and components are mounted on the substrate; The metal bumps between the redistribution layer and the substrate are covered and protected using the bottom filling process; Mounting a heat sink ring on the substrate; Use ball planting technology and surface mounting technology to plant solder balls and mount components on the back of the substrate; The heat sink fins are mounted on the plastic packaging layer, and the heat sink fins are in direct contact with the high thermal conductivity chip.

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