Current-to-voltage conversion circuit for suppressing common-mode interference

Abstract

The present application relates to a kind of current voltage acquisition circuits of common mode interference inhibition, current amplification module, current transformer, high pass filter, interference acquisition module, interference analysis module and inhibition execution module;By such design, the inhibition effect of common mode interference is more optimal compared to traditional sampling circuit, the error caused by the deviation of sampling signal due to interference is avoided to the greatest extent, especially applicable to the occasion of interference scene or interference source change, the changing interference source can be calculated by sampling statistics, so as to adjust the inhibition ratio of common mode inhibition, accurately sampling effect is obtained by tracking environmental conditions dynamically.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of acquisition circuit, more particularly, to a current-to-voltage acquisition circuit for suppressing common-mode interference. BACKGROUND

[0002] Direct current detection technology is widely used in power supply monitoring, electronic product overcurrent protection and other product design. According to the sampling position of current acquisition, it can be classified into two types: 1. Sampling from the negative electrode, which is called low-end sampling; 2. Sampling from the positive electrode, which is called high-end sampling. Low-end sampling circuit is simple and low in cost, but it is not suitable for multi-output environment. In multi-port output application, each current flows from the respective positive output to the negative common line, so high-end sampling is suitable for collecting positive current in this scenario. It is suitable for the design of current acquisition, voltage acquisition equipment, electrical sensor involved in high-voltage power grid system, or detection technology module in new energy electric vehicle charging technology.

[0003] At present, the high-end current acquisition technology mainly includes the following two main design methods, as shown in the following two figures. Figure 1 The follow-up amplification circuit composed of special chips such as Maxim MAX471 and INA199 of Ti: the other is to use professional high common-mode rejection ratio OP A2992 operational amplifier chip to compose an amplification circuit, as shown in the following figure. Figure 2 However, both of these two schemes need to rely on professional chips, and the common-mode rejection part is a static design. The common-mode interference may change dynamically with the environment and scene and other loads, and if static common-mode rejection elements are used, reverse current may be generated in the transient state of common-mode interference change, thereby affecting the reliability of the acquisition value. Generally, the influence is eliminated by calculating the average value of the acquisition voltage to obtain a more accurate acquisition voltage value. However, if the common-mode interference is large and the acquisition scene changes continuously (for example, the physical position of the load changes continuously), the average method is also prone to large errors, and the average method has a large limitation, and it is difficult to obtain accurate acquisition results. SUMMARY

[0004] Therefore, the present application aims to provide a current-to-voltage acquisition circuit for suppressing common-mode interference.

[0005] In order to solve the above technical problems, the technical scheme of the present application is as follows: a current-to-voltage acquisition circuit for suppressing common-mode interference, a current amplification module, a current transformer, a high-pass filter, an interference acquisition module, an interference analysis module, and a suppression execution module.

[0006] The current amplification module is coupled to an acquisition load and outputs an amplified acquisition voltage;

[0007] The current transformer is coupled to a power circuit, and the high-pass filter is coupled to the current transformer.

[0008] The interference collection module is coupled to the high-pass filter to receive the interference current and output the interference voltage;

[0009] The interference analysis module is coupled to the interference collection module to receive the interference voltage and output the suppression correction voltage;

[0010] The suppression execution module includes a collection input end, a suppression input end, and a collection output end, the collection input end receives the amplified collection voltage, the suppression input end receives the suppression correction voltage, and the collection output end outputs a sampling collection voltage according to the amplified collection voltage and the suppression correction voltage.

[0011] Further, the current amplification module includes a first amplification resistor, a second amplification resistor, a collection operational amplifier, and an amplification output resistor, the first amplification resistor is coupled to one end of a collection load and a positive input end of the collection operational amplifier, the second amplification resistor is coupled to the other end of the collection load and a negative input end of the collection operational amplifier, and the amplification output resistor is coupled to an output end of the collection operational amplifier.

[0012] Further, the interference collection module includes a window reset unit and a voltage integration unit;

[0013] The window reset unit is configured with a preset collection window period, and the voltage integration unit is reset every interval of the collection window period;

[0014] The input end of the voltage integration unit receives the interference current and performs integration operation on the interference current to output an integrated voltage signal.

[0015] Further, the window reset unit includes a timing crystal oscillator, a first reset capacitor, a second reset capacitor, a first reset resistor, a second reset resistor, a first reset triode, a delay inverter group, and a controllable switch tube;

[0016] One end of the timing crystal oscillator is coupled to the base of the first reset triode, and the other end is coupled to the emitter of the first reset triode through the second reset capacitor; the second reset capacitor is connected in parallel with the second reset resistor, the first reset capacitor is coupled between the base and the emitter of the first reset triode, the first reset capacitor is coupled between the collector and the base of the first reset triode, the anode end of the delay inverter group is coupled to the second reset capacitor, the cathode end is coupled to the controlled end of the controllable switch tube, and the controllable switch tube is coupled to the voltage integration unit.

[0017] Further, the voltage integration unit includes an integration amplifier, an integration resistor, and an integration capacitor;

[0018] One end of the integral resistance is coupled to an output end of a high-pass filter, the other end is coupled to a negative input end of an integral amplifier, the integral capacitor is coupled between the negative input end and the output end of the integral amplifier, and the positive input end of the integral amplifier is grounded.

[0019] Further, the interference analysis module comprises a voltage intercepting unit, a threshold generating unit, a following judgment unit, a low limit suppressing unit, a high limit suppressing unit, and a range suppressing unit.

[0020] The voltage intercepting unit is configured to intercept the interference voltage at the previous time to generate a captured voltage.

[0021] The threshold generating unit is configured to generate a threshold voltage according to the captured voltage.

[0022] The following judgment unit receives the interference voltage at the current time, activates the high limit suppressing unit when the interference voltage is higher than the threshold voltage, activates the low limit suppressing unit when the interference voltage is lower than the threshold voltage, and activates the range suppressing unit when the interference voltage falls within the threshold voltage.

[0023] The low limit suppressing unit is configured to generate a low limit suppression voltage as the suppression correction voltage according to the interference voltage at the current time.

[0024] The high limit suppressing unit is configured to generate a high limit suppression voltage as the suppression correction voltage according to the interference voltage at the current time.

[0025] The range suppressing unit is configured to generate a range suppression voltage as the suppression correction voltage according to the interference voltage at the current time.

[0026] Further, the voltage intercepting unit comprises a delay sub-circuit and a register flip-flop, the delay sub-circuit outputs a trigger signal to the register flip-flop every sampling window period, the register flip-flop receives the interference voltage at the receiving end, and the register flip-flop outputs the captured voltage when receiving the trigger signal.

[0027] Further, the threshold generating unit comprises a subtraction sub-circuit and an addition sub-circuit, the subtraction sub-circuit is configured with a first voltage threshold, the addition sub-circuit is configured with a second voltage threshold, the subtraction sub-circuit outputs a lower threshold voltage according to the captured voltage, the lower threshold voltage is the captured voltage minus the first voltage threshold, and the addition sub-circuit outputs an upper threshold voltage according to the captured voltage, the upper threshold voltage is the captured voltage plus the second voltage threshold.

[0028] Further, the following judgment unit comprises a first follow-up comparator, a second follow-up comparator and an encoder, the negative input end of the first follow-up comparator is connected with the subtraction sub-circuit, the positive input end of the second follow-up comparator is connected with the addition sub-circuit, the positive input end of the first follow-up comparator and the interference voltage of the second follow-up comparator.

[0029] Further, the following judgment unit comprises a first follow-up comparator, a second follow-up comparator and an encoder, the negative input end of the first follow-up comparator is connected with the subtraction sub-circuit, the positive input end of the second follow-up comparator is connected with the addition sub-circuit, the positive input end of the first follow-up comparator and the interference voltage of the second follow-up comparator.

[0030] The technical effects of the present application mainly embody in the following aspects: by such design, the common-mode interference suppression effect is better than that of the traditional sampling circuit, the error caused by the sampling signal deviation due to interference is avoided to the greatest extent, and the present application is particularly suitable for the occasions where the interference scene or interference source changes, and the changing interference source can be calculated through sampling statistics, so that the common-mode suppression ratio is adjusted, and the environment is tracked dynamically to obtain accurate sampling effect. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 Prior art circuit of the high-end sampling circuit of the present application Figure 1 ;

[0032] Figure 2 Prior art circuit of the high-end sampling circuit of the present application Figure 2 ;

[0033] Figure 3 Circuit principle diagram of the current-to-voltage sampling circuit for suppressing common-mode interference

[0034] Figure 4 Circuit principle diagram of the low-limit suppression unit

[0035] Figure 5 Circuit principle diagram of the range suppression unit

[0036] Figure 6 Circuit principle diagram of the high-limit suppression unit

[0037] 100, current amplification module; 200, current transformer; 300, high-pass filter; 400, interference acquisition module; 410, window resetting unit; 420, voltage integration unit; 500, interference analysis module; 510, voltage intercepting unit; 520, threshold generating unit; 530, following judging unit; 540, low limit suppressing unit; 550, high limit suppressing unit; 560, range suppressing unit; 600, suppression executing module. DETAILED DESCRIPTION

[0038] The specific embodiments of the present application are further described in detail below with reference to the accompanying drawings, so that the technical scheme of the present application is easier to understand and master.

[0039] A current-to-voltage acquisition circuit for suppressing common-mode interference, comprising a current amplification module 100, a current transformer 200, a high-pass filter 300, an interference acquisition module 400, an interference analysis module 500, and a suppression executing module 600;

[0040] The current amplification module 100 is coupled to an acquisition load and outputs an amplified acquisition voltage;

[0041] The current amplification module 100 comprises a first amplification resistor R11, a second amplification resistor R12, a collection operational amplifier U1, and an amplification output resistor R13. The first amplification resistor R11 is coupled to one end of a collection load and the positive input terminal of the collection operational amplifier U1. The second amplification resistor R12 is coupled to the other end of the collection load and the negative input terminal of the collection operational amplifier U1. The amplification output resistor R13 is coupled to the output terminal of the collection operational amplifier. The current amplification module 100 amplifies the current passing through the collection load and outputs a collection voltage. The first amplification resistor and the second amplification resistor: symmetrically match the input path and suppress common-mode interference. Selection parameters: resistance: 10kΩ ±0.1% (high-precision metal film resistor); matching error: <0.05% (guaranteed common-mode rejection ratio); temperature coefficient: ±25ppm / ℃ (low temperature drift). The collection operational amplifier: differentially amplifies the voltage signal generated by the load current. Selection parameters: model: AD8221 or OPA2188; key parameters: common-mode rejection ratio (CMRR): ≥120dB @ 1kHz, input bias current: <1nA (low noise), bandwidth: ≥10MHz (responds to fast signals), power supply voltage: ±15V (supports a wide dynamic range). The amplification output resistor: sets the gain ratio and converts the amplified current into a voltage output. Selection parameters: resistance: 20kΩ ±0.1% (matched with R1 / R2), power: 0.25W (meets the maximum output current requirement), type: metal film resistor (low noise). Differential input suppresses common-mode interference: when the load current flows through the collection load (RL), a voltage drop (ΔV= I×RL) is generated across the RL. R1 and R2 symmetrically send the differential component of ΔV to the positive and negative input terminals of the operational amplifier. Common-mode interference (such as power supply noise) is suppressed due to the strict matching of R1 / R2. This suppression method is different from dynamic suppression and belongs to static suppression, that is, the suppression effect does not change with the interference.

[0042] The current transformer 200 is coupled to a power circuit, and the high-pass filter 300 is coupled to the current transformer 200. The high-pass filter 300 is configured as a high-pass filter circuit composed of R31\R32\R33\R34\C32 and U3 operational amplifier. Thus, the interference current can be filtered.

[0043] The interference collection module 400 is coupled to the high-pass filter 300 to receive the interference current and output the interference voltage. The interference collection module 400 comprises a window reset unit 410 and a voltage integration unit 420.

[0044] The window reset unit 410 is configured with a preset collection window period. The voltage integration unit 420 is reset every interval of the collection window period.

[0045] The window reset unit 410 comprises a timing crystal oscillator X4, a first reset capacitor C41, a second reset capacitor C42, a first reset resistor R41, a second reset resistor R42, a first reset triode Q41, a delay inverter group D41, a controllable switch tube D42;

[0046] One end of the timing crystal oscillator X4 is coupled to the base of the first reset triode Q41, and the other end is coupled to the emitter of the first reset triode Q41 through the second reset capacitor C42; the second reset capacitor C42 is connected in parallel with the second reset resistor R42, and the first reset capacitor C41 is coupled between the base and the emitter of the first reset triode Q41; the first reset capacitor C41 is coupled between the collector and the base of the first reset triode Q41, the anode end of the delay inverter group is coupled to the second reset capacitor C42, and the cathode end is coupled to the controlled end of the controllable switch tube D42; the controllable switch tube D42 is coupled to the voltage integration unit 420. By configuring the collection window period through the timing crystal oscillator X4 and corresponding electrical elements, a signal is sent to the corresponding controllable switch tube every collection window period, and the controllable switch tube is controlled to be turned on through the time delay of the delay inverter group. When the controllable switch tube is turned on, the integration capacitor is discharged to ground, and the reset action of the voltage integration unit 420 is completed. The timing crystal oscillator provides a reference clock signal to determine the collection window period, and the frequency is 16.384kHz (matching the 500ms period). It includes a cascaded CD4060 frequency divider to generate a 1-second second pulse signal, and the temperature drift is ±20ppm (high stability). The first reset capacitor crystal oscillator has a start-up capacitor to stabilize the oscillation frequency, and the capacitance value is 12pF (matching the crystal oscillator parameters). Type: NPO ceramic capacitor (low temperature coefficient) The second reset capacitor and the resistor form an RC delay circuit to control the trigger timing of the inverter, and the capacitance value is 100nF- The voltage resistance is 16V (patch ceramic capacitor). The first reset resistor limits the base current of the triode to prevent overdrive, and the resistance value is 10kΩ ±1%, and the power is 0.125W (0805 package). The first reset triode amplifies and drives the delay inverter group with the crystal oscillator signal, the model number is MMBT3904 (NPN type), and the parameters are Ic=200mA, Vceo=40V. The delay inverter group divides the clock signal and adds a delay to generate a controllable switch tube trigger signal, the model number is CD4060 (14-stage binary counter), and the delay configuration is 500ms (achieved through a frequency division chain). The controllable switch tube is turned on after receiving the trigger signal to discharge the integration capacitor, the model number is AO3400 (N-channel MOSFET), and the parameters are Vds=30V, Rds(on)=50mΩ (low conduction loss). The delay inverter group adds a delay of about 10μs to the pulse to eliminate the risk of false triggering of the switch tube. When the controllable switch tube (AO3400) is turned on, the integration capacitor is quickly discharged through a low-impedance path (Rds(on)=50mΩ). After the discharge is completed, the switch tube is turned off, and the voltage integration unit 420 enters the next collection period.

[0047] The input end of the voltage integration unit 420 receives the interference current and integrates the interference current to output an integrated voltage signal.

[0048] The voltage integration unit 420 includes an integration amplifier U4, an integration resistor R43, and an integration capacitor C43.

[0049] One end of the integration resistor C43 is coupled to the output end of the high-pass filter 300, and the other end is coupled to the negative input end of the integration amplifier. The integration capacitor is coupled between the negative input end and the output end of the integration amplifier, and the positive input end of the integration amplifier is grounded. The core function of the voltage integration unit 420 is to convert the input current signal into a linearly increasing voltage signal, which is based on the integration characteristics of the operational amplifier. The specific working process is as follows:

[0050] ‌Input current integration: The input current flows through the input integration resistor, generating a voltage drop across the resistor, forming an input voltage signal. This voltage is input through the inverting input of the operational amplifier, and the charge accumulation is completed through the integration capacitor.

[0051] ‌Output voltage generation: The charging current of the integration capacitor is maintained constant by the virtual short feature of the operational amplifier. The output voltage is proportional to the integral of the input current, and the formula is:

[0052]

[0053] The negative sign indicates that the output is inversely proportional to the input.

[0054] ‌Time constant control: The integration time constant is determined by.

[0055] R43× which directly affects the voltage slope. For example, R43=10kΩ.

[0056] When =1μF, the time constant is 10ms, and the output increases at a rate of 0.1V / ms.

[0057] Collecting operational amplifiers (OPAMP): Function: realize virtual short and virtual break, maintain the linearity of the integration current. Key parameters:

[0058] ‌Input bias current: <1nA (such as AD8605), to avoid integration errors caused by capacitor leakage current.

[0059] ‌Bandwidth: ≥10MHz (such as OPA2188), to ensure the integration accuracy of high-frequency signals.

[0060] ‌Supply voltage: ±15V, supporting a wide dynamic range output.

[0061] Integral capacitor (Cint): Function: store charge and generate output voltage. Selection requirement: capacitance: 1 μF (typical value), adjust according to integral time requirement. Type: polypropylene film capacitor (such as WIMA MKP series), low leakage current (<1 nA), high stability. Withstand voltage: ≥50 V (such as 100 V specification), prevent high voltage breakdown.3. Input resistance (Rin) Function: convert input current into voltage signal, control integral rate. Selection requirement: resistance: 10 kΩ (typical value), error ±0.1% (such as Vishay precision metal film resistor). Temperature coefficient: ≤±25 ppm / °C, reduce temperature drift influence.

[0062] The interference analysis module 500 is coupled to the interference collection module 400 to receive an interference voltage and output a suppression correction voltage; the interference analysis module 500 includes a voltage intercepting unit 510, a following judgment unit 530, a low limit suppression unit 540, a high limit suppression unit 550, and a range suppression unit 560.

[0063] The voltage intercepting unit 510 is used to intercept the interference voltage at the last moment to generate a capture voltage; the voltage intercepting unit 510 includes a delay sub-circuit and a register flip-flop, the delay sub-circuit outputs a trigger signal to the register flip-flop every interval of the collection window, the receiving end of the register flip-flop receives the interference voltage, and the register flip-flop outputs the capture voltage when receiving the trigger signal. The principle of the voltage intercepting unit 510 is to obtain the interference voltage and store it as a capture voltage in the register, then the delay sub-circuit delays, when the next interference voltage is generated, the interference voltage at the last moment is output from the register, which is specifically delayed by the 555 timing chip, the time is set to 1 second, the output of the capture voltage is completed by triggering, and then the interference voltage will trigger the reset pin to complete the zero clearing action. The register flip-flop includes an ADC0809 analog voltage converter to digital signal, and latches to the register under the clock trigger, the register flip-flop (such as CD4013) triggers the current digital signal to be stored in the D end, and is output to the Q end when the clock signal (CLK) arrives. The delay sub-circuit composed of the 555 timer is a relatively common design in the art, and details are shown in the circuit diagram part, which will not be repeated here.

[0064] The threshold generating unit 520 is configured to generate a threshold voltage according to the capture voltage; the threshold generating unit 520 comprises a subtraction sub-circuit and an addition sub-circuit, the subtraction sub-circuit is configured with a first voltage threshold, the addition sub-circuit is configured with a second voltage threshold, the subtraction sub-circuit outputs a threshold lower limit voltage according to the capture voltage, the threshold lower limit voltage is the capture voltage minus the first voltage threshold, the addition sub-circuit outputs a threshold upper limit voltage according to the capture voltage, the threshold upper limit voltage is the capture voltage plus the second voltage threshold. The threshold voltage is a range value, which is composed of the threshold upper limit voltage and the threshold lower limit voltage, the addition sub-circuit and the subtraction sub-circuit respectively realize the determination of the range value by constructing an adder and a subtractor, and the specific circuit principle is a common circuit, which will not be described here.

[0065] The following judgment unit 530 receives the interference voltage at the current moment, activates the high limit suppression unit 550 when the interference voltage is higher than the threshold voltage, activates the low limit suppression unit 540 when the interference voltage is lower than the threshold voltage, and activates the range suppression unit 560 when the interference voltage falls within the threshold voltage; the following judgment unit 530 comprises a first following comparator, a second following comparator and an encoder, the negative input end of the first following comparator is coupled with the subtraction sub-circuit, the positive input end of the second following comparator is coupled with the addition sub-circuit, and the positive input end of the first following comparator and the interference voltage of the second following comparator. The principle of the following judgment unit 530 is as follows: two comparators are used to complete the identification, if the interference voltage is greater than the upper limit, the comparator U55 outputs 1 and the comparator U56 outputs 0, if the interference voltage is less than the upper limit and greater than the lower limit, the comparator U55 outputs 1 and the comparator U56 outputs 1, if the interference voltage is less than the lower limit, the comparator U55 outputs 0 and the comparator U56 outputs 1, and the encoder outputs a signal Y1, Y2 or Y3. The low limit suppression unit 540, the high limit suppression unit 550 and the range suppression unit 560 are all calculation circuits, but different calculation logics are adopted:

[0066] The low limit suppression unit is configured to generate a low limit suppression voltage as the suppression correction voltage according to the interference voltage at the current moment; referring to Figure 4 The correction voltage calculation formula is shown in the following formula (1):

[0067]

[0068] Wherein K is the gain of the amplifier, is a preset low limit suppression reference value.

[0069] The high limit suppression unit is configured to generate a high limit suppression voltage as the suppression correction voltage according to the interference voltage at the current moment; referring to Figure 6 The correction voltage calculation formula is shown in the following formula (2):

[0070]

[0071] wherein K is an amplifier gain, is a preset upper limit suppression reference value.

[0072] The range suppression unit is configured to generate a range suppression voltage as the suppression correction voltage according to the interference voltage at the current moment. As shown in Figure 5 The correction voltage calculation formula is

[0073]

[0074] It can be known from the above scheme that if the interference voltage fluctuates downward, that is, the interference voltage is lower than the lower limit, the interference voltage can be pulled down by the above scheme, the output of the suppression correction voltage is suppressed, if the interference voltage is higher than the upper limit, the interference voltage is subtracted by the reference value and then pulled down, and if the interference voltage is relatively stable, the output of the suppression correction voltage is continuously increased, the suppression effect is improved, and the collection accuracy is ensured. Therefore, when the interference voltage changes, the collection strategy also changes, so that in the case of large environmental changes, the suppression gain is not continuously increased and falls into convergence.

[0075] The suppression execution module 600 includes a collection input end, a suppression input end, and a collection output end. The collection input end receives the amplified collection voltage, the suppression input end receives the suppression correction voltage, and the collection output end outputs a sampling collection voltage according to the amplified collection voltage and the suppression correction voltage. The suppression execution module 600 includes an adjustable impedance, a first suppression triode, a second suppression triode, a first suppression resistor, and a second suppression resistor. The base of the first suppression triode forms the collection input end, the emitter of the second suppression triode is coupled to the adjustable impedance, the controlled end of the adjustable impedance forms the suppression input end, the first suppression resistor is coupled between the base of the first suppression triode and the collector of the second suppression triode, and the second suppression resistor is coupled to the emitter of the first suppression triode, and the node formed by the coupling forms the collection output end. By adjusting the size of the adjustable impedance, the triode gain is adjusted to adjust the effect of common-mode interference suppression. Gain adjustment mechanism: a common-emitter amplification circuit is adopted, the base bias resistor (adjustable impedance) is adjusted to change the triode static working point (Q point), so as to adjust the voltage gain and optimize the common-mode rejection ratio (CMRR) to suppress the coupling of common-mode signals to the output end. Preferably, a filter capacitor (such as a 0.1 μF ceramic capacitor) is added between the base and the ground to filter out high-frequency noise. Dynamic response optimization: a buffer circuit (such as an RC network: delays the signal change rate and reduces transient interference) is connected in parallel at the collector output end.

[0076] Of course, the above are only typical examples of the present application, in addition to which the present application can have other various specific embodiments, and any technical solution formed by equivalent replacement or equivalent transformation falls within the scope of the present application.

Claims

1. A current-to-voltage conversion circuit for suppressing common-mode interference, characterized by: The current amplification module, the current transformer, the high-pass filter, the interference acquisition module, the interference analysis module and the suppression execution module; The current amplification module is coupled to the acquisition load and outputs an amplified acquisition voltage; The current transformer is coupled to the power circuit, and the high-pass filter is coupled to the current transformer; The interference acquisition module is coupled to the high-pass filter to receive the interference current and outputs an interference voltage; The interference analysis module is coupled to the interference acquisition module to receive the interference voltage and outputs a suppression correction voltage; the interference analysis module comprises a voltage intercepting unit, a threshold generating unit, a following judging unit, a low limit suppression unit, a high limit suppression unit and a range suppression unit; The suppression execution module comprises an acquisition input end, a suppression input end and an acquisition output end; the acquisition input end receives the amplified acquisition voltage, the suppression input end receives the suppression correction voltage, and the acquisition output end outputs a sampling acquisition voltage according to the amplified acquisition voltage and the suppression correction voltage; The suppression execution module comprises an adjustable impedance, a first suppression triode, a second suppression triode, a first suppression resistor and a second suppression resistor; the base of the first suppression triode forms the acquisition input end; the emitter of the second suppression triode is coupled to the adjustable impedance; the controlled end of the adjustable impedance forms the suppression input end; the first suppression resistor is coupled between the base of the first suppression triode and the collector of the second suppression triode; the second suppression resistor is coupled to the emitter of the first suppression triode, and the node formed by the coupling forms the acquisition output end.

2. A current-to-voltage sampling circuit for suppressing common mode interference as defined in claim 1, wherein: The current amplification module comprises a first amplification resistor, a second amplification resistor, an acquisition operational amplifier and an amplification output resistor; the first amplification resistor is coupled to one end of the acquisition load and the positive input end of the acquisition operational amplifier; the second amplification resistor is coupled to the other end of the acquisition load and the negative input end of the acquisition operational amplifier; and the amplification output resistor is coupled to the output end of the acquisition operational amplifier.

3. The current-to-voltage sampling circuit that suppresses common mode interference as recited in claim 1, wherein: The interference acquisition module comprises a window resetting unit and a voltage integration unit; The window resetting unit is configured with a preset acquisition window period; the voltage integration unit is reset every interval of the acquisition window period; The input end of the voltage integration unit receives the interference current and performs integration operation on the interference current to output an integrated voltage signal.

4. A current-to-voltage sampling circuit for suppressing common mode interference as defined in claim 3, wherein: The window resetting unit comprises a timing crystal oscillator, a first reset capacitor, a second reset capacitor, a first reset resistor, a second reset resistor, a first reset triode, a delay inverter group and a controllable switch tube; One end of the timing crystal oscillator is coupled to the base of the first reset triode, and the other end is coupled to the emitter of the first reset triode through the second reset capacitor; the second reset capacitor is connected in parallel with the second reset resistor; the first reset capacitor is coupled between the base and the emitter of the first reset triode; the first reset capacitor is coupled between the collector and the base of the first reset triode; the anode end of the delay inverter group is coupled to the second reset capacitor, and the cathode end is coupled to the controlled end of the controllable switch tube; The controllable switch tube is coupled to the voltage integration unit.

5. A current-to-voltage sampling circuit that suppresses common mode interference as defined in claim 3, wherein: The voltage integration unit comprises an integration amplifier, an integration resistor and an integration capacitor. One end of the integration resistor is coupled to an output end of the high-pass filter, the other end is coupled to a negative input end of the integration amplifier, the integration capacitor is coupled between the negative input end and an output end of the integration amplifier, and a positive input end of the integration amplifier is grounded.

6. The current-to-voltage acquisition circuit for suppressing common-mode interference according to claim 1, wherein: The voltage intercepting unit is configured to intercept the interference voltage at the previous time to generate a captured voltage. The threshold generating unit is configured to generate a threshold voltage according to the captured voltage. The following judgment unit receives the interference voltage at the current time, activates the high-limit suppression unit when the interference voltage is higher than the threshold voltage, activates the low-limit suppression unit when the interference voltage is lower than the threshold voltage, and activates the range suppression unit when the interference voltage falls within the threshold voltage. The low-limit suppression unit is configured to generate a low-limit suppression voltage as the suppression correction voltage according to the interference voltage at the current time. The high-limit suppression unit is configured to generate a high-limit suppression voltage as the suppression correction voltage according to the interference voltage at the current time. The range suppression unit is configured to generate a range suppression voltage as the suppression correction voltage according to the interference voltage at the current time.

7. A current-to-voltage acquisition circuit for suppressing common-mode interference as described in claim 6, characterized in that: The voltage intercepting unit comprises a delay sub-circuit and a register flip-flop, the delay sub-circuit outputs a trigger signal to the register flip-flop every sampling window period, the register flip-flop receives the interference voltage at the receiving end, and the register flip-flop outputs the captured voltage when receiving the trigger signal.

8. A current-to-voltage sampling circuit that suppresses common mode interference as defined in claim 6, wherein: The threshold generating unit comprises a subtraction sub-circuit and an addition sub-circuit, the subtraction sub-circuit is configured with a first voltage threshold, the addition sub-circuit is configured with a second voltage threshold, the subtraction sub-circuit outputs a lower threshold voltage according to the captured voltage, the lower threshold voltage is the captured voltage minus the first voltage threshold, the addition sub-circuit outputs an upper threshold voltage according to the captured voltage, and the upper threshold voltage is the captured voltage plus the second voltage threshold.

9. A current to voltage sampling circuit for suppressing common mode interference as defined in claim 8, wherein: The following judgment unit comprises a first following comparator, a second following comparator and an encoder, the negative input end of the first following comparator is coupled to the subtraction sub-circuit, the positive input end of the second following comparator is coupled to the addition sub-circuit, and the positive input end of the first following comparator and the interference voltage of the second following comparator.

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