Photomask group and overlay error measuring method

Abstract

The invention discloses a photomask group and an overlay error measurement method, and the scheme provides a photomask which can be repeatedly used for multiple times, a plurality of groups of first mark patterns can be transferred to a front layer of a wafer at one time through a first photomask in the photomask group to form a first overlay mark group, and when a second photomask in the photomask group is used, the first overlay mark group is transferred to the front layer of the wafer at one time. In each time of etching, only a certain group of mark patterns in the second photomask are transferred to the current film layer of the wafer so as to be combined with the first overlay mark group to determine the overlay error of the photoetching process, and the plurality of mark pattern groups are arranged on the second photomask, so that the second photomask can be repeatedly used for a plurality of photoetching processes of a product, and the production efficiency is improved. And the preparation cost of the semiconductor is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of integrated circuit process manufacturing, and in particular to a mask set and a method for measuring overlay errors. Background Art

[0002] In semiconductor technology, as semiconductor processes become more and more complex, the requirements for semiconductor processes are also gradually increasing. In some processes, it is necessary to perform photolithography processes on the same position in the wafer multiple times. Each photolithography process requires an overlay mark. The overlay mark is used to detect overlay errors to achieve alignment of the photolithography device, and the exposure of the photolithography process will affect the display of subsequent overlay marks. Therefore, each photolithography process requires a corresponding new set of overlay marks.

[0003] In the related art, each photolithography process corresponds to a redesigned photomask with new overlay marks, but the preparation of the photomask requires a certain amount of money, which increases the production cost of semiconductors. Summary of the Invention

[0004] The present invention provides a mask assembly, a method for measuring overlay errors, and a mask manufacturing method, which effectively reduces the manufacturing cost of semiconductors. The technical solution is as follows:

[0005] In one aspect, a mask set is provided, comprising:

[0006] a first light mask and a second light mask;

[0007] The first mask has a plurality of first mark pattern groups arranged from inside to outside, each first mark pattern group includes mark patterns located in multiple orientations, and the plurality of first mark pattern groups are used to form an overlay mark group on the front layer of the wafer;

[0008] The second mask has a plurality of second mark pattern groups arranged from the inside to the outside, each second mark pattern group includes mark patterns located in multiple orientations, and the plurality of second mark pattern groups are used to form corresponding overlay mark groups when performing different etching processes on the wafer;

[0009] The marking patterns of the first marking pattern group correspond one-to-one to the marking patterns of the second marking pattern group.

[0010] This method can transfer multiple groups of first mark patterns to the wafer at one time through the first mask in the mask group to form a first set of etching mark groups. When using the second mask in the mask group, only a certain group of mark patterns in the second mask is transferred to the current film layer of the wafer each time etching is performed, which is combined with the first set of etching mark groups to determine the overlay error of this lithography process. Since there are multiple groups of mark pattern groups on the second mask, the second mask can be reused for multiple lithography processes of the product, thereby reducing the production cost of semiconductors.

[0011] In some embodiments, the marking pattern in the first marking pattern group includes a closed or non-closed figure, and the figure is one of a straight line, a cross, a circle, an elliptical ring, an irregular ring and a polygonal ring; and / or

[0012] The marking patterns in the second marking pattern group include closed or non-closed graphics, and the graphics are one of a straight line, a cross, a circular ring, an elliptical ring, an irregular ring and a polygonal ring.

[0013] In some embodiments, the marking patterns in the first marking pattern group include at least one of numbers, letters, preset symbols, preset lines, preset regular patterns and preset irregular patterns; and / or

[0014] The marking patterns in the second marking pattern group include at least one of numbers, letters, preset symbols, preset lines, preset regular patterns and preset irregular patterns.

[0015] In some embodiments, the marking patterns in each first marking pattern group are distributed at equal intervals in multiple directions; and / or

[0016] The marking patterns in each second marking pattern group are distributed at equal intervals in multiple directions.

[0017] In some embodiments, the marking patterns in each first marking pattern group are unevenly distributed in multiple directions; and / or

[0018] The marking patterns in each second marking pattern group are unevenly distributed in multiple directions.

[0019] In some embodiments, the plurality of first marking pattern groups arranged from the inside out have marking patterns at multiple positions in each group having the same shape, and marking patterns in different groups have different shapes; and / or

[0020] The plurality of second marking pattern groups arranged from the inside to the outside, each group includes marking patterns at multiple positions with the same shape, and the marking patterns in different groups have different shapes.

[0021] In some embodiments, the plurality of first marking pattern groups are arranged from inside to outside on the first mask in any one of a square, a rectangle and a ring form; and / or

[0022] The plurality of second marking pattern groups are arranged from inside to outside on the second mask in any one of a square, a rectangle and a ring form.

[0023] In another aspect, a method for measuring overlay error is provided, the method comprising:

[0024] forming a plurality of first overlay mark groups on the front layer of the wafer using a first mask in the mask set, wherein the first mask has a plurality of first mark pattern groups arranged from inside to outside, each first mark pattern group corresponding to one of the first overlay mark groups, and each first mark pattern group includes mark patterns located at a plurality of positions;

[0025] In a photolithography process of the wafer, each time etching is performed, different exposure ranges on a second photomask in the photomask group are exposed to form a corresponding second overlay mark group on a current film layer of the wafer, the second photomask having a plurality of second mark pattern groups arranged from the inside to the outside, different second mark pattern groups corresponding to different exposure ranges, each second mark pattern group corresponding to one second overlay mark group, the overlay marks of the second overlay mark group corresponding one-to-one to the overlay marks of the first overlay mark group, and each layer etched on the wafer corresponds to one second overlay mark group among the plurality of second overlay mark groups;

[0026] An overlay error of each etching is obtained based on the first overlay mark group and the second overlay mark group.

[0027] In some embodiments, obtaining the overlay error of each etching based on the first overlay mark group and the second overlay mark group includes:

[0028] After any etching, detecting a plurality of first position coordinates of the first set of engraved marks on the wafer and a plurality of second position coordinates of the second set of engraved marks on the wafer after etching;

[0029] For the first position coordinates of the overlay mark at the target position in the first overlay mark group and the second position coordinates of the overlay mark at the target position in the second overlay mark group, the difference between the coordinates is obtained, and the overlay error of this etching is obtained based on the coordinate difference.

[0030] In some embodiments, obtaining the overlay error of each etching based on the first overlay mark group and the second overlay mark group includes:

[0031] After any etching, detecting a plurality of first position coordinates of the first set of engraved marks on the wafer and a plurality of second position coordinates of the second set of engraved marks on the wafer after etching;

[0032] For the first position coordinates of the overlay mark of the target pattern in the first overlay mark group and the second position coordinates of the overlay mark of the target pattern in the second overlay mark group, the difference between the coordinates is obtained, and the overlay error of this etching is obtained based on the coordinate difference. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 is a schematic diagram of a photomask set provided by one or more exemplary embodiments of the present application;

[0035] Figure 2 is a flow chart of a method for using a photomask provided by one or more exemplary embodiments of the present application;

[0036] Figure 3 is a schematic cross-sectional view of a wafer on which a sacrificial material is deposited, provided by one or more exemplary embodiments of the present application;

[0037] Figure 4 is a schematic diagram of an exposure range in a second photomask provided by one or more exemplary embodiments of the present application;

[0038] Figure 5 is a schematic diagram of an exposure range in a second photomask provided by one or more exemplary embodiments of the present application;

[0039] Figure 6 FIG. 4 is a graph showing the relationship between the number of times the second photomask is reused and the available area of ​​the device structure pattern according to one or more exemplary embodiments of the present application. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0041] In an embodiment of the present application, a mask set is provided, which includes a first mask and a second mask. Figure 1 , Figure 1(A) in the figure shows the structure of the first mask in the mask group, which has a plurality of first mark pattern groups 101 to 103 arranged from the inside to the outside, each first mark pattern group includes mark patterns located in multiple orientations, and the plurality of first mark pattern groups are used to form an overlay mark group on the front layer of the wafer.

[0042] The second mask has multiple second mark pattern groups 109 to 111 arranged from the inside to the outside, each second mark pattern group includes mark patterns located in multiple directions, and the multiple second mark pattern groups are used to form corresponding overlay mark groups when performing different etching processes on the wafer; wherein, the mark patterns of the first mark pattern group correspond one-to-one to the mark patterns of the second mark pattern group.

[0043] Among them, the first mask includes a central area 100 for forming a device structure on the front layer of the wafer and an identification design area other than the central area 100, and the identification design area includes the above-mentioned multiple first marking pattern groups. The device structure formed by the central area 100 includes the device structure of the semiconductor device, such as the source, drain and capacitor, etc. The multiple first marking pattern groups include first marking pattern groups 101 to 103. It should be noted that the number of marking pattern groups shown in the figure is only an example. The number of the first marking pattern groups can be more and can be designed according to the number of times the mask group is reused, that is, it can be designed according to the photolithography process of the product, etc. The embodiment of the present application does not limit this. Among them, Figure 1 As shown in Figure (A), each first mark pattern group includes first mark patterns located in multiple orientations. The figure only takes the example of each first mark pattern group including mark patterns located in four orientations, wherein, taking the first mark pattern group 101 as an example, it includes mark patterns 101A to 101D. The first photomask is used to form overlay marks on the front layer of the wafer. That is, the first photomask is used to form multiple first overlay mark groups corresponding to the multiple first mark pattern groups on the wafer through a single etching process based on the multiple first mark pattern groups on the first photomask. That is, each overlay mark located on the front layer of the wafer corresponding to each mark pattern in the multiple first mark pattern groups is formed.

[0044] Figure 1(B) in the figure shows the structure of the second mask in the mask set. The second mask includes a central region 108 for forming device structures on film layers other than the front layer of the wafer, and a mark design region outside the central region 108. The mark design region includes multiple second mark pattern groups. The device structures formed in the central region 108 include semiconductor device structures, such as source, drain, and capacitor. The multiple second mark pattern groups include second mark pattern groups 109 to 111. The second mark pattern group 109 in the second mask corresponds to the first mark pattern group 101 in the first mask, the second mark pattern group 110 corresponds to the first mark pattern group 102, and the second mark pattern group 111 corresponds to the first mark pattern group 103. Each second mark pattern group on the second mask includes mark patterns in multiple directions. In this embodiment of the application, each second mark pattern group includes mark patterns in four directions as an example. Taking the second mark pattern group 109 as an example, it includes mark patterns 109A to 109D.

[0045] In the embodiment of the present application, there is no limit on the number of marking patterns located in multiple directions included in each marking pattern group on the first mask and the second mask, and there is no limit on the number of directions of the multiple directions included in each marking pattern group.

[0046] The above-mentioned mask group, since the first mask includes multiple first mark pattern groups corresponding to multiple second mark pattern groups on the second mask, after exposure using the first mask, multiple groups of first mark patterns can be transferred to the wafer at one time to form a first set of engraved mark groups. When using the second mask, only a certain group of mark patterns in the second mask can be transferred to the currently etched film layer of the wafer at a time, which can be combined with the first set of engraved mark groups to determine the overlay error of this photolithography process. Since there are multiple groups of mark pattern groups on the second mask, it can be repeatedly used for multiple photolithography processes of the product, thereby reducing the preparation cost of the semiconductor.

[0047] In some embodiments, the marking patterns in the first marking pattern group include closed or non-closed figures, and the figures are one of a straight line, a cross, a circular ring, an elliptical ring, an irregular ring and a polygonal ring; and / or, the marking patterns in the second marking pattern group include closed or non-closed figures, and the figures are one of a straight line, a cross, a circular ring, an elliptical ring, an irregular ring and a polygonal ring.

[0048] It should be noted that the marking patterns in the first marking pattern group can be any of the aforementioned patterns. These patterns can be formed on the mask during the mask preparation process, and their dimensions are adapted to the accuracy of overlay measurement. These patterns have a center or vertex to facilitate determining their position. The second marking pattern group is similar to the first marking pattern group and will not be further described here. Optionally, the dimensions of the patterns in the first marking pattern group are larger than those in the second marking pattern group.

[0049] Furthermore, the first and second marking pattern groups may include different graphics. For example, the graphics in the first marking pattern group may all be crosses, while the graphics in the second marking pattern group may all be rings. Furthermore, for multiple second marking pattern groups, the graphics in each second marking pattern group may be the same or different. For example, the graphics in the inner second marking pattern group may be crosses, while the graphics in the outer second marking pattern group may be rings.

[0050] In some embodiments, the marking patterns in the first marking pattern group include at least one of numbers, letters, preset symbols, preset lines, preset regular graphics, and preset irregular graphics; and / or, the marking patterns in the second marking pattern group include at least one of numbers, letters, preset symbols, preset lines, preset regular graphics, and preset irregular graphics.

[0051] It should be noted that the marking patterns in the first marking pattern group can be any of the types described above. These marking patterns can be formed on the mask during the mask preparation process, and their dimensions are adapted to the accuracy of overlay measurement. A vertex, a portion of the marking pattern, or a line, such as a number, letter, or symbol, can be used to determine the position of the marking pattern. The second marking pattern group is similar to the first marking pattern group and will not be further described here. Optionally, the marking patterns in the first marking pattern group are larger in size than those in the second marking pattern group.

[0052] In addition, the marking patterns included in the first and second marking pattern groups can be different. For example, the marking patterns in the first marking pattern group are all numbers, while the marking patterns in the second marking pattern group are all letters. Furthermore, for multiple second marking pattern groups, the patterns in each second marking pattern group can be the same or different. For example, the marking patterns in the inner second marking pattern group are symbols, while the marking patterns in the outer second marking pattern group are letters.

[0053] In some embodiments, the marking patterns in each first marking pattern group are equally spaced across multiple orientations; and / or the marking patterns in each second marking pattern group are equally spaced across multiple orientations. By equally spaced across multiple orientations, overlay error can be measured uniformly across all orientations, thereby obtaining a more accurate overlay error.

[0054] Optionally, the corresponding first marking pattern group and the second marking pattern group contain the same number of marking patterns, corresponding positions, and the spacing between two adjacent marking patterns in the same group is equal. The spacing may refer to the straight-line distance between the center points of the two marking patterns.

[0055] The same quantity and corresponding position means that the corresponding first marking pattern group and second marking pattern group include multiple pairs of marking patterns located in the same orientation. For example, the first marking pattern group includes four marking patterns located in four orientations respectively, and its corresponding second marking pattern group also includes four marking patterns located in the four orientations.

[0056] In some embodiments, the marking patterns in each first marking pattern group are unevenly distributed in multiple directions; and / or the marking patterns in each second marking pattern group are unevenly distributed in multiple directions.

[0057] Optionally, the corresponding first and second marking pattern groups contain the same number of marking patterns and corresponding positions, and the spacing between two adjacent marking patterns in the same group may be unequal. The spacing may refer to the straight-line distance between the center points of the two marking patterns. For example, for the four marking patterns in the first marking pattern group, the distance between the upper marking pattern and the marking patterns on its left and right sides is referred to as the first distance, and the distance between the lower marking pattern and the marking patterns on its left and right sides is referred to as the second distance, and the first distance is not equal to the second distance.

[0058] It should be noted that the position of the marking pattern can be determined based on design requirements, for example, based on the device structure pattern of the product, to ensure accurate measurement of the overlay error with maximum space utilization, thereby achieving calibration.

[0059] In some embodiments, the multiple first marking pattern groups arranged from the inside to the outside, each group includes marking patterns located at multiple positions with the same shape, and the shapes of marking patterns between different groups are different; and / or, the multiple second marking pattern groups arranged from the inside to the outside, each group includes marking patterns located at multiple positions with the same shape, and the shapes of marking patterns between different groups are different.

[0060] For the ease of detection, the marking patterns within the first marking pattern group can be designed as multiple identical marking patterns. For example, all marking patterns within a first marking pattern group are cross-shaped. Alternatively, for the ease of distinction, the first marking pattern group can be designed as multiple different marking patterns. For example, for the marking patterns located in the four directions of up, down, left, and right, each marking pattern is in the shape of an arrow indicating the corresponding direction. For the marking patterns within the second marking pattern group, for the ease of detection, they can be designed as multiple identical marking patterns. For example, all marking patterns within a second marking pattern group are cross-shaped. Alternatively, for the ease of distinction, the second marking pattern group can be designed as multiple different marking patterns. For example, for the marking patterns located in the four directions of up, down, left, and right, each marking pattern is in the shape of an arrow indicating the corresponding direction.

[0061] Of course, for the first marking pattern group and the second marking pattern group, the two types of marking pattern groups can use the same marking pattern within the group, or can use different marking patterns within the group, and the embodiment of the present application does not limit this.

[0062] In some embodiments, the multiple first marking pattern groups are arranged from the inside to the outside on the first mask in any form of a square, a rectangle and a ring; and / or, the multiple second marking pattern groups are arranged from the inside to the outside on the second mask in any form of a square, a rectangle and a ring.

[0063] Among them, for each first marking pattern group, the marking patterns included in the group can be arranged into any form of the above-mentioned square, rectangle and ring; for each second marking pattern group, the marking patterns included in the group can be arranged into any form of the above-mentioned square, rectangle and ring.

[0064] Optionally, the corresponding first and second marking pattern groups may be arranged in the same manner. Of course, their arrangements may also be different. For example, the marking patterns in the first marking pattern group may be arranged in a square manner, while the marking patterns in the corresponding second marking pattern group may be arranged in a rectangular manner. Of course, the arrangements of the first and second marking pattern groups may be the same or different. For example, the first and second marking pattern groups may both be arranged in a square manner.

[0065] It should be noted that the first mark pattern group and the second mark pattern group corresponding to the above-mentioned first mask and the second mask refer to the first mark pattern group and the second mark pattern group used for overlay error detection. For example, the first mask includes three first mark pattern groups arranged from the inside to the outside, and the second mask includes three second mark pattern groups arranged from the inside to the outside, wherein the first mark pattern group located in the innermost layer and the second mark pattern group located in the innermost layer are the corresponding first mark pattern group and the second mark pattern group, the first mark pattern group located in the middle layer and the second mark pattern group located in the middle layer are the corresponding first mark pattern group and the second mark pattern group, the first mark pattern group located in the outermost layer and the second mark pattern group located in the outermost layer are the corresponding first mark pattern group and the second mark pattern group, and other structures can be deduced by analogy.

[0066] Combined with the above introduction to the mask group, Figure 2 This is a flow chart of a method for using a photomask provided by an exemplary embodiment of the present application. Figure 2 As shown, the method includes the following steps.

[0067] Step 201 , uniformly coating a layer of photoresist on the wafer, placing the wafer coated with the photoresist on a silicon wafer workbench, and aligning the lens group, the first mask or the second mask in the mask group, and the silicon wafer workbench.

[0068] Among them, photoresist is a photosensitive material. Its solubility will change after being irradiated or radiated by ultraviolet light, electron beam, ion beam, X-ray and other light. Therefore, the photoresist evenly coated on the wafer will dissolve the irradiated part after laser irradiation, and the dissolved photoresist will be removed. The remaining unirradiated photoresist forms a pattern on the wafer, and in the subsequent etching process of the wafer, it acts as a protective layer of the wafer to protect the part covered by the photoresist from being etched, thereby transferring the pattern to the wafer.

[0069] Among them, the lens group is the lens group of the photolithography machine, which is used to focus the laser emitted by the photolithography machine on the wafer, focusing it into a point on the wafer, thereby ensuring that the laser is irradiated on the wafer with the highest intensity.

[0070] Among them, the silicon wafer workbench is a workbench for placing wafers, which can control the position of the wafer, thereby enabling the photolithography machine to accurately irradiate the wafer.

[0071] In some embodiments, before exposure, the lens group, mask group and silicon wafer workbench need to be aligned to ensure that the laser can pass through the lens group and mask group, and focus the pattern in the mask group on the wafer on the silicon wafer workbench, thereby realizing the photolithography process.

[0072] In step 202, a plurality of first set mark groups are formed on the front layer of the wafer through the first mask in the mask group, and the first mask has a plurality of first mark pattern groups arranged from the inside to the outside, each first mark pattern group corresponds to a first set mark group, and each first mark pattern group includes mark patterns located in multiple orientations.

[0073] Each first marking pattern group includes a plurality of marking patterns in different directions. The plurality of marking patterns are located around the central area of ​​the first mask in a surrounding manner, and the plurality of first marking pattern groups are in a nested relationship.

[0074] In some embodiments, the laser emitted by the photolithography machine is controlled to pass through the first mask to transfer the marking patterns of the multiple first marking pattern groups on the first mask to the wafer to form multiple first set marking groups on the front layer of the wafer. The multiple first set marking groups formed on the wafer serve as alignment marks and are used as alignment references for the reused second mask in subsequent exposure operations.

[0075] Combined with reference Figure 1 , Figure 1 FIG (A) shows the structure of the first mask and a plurality of first marking pattern groups on the first mask. In FIG (A), the marking patterns in each first marking pattern group have the same shape and are all square.

[0076] Step 203 : depositing a sacrificial material on the wafer and performing a CMP process on the wafer to planarize the wafer surface.

[0077] During the alignment process, the overlay marks are measured through image recognition. This involves capturing the overlay marks on the wafer for image recognition. Therefore, to ensure recognition, the sacrificial material must have a high light transmittance so that the image capture device can capture the overlay marks on the wafer. Furthermore, the sacrificial material must ensure that the overlay mark group is not damaged by subsequent etching processes. A sufficiently smooth surface after CMP polishing can also eliminate bubbles on the surface of the sacrificial material, thereby preventing bubbles from refracting and reflecting laser light during the photolithography process, which would reduce pattern resolution and further ensure the accuracy of subsequent alignment.

[0078] refer to Figure 3 , Figure 3 This is a schematic cross-sectional view of a wafer after sacrificial material is deposited and polished, provided in one or more exemplary embodiments of the present application. As shown in the figure, an overlay mark 301 has been formed on the wafer 300, and a sacrificial material 302 is contained within the overlay mark 301.

[0079] Step 204, in the photolithography process of the wafer, each time etching is performed, the exposure range corresponding to the different second mark pattern groups on the second mask in the mask group is exposed to form different second set engraving mark groups on the current film layer of the wafer, and the second mask has multiple second mark pattern groups arranged from the inside to the outside, and each second mark pattern group corresponds to a second set engraving mark group.

[0080] The current film layer refers to the film layer corresponding to the current photolithography process. In some embodiments, the laser of the photolithography machine can illuminate different areas of the second mask, and each illumination selects only one area, which is the exposure range of the second mask. Different exposure ranges correspond to different second mark pattern groups, thereby forming a respective second set of engraved marks on the film layer corresponding to each photolithography process. The process of forming the second set of engraved marks includes the following steps 204A-204C:

[0081] 204A: The exposure range includes a first exposure range and a second exposure range, and the first exposure range is nested in the second exposure range.

[0082] The first exposure range and the second exposure range are any two exposure ranges in the second mask, that is, the second mask includes two or more second mark pattern groups corresponding to two or more exposure ranges.

[0083] Among them, when performing the photolithography process, the selection of different exposure ranges should be from small range to large range, referring to Figure 4 , Figure 4 This is a schematic diagram of the exposure range in the second mask provided by one or more exemplary embodiments of the present application. As shown in the figure, the exposure range includes a first exposure range 400 and a second exposure range 401, and the first exposure range 400 is nested in the second exposure range 401.

[0084] In a semiconductor process in which a wafer is etched multiple times, the device needs to be aligned for each etching. During the alignment, the overlay mark is used as the alignment mark. That is, each etching needs to form a new set of overlay marks based on the existing multiple first overlay mark groups on the wafer. In current technology, a mask needs to be replaced for each etching. In an embodiment of the present application, a second mask is provided. The second mask can be used for multiple exposure ranges, and different exposure ranges have second mark pattern groups. When the wafer is subjected to the photolithography process again, the exposure range different from the last photolithography process is exposed. Each exposure can transfer a second mark pattern group of the second mask to the currently etched film layer on the wafer to form a second overlay mark group. Since different etching processes can expose different exposure ranges, the second mask can be reused.

[0085] 204B: Exposing the first exposure range on the second mask in the mask set to form a second set of engraved marks on the wafer corresponding to the first exposure range.

[0086] In some embodiments, when performing any etching using a second photomask, the photolithography machine exposes a first exposure range on the second photomask, transfers the second mark pattern group within the first exposure range to the wafer, and forms a second overlay mark group corresponding to the first exposure range, which is used to obtain an overlay error by combining the position of the first overlay mark group corresponding to the current etching among the multiple first overlay mark groups already on the wafer. The first exposure range is the exposure range corresponding to the current etching.

[0087] 204C: Exposing a second exposure range on a second mask in the mask set to form a second set of engraved marks on the wafer corresponding to the second exposure range.

[0088] In some embodiments, when the second mask is used for the second time, the photolithography machine exposes the second exposure range on the second mask, transfers the second mark pattern group in the second exposure range to the wafer, and forms a second set of engraved marks corresponding to the second exposure range.

[0089] In some embodiments, the exposure range may be multiple, and the number of the exposure ranges corresponds to the number of times the second mask is used. Each use exposes a different exposure range, forming a different second set of engraved marks on the current film layer of the wafer. Figure 5 , Figure 5 This is a schematic diagram of the exposure range in the second mask provided by one or more exemplary embodiments of the present application. As shown in the figure, there are three exposure ranges, including a first exposure range 500, a second exposure range 501 and a third exposure range 502, so the second mask can be used three times.

[0090] Step 205 : Obtaining an overlay error for each etching based on the first overlay mark group and the second overlay mark group obtained in each etching.

[0091] In some embodiments, after any etching, multiple first position coordinates of the first overlay mark group on the wafer and multiple second position coordinates of the second overlay mark group on the wafer after etching are detected; for the first position coordinates of the overlay mark on the target position in the first overlay mark group and the second position coordinates of the overlay mark on the target position in the second overlay mark group, the difference between the coordinates is obtained, and based on the coordinate difference, the overlay error of this etching is obtained.

[0092] In the above process, after any etching, the deviation between the position coordinates of the center point of the overlay mark at the target position in the first overlay mark group and the position coordinates of the center point of the overlay mark at the target position in the second overlay mark group on the current film layer is calculated. The deviation includes direction and distance, and the distance is the overlay error. Optionally, the corresponding mark patterns originally have a certain deviation between the design positions on the mask (such as the center positions of the mark patterns). If the mark patterns are transferred to the wafer, the deviation between the overlay marks formed therefrom changes relative to the original deviation between the mark patterns. For example, the deviation becomes larger or smaller, indicating that there may be an error in alignment. Therefore, based on the offset between the measured deviation and the original deviation, based on the overlay error, the positions of the lithography machine, the mask group, the silicon wafer workbench, etc. can be adjusted to achieve alignment between the multiple devices, thereby achieving precise etching.

[0093] Of course, for each overlay mark group, it includes multiple overlay marks, that is, the above measurement can be the measurement of the position coordinates of all overlay marks in the overlay mark group. After obtaining the overlay error between each overlay mark in the first overlay mark group and the overlay mark at the corresponding position in the second overlay mark group, the average value can be calculated based on the multiple overlay errors to obtain the overlay error of this etching, so as to ensure the accuracy of the overlay error and further ensure the accuracy of the alignment.

[0094] In addition, an embodiment of the present application provides a method for preparing a photomask, comprising: determining the number of mark pattern groups, a mark design area, and a plurality of exposure ranges from the inside to the outside in the mark design area based on the device structure of the product and the photolithography process of the product, wherein the mark design area indicates the position of the mark pattern group on the photomask; determining design parameters of a plurality of first mark pattern groups based on the pattern of the product, the mark design area, and the number of mark pattern groups, and determining design parameters of a plurality of second mark pattern groups based on the number of mark pattern groups and the plurality of exposure ranges; determining design parameters of a plurality of first mark pattern groups based on the pattern of the product, the design parameters of the plurality of first mark pattern groups, and the design parameters of the plurality of second mark pattern groups based on the pattern of the product, the design parameters of the plurality of first mark pattern groups, and the design parameters of the plurality of second mark pattern groups Parameters, prepare the first mask and the second mask in the mask group; wherein, the first mask has a plurality of first mark pattern groups arranged from the inside to the outside, each first mark pattern group includes mark patterns located at a plurality of orientations, and the plurality of first mark pattern groups are used to form an overlay mark group on the front layer of the wafer; the second mask has a plurality of second mark pattern groups arranged from the inside to the outside, each second mark pattern group includes mark patterns located at a plurality of orientations, and the plurality of second mark pattern groups are used to form corresponding overlay mark groups when performing different etching processes on the wafer; the mark patterns of the first mark pattern group correspond one to one to the mark patterns of the second mark pattern group.

[0095] Among them, the design parameters include the number of times the mask is reused, the overlay mark size, the graphic blocking distance, the cutting path width, and the available area of ​​the device structure pattern, wherein the overlay mark size (that is, the mark pattern on the mask) represents the length and width of the overlay mark in the overlay mark group, the graphic blocking distance represents the distance between adjacent mark patterns between different second mark pattern groups, and is used to prevent the scattered light formed when each mark pattern is exposed from irradiating the adjacent mark pattern, thereby affecting the subsequent exposure of the adjacent second mark pattern, the cutting path width represents the distance between chips, and the area of ​​the device structure pattern represents the area of ​​the central area on the mask, that is, the area of ​​the pattern used to form the device structure. Of course, the design parameters can also include other types of parameters.

[0096] The product pattern refers to the device structure pattern. The device structure pattern should be designed on the mask to form the corresponding device structure on the wafer. For the first and second masks, it is necessary to consider not only the area of ​​the device structure pattern, but also the area on the mask where the marking pattern for forming the overlay mark should be designed, that is, the mark design area. Figure 6 , Figure 6 This is a relationship diagram between the number of times the second mask is reused and the available area of ​​the device structure pattern provided by one or more exemplary embodiments of the present application. As shown in the figure, as the number of times the mask is reused increases, the available area of ​​the device structure pattern gradually decreases.

[0097] For a product, the specific lithography process determines the number of times the mask can be reused, that is, the number of mark pattern groups that need to be designed. For example, if the product's lithography process requires N etching steps, the mask needs to be reused N times. Accordingly, at least N mark pattern groups can be designed on the first and second masks, respectively. During the first etching step, the N first mark pattern groups from the first mask can be transferred to the wafer, serving as a reference for alignment in subsequent etching steps.

[0098] Accordingly, after the pattern of the product, the mark design area, and the number of mark pattern groups are determined, the design positions of the mark patterns in the multiple first mark pattern groups can be determined based on the above information. The distance between each exposure range can be determined based on the photolithography process, that is, the distance between each mark pattern group can also be determined based on the photolithography process. Among them, the distance can be a preset distance, and can also be adjusted based on preparation requirements. For example, still taking the above-mentioned N etching processes as an example, after calculation, it is determined that the mask cannot accommodate the mark pattern groups corresponding to all etching processes, then the distance between the two mark pattern groups can be designed to be less than the value of the above-mentioned preset distance, so that more mark pattern groups can be accommodated on the mask. Of course, the above design must meet the preparation requirements of the product.

[0099] In addition, the form of the marking pattern can be, for example, a graphic or a character, etc. The specific form of the marking pattern, the number of marking patterns in the first marking pattern group and the second marking pattern group, and the corresponding marking pattern size (that is, the overlay mark size, etc.) can also be determined according to the detection requirements of the overlay error, and the embodiments of the present application do not limit this.

[0100] After determining the number of the first marking pattern group and the second marking pattern group, the number of marking patterns in each marking pattern group, and the position of each marking pattern on the mask, the specific structure of the mask can be determined based on the various types of information determined to prepare the mask.

[0101] For example, the design parameters of the second mask are shown in Table 1 below.

[0102] Table 1

[0103]

[0104]

[0105] In some embodiments, since not only the device structure pattern needs to be designed on the second mask, but a mark design area also needs to be reserved for designing the second mark pattern group, the sizes of the areas used to design these two types of patterns affect each other. The number of second mark pattern groups on the second mask corresponds to the number of times the second mask is reused. If you want to design the second mask to be reused more times, you need to design more groups of second mark pattern groups on the second mask, and the smaller the available area of ​​the device structure pattern. It can be seen from the calculated data in Table 1 above that if the second mask is designed to be reused 32 times, the available area of ​​the device structure pattern on the mask is -3.9595, that is, the second mask can be designed to be reused up to 31 times.

[0106] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" refers to one or more, and the term "plurality" refers to two or more, unless otherwise clearly defined.

[0107] In this application, the term "and / or" simply describes an association between related objects, indicating that three possible relationships exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0108] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A mask set, characterized in that: The mask set includes: a first light mask and a second light mask; The first mask has a plurality of first mark pattern groups arranged from inside to outside, each first mark pattern group includes mark patterns located in multiple orientations, and the plurality of first mark pattern groups are used to form an overlay mark group on the front layer of the wafer; The second mask has a plurality of second mark pattern groups arranged from the inside to the outside, each second mark pattern group includes mark patterns located in multiple orientations, and the plurality of second mark pattern groups are used to form corresponding overlay mark groups when performing different etching processes on the wafer; The marking patterns of the first marking pattern group correspond one-to-one to the marking patterns of the second marking pattern group.

2. The mask assembly according to claim 1, wherein: The marking patterns in the first marking pattern group include closed or non-closed graphics, and the graphics are one of a straight line, a cross, a circle, an elliptical ring, an irregular ring and a polygonal ring; and / or The marking patterns in the second marking pattern group include closed or non-closed graphics, and the graphics are one of a straight line, a cross, a circular ring, an elliptical ring, an irregular ring and a polygonal ring.

3. The mask assembly according to claim 1, wherein: The marking patterns in the first marking pattern group include at least one of numbers, letters, preset symbols, preset lines, preset regular patterns and preset irregular patterns; and / or The marking patterns in the second marking pattern group include at least one of numbers, letters, preset symbols, preset lines, preset regular patterns and preset irregular patterns.

4. The mask assembly according to claim 1, wherein: The marking patterns in each first marking pattern group are distributed at equal intervals in multiple directions; and / or The marking patterns in each second marking pattern group are distributed at equal intervals in multiple directions.

5. The mask assembly according to claim 1, wherein: The marking patterns in each first marking pattern group are unevenly distributed in multiple directions; and / or The marking patterns in each second marking pattern group are unevenly distributed in multiple directions.

6. The mask assembly according to claim 1, wherein: The plurality of first marking pattern groups arranged from the inside out, each group includes marking patterns at multiple positions having the same shape, and marking patterns in different groups have different shapes; and / or The plurality of second marking pattern groups arranged from the inside to the outside, each group includes marking patterns at multiple positions with the same shape, and the marking patterns in different groups have different shapes.

7. The mask assembly according to claim 1, wherein: The plurality of first marking pattern groups are arranged from inside to outside on the first mask in any one of a square, a rectangle and a ring form; and / or The plurality of second marking pattern groups are arranged from inside to outside on the second mask in any one of a square, a rectangle and a ring form.

8. A method for measuring overlay error, characterized in that: The method comprises: forming a plurality of first overlay mark groups on the front layer of the wafer using a first mask in the mask set, wherein the first mask has a plurality of first mark pattern groups arranged from inside to outside, each first mark pattern group corresponding to one of the first overlay mark groups, and each first mark pattern group includes mark patterns located at a plurality of positions; In a photolithography process of the wafer, each time etching is performed, different exposure ranges on a second photomask in the photomask group are exposed to form a corresponding second overlay mark group on a current film layer of the wafer, the second photomask having a plurality of second mark pattern groups arranged from the inside to the outside, different second mark pattern groups corresponding to different exposure ranges, each second mark pattern group corresponding to one second overlay mark group, the overlay marks of the second overlay mark group corresponding one-to-one to the overlay marks of the first overlay mark group, and each layer etched on the wafer corresponds to one second overlay mark group among the plurality of second overlay mark groups; An overlay error of each etching is obtained based on the first overlay mark group and the second overlay mark group.

9. The method according to claim 8, characterized in that The obtaining of an overlay error of each etching based on the first overlay mark group and the second overlay mark group includes: After any etching, detecting a plurality of first position coordinates of the first set of engraved marks on the wafer and a plurality of second position coordinates of the second set of engraved marks on the wafer after etching; For the first position coordinates of the overlay mark at the target position in the first overlay mark group and the second position coordinates of the overlay mark at the target position in the second overlay mark group, the difference between the coordinates is obtained, and the overlay error of this etching is obtained based on the coordinate difference.

10. The method according to claim 8, characterized in that The obtaining of an overlay error of each etching based on the first overlay mark group and the second overlay mark group includes: After any etching, detecting a plurality of first position coordinates of the first set of engraved marks on the wafer and a plurality of second position coordinates of the second set of engraved marks on the wafer after etching; For the first position coordinates of the overlay mark of the target pattern in the first overlay mark group and the second position coordinates of the overlay mark of the target pattern in the second overlay mark group, the difference between the coordinates is obtained, and the overlay error of this etching is obtained based on the coordinate difference.

Images