Low-end ideal diode controlled by fast rear-end auxiliary tube based on NMOS (N-channel Metal Oxide Semiconductor) tube

Abstract

The invention discloses a fast rear-end auxiliary tube control low-end ideal diode based on an NMOS (N-channel Metal Oxide Semiconductor) tube, which relates to the technical field of power diodes and comprises a power supply VCC, an NMOS main tube V1, a comparator circuit, a bias power supply and a driving circuit, the comparator circuit comprises two independent auxiliary tubes or pair tubes and a resistor; the comparator circuit is used for comparing voltages at two ends of a source electrode and a drain electrode of the NMOS main tube V1, and a comparison signal of the comparator circuit transmits an amplification signal to a grid electrode of the NMOS main tube V1 through the driving circuit to control the conduction and cut-off of the NMOS main tube V1; and a current bleeder resistor R3 is also connected between the grid electrode and the source electrode of the NMOS main tube V1. Compared with the prior art, the fast type rear-end auxiliary tube control low-end ideal diode based on the NMOS tube has the advantages that backward flowing can be prevented, and a pre-stage circuit can be protected.

Description

Technical Field

[0001] The present invention relates to the technical field of power diodes, and in particular to a low-end ideal diode controlled by a fast-type back-end auxiliary tube based on an NMOS tube. Background Art

[0002] Due to its unidirectional conduction characteristics, the diode has a relatively high reverse voltage resistance and a very small reverse current, and has an excellent backflow prevention function. The Schottky diode has a small voltage drop on the power supply connected in series, has a relatively low reverse voltage resistance, a large reverse current, and a weak backflow prevention function. Using a MOS tube as an ideal diode has a relatively small voltage drop and a low impedance characteristic, but has a low reverse voltage resistance. The ideal diode implementation schemes that are most similar to the present invention are as follows, but they all have certain shortcomings.

[0003] NMOS transistors use electrons as "majority carriers," and electrons have higher mobility than holes, the "majority carriers" of PMOS transistors. At the same physical density, NMOS transistors have higher transconductance and lower on-resistance than PMOS transistors. The on-resistance of NMOS transistors is generally 1 / 3 to 1 / 2 that of PMOS transistors of the same size. For the same on-resistance, NMOS transistors generally require less silicon wafers, resulting in lower gate capacitance and threshold voltage than PMOS transistors. However, due to the higher on-resistance of PMOS transistors, their higher price, slower speed, and limited replacement options, NMOS transistors are still commonly used in low-end switch drivers.

[0004] It is precisely because of the excellent performance of NMOS tubes that NMOS tubes are still mostly used in high current situations. Therefore, low-end ideal diodes based on NMOS tubes as main tubes are very common. The specific schemes are NMOS main tube + NPN pair tubes (auxiliary tubes) or NMOS main tube + NMOS pair tubes (auxiliary tubes). The schematic diagrams of these technical schemes are as follows: Figure 1 、 Figure 2 shown.

[0005] NMOS main tube + NPN pair tube (auxiliary tube) technical solution: Figure 1 As shown, the circuit consists of an NMOS main transistor and two NPN auxiliary transistors. An additional auxiliary bias power supply VBIAS is required (the load power supply VCC can be used directly for biasing). Using two NPN transistors with the same parameters can ensure that the parameters of the two NPN transistors are basically equal. Preferably, a pair of NPN transistors packaged together can ensure that the parameters of the two NPN transistors are almost equal, thus ensuring proper switching and anti-backflow functions. The disadvantage is that the bias resistor of the NPN pair of transistors is in the kiloohm range, and the static operating current consumption is at least in the milliampere range, which is a large current loss.

[0006] The NMOS main tube + NPN pair tube (auxiliary tube) technical solution better realizes the low-end ideal diode function, controlling the conduction and cutoff of the NMOS main tube V1: when the load low-end potential VD is not less than the negative electrode of the power supply GND, the NMOS main tube V1 is turned on; otherwise, the NMOS main tube V1 is cut off, preventing the current of the negative electrode of the power supply GND from flowing back to the low-end potential VD of the load, protecting the input power circuit, which is equivalent to a low-end ideal diode. In order to save costs, the bias power supply VBIAS is generally omitted, that is, VBIAS is connected to the power supply VCC.

[0007] NMOS main tube + NMOS pair tube (auxiliary tube) technical solution: Figure 2 As shown, the circuit consists of an NMOS main tube + two NMOS auxiliary tubes. An additional auxiliary bias power supply, VBIAS, is also required (the load power supply VCC can be used for direct biasing). Using two NMOS tubes with the same parameters can ensure that the parameters of the two NMOS tubes are basically equal. Preferably, an NMOS pair of tubes packaged together can ensure that the parameters of the two NMOS tubes are almost equal, thus ensuring proper switching and anti-backflow functions. The bias resistance of the NMOS pair of tubes is in the megohm level, and the static operating current consumption is in the microampere level. The current consumption is much lower than the technical solution of the NMOS main tube + NPN pair of tubes (auxiliary tubes). The disadvantage is that an additional auxiliary power supply is required.

[0008] Similarly, the NMOS main tube + NMOS pair solution also effectively implements the low-end ideal diode function. To minimize power consumption, the resistors R1 and R2 are relatively large in both solutions: in the kiloohm range for the NMOS main tube + NPN pair (auxiliary tube) solution, and in the megohm range for the NMOS main tube + NMOS pair (auxiliary tube) solution.

[0009] NPN transistor switching characteristics: Junction capacitance exists between the base, emitter, collector, and emitter of an NPN transistor. When switching between the cutoff state and the saturated conduction state, the internal charge storage and release takes time, causing the collector output voltage to lag behind the input voltage. To reduce power consumption and achieve the lowest possible output level, the NPN transistor must be placed in the saturated conduction state. The charge storage effect in the saturated conduction state is the primary cause of circuit transmission delay. To increase switching speed, TTL circuits can be replaced with ECL circuits. ECL circuits design the conduction state to be in the non-saturated linear region, effectively increasing switching speed, but this comes at the expense of power consumption.

[0010] Compared with transistor BJT tube, MOS tube is a unipolar device with no carrier accumulation time. The switching speed of MOS tube is faster. The main reason is that the turn-on time t ON and fall time t fFaster. Generally, the circuit will speed up the rise time t r and fall time t f , but in fact the closing time t OFF MOS tubes have a higher switching speed, with a switching time of 10ns to 100ns and a higher operating frequency.

[0011] Compared to bipolar junction transistors, it is generally believed that MOS transistors do not require current to conduct, as long as the gate and source voltages are above a certain voltage. This is easy to achieve, but it also requires speed.

[0012] In the structure of the MOS tube, it can be seen that there are parasitic capacitances C between the gate and the source, and between the gate and the drain. GS 、C GD , there is Miller effect, in the source grounded amplifier circuit, its equivalent input capacitance Ci=(1+Av)×(C GD +C GS ), where Av is the amplification factor. Driving a MOS transistor actually involves charging and discharging the equivalent input capacitance. Charging a capacitor requires a current, and because the capacitor is considered a short circuit at the moment of charging, the instantaneous current is relatively high. Therefore, the gate resistor can be used to control the current, thereby controlling the turn-on and turn-off times of the MOS transistor. A too rapid current will result in an excessively high voltage rate of change (dV / dt).

[0013] When designing a MOS transistor driver, the first thing to consider is the amount of instantaneous current it can provide, followed by the level of the on-state voltage: NMOS transistors are commonly used for low-end drivers (or NMOS transistors are natural low-end ideal diodes that only require a load power supply to control), and when they are turned on, the gate voltage must be greater than the source voltage. However, when the low-end driven NMOS transistor is turned on, the difference between the source voltage and the drain voltage (usually connected to the negative pole of the power supply) is very small (about 0V). If a voltage higher than the source voltage is required in the same power supply system, only the load power supply can be used, eliminating the bias voltage, making it very convenient to implement and saving costs.

[0014] For MOS transistors, the point capacitance between the gate and substrate is relatively small, so even a small amount of induced charge can generate a very high voltage. Because the impedance RGS between the gate and source is very large, the induced charge is difficult to release. As a result, the high voltage generated by the induced charge can break through the thin insulation layer, causing damage to the MOS transistor. Therefore, whether the MOS transistor is stored or in operation, a resistor should be connected in parallel between the gate and source to provide a DC bias path to prevent the gate from floating. When mounting or soldering, the soldering iron or placement machine should be well grounded.

[0015] Although NMOS V1 is a voltage-type device, due to the presence of parasitic capacitance C GSAnd parasitic resistance, there will be an RC circuit for charging and discharging at the moment of switching on and off. If the collector current I of the V2 tube is smaller, C Or drain current I D To drive the gate of NMOS V1, the switching speed of NMOS V1 is obviously not fast enough. If you want to speed up the switching speed, you must improve the driving capability of the switch. You can reduce the values ​​of resistors R1 and R2 to increase the current driving capability, but at the same time it will also increase the loss, which may not be worth the gain.

[0016] from Figure 1 (NMOS main tube + NPN pair tube technical solution), Figure 2 (NMOS main tube + NMOS pair technology solution) It can be seen that under low-power characteristics, the switching speed of NMOS main tube V1 needs to be improved. It is necessary to design a fast low-side ideal diode to increase the conduction and cutoff speed of NMOS main tube V1. Therefore, it is necessary to design a fast back-end auxiliary tube to control the low-side ideal diode to solve this problem. Summary of the Invention

[0017] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a method for controlling a low-end ideal diode based on a fast-type back-end auxiliary tube of an NMOS tube.

[0018] In order to solve the above technical problems, the present invention is implemented through the following technical solutions.

[0019] A low-end ideal diode controlled by a fast-type rear-end auxiliary tube based on an NMOS tube comprises a circuit including a power supply VCC, an NMOS tube V1, a comparator circuit, a bias power supply and a drive circuit.

[0020] The comparator circuit includes two independent auxiliary tubes or a pair of tubes and a resistor.

[0021] The comparator circuit is used to compare the voltages at the source and drain of the NMOS main body V1. The comparison signal of the comparator circuit is transmitted through the drive circuit to the gate of the NMOS main body V1 to control the conduction and cutoff of the NMOS main body V1.

[0022] A current discharge resistor R3 is further connected between the gate and source of the NMOS main tube V1.

[0023] Preferably, the two independent auxiliary tubes are NMOS auxiliary tubes V2 and V3, and the resistors include resistors R1 and R2.

[0024] The drain of the NMOS auxiliary tube V2 is connected to the bias power supply through the resistor R1, the source is connected to the source of the NMOS main tube V1, the gate is connected to the gate of the NMOS auxiliary tube V3, and the drain and gate of the NMOS auxiliary tube V2 are short-circuited.

[0025] The drain of the NMOS auxiliary tube V3 is connected to the bias power supply through the resistor R2 , the source is connected to the drain of the NMOS main tube V1 , and the gate is connected to the gate of the NMOS auxiliary tube V2 .

[0026] Preferably, the driving circuit is any one of a three-port driving circuit or a four-port driving circuit.

[0027] Preferably, in the three-port driving circuit, the DV terminal is connected to a bias power supply, the DI terminal is connected to the drain of the NMOS auxiliary tube V3, and the DO terminal is connected to the gate of the NMOS main tube V1.

[0028] Preferably, the three-port drive circuit includes any one of a single-transistor drive circuit, a Darlington transistor drive circuit, and a combination module drive circuit.

[0029] Preferably, in the four-port driving circuit, the DV terminal is connected to the bias power supply, the DI terminal is connected to the drain of the NMOS auxiliary tube V3, the DO terminal is connected to the gate of the NMOS main tube V1, and the DR terminal is connected to the drain of the NMOS main tube V1.

[0030] Preferably, the four-port drive circuit includes any one of a totem pole drive, a load switch drive, and a totem pole composite drive circuit.

[0031] Preferably, the bias power supply is a load power supply VCC.

[0032] The advantages of the present invention over the prior art are that the circuit has the functions of preventing backflow, protecting the preceding circuit and the ideal diode, and can also accelerate the conduction and cutoff of the low-end ideal diode. The drive module designed by the present invention has a simple circuit, low cost and strong practicality.

[0033] The present invention provides sixteen driving circuits in three-port and four-port forms. Circuit principle analysis and software simulation verification show that the designed circuits can be used as low-end ideal diodes to prevent backflow and protect the previous stage circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is the schematic diagram of the low-end ideal diode implemented by the existing NPN pair comparator;

[0035] Figure 2 This is the schematic diagram of the low-end ideal diode implemented by the existing NMOS pair comparator;

[0036] Figure 3 The principle block diagram of the low-side ideal diode composed of three-port drive;

[0037] Figure 4The principle block diagram of the low-side ideal diode composed of four-port drive;

[0038] Figure 5 It is a single-tube driver module;

[0039] Figure 6 It is the Darlington tube driver module;

[0040] Figure 7 It is a combination circuit driving module;

[0041] Figure 8 It is the totem pole driver module;

[0042] Figure 9 It is a load switch driving module;

[0043] Figure 10 It is a totem pole composite drive module;

[0044] Figure 11 The low-end ideal diode (1) is formed by the PNP tube driver module;

[0045] Figure 12 The low-end ideal diode (II) formed by the PMOS tube driver module;

[0046] Figure 13 The low-end ideal diode (three) is composed of Darlington (PNP tube + PNP tube);

[0047] Figure 14 The low-end ideal diode (four) is composed of Darlington (PNP tube + NPN tube);

[0048] Figure 15 The low-end ideal diode (V) is composed of a PNP tube + a diode;

[0049] Figure 16 The low-end ideal diode (six) is composed of a PNP tube + resistor;

[0050] Figure 17 It is a BJT type totem pole: a low-end ideal diode composed of a PNP tube + a PNP tube (seven);

[0051] Figure 18 It is a MOS type totem pole: a low-end ideal diode composed of a PMOS tube + an NMOS tube (eight);

[0052] Figure 19 For the load switch: a low-end ideal diode (9) consisting of a PNP main transistor and a PNP auxiliary transistor;

[0053] Figure 20 For the load switch: a low-end ideal diode (10) consisting of a PNP main tube + a PMOS auxiliary tube;

[0054] Figure 21 For the load switch: a low-end ideal diode (11) consisting of a PMOS main tube + a PNP auxiliary tube;

[0055] Figure 22 For the load switch: a low-end ideal diode (12) composed of a PMOS main tube + a PMOS auxiliary tube;

[0056] Figure 23 The low-end ideal diode (13) is composed of a PNP tube + a BJT type totem pole;

[0057] Figure 24 A low-end ideal diode (14) consisting of a PNP tube + a MOS totem pole;

[0058] Figure 25 A low-end ideal diode (15) consisting of a PMOS tube + a BJT type totem pole;

[0059] Figure 26 A low-end ideal diode (16) consisting of a PMOS tube + a MOS type totem pole;

[0060] Figure 27 for Figure 11 Forward bias simulation;

[0061] Figure 28 for Figure 12 Forward bias simulation;

[0062] Figure 29 for Figure 13 Forward bias simulation;

[0063] Figure 30 for Figure 15 Forward bias simulation;

[0064] Figure 31 for Figure 17 Forward bias simulation;

[0065] Figure 32 for Figure 18 Forward bias simulation;

[0066] Figure 33 for Figure 19 Forward bias simulation;

[0067] Figure 34 for Figure 23 Forward bias simulation;

[0068] Figure 35 for Figure 24 Forward bias simulation;

[0069] Figure 36 for Figure 25 Forward bias simulation;

[0070] Figure 37 for Figure 26 Forward bias simulation. DETAILED DESCRIPTION

[0071] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in many different ways as defined and covered by the claims.

[0072] A fast-type back-end auxiliary tube based on an NMOS tube controls a low-end ideal diode, including an NMOS main tube, a comparator circuit, a drive circuit, a bias power supply, etc.; the comparator circuit is composed of two independent NMOS (NPN) auxiliary tubes or an NMOS (NPN) pair of tubes V2 and V3 with the same parameters and packaged together, resistors R1 and R2, etc.

[0073] Preferably, the comparator is used to compare the potential VD of the load low end and the negative electrode GND of the power supply. The comparison signal output by the comparator is connected to the gate of the NMOS supervisor V1 through the driving circuit to control the conduction and cutoff of the NMOS supervisor V1.

[0074] Preferably, the driving circuit has a strong current driving capability for the NMOS tube, which improves the switching speed of the NMOS tube. The driving circuit can be divided into three-port driving and four-port driving according to the number of interfaces. The three-port driving can be divided into single tube driving, Darlington transistor driving, combination circuit driving, etc.; the four-port driving can be divided into totem pole driving, load switch driving, totem pole composite driving, etc. Taking the NMOS auxiliary tube as an example, in Figure 2 On the basis of adding three-port driver, the schematic diagram is as follows Figure 3 As shown; add four-port drive, the schematic diagram is as follows Figure 4 As shown; the fast low-end ideal diode based on the NPN auxiliary tube is similar and will not be described in detail.

[0075] The three-port driver schematic is as follows Figure 3 As shown, there are three interfaces: driver bias power supply DV (abbreviation of Driver Voltage), driver input signal DI (abbreviation of Driver Input Signal), and driver output current amplified signal DO (abbreviation of Driver Output Signal). DV is connected to the bias power supply VBAIS (or load power supply VCC), DI is connected to VC, and DO is connected to VB, as shown below.

[0076] (1) Single-tube driver, its composition is divided into: PNP tube, PMOS tube, etc. Figure 5 shown.

[0077] (2) Darlington transistor is also called compound transistor. Combining two transistors is equivalent to a new transistor. In theory, the amplification factor of Darlington transistor is the product of the amplification factors of the two transistors, which is equivalent to two-stage current amplification. Darlington transistor can be regarded as a direct-coupled current amplifier. The transistors are directly connected in series without any coupling elements. The biggest function of the transistor series connection is to provide high current amplification gain. Its composition is divided into: Darlington transistors composed of the same type of transistors (PNP transistor + PNP transistor) are called homopolar Darlington transistors (equivalent to new PNP transistors), and Darlington transistors composed of different types of transistors (PNP transistor + NPN transistor) are called heteropolar Darlington transistors (equivalent to new PNP transistors). Figure 6 shown.

[0078] (3) Combination circuit, which is composed of: PNP+diode, PNP+resistor, respectively Figure 7 shown.

[0079] The four-port driver schematic is as follows Figure 4 As shown, there are four interfaces: driver bias supply DV (Driver Voltage), driver input signal DI (Driver Input Signal), driver output current amplification signal DO (Driver Output Signal), and driver reference supply DR (Driver Reference Voltage, typically the negative terminal of power supply VCC). DV connects to bias supply VBAIS (or load power supply VCC), DI connects to VC, DO connects to VB, and DR connects to the negative terminal of power supply VCC. Four-port drive circuits can be constructed in a variety of ways, including totem pole drive, load switch drive, and totem pole composite drive, as shown below.

[0080] (1) Totem pole drive, its composition is divided into: BJT type totem pole (PNP tube + PNP tube), MOS type totem pole (PMOS tube + NMOS tube), such as Figure 8 shown.

[0081] (2) Load switch drive, its composition is divided into: PNP main + PNP auxiliary tube, PNP main + PMOS auxiliary tube, PMOS main + PNP auxiliary tube, PMOS main + PMOS auxiliary tube, etc. Figure 9 shown.

[0082] (3) Totem pole composite drive: adding a transistor to the back end of the totem pole drive is equivalent to adding a current amplifier circuit. Its composition is divided into: PNP tube + BJT type totem pole (PNP tube + PNP tube), PNP tube + MOS type totem pole (PMOS tube + NMOS tube), PMOS tube + BJT type totem pole (PNP tube + PNP tube), PMOS tube + MOS type totem pole (PMOS tube + NMOS tube), such as Figure 10 shown.

[0083] Preferably, the Figure 3 Use of the three-port driver module Figure 5 The schematic diagram of the PNP tube is as follows Figure 11 As shown: To save costs, it is generally necessary to omit the bias power supply VBIAS, that is, VBIAS is connected to the power supply VCC. The working principle is as follows: When the load low-end potential VD is not less than the negative power supply GND, the NMOS tube V2 is weakly turned on and the NMOS tube V3 is turned on. The comparator outputs the comparison signal VC (connected to DI) level, VC=VCC-V F , PNP tube V4 is saturated and turned on, VC (connected to DI) is converted into VB (connected to DO) signal through the driving circuit, VB≈VCC, the gate of NMOS supervisor V1 is high level, NMOS supervisor V1 is turned on, and the strong current of VCC drives the gate of NMOS supervisor V1 through the low impedance channel (emitter to collector) of V4 tube, and NMOS supervisor V1 is quickly turned on.

[0084] When the load low-end potential VD is lower than the negative electrode GND of the power supply (the negative electrode GND is connected to the power supply VCC2, and the power supply voltage VCC2>VCC): the NMOS tube V2 is cut off (cannot form a closed loop), the drain-source channel of the NMOS tube V3 is cut off (but the body diode is turned on), and the comparator outputs the comparison signal VC≈VCC2-V F , the driving module PNP tube V4 is cut off, VC cannot be converted into VB signal through the driving circuit, and the VB signal is pulled up to VCC by resistor R3. VB≈VCC, that is, the gate-source voltage difference V1 of the NMOS supervisor V1 GS =VB-VCC≈0V<V TN , the charge on the gate junction capacitance of the NMOS supervisor V1 is quickly released to the load low-end potential VD through the resistor R3, and the NMOS supervisor V1 is quickly cut off.

[0085] Figure 3 Use of the three-port driver module Figure 5 The schematic diagram of the PMOS tube is as follows Figure 12 As shown, the working process is Figure 11 The driving circuit is similar, and so on, which will not be described in detail.

[0086] Preferably, the Figure 3Use of the three-port driver module Figure 6 The schematic diagram of the Darlington (PNP tube + PNP tube) is as follows Figure 13 As shown, the working principle is as follows: when the load low-end potential VD is not less than the negative power supply GND, the NMOS tube V2 is weakly turned on, the NMOS tube V3 is turned on, and the comparator outputs the comparison signal VC (connected to DI) level, VC=VCC-2×V F , Darlington tubes V4 and V5 are saturated and turned on, VC (connected to DI) is converted into VB (connected to DO) signal through the Darlington drive circuit, VB≈VCC, the gate of NMOS supervisor V1 is high level, NMOS supervisor V1 is turned on, and the strong current of VCC drives the gate of NMOS supervisor V1 through the low impedance channel of Darlington tubes V4 and V5, and NMOS supervisor V1 is quickly turned on.

[0087] When the load low-end potential VD is lower than the negative electrode GND of the power supply (the negative electrode GND is connected to the power supply VCC2, and the power supply voltage VCC2>VCC): the NMOS tube V2 is cut off (cannot form a closed loop), the drain-source channel of the NMOS tube V3 is cut off (but the body diode is turned on), and the comparator outputs the comparison signal VC≈VCC2-V F >VCC-2×V F , the Darlington transistor V4 and V5 of the driving circuit are cut off, VC cannot be converted into VB signal through the driving circuit, and the VB signal is pulled up to VCC by resistor R3. VB≈VCC, that is, the gate-source voltage difference V1 of the NMOS supervisor V1 GS =VB-VCC≈0V<V TN , the charge on the gate junction capacitance of the NMOS supervisor V1 is quickly released to the load low-end potential VD through the resistor R3, and the NMOS supervisor V1 is quickly cut off.

[0088] Figure 3 Use of the three-port driver module Figure 6 The schematic diagram of the Darlington (PNP tube + NPN tube) is as follows Figure 14 As shown, the working process is Figure 13 The Darlington tube driving circuit is similar, and so on, I will not go into details.

[0089] From the above, we can see that the composition of the NMOS main tube and the bias power supply is unique, but the auxiliary tube of the comparator circuit has two compositions: NPN pair tube and NMOS pair tube. The drive circuit has 16 compositions. From the combination knowledge, we can know that there are a total of 32 combinations. The auxiliary tube of the comparator circuit takes the NMOS pair tube as an example. The composition of the drive module and the corresponding implementation method are shown in Table 1. The low-end ideal diode controlled by the fast back-end auxiliary tube based on the NPN auxiliary tube is similar, and so on. No further details are given.

[0090] Table 1 Driver module combination

[0091]

[0092]

[0093] Since there are many ways to form the composition, only the first embodiment ( Figure 11 ), Implementation Method 3 ( Figure 13 ), Implementation Method Five ( Figure 15 ), Implementation Method 7 ( Figure 17 ), Implementation Method Nine ( Figure 19 ), Implementation Method Thirteen ( Figure 23 ), Implementation Method 14 ( Figure 24 ), Implementation 15 ( Figure 25 ) is described in detail, and the remaining implementation methods are similar and will not be repeated here.

[0094] Implementation Method 1

[0095] The circuit corresponding to the first embodiment is as follows Figure 11 As shown: the comparator circuit consists of two independent NMOS auxiliary tubes V2 and V3, resistors R1 and R2, etc. The driving tube used in the driving circuit is a PNP tube.

[0096] Since the NMOS V1 is a voltage-type device, its gate and source impedances are very large, and the power supply VCC>V TN (V TN (where ΔV is the NMOS transistor's turn-on threshold voltage). A weak current path always exists between the power supply VCC and the NMOS transistor V1. Even when the emitter junction of transistor V4 is cut off, a weak (nanoampere-level) current still flows between the emitter and collector. Even this weak current can increase the gate voltage of NMOS transistor V1, turning on NMOS transistor V1. If gate-source bias resistor R3 is added, this weak current flows through R3 into the negative terminal of the power supply, reducing the gate-source voltage difference to approximately 0V and turning off NMOS transistor V1. Resistor R3 can be considered a bias resistor or current bleeder. Resistor R3 cannot be omitted, nor can its value be too large, otherwise the gate-source voltage difference of NMOS transistor V1 will increase, turning on NMOS transistor V1.

[0097] When the load low-end potential VD is not less than the power supply negative electrode GND, the comparator outputs the comparison signal VC as a high level: VC = VCC - V F , V2 tube is weakly turned on (due to the short circuit between the drain and the gate, the corresponding drain-source voltage difference V2 DS Relatively small, V2 DS =V2 GS =V TN), V3 tube is turned on (the corresponding drain-source voltage difference is relatively large); the driving module PNP tube V4 is saturated and turned on, VB≈VCC, VC amplifies the current through the driving tube V4, and obtains a strong current VB signal to drive the gate of the NMOS supervisor V1. The gate-source voltage difference of the NMOS supervisor V1 is V1 GS =VB-0V=VCC>V TN , NMOS supervisor V1 is turned on quickly.

[0098] When the load low-end potential VD is less than the negative electrode GND of the power supply (the negative electrode GND is connected to the power supply VCC2, and the power supply voltage VCC2>VCC), the comparator outputs the comparison signal VC, and the V2 tube is cut off (it cannot form a closed loop. Since the drain resistor R1 has a large resistance, the corresponding drain current is negligible, and the drain-source voltage difference V2 DS ≈0V), the drain-source channel of V3 is cut off, the body diode is turned on, VC≈VCC2-V F >VCC-V F , the emitter and base voltage difference of the driving tube V4 is V4 EC =VCC-VC≈VCC-VCC2+V F <V F , the driver tube V4 is cut off, VC cannot be converted into VB signal through the driver tube V4, and the VB signal is pulled up to VCC by the resistor R3, VB≈VCC, that is, the gate-source voltage difference V1 of the NMOS supervisor V1 GS =VB-VCC≈0V<V TN , the charge on the gate junction capacitance of the NMOS supervisor V1 is quickly released to the load low-end potential VD through the resistor R3, and the NMOS supervisor V1 is quickly cut off.

[0099] Implementation Method 3

[0100] The circuit corresponding to the third embodiment is as follows Figure 13 As shown in the figure, the driver circuit uses a Darlington transistor (PNP + PNP). Darlington transistors can provide high current, with a much greater current amplification factor than a single PNP transistor. They possess exceptionally strong drive capability, enabling the NMOS transistor V1 to turn on instantly. When the NMOS transistor V1 turns off, the charge on the gate junction capacitance is rapidly released through resistor R3 to the load's low-end potential, VD, quickly turning off the NMOS transistor V1.

[0101] Implementation Method Five

[0102] The circuit corresponding to the fifth embodiment is as follows Figure 15As shown in the figure, the driver circuit uses a PNP transistor + diode. The strong drive current provided by PNP transistor V4 can instantly turn on NMOS transistor V1. When NMOS transistor V1 turns off, the charge on the gate junction capacitance is quickly discharged through resistor R3 to the load low-end potential VD, and NMOS transistor V1 is quickly turned off.

[0103] Implementation Method Seven

[0104] The circuit corresponding to the seventh embodiment is as follows Figure 17 As shown, the driver circuit uses a BJT totem-pole circuit (PNP + PNP). The strong drive current provided by PNP V4 instantly turns on NMOS V1. When NMOS V1 turns off, PNP V5 turns on. The emitter and collector channels of PNP V5 and resistor R3 quickly release to the load's low-end potentials, GND and VD, respectively, quickly turning off NMOS V1.

[0105] Implementation Method Nine

[0106] The circuit corresponding to the ninth embodiment is as follows Figure 19 As shown in the figure, the driver circuit uses a load switch (PN main transistor + PNP auxiliary transistor). The strong drive current provided by PNP transistor V4 quickly turns on NMOS transistor V1. When NMOS transistor V1 turns off, the charge on the gate junction capacitance is quickly discharged through resistor R3 to the load low-end potential VD, and NMOS transistor V1 is quickly turned off.

[0107] Implementation Method Thirteen

[0108] The circuit corresponding to the thirteenth embodiment is as follows Figure 23 As shown, the driver circuit uses a PNP transistor + BJT totem pole (PNP + PNP) transistor, creating a totem pole composite drive module that can provide higher current than a totem pole (PNP + PNP) or single PNP transistor. The strong drive current provided by PNP transistor V4 enables rapid turn-on of NMOS transistor V1. When NMOS transistor V1 turns off, PNP transistor V5 turns on. When NMOS transistor V1 turns off, PNP transistor V5 accelerates turn-off: PNP transistor V5's emitter and collector channels and resistor R3 quickly release to the load's low-end potentials GND and VD, respectively, quickly turning off NMOS transistor V1.

[0109] Implementation Method 15

[0110] The circuit corresponding to the fifteenth embodiment is as follows Figure 25As shown, the driver circuit uses a PMOS transistor + BJT totem pole (PNP + PNP) transistor combination. This totem pole composite drive module can provide higher current than a totem pole (PNP + PNP) or single PNP transistor. The strong drive current provided by PNP transistor V4 enables the NMOS transistor V1 to turn on quickly. When NMOS transistor V1 turns off, PNP transistor V5 turns on. When the NMOS transistor V1 turns off, PNP transistor V5 accelerates the shutdown process: the emitter and collector channels of PNP transistor V5 and resistor R3 quickly release to the load low-end potential VD and GND, respectively, quickly turning off the NMOS transistor V1.

[0111] according to Figures 11 to 26 The circuit schematic is simulated and tested using the National Instruments simulation software Multisim (version V14.0). The NMOS tube is NXP, model BSP030, with a minimum on-threshold voltage of V TN(MIN) =1V, maximum value V TN(MAX) =2.8V, typical value V is not given TN , the conduction current is up to 10A, the conduction resistance R DS(ON) =30mΩ(V GS =10V), R DS(ON) =50mΩ(V GS =4.5V), take |V GS(MAX) |=8V、|V DS(MAX) |=30V; the PMOS tube is from ON Semiconductor, model NVTFS5124PLTAG, with a minimum on-threshold voltage of V TP(MIN) =-1.5V, maximum V TP(MAX) =-2.5V, typical value V not given TP , the on-state current can reach -6A, the on-state resistance R DS(ON) =0.26Ω(V GS =-10V), R DS(ON) =0.38Ω(V GS = -4.5V). The NPN transistor used is Generic, model 2N2222A; the PNP transistor used is Generic, model 2N2905. The load resistor RL = 10Ω. The specific simulation test is as follows.

[0112] Implementation Method 1 Simulation

[0113] DC power supply forward bias simulation test (when the load low-end potential VD is not less than the power supply negative electrode GND), VCC = VCC1 = 12V (switch J1 is closed), the simulation is as follows Figure 27 As shown: the drain conduction current is I2 D =10.5μA (test point PR6), I3D =12.7μA (test point PR7), the comparator outputs the comparison signal VC=11.4V, the NMOS tube V3 is turned on (the conduction voltage drop V3 DS =11.4V, the drain-source channel on-resistance is R DS(ON) =V3 DS / I3 D =897kΩ), NMOS tube V2 conduction voltage drop V2 DS =V2 GS =V TN =1.45V, NMOS tube V2 is turned on (the drain-source channel conduction impedance is R DS(ON) =V2 DS / I2 D =138kΩ), PNP tube V4 is saturated and turned on, VB = 11.9V, V1 GS =VB-22.7mV≈11.9V>V TN , NMOS V1 is turned on quickly. When forward conducting, the NMOS V1 conduction voltage drop is 22.7mV-0V=22.7mV, which is much lower than the diode conduction voltage drop V F , load current 1.20A (test point PR5), NMOS V1 corresponding drain-source channel on-resistance R DS(ON) ≈22.7mV / 1.20A=18.9mΩ, the drain-source channel on-resistance is lower than that of the equivalent PMOS tube.

[0114] DC power supply reverse bias simulation test (the load low-end potential VD is less than the power supply negative electrode GND, that is, the negative electrode GND is connected to the power supply VCC2, and the power supply voltage VCC2>VCC): NMOS tube V2 is cut off (cannot form a closed loop), the drain-source channel of NMOS tube V3 is cut off (but the body diode is turned on), and the comparator outputs the comparison signal VC, VC≈VCC2-V F >VCC-V F , the driving circuit V4 is cut off, VC cannot be converted into VB signal through the driving circuit, and the VB signal is pulled up to VCC by resistor R3, VB≈VCC, that is, the gate-source voltage difference V1 of the NMOS supervisor V1 GS =VB-VCC≈0V<V TN The charge on the gate junction capacitance of the NMOS V1 is quickly released to the negative electrode of the power supply VCC through the resistor R3, and the NMOS V1 is quickly cut off. The simulation is omitted.

[0115] Due to the large number of composition methods, only the first embodiment ( Figure 11 ), Implementation Method 2 ( Figure 12 ), Implementation Method 3 ( Figure 13 ), Implementation Method Five ( Figure 15 ), Implementation Method 7 ( Figure 17 ), Implementation Method Eight ( Figure 18 ), Implementation Method Nine ( Figure 19 ), Implementation Method Thirteen ( Figure 23 ), Implementation Method 14 ( Figure 24 ), Implementation 15 ( Figure 25 ), Implementation 16 ( Figure 26 ) are shown in Table 2, and the rest of the simulations are omitted.

[0116] Table 2 Implementation Method Simulation

[0117]

[0118] As can be seen from the above table, when the power is forward-conducting, NMOS transistor V2 is weakly conductive and NMOS transistor V3 is conductive. When the power is reverse-conducting, NMOS transistor V2 is cut off (cannot form a closed loop) and NMOS transistor V3 is cut off.

[0119] The beneficial effects of the present invention are as follows: the circuit is composed of an NMOS main tube, a comparator circuit and a drive circuit, etc. The comparator circuit is composed of two independent NMOS (NPN) auxiliary tubes or an NMOS (NPN) pair of tubes with the same parameters and packaged together, a resistor, etc., and a total of sixteen drive circuits in two forms of three ports and four ports are designed to accelerate the conduction and cutoff of the low-end ideal diode. Through the analysis of the drive circuit principle and software simulation verification, it is shown that the designed circuit can realize the functions of preventing backflow, protecting the previous stage circuit, the ideal diode, etc., and the circuit has the advantages of simplicity and low cost.

[0120] The above describes in detail the preferred embodiments of the present invention. It should be understood that those skilled in the art can make numerous modifications and variations based on the concepts of the present invention without inventive effort. Therefore, any technical solutions that can be derived by those skilled in the art through logical analysis, reasoning, or limited experimentation based on the concepts of the present invention and the prior art should be within the scope of protection defined by the claims.

Claims

1. A fast-type back-end auxiliary tube based on an NMOS tube controls a low-end ideal diode, characterized by: The circuit includes a power supply VCC, an NMOS supervisor V1, a comparator circuit, a bias power supply and a driving circuit; The comparator circuit comprises two independent auxiliary tubes or a pair of tubes and a resistor; The comparator circuit is used to compare the voltages at the source and drain of the NMOS main body V1. The comparison signal of the comparator circuit is transmitted through the drive circuit to the gate of the NMOS main body V1 to control the conduction and cutoff of the NMOS main body V1. A current discharge resistor R3 is further connected between the gate and source of the NMOS main tube V1.

2. The method according to claim 1, wherein: The two independent auxiliary tubes are NMOS auxiliary tubes V2 and V3, and the resistors include resistors R1 and R2; The drain of the NMOS auxiliary tube V2 is connected to the bias power supply through the resistor R1, the source is connected to the source of the NMOS main tube V1, the gate is connected to the gate of the NMOS auxiliary tube V3, and the drain and gate of the NMOS auxiliary tube V2 are short-circuited; The drain of the NMOS auxiliary tube V3 is connected to the bias power supply through the resistor R2 , the source is connected to the drain of the NMOS main tube V1 , and the gate is connected to the gate of the NMOS auxiliary tube V2 .

3. The method according to claim 2, wherein: The driving circuit is any one of a three-port driving circuit and a four-port driving circuit.

4. The method according to claim 3, wherein: In the three-port driving circuit, the DV terminal is connected to a bias power supply, the DI terminal is connected to the drain of the NMOS auxiliary tube V3, and the DO terminal is connected to the gate of the NMOS main tube V1.

5. The method according to claim 4, wherein: The three-port drive circuit includes any one of a single-tube drive circuit, a Darlington transistor drive circuit, and a combination module drive circuit.

6. The method according to claim 3, wherein: In the four-port drive circuit, the DV terminal is connected to the bias power supply, the DI terminal is connected to the drain of the NMOS auxiliary tube V3, the DO terminal is connected to the gate of the NMOS main tube V1, and the DR terminal is connected to the drain of the NMOS main tube V1.

7. The method according to claim 6, wherein: The four-port driving circuit includes any one of a totem pole driving circuit, a load switch driving circuit, and a totem pole composite driving circuit.

8. The NMOS fast-type back-end auxiliary tube-based low-end ideal diode control method according to any one of claims 1 to 7, characterized in that: The bias power supply is the load power supply VCC.

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