Programming method of memory device, memory device and memory system

Abstract

The embodiment of the invention discloses a programming method of a memory device, the memory device and a memory system. The programming method comprises the following steps: applying a programming voltage to a selected word line; applying a first pass voltage to a first word line adjacent to the selected word line; and applying a second pass voltage to a second word line adjacent to the selected word line; wherein the first passing voltage and the second passing voltage comprise at least two rising stages, and the rising moments of at least one rising stage in other rising stages after the first rising stage of the first passing voltage and the second passing voltage are different. The rising moment is the moment when the voltage value starts to increase on the basis of a certain voltage value.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and more particularly, to a programming method for a memory device. Background Art

[0002] Memory devices are used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has become a mainstream product in the memory market due to its high storage density, manageable production costs, suitable programming and erasing speeds, and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems. Summary of the Invention

[0004] According to one aspect of an embodiment of the present application, a programming method for a memory device is provided, comprising: applying a programming voltage to a selected word line;

[0005] applying a first pass voltage to a first word line adjacent to the selected word line;

[0006] and applying a second pass voltage to a second word line adjacent to the selected word line;

[0007] In which, the first pass voltage and the second pass voltage include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the first pass voltage and the second pass voltage is different, and the rising time is the time when the voltage value starts to increase based on a certain voltage value.

[0008] In the above solution, the at least two ascending stages include: two ascending stages;

[0009] A rising moment of the second rising phase of the second pass voltage is earlier than a rising moment of the second rising phase of the first pass voltage.

[0010] In the above solution, the time interval between the rising moment of the second rising phase of the first pass voltage and the rising moment of the second rising phase of the second pass voltage is affected by the pulse width of the programming voltage and the rising speed of the rising phase of the programming voltage.

[0011] In the above scheme, the first pass voltage and the second pass voltage are provided by different voltage sources, and when the maximum voltage value of the first pass voltage is constant, the pulse width of each rising stage provided by the control voltage source is controlled to control the speed at which the first pass voltage reaches the maximum voltage value; or, when the maximum voltage value of the second pass voltage is constant, the pulse width of each rising stage provided by the control voltage source is controlled to control the speed at which the second pass voltage reaches the maximum voltage value.

[0012] In the above solution, after each rising phase ends, the maximum voltage value of the first pass voltage is equal to the maximum voltage value of the second pass voltage.

[0013] In the above solution, the method further includes:

[0014] applying a third pass voltage to other word lines except the first word line, the second word line, and the selected word line;

[0015] After each rising phase ends, the maximum voltage value of the third pass voltage is different from the maximum voltage values ​​of the first pass voltage and the second pass voltage.

[0016] In the above scheme, programming the memory cells coupled to the selected word line includes a plurality of pulse phases;

[0017] In which, in the previous pulse stage, a first sub-programming voltage is applied to the selected word line; in the next pulse stage, a second sub-programming voltage is applied to the selected word line; the voltage value of the first sub-programming voltage is smaller than the voltage value of the second sub-programming voltage.

[0018] In the above scheme, programming the memory cells coupled to the selected word line includes multiple pulse phases; wherein,

[0019] In the previous pulse phase, a first sub-pass voltage is applied to the first word line, and a second sub-pass voltage is applied to the second word line;

[0020] In the next pulse phase, a third sub-pass voltage is applied to the first word line, and a fourth sub-pass voltage is applied to the second word line;

[0021] After each rising phase, the voltage value of the first sub-pass voltage is smaller than the voltage value of the third sub-pass voltage; and the voltage value of the second sub-pass voltage is smaller than the voltage value of the fourth sub-pass voltage.

[0022] In the above scheme, programming of the memory cell coupled to the selected word line includes multiple pulse stages; and in each pulse stage, the pass voltage applied to the first word line and the pass voltage applied to the second word line both include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the pass voltage applied to the first word line and the pass voltage applied to the second word line is different.

[0023] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a memory cell array, the memory cell array comprising a plurality of memory strings; each of the memory strings comprising a plurality of memory cells;

[0024] A plurality of word lines; each word line is coupled to a corresponding memory cell in each of the memory strings;

[0025] and a peripheral circuit coupled to the plurality of word lines; wherein the peripheral circuit is configured as follows:

[0026] applying a programming voltage to the selected word line;

[0027] applying a first pass voltage to a first word line adjacent to the selected word line; and

[0028] applying a second pass voltage to a second word line adjacent to the selected word line;

[0029] In which, the first pass voltage and the second pass voltage include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the first pass voltage and the second pass voltage is different, and the rising time is the time when the voltage value of the pass voltage starts to increase based on a certain voltage value.

[0030] In the above solution, the at least two rising stages include: two rising stages; and a rising moment of the second rising stage of the second pass voltage is earlier than a rising moment of the second rising stage of the first pass voltage.

[0031] In the above solution, the time interval between the rising moment of the second rising phase of the first pass voltage and the rising moment of the second rising phase of the second pass voltage is affected by the pulse width of the programming voltage and the rising speed of the rising phase of the programming voltage.

[0032] In the above solution, the peripheral circuit further includes a first voltage source and a second voltage source, wherein;

[0033] The first voltage source is configured to: apply the first pass voltage to the first word line;

[0034] The second voltage source is configured to: apply the second pass voltage to the second word line,

[0035] Among them, when the maximum voltage value of the first pass voltage is constant, the speed at which the first pass voltage reaches the maximum voltage value is controlled by controlling the pulse width of each rising stage provided by the first voltage source; when the maximum voltage of the second pass voltage is constant, the speed at which the second pass voltage reaches the maximum voltage value is controlled by controlling the pulse width of each rising stage provided by the second voltage source.

[0036] In the above scheme, the peripheral circuit is further configured to: apply a third pass voltage to other word lines among the multiple word lines except the first word line, the second word line and the selected word line; wherein, after each rising stage, the maximum voltage value of the third pass voltage is different from the maximum voltage values ​​of the first pass voltage and the second pass voltage.

[0037] In the above scheme, programming the memory cells coupled to the selected word line includes a plurality of pulse phases;

[0038] In which, in the previous pulse stage, a first sub-programming voltage is applied to the selected word line; in the next pulse stage, a second sub-programming voltage is applied to the selected word line; the voltage value of the first sub-programming voltage is smaller than the voltage value of the second sub-programming voltage.

[0039] In the above scheme, programming the memory cells coupled to the selected word line includes multiple pulse phases; wherein,

[0040] In the previous pulse phase, a first sub-pass voltage is applied to the first word line, and a second sub-pass voltage is applied to the second word line;

[0041] In the next pulse phase, a third sub-pass voltage is applied to the first word line, and a fourth sub-pass voltage is applied to the second word line;

[0042] After each rising phase, the voltage value of the first sub-pass voltage is smaller than the voltage value of the third sub-pass voltage; and the voltage value of the second sub-pass voltage is smaller than the voltage value of the fourth sub-pass voltage.

[0043] In the above scheme, programming of the memory cell coupled to the selected word line includes multiple pulse stages; and in each pulse stage, the pass voltage applied to the first word line and the pass voltage applied to the second word line both include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the pass voltage applied to the first word line and the pass voltage applied to the second word line is different.

[0044] In the above solution, after each rising phase ends, the maximum voltage value of the first pass voltage is equal to the maximum voltage value of the second pass voltage.

[0045] According to another aspect of the embodiments of the present application, a memory system is provided, comprising: one or more memory devices as described in any one of the above, and a memory controller coupled to the memory devices and configured to control the memory devices.

[0046] In the above solution, the memory system is contained in a solid state drive SSD or a memory card.

[0047] Embodiments of the present application provide a programming method for a memory device, a memory device, and a memory system. The programming method includes: applying a programming voltage to a selected word line; applying a first pass voltage to a first word line adjacent to the selected word line; and applying a second pass voltage to a second word line adjacent to the selected word line; wherein the first pass voltage and the second pass voltage include at least two rising stages, and the first pass voltage and the second pass voltage have different rising times in at least one of the other rising stages after the first rising stage, and the rising time is the time when the voltage value begins to increase based on a certain voltage value. The programming method provided in the embodiment of the present application improves program interference and increases the read window margin by applying a pass voltage including at least two rising stages to two adjacent word lines of the selected word line, so that at least one of the other rising stages after the first rising stage has different rising times. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In the accompanying drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0049] Figure 1 A block diagram of an exemplary system having a memory system provided in an embodiment of the present application;

[0050] Figure 2 A block diagram of an exemplary memory card having a memory system provided in an embodiment of the present application;

[0051] Figure 3 A schematic diagram of an exemplary solid-state drive having a memory system provided in an embodiment of the present application;

[0052] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuits provided in an embodiment of the present application;

[0053] Figure 5A schematic cross-sectional view of an exemplary memory cell array including NAND memory strings provided in an embodiment of the present application;

[0054] Figure 6 A schematic structural diagram of a peripheral circuit of a memory device provided in an embodiment of the present application;

[0055] Figure 7 A schematic diagram of the voltage waveform of each word line during programming provided in the embodiment of the present application Figure 1 ;

[0056] Figure 8 A schematic diagram of the threshold voltage distribution of a DLC type memory cell provided in an embodiment of the present application;

[0057] Figure 9 A schematic diagram of the threshold voltage distribution of a TLC type memory cell provided in an embodiment of the present application;

[0058] Figure 10 A schematic diagram of the threshold voltage distribution of a QLC type memory cell provided in an embodiment of the present application;

[0059] Figure 11 A flowchart of a method for programming a memory device provided in an embodiment of the present application;

[0060] Figure 12 A schematic diagram of the voltage waveform of each word line during programming provided in the embodiment of the present application Figure 2 ;

[0061] Figure 13 A schematic diagram of the voltage waveform of each word line during programming provided in the embodiment of the present application Figure 3 ;

[0062] Figure 14 A schematic diagram of the structure of the step pulse of the ISPP method provided in an embodiment of the present application;

[0063] Figure 15 A schematic structural diagram of a memory device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0065] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0066] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0067] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0068] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0069] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0070] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0071] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0072] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0073] The embodiments of the present application are further described in detail below with reference to the accompanying drawings and specific embodiments.

[0074] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present application is shown. Figure 1 In the embodiment, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memory devices 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on chip (SoC), wherein the system on chip may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the memory device 104. Specifically, the memory device 104 may be any memory disclosed in this application, such as phase change random access memory (PCRAM), three-dimensional NAND flash memory, and the like.

[0075] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded Multi Media Card (eMMC), where the SSD or eMMC is used as data storage for mobile devices with high duty cycle environments such as smartphones, tablet computers, and laptop computers, as well as enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) on data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnection (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, etc.

[0076] In some embodiments, the memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2 In one example shown, the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. Memory cards may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card that connects the memory card to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 3 In another example shown, the memory controller 106 and the plurality of memory devices 104 may be integrated into a solid state drive (SSD) 302. The SSD may also include a computer that interfaces the SSD with a host (e.g., Figure 1 The memory controller 106 may further include an SSD connector 304 coupled to the host computer 108. In some embodiments, the SSD may have a greater storage capacity and / or operating speed than a memory card. Furthermore, the memory controller 106 may be configured to control erase, read, and write operations of the memory device 104.

[0077] Among them, Figure 4As shown, the memory device 104 may include a memory cell array 401 and a peripheral circuit 402 coupled to the memory cell array 401, wherein the memory cell array 401 may be a NAND flash memory array, wherein the memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the storage region of the memory cell 406. Each memory cell 406 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0078] In some embodiments, each memory cell 406 is a single-level cell (SLC) that has two possible data states and therefore can store one bit of data. For example, the first data state "0" can correspond to a first voltage range, and the second data state "1" can correspond to a second voltage range. In some embodiments, the first voltage range and the second voltage range can be referred to as the threshold voltage distribution of the memory cell. In some embodiments, each memory cell 406 can be a multi-level cell (MLC). For example, an MLC can store two bits per cell (also known as a double-level cell (DLC); for another example, it can store three bits per cell (also known as a tri-level cell (TLC); or for another example, it can store four bits per cell (also known as a quadruple-level cell (QLC)). Regardless of the type of memory cell, the data state includes an erased state and (one or more) programmed states. When a programming operation is performed on the memory cell, the memory cell in the erased state is programmed to a certain programmed state. Generally speaking, the voltage value in the voltage range corresponding to the programmed state of the memory cell is relatively large.

[0079] like Figure 4As shown, each NAND string 408 may include a source select gate (SSG) 410 at its source terminal and a drain select gate (DSG) 412 at its drain terminal. The SSG 410 and DSG 412 may be configured to activate a selected NAND string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND strings 408 in the same memory block 404 are coupled via the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND strings 408 in the same memory block 404 have an array common source (ACS). According to some embodiments, the DSG 412 of each NAND string 408 is coupled to a corresponding bit line 416, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having DSG 412) or a deselect voltage (e.g., 0 volts (V)) to the corresponding DSG 412 via one or more drain select lines (Drain Selective Line) or top select lines (Top Selective Line) 413 and / or applying a select voltage (e.g., higher than the threshold voltage of the transistor having SSG 410) or a deselect voltage (e.g., 0 V) ​​to the corresponding SSG 410 via one or more source select lines (Source Selective Line) or bottom select lines (Bottom Selective Line) 415.

[0080] like Figure 4 As shown, the NAND memory string 408 can be organized into a plurality of memory blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each memory block 404 is a basic data unit with an erase operation, that is, all memory cells 406 on the same memory block 404 are erased at the same time. In order to erase the memory cells 406 in the selected memory block 404, the source lines 414 coupled to the selected memory block 404 and the unselected memory blocks 404 in the same plane (Plane) as the selected memory block 404 can be biased with an erase voltage (Vers) (e.g., a high positive voltage of 20V or higher). It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of blocks or any suitable fraction of blocks. As shown Figure 4 As shown, the memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418 , that is, the same word line 418 can be coupled to memory cells at the same position (ie, corresponding memory cells) in multiple memory strings.

[0081] Figure 5 1 shows a cross-sectional side view of an exemplary memory cell array 401 including NAND memory strings 408 according to some aspects of the present application. Figure 5 As shown in FIG, NAND memory string 408 may include a stacked structure 510, which includes multiple gate layers 511 and multiple insulating layers 512 that are alternately stacked in sequence, and a memory string 408 that vertically penetrates the gate layers 511 and the insulating layers 512. The gate layers 511 and the insulating layers 512 may be alternately stacked, with two adjacent gate layers 511 separated by a layer of insulating layer 512. The number of pairs of gate layers 511 and insulating layers 512 in the stacked structure 510 may determine the number of memory cells included in the memory cell array 401.

[0082] The gate layer 511 may be formed of a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 511 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 511 includes a doped polysilicon layer. Each gate layer 511 may include a control gate surrounding a memory cell. The gate layer 511 at the top of the stacked structure 510 can extend laterally to serve as an upper select gate line 513, also known as a TSG line 413. The upper select gate line 513 is also the lead line of the upper select gate (TSG) 412 described above, which can be connected to a corresponding select voltage or cancel voltage. The gate layer 511 at the bottom of the stacked structure 510 can extend laterally to serve as a lower select gate line 514, also known as a source select line (or bottom select line) 415. The lower select gate line 514 is also the lead line of the lower select gate (BSG) 410 described above, which can be connected to a corresponding select voltage or cancel voltage. The gate layer 511 extending laterally between the upper and lower select gate lines can serve as a word line layer 503. These word line layers 503 are also the word lines 418 described above.

[0083] In some embodiments, the stacked structure 510 may be disposed on a substrate 501. The substrate 501 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0084] In some embodiments, the NAND memory string 408 includes a channel structure (CH) 516 extending vertically through the stacked structure 510. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure can have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0085] Return Reference Figure 4 , the peripheral circuit 402 may be coupled to the memory cell array 401 via the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 401 by applying a voltage signal and / or a current signal to each target memory cell 406 and sensing a voltage signal and / or a current signal from each target memory cell 406 via the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuits are shown, and the peripheral circuit 402 may include a page buffer / sense amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, a control logic 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, the peripheral circuit 402 may also include Figure 6 Additional circuitry not shown.

[0086] Specifically, the page buffer / sense amplifier 604 can be configured to read data from the memory cell array 401 and program (write) data to the memory cell array 401 based on control signals from the control logic 612. In one example, the page buffer / sense amplifier 604 can store program data (or write data) to be programmed into the memory cells coupled to a word line in the memory cell array 401. In another example, the page buffer / sense amplifier 604 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cells 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 604 can also sense low-power signals from the bit lines 416 representing the data bits stored in the memory cells 406 and amplify small voltage swings to recognizable logic levels during read operations. The column decoder / bit line driver 606 can be configured to be controlled by the control logic 612 and select one or more NAND memory strings 408 by applying bit line voltages generated by the voltage generator 610.

[0087] The row decoder / word line driver 608 can be configured to be controlled by control logic 612 and to select / deselect memory blocks 404 of the memory cell array 401 and to select / deselect word lines 418 of the memory blocks 404. The row decoder / word line driver 608 can also be configured to drive the word lines 418 using word line voltages generated from a voltage generator 610 and to perform programming and reading operations on the memory cells 406 coupled to the selected word line(s) 418. In some embodiments, the row decoder / word line driver 608 can also select / deselect and drive the SSG lines 415 and the DSG lines 413. The voltage generator 610 can be configured to be controlled by control logic 612 and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 401.

[0088] Among them, the control logic 612 can be coupled to each circuit described above and is configured to control the operation of each peripheral circuit. The register 614 can be coupled to the control logic 612 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 616 can be coupled to the control logic 612 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 612, as well as buffer status information received from the control logic 612 and relay it to the host. The interface 616 can also be coupled to the column decoder / bit line driver 606 via the data bus 618 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 401 or relay or buffer data from the memory cell array 401.

[0089] In some specific embodiments, a certain programming operation may include multiple stages. For example, the programming operation may include a channel precharge stage, a channel boost stage, a programming pulse stage, and a recovery stage. The voltage waveform is as follows: Figure 7 As shown. During the channel precharge phase (T1-T2), the voltage generator can generate the voltages required for the subsequent phase, such as the voltages applied to each gate and the channel boost voltage. During the channel boost phase (T2-T3), the channel boost voltage can be applied to the selected word line. During the programming pulse phase (T3-T4), the target voltage for each programming step can be applied to the selected word line. During the recovery phase (after T4), the voltage of both the unselected word lines and the selected word line can be reduced to the corresponding voltage, such as Vcc and Vdd. During the recovery phase, the voltage can be reduced to the corresponding voltage through one or more step-by-step steps, such as first reducing the voltage to an intermediate voltage and maintaining it at the intermediate voltage for a period of time before reducing the voltage to the corresponding voltage.

[0090] For the storage system and memory described above, the read window margin (RWM) is an important parameter for correctly reading the data of the storage cell. There are two definitions of RWM: First, RWM is the sum of the intervals between the threshold voltage distributions corresponding to two adjacent data states of the storage cell, for example, Figure 8 The threshold voltage distribution of the MLC type memory cell is described as follows. Figure 8 As shown, the first RWM of an MLC type (also known as a DLC type) memory cell can be the voltage interval between the erase state S1 and the programmed state S2. Second, the RWM can be defined as the voltage interval between the program verification voltage of the programmed state of the memory cell and the read voltage used to distinguish the programmed state from its adjacent data state, such as Figure 8The RWM contained in is: V RD1 The voltage interval between the maximum value of the threshold voltage distribution of the erased state S1, V RD1 to V FY1 The voltage range between RD2 The voltage interval between the maximum value of the threshold voltage distribution of the first programming state S2 erased state, V RD2 to V FY2 The voltage range between RD3 The voltage interval between the maximum value of the threshold voltage distribution of the second programming state S3 and V RD3 to V FY3 The voltage range between RD1 、V RD2 、V RD3 V is the reading voltage for distinguishing between the erased state S1 and the programmed state S2, the reading voltage for distinguishing between the programmed state S2 and the programmed state S3, and the reading voltage for distinguishing between the programmed state S3 and the programmed state S4; FY1 、V FY2 、V FY3 They are respectively the programming verification voltage of programming state S2, the programming verification voltage of programming state S3, and the programming verification voltage of programming state S4. As the density of data storage of a single memory cell increases further, the width of RWM decreases, for example, Figure 9 The threshold voltage distribution of the TLC type memory cell is shown in FIG. Figure 10 The threshold voltage distribution of the QLC type memory cell shown in the figure shows the RWM ratio of the two. Figure 8 The DLC type memory cell shown has a narrow RWM. When performing a read operation on the memory device, a sufficiently wide RWM is required to correctly read the data in the memory cell. For 3D NAND flash memory, as the number of stacked layers increases, program disturbance (PGM) becomes more severe due to coupling effects between layers and other reasons, resulting in insufficient RWM width.

[0091] In order to solve one or more of the above technical problems, such as Figure 11 As shown, the programming method of the memory device provided in the embodiment of the present application may include:

[0092] applying a programming voltage to the selected word line;

[0093] applying a first pass voltage to a first word line adjacent to the selected word line; and applying a second pass voltage to a second word line adjacent to the selected word line;

[0094] In which, the first pass voltage and the second pass voltage include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the first pass voltage and the second pass voltage is different, and the rising time is the time when the voltage value starts to increase based on a certain voltage value.

[0095] Here, the selected word line may be a word line 418 coupled to a memory cell to be programmed (or a memory cell to be written with data). A first word line adjacent to the selected word line and a second word line adjacent to the selected word line may be connected as shown in FIG. Figure 4 The word lines of the memory cells above and below the selected word line are shown. Figure 4 As shown, assuming that the selected word line is word line 418a; the first word line and the second word line may be word lines adjacent to word line 418a, namely word line 418b and word line 418b', or the first word line and the second word line may be word lines adjacent to word line 418a, namely word line 418b' and word line 418b.

[0096] Based on this, the programming method provided in an embodiment of the present application may be: when programming a memory cell coupled to a selected word line, a programming voltage is applied to the selected word line, a first pass voltage is applied to a first word line adjacent to the selected word line, and a second pass voltage is applied to a second word line adjacent to the selected word line, wherein the first pass voltage and the second pass voltage include at least two rising phases, and at least one of the rising phases after the first rising phase of the first pass voltage and the second pass voltage has a different rising time, wherein the rising time is the time when the voltage value begins to increase from a certain voltage value. That is, in an embodiment of the present application, when programming a memory cell coupled to the selected word line, the pass voltages of two non-selected word lines adjacent to the selected word line (such as the first word line and the second sub-line) are applied using at least a two-step ramp method, and after the first rising phase of the pass voltages of the two non-selected word lines, the rising time of at least one rising phase is different, thereby increasing the high channel potential, improving program disturb (PGM disturb), and thereby increasing RWM. At the same time, the first pass voltage and the second pass voltage start to ramp at different times. Through the coupling effect between the word lines, the programming voltage of the selected word line can be made more uniform, thereby improving the programming efficiency and shortening the programming time.

[0097] Here, the so-called different rising time of at least one of the rising stages of the first pass voltage and the second pass voltage after the first rising stage may include: the rising time of at least one of the rising stages after the first rising stage of the first pass voltage is earlier than the rising time of at least one of the rising stages after the first rising stage of the second pass voltage, or the rising time of at least one of the rising stages after the first rising stage of the second pass voltage is earlier than the rising time of at least one of the rising stages after the first rising stage of the second pass voltage. The specific situation depends on actual circumstances.

[0098] An optional implementation, such as Figure 12 As shown, the at least two rising phases may include: two rising phases; and a rising moment of the second rising phase of the second pass voltage is earlier than a rising moment of the second rising phase of the first pass voltage.

[0099] like Figure 12 As shown, assuming that the selected word line is word line WLn, the first word line is word line WLn-1, and the second word line is word line WLn+1. At this time, the word line WLn is applied with a programming voltage Vpgm; the word line WLn-1 is applied with a first pass voltage; and the word line WLn+1 is applied with a second pass voltage. Figure 12 As shown, the first pass voltage and the second pass voltage both include two rising stages, and the rising moment of the second rising stage of the second pass voltage (i.e., rising at time T6) precedes (or is earlier than) the rising moment of the second rising stage of the first pass voltage (i.e., rising at time T7).

[0100] In some embodiments, the time interval between the rising time of the second rising phase of the first pass voltage and the rising time of the second rising phase of the second pass voltage is affected by the pulse width of the programming voltage and the rising speed of the rising phase of the programming voltage.

[0101] That is to say, if Figure 12 In the programming voltage waveform shown, the time interval between T6 and T7 is affected by the pulse width of the programming voltage applied to the selected word line and the rising speed of the rising phase of the programming voltage.

[0102] Among them, Figure 12 As shown, the time interval between T5 and T9 is the pulse width of the programming voltage; the time interval between T5 and T7 is the rising phase of the programming voltage; and T8 is the time when the first pass voltage reaches its maximum value.

[0103] It should be known that in order to program the memory cells coupled to the word line WLn, the memory cells coupled to the word line WLn-1 and the word line WLn+1 in the same memory string must be in the on state. Figure 12 As shown in the programming voltage waveform, the time at which the first pass voltage rises to its maximum value cannot be later than the time at which the programming voltage drops from its maximum value. That is, the time at which the first pass voltage rises to its maximum value must be before T9. Furthermore, the programming process requires a certain amount of time, that is, the programming voltage needs to reach its maximum value for a period of time. Therefore, to reserve sufficient time for programming, the time interval between T8 and T9 cannot be too small. In other words, the time at which the first pass voltage rises to its maximum value must be before T9, and to reserve sufficient programming time, the time interval between the rising time of the second rising phase of the first pass voltage and the rising time of the second rising phase of the second pass voltage is affected by the pulse width of the programming voltage. Furthermore, the pulse width of the programming voltage includes the voltage rising phase and the holding phase at the maximum voltage value. If the entire programming voltage pulse width is constant, the length of the rising phase affects the duration of the holding phase of the maximum voltage value of the programming voltage, which in turn affects the time interval between the rising time of the second rising phase of the first pass voltage and the rising time of the second rising phase of the second pass voltage.

[0104] In some embodiments, the first pass voltage and the second pass voltage are provided by different voltage sources, and when the maximum voltage value of the first pass voltage is constant, the pulse width of each rising stage provided by the control voltage source is controlled to control the speed at which the first pass voltage reaches the maximum voltage value; or, when the maximum voltage value of the second pass voltage is constant, the pulse width of each rising stage provided by the control voltage source is controlled to control the speed at which the second pass voltage reaches the maximum voltage value.

[0105] Here, the first pass voltage and the second pass voltage have different rising times in at least one rising phase after the first rising phase. Therefore, the first pass voltage and the second pass voltage are provided by different power supplies. Furthermore, when the maximum voltage value of the first pass voltage is constant, the speed at which the first pass voltage reaches the maximum voltage value is controlled by controlling the pulse width of each rising phase provided by the voltage source. Furthermore, when the maximum voltage value of the second pass voltage is constant, the speed at which the second pass voltage reaches the maximum voltage value is controlled by controlling the pulse width of each rising phase provided by the voltage source.

[0106] Specific understanding, such as Figure 13As shown, the two rising phases of the first pass voltage are between T10 and T11, and between T14 and T15; and the two rising phases of the second pass voltage are between T10 and T11, and between T12 and T13. If the maximum voltage values ​​of the first and second pass voltages are constant, the speed at which the first pass voltage reaches its maximum voltage value can be controlled by controlling the lengths of T10 and T11, and T14 and T15, that is, the pulse widths during the rising phases. Similarly, the speed at which the second pass voltage reaches its maximum voltage value can be controlled by controlling the lengths of T10 and T11, and T12 and T13, that is, the pulse widths during the rising phases.

[0107] In some embodiments, after each rising phase ends, the maximum voltage value of the first pass voltage is equal to the maximum voltage value of the second pass voltage.

[0108] Based on the above description, during the programming of the memory cells coupled to the selected word line, the memory cells of the same memory string must be in the on state. Then, since some of the memory cells of the same memory string have been programmed and some are in the unprogrammed state (i.e., the erased state), when applying the pass voltage, the corresponding pass voltage can be applied according to the data state of the memory cell, or a larger pass voltage can be uniformly applied to make the memory cells of the same memory string except the memory cells to be programmed in the on state, so as to simplify the operation.

[0109] Here, as Figure 13 As shown, after each rising stage, the maximum voltage value of the first pass voltage and the maximum voltage value of the second pass voltage are equal, which can mean that the voltage value of the first pass voltage after time T15 and the voltage value of the second pass voltage after time T13 can be equal.

[0110] In some embodiments, the method may further include:

[0111] applying a third pass voltage to other word lines except the first word line, the second word line, and the selected word line;

[0112] After each rising phase ends, the maximum voltage value of the third pass voltage is different from the maximum voltage values ​​of the first pass voltage and the second pass voltage.

[0113] Here, the third pass voltage refers to the pass voltage applied to non-selected word lines other than the first and second word lines. Based on the above description, the maximum value of the third pass voltage is the same as the maximum value of the first and second pass voltages. However, in actual applications, different pass voltages may be applied to memory cells in different layers (or word line couplings) for other reasons, such as a large pass voltage causing hot electron injection (HCI). In other words, the maximum value of the third pass voltage may be different from the maximum values ​​of the first and second pass voltages.

[0114] In some embodiments, programming the memory cells coupled to the selected word line includes a plurality of pulse phases;

[0115] In which, in the previous pulse stage, a first sub-programming voltage is applied to the selected word line; in the next pulse stage, a second sub-programming voltage is applied to the selected word line; the voltage value of the first sub-programming voltage is smaller than the voltage value of the second sub-programming voltage.

[0116] What is described here is Incremental Step Pulse Programming (ISPP). That is, the memory cells coupled to the selected sub-line are programmed using the ISPP method. Here, the so-called ISPP can be based on a step voltage to gradually increase the word line bias voltage while programming multiple memory cells several times, so that the multiple memory cells are programmed to corresponding data states among multiple data states. Among them, the incremental step pulse V pgm For reference Figure 14 That is, the programming pulse applied to the word line coupled to the programmed memory cell is gradually increased in a certain increment until the programmed memory cell is programmed to the target data state. It should be noted that applying a programming pulse once can be called a programming loop (PGM Loop).

[0117] Here, that is, programming the memory cells coupled to the selected word line includes a plurality of pulse phases, each pulse phase corresponding to a sub-programming voltage, and as shown in FIG. Figure 14 As shown in FIG. 1 , in the previous pulse stage, the voltage value of the first sub-programming voltage applied is smaller than the second word programming voltage applied in the next pulse stage. The voltage waveform of each pulse stage can be as follows: Figure 12 The voltage waveform on the word line WLn is shown.

[0118] In some embodiments, programming the memory cells coupled to the selected word line includes multiple pulse phases; wherein,

[0119] In the previous pulse phase, a first sub-pass voltage is applied to the first word line, and a second sub-pass voltage is applied to the second word line;

[0120] In the next pulse phase, a third sub-pass voltage is applied to the first word line, and a fourth sub-pass voltage is applied to the second word line;

[0121] After each rising phase, the voltage value of the first sub-pass voltage is smaller than the voltage value of the third sub-pass voltage; and the voltage value of the second sub-pass voltage is smaller than the voltage value of the fourth sub-pass voltage.

[0122] Similarly, during the ISPP programming process, the pass voltage can also be stepped. That is, the maximum voltage value of the first sub-pass voltage applied to the first word line in the previous pulse phase is smaller than the maximum voltage value of the third sub-pass voltage applied to the first word line in the next pulse phase. Similarly, the second sub-pass voltage applied to the second word line in the previous pulse phase is smaller than the fourth sub-pass voltage applied to the second word line in the next pulse phase.

[0123] In some embodiments, programming of the memory cells coupled to the selected word line includes multiple pulse stages; and in each pulse stage, the pass voltage applied to the first word line and the pass voltage applied to the second word line each include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the pass voltage applied to the first word line and the pass voltage applied to the second word line is different.

[0124] It should be noted that, in each of the multiple pulse phases during the ISPP programming process, the voltage waveforms of the selected word line, the first word line, and the second word line can be as follows: Figure 12 As shown, the pass voltage applied to the first word line and the pass voltage applied to the second word line include at least two rising stages, and the rising time of at least one rising stage in the other rising stages after the first rising stage is different.

[0125] The programming method provided in the embodiment of the present application adjusts the rising time of the pass voltage applied to the two word lines adjacent to the selected sub-line, and the rising time of at least one rising stage in the other rising stages after the first rising stage is different. Through the coupling effect between WL, the programming voltage of the selected word line can be made more uniform, thereby improving the programming efficiency, thereby improving programming interference, and increasing RWM.

[0126] like Figure 15 As shown, according to another aspect of an embodiment of the present application, a memory device 150 is provided, comprising: a memory cell array 1501, wherein the memory cell array comprises a plurality of memory strings; each of the memory strings comprises a plurality of memory cells;

[0127] A plurality of word lines; each word line is coupled to a corresponding memory cell in each of the memory strings;

[0128] and a peripheral circuit 1502 coupled to the plurality of word lines; wherein the peripheral circuit 1502 is configured as follows:

[0129] applying a programming voltage to the selected word line;

[0130] applying a first pass voltage to a first word line adjacent to the selected word line; and

[0131] applying a second pass voltage to a second word line adjacent to the selected word line;

[0132] In which, the first pass voltage and the second pass voltage include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the first pass voltage and the second pass voltage is different, and the rising time is the time when the voltage value of the pass voltage starts to increase based on a certain voltage value.

[0133] In some embodiments, the at least two rising phases include: two rising phases; and a rising time of the second rising phase of the second pass voltage is earlier than a rising time of the second rising phase of the first pass voltage.

[0134] In some embodiments, the time interval between the rising time of the second rising phase of the first pass voltage and the rising time of the second rising phase of the second pass voltage is affected by the pulse width of the programming voltage and the rising speed of the rising phase of the programming voltage.

[0135] In some embodiments, the peripheral circuit further includes a first voltage source and a second voltage source, wherein;

[0136] The first voltage source is configured to: apply the first pass voltage to the first word line;

[0137] The second voltage source is configured to: apply the second pass voltage to the second word line,

[0138] Among them, when the maximum voltage value of the first pass voltage is constant, the speed at which the first pass voltage reaches the maximum voltage value is controlled by controlling the pulse width of each rising stage provided by the first voltage source; when the maximum voltage of the second pass voltage is constant, the speed at which the second pass voltage reaches the maximum voltage value is controlled by controlling the pulse width of each rising stage provided by the second voltage source.

[0139] In some embodiments, the peripheral circuit is further configured to: apply a third pass voltage to other word lines among the multiple word lines except the first word line, the second word line and the selected word line; wherein, after each rising stage, the maximum voltage value of the third pass voltage is different from the maximum voltage values ​​of the first pass voltage and the second pass voltage.

[0140] In some embodiments, programming the memory cells coupled to the selected word line includes a plurality of pulse phases;

[0141] In which, in the previous pulse stage, a first sub-programming voltage is applied to the selected word line; in the next pulse stage, a second sub-programming voltage is applied to the selected word line; the voltage value of the first sub-programming voltage is smaller than the voltage value of the second sub-programming voltage.

[0142] In some embodiments, programming the memory cells coupled to the selected word line includes multiple pulse phases; wherein,

[0143] In the previous pulse phase, a first sub-pass voltage is applied to the first word line, and a second sub-pass voltage is applied to the second word line;

[0144] In the next pulse phase, a third sub-pass voltage is applied to the first word line, and a fourth sub-pass voltage is applied to the second word line;

[0145] After each rising phase, the voltage value of the first sub-pass voltage is smaller than the voltage value of the third sub-pass voltage; and the voltage value of the second sub-pass voltage is smaller than the voltage value of the fourth sub-pass voltage.

[0146] In some embodiments, programming of the memory cells coupled to the selected word line includes multiple pulse stages; and in each pulse stage, the pass voltage applied to the first word line and the pass voltage applied to the second word line each include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the pass voltage applied to the first word line and the pass voltage applied to the second word line is different.

[0147] In some embodiments, after each rising phase ends, the maximum voltage value of the first pass voltage is equal to the maximum voltage value of the second pass voltage.

[0148] It should be noted that the memory device 150, memory cell array 1501 and peripheral circuit 1502 described here are similar to those described above. Figures 1 to 6 The memory device, memory cell array, and peripheral circuit structures described in the embodiment are basically similar and will not be described in detail here. Here, only the structures concerned with the embodiment of the present application and the structures related to the programming method are described.

[0149] According to another aspect of the embodiments of the present application, a memory system is provided, comprising: one or more memory devices as described in any one of the above items and a memory controller coupled to and controlling the memory devices.

[0150] In some embodiments, the memory system is included in a solid state drive (SSD) or a memory card.

[0151] It should be noted that, as mentioned above Figures 1 to 3 Description, the memory system can communicate with the host (Host). The host and / or the memory system can be included in various products, such as Internet of Things (IoT) devices, such as refrigerators or other devices, sensors, motors, mobile communication devices, cars, unmanned driving, etc., to support product processing, communication or control. In one embodiment, the memory system can be a discrete memory or memory component of the host device. In other embodiments, the memory system can also be part of an integrated circuit, such as part of a system on chip (SOC). At this time, the memory system is stacked or otherwise assembled with one or more components of the host. In other embodiments, the aforementioned memory system can be implemented and packaged in products such as memory cards, drives, etc. In one example, the memory controller and a single memory device of the memory system can be integrated into the memory card, as shown above. Figure 2 In another example, the memory controller and multiple memory devices can be integrated into the SSD, as shown in the previous example. Figure 3 shown.

[0152] In some embodiments, the host described above may include a processor and a host RAM, wherein the host RAM may include DRAM, SDRAM, or any other suitable volatile or non-volatile memory device. One or more communication interfaces may be provided on the memory system to communicate with one or more components in the host. The one or more components in the host may be a Serial Advanced Technology Attachment (SATA) interface, a high-speed peripheral component interconnect (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC interface, or a SATA-based microprocessor. TM interfaces, etc. The host may also include electronic components, a memory card reader, or one or more other electronic components external to the memory system.

[0153] In some embodiments, a memory controller may receive instructions from a host and communicate with the memory device, such as executing a write or erase instruction to transfer data to one or more memory cells, planes, sub-blocks, blocks, or pages in the memory device; or executing a read instruction to transfer data to the host. In hardware, the memory controller may include one or more controller units, circuits, or components configured to control access across the memory device and provide a translation layer between the host and the memory system. The memory controller may also include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from the memory device. The memory controller may also include a memory management unit and an array control unit. The memory management unit may include circuit hardware or firmware, such as multiple components or integrated circuits associated with various memory management functions. Taking NAND memory as an example, memory system operation or management functions are described. Those skilled in the art will appreciate that other forms of non-volatile memory may have similar memory operation or management functions. NAND memory management functions may include wear leveling, such as garbage collection or reclamation, error detection or correction, block retirement, or one or more other memory management functions. The memory management unit may process host instructions into commands recognizable by the memory system, such as parsing or formatting instructions received from the host into commands related to the operation of the memory device. Alternatively, the memory management unit may generate device commands for the array control unit or one or more other components of the memory system, such as commands implementing various memory management functions. The memory management unit may be configured to include a set of management tables for maintaining various information associated with one or more components of the memory system, such as various information related to a memory cell array or one or more memory cells coupled to the memory controller. For example, the management tables may include information such as block age, block erase count, error history, or one or more error counts for one or more blocks of memory cells coupled to the memory controller. Error counts may include operation error counts, read bit error counts, etc. In some embodiments, if the detected error count exceeds a certain threshold, the bit error is considered uncorrectable. In some embodiments, the management tables may maintain counts of correctable or uncorrectable bit errors. The management tables may also include one or more L2P tables, which include one or more L2P pointers that associate logical addresses with physical addresses at the memory device. In some embodiments, the management table may include an unencrypted L2P table and / or an encrypted L2P table. The unencrypted L2P table may include an L2P pointer indicating an unencrypted logical address and an unencrypted physical address; the encrypted L2P table may include an encrypted physical address and an encrypted L2P pointer indicating an unencrypted logical address.In actual applications, the management table can be displayed in the memory management unit, that is, the management table can be stored in the RAM of the memory controller. In other embodiments, the management table can also be stored in the memory device. During use, the memory management unit can read part or all of the cached management table from the RAM of the memory controller; it can also read the management table from the memory device.

[0154] The array control unit may include a circuit system or components configured to control and complete the following memory device operations, such as controlling the writing of data to one or more memory cells in a memory system coupled to the memory controller, reading data from the one or more memory cells, or erasing the one or more memory cells. The array control unit may receive commands sent by the host or host commands generated internally by the memory management unit. The host commands may be commands associated with wear leveling, error detection or correction, etc.

[0155] The array control unit may further include an error correction code (ECC) component that may include an ECC engine or other circuitry for detecting or correcting errors associated with writing data to or reading data from one or more memory cells in a memory system coupled to the memory controller. The memory controller is configured to effectively detect and recover from error events associated with various operations or data storage, such as bit errors, operational errors, etc., while maintaining the integrity of data transmitted between a host and the memory system or the integrity of stored data, such as by using redundant RAID storage, and removing, such as retiring, failed memory resources, such as memory cells, memory arrays, pages, blocks, etc., to prevent future errors.

[0156] In the aforementioned memory system, in some embodiments, a memory device is provided, comprising: a memory cell array, the memory cell array comprising a plurality of memory strings; each of the memory strings comprising a plurality of memory cells;

[0157] A plurality of word lines; each word line is coupled to a corresponding memory cell in each of the memory strings;

[0158] and a peripheral circuit coupled to the plurality of word lines; wherein the peripheral circuit is configured as follows:

[0159] applying a programming voltage to the selected word line;

[0160] applying a first pass voltage to a first word line adjacent to the selected word line; and

[0161] applying a second pass voltage to a second word line adjacent to the selected word line;

[0162] In which, the first pass voltage and the second pass voltage include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the first pass voltage and the second pass voltage is different, and the rising time is the time when the voltage value of the pass voltage starts to increase based on a certain voltage value.

[0163] In the above solution, the at least two rising stages include: two rising stages; and a rising moment of the second rising stage of the second pass voltage is earlier than a rising moment of the second rising stage of the first pass voltage.

[0164] In the above solution, the time interval between the rising moment of the second rising phase of the first pass voltage and the rising moment of the second rising phase of the second pass voltage is affected by the pulse width of the programming voltage and the rising speed of the rising phase of the programming voltage.

[0165] In the above solution, the peripheral circuit further includes a first voltage source and a second voltage source, wherein;

[0166] The first voltage source is configured to: apply the first pass voltage to the first word line;

[0167] The second voltage source is configured to: apply the second pass voltage to the second word line,

[0168] Among them, when the maximum voltage value of the first pass voltage is constant, the speed at which the first pass voltage reaches the maximum voltage value is controlled by controlling the pulse width of each rising stage provided by the first voltage source; when the maximum voltage of the second pass voltage is constant, the speed at which the second pass voltage reaches the maximum voltage value is controlled by controlling the pulse width of each rising stage provided by the second voltage source.

[0169] In the above scheme, the peripheral circuit is further configured to: apply a third pass voltage to other word lines among the multiple word lines except the first word line, the second word line and the selected word line; wherein, after each rising stage, the maximum voltage value of the third pass voltage is different from the maximum voltage values ​​of the first pass voltage and the second pass voltage.

[0170] In the above scheme, programming the memory cells coupled to the selected word line includes a plurality of pulse phases;

[0171] In which, in the previous pulse stage, a first sub-programming voltage is applied to the selected word line; in the next pulse stage, a second sub-programming voltage is applied to the selected word line; the voltage value of the first sub-programming voltage is smaller than the voltage value of the second sub-programming voltage.

[0172] In the above scheme, programming the memory cells coupled to the selected word line includes multiple pulse phases; wherein,

[0173] In the previous pulse phase, a first sub-pass voltage is applied to the first word line, and a second sub-pass voltage is applied to the second word line;

[0174] In the next pulse phase, a third sub-pass voltage is applied to the first word line, and a fourth sub-pass voltage is applied to the second word line;

[0175] After each rising phase, the voltage value of the first sub-pass voltage is smaller than the voltage value of the third sub-pass voltage; and the voltage value of the second sub-pass voltage is smaller than the voltage value of the fourth sub-pass voltage.

[0176] In the above scheme, programming of the memory cell coupled to the selected word line includes multiple pulse stages; and in each pulse stage, the pass voltage applied to the first word line and the pass voltage applied to the second word line both include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the pass voltage applied to the first word line and the pass voltage applied to the second word line is different.

[0177] In the above solution, after each rising phase, the maximum voltage value of the first pass voltage and the maximum voltage value of the second pass voltage are equal. It should be noted that the memory system includes the aforementioned memory device, and therefore, both have the same technical features. Terms used in the memory system have been explained in detail in the aforementioned memory device and are equally applicable here, so they will not be repeated here.

[0178] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments may be used, such as those available to a person of ordinary skill in the art upon reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to simplify the present invention. This should not be interpreted as meaning that unclaimed disclosed features are essential to any claim. On the contrary, the disclosed subject matter may be less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment, and it is expected that these embodiments may be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

Claims

1. A method for programming a memory device, characterized in that: include: applying a programming voltage to the selected word line; applying a first pass voltage to a first word line adjacent to the selected word line; and applying a second pass voltage to a second word line adjacent to the selected word line; In which, the first pass voltage and the second pass voltage include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the first pass voltage and the second pass voltage is different, and the rising time is the time when the voltage value starts to increase based on a certain voltage value.

2. The programming method according to claim 1, wherein: The at least two ascending stages include: two ascending stages; A rising moment of the second rising phase of the second pass voltage is earlier than a rising moment of the second rising phase of the first pass voltage.

3. The programming method according to claim 2, wherein: The time interval between the rising time of the second rising phase of the first pass voltage and the rising time of the second rising phase of the second pass voltage is affected by the pulse width of the programming voltage and the rising speed of the rising phase of the programming voltage.

4. The programming method according to claim 1, wherein: The first pass voltage and the second pass voltage are provided by different voltage sources, and when the maximum voltage value of the first pass voltage is constant, the pulse width of each rising stage provided by the control voltage source is controlled to control the speed at which the first pass voltage reaches the maximum voltage value; or, when the maximum voltage value of the second pass voltage is constant, the pulse width of each rising stage provided by the control voltage source is controlled to control the speed at which the second pass voltage reaches the maximum voltage value.

5. The programming method according to claim 1 or 4, characterized in that: After each rising phase ends, the maximum voltage value of the first pass voltage is equal to the maximum voltage value of the second pass voltage.

6. The programming method according to claim 1, wherein: The method further comprises: applying a third pass voltage to other word lines except the first word line, the second word line, and the selected word line; After each rising phase ends, the maximum voltage value of the third pass voltage is different from the maximum voltage values ​​of the first pass voltage and the second pass voltage.

7. The programming method according to claim 1, wherein: Programming memory cells coupled to the selected word line includes a plurality of pulse phases; In which, in the previous pulse stage, a first sub-programming voltage is applied to the selected word line; in the next pulse stage, a second sub-programming voltage is applied to the selected word line; the voltage value of the first sub-programming voltage is smaller than the voltage value of the second sub-programming voltage.

8. The programming method according to claim 1, wherein: Programming the memory cells coupled to the selected word line includes a plurality of pulse phases; wherein, In the previous pulse phase, a first sub-pass voltage is applied to the first word line, and a second sub-pass voltage is applied to the second word line; In the next pulse phase, a third sub-pass voltage is applied to the first word line, and a fourth sub-pass voltage is applied to the second word line; After each rising phase, the voltage value of the first sub-pass voltage is smaller than the voltage value of the third sub-pass voltage; and the voltage value of the second sub-pass voltage is smaller than the voltage value of the fourth sub-pass voltage.

9. The programming method according to claim 1, wherein: Programming the memory cells coupled to the selected word line includes multiple pulse stages; and in each pulse stage, the pass voltage applied to the first word line and the pass voltage applied to the second word line each include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the pass voltage applied to the first word line and the pass voltage applied to the second word line is different.

10. A memory device, characterized in that: include: a memory cell array, the memory cell array comprising a plurality of memory strings; Each of the storage strings includes a plurality of storage units; multiple word lines; Each word line is coupled to a corresponding memory cell in each of the memory strings; and a peripheral circuit coupled to the plurality of word lines; wherein the peripheral circuit is configured as follows: applying a programming voltage to the selected word line; applying a first pass voltage to a first word line adjacent to the selected word line; and applying a second pass voltage to a second word line adjacent to the selected word line; In which, the first pass voltage and the second pass voltage include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the first pass voltage and the second pass voltage is different, and the rising time is the time when the voltage value of the pass voltage starts to increase based on a certain voltage value.

11. The memory device according to claim 10, wherein: The at least two rising phases include: two rising phases; and a rising moment of the second rising phase of the second pass voltage is earlier than a rising moment of the second rising phase of the first pass voltage.

12. The memory device according to claim 11, wherein: The time interval between the rising time of the second rising phase of the first pass voltage and the rising time of the second rising phase of the second pass voltage is affected by the pulse width of the programming voltage and the rising speed of the rising phase of the programming voltage.

13. The memory device according to claim 10, wherein: The peripheral circuit further includes a first voltage source and a second voltage source, wherein; The first voltage source is configured to: apply the first pass voltage to the first word line; The second voltage source is configured to: apply the second pass voltage to the second word line, Among them, when the maximum voltage value of the first pass voltage is constant, the speed at which the first pass voltage reaches the maximum voltage value is controlled by controlling the pulse width of each rising stage provided by the first voltage source; when the maximum voltage of the second pass voltage is constant, the speed at which the second pass voltage reaches the maximum voltage value is controlled by controlling the pulse width of each rising stage provided by the second voltage source.

14. The memory device according to claim 10, wherein: The peripheral circuit is further configured to: apply a third pass voltage to other word lines among the multiple word lines except the first word line, the second word line and the selected word line; wherein, after each rising stage, the maximum voltage value of the third pass voltage is different from the maximum voltage values ​​of the first pass voltage and the second pass voltage.

15. The memory device according to claim 10, wherein: Programming memory cells coupled to the selected word line includes a plurality of pulse phases; In which, in the previous pulse stage, a first sub-programming voltage is applied to the selected word line; in the next pulse stage, a second sub-programming voltage is applied to the selected word line; the voltage value of the first sub-programming voltage is smaller than the voltage value of the second sub-programming voltage.

16. The memory device according to claim 10, wherein: Programming the memory cells coupled to the selected word line includes a plurality of pulse phases; wherein, In the previous pulse phase, a first sub-pass voltage is applied to the first word line, and a second sub-pass voltage is applied to the second word line; In the next pulse phase, a third sub-pass voltage is applied to the first word line, and a fourth sub-pass voltage is applied to the second word line; After each rising phase, the voltage value of the first sub-pass voltage is smaller than the voltage value of the third sub-pass voltage; and the voltage value of the second sub-pass voltage is smaller than the voltage value of the fourth sub-pass voltage.

17. The memory device according to claim 10, wherein: Programming the memory cells coupled to the selected word line includes multiple pulse stages; and in each pulse stage, the pass voltage applied to the first word line and the pass voltage applied to the second word line each include at least two rising stages, and the rising time of at least one of the other rising stages after the first rising stage of the pass voltage applied to the first word line and the pass voltage applied to the second word line is different.

18. The memory device according to claim 10 or 13, characterized in that After each rising phase ends, the maximum voltage value of the first pass voltage is equal to the maximum voltage value of the second pass voltage.

19. A memory system, characterized in that: include: One or more memory devices according to any one of claims 10 to 18, and a memory controller coupled to the memory device and configured to control the memory device.

20. The memory system according to claim 19, wherein: The memory system is contained within a solid state drive SSD or a memory card.

Images