A high common-mode rejection ratio precision current sense amplifier

Abstract

The application discloses a high common-mode rejection ratio precision current detection amplifier, comprising: a high common-mode rejection ratio input stage circuit, which samples an input common-mode voltage signal through VCMCP1, outputs a boosted voltage to a first chopping switch and a PMOS input pair tube, and provides an input stage power potential; a transconductance amplification circuit, which adopts a chopping architecture, is connected with the high common-mode rejection ratio input stage circuit, and comprises a second chopping switch, a second amplifier, a third amplifier and a ripple suppression loop, is used for reducing a misadjustment voltage and an output ripple, and generates an output voltage VOUT; and a precision resistance trimming network, in which an input common-mode voltage signal is trimmed for resistance mismatch through a common-mode rejection ratio trimming circuit, and VCMCP2 provides a control voltage for trimming logic, so that a conduction resistance of a trimming switch is constant. The amplifier can effectively solve the problems of rail-to-rail input stage misadjustment voltage drift, resistance network mismatch and insufficient common-mode rejection ratio in the prior art.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high common-mode rejection ratio precision current sensing amplifier. Background Technology

[0002] High CMRR (Common-Mode Rejection Ratio), low offset voltage, and low noise precision operational amplifiers are widely used in precision systems, such as building precision constant current sources, instrumentation amplifiers, and current-sensing amplifiers. However, general low-voltage differential amplifiers typically face limitations such as large amplifier offset voltage, sudden shifts in input stage transistor switching offset voltage, and significant mismatch in the differential resistor matching network. Therefore, achieving high CMRR requires addressing both the precision operational amplifier core and the resistor matching network.

[0003] For precision operational amplifier (op-amp) core design, mainstream research in academia and industry focuses on suppressing output ripple based on chopper architectures. Among these, the Auto-correction Feedback (ACFB) is widely used due to its excellent offset voltage and ripple suppression, meeting the offset voltage and ripple requirements of precision differential amplifiers. However, this structure still suffers from the common-mode switching point problem. The op-amp rail-to-rail input uses NMOS and PMOS transistor pairs for switching, causing a sudden change in offset voltage near the common-mode switching point. This results in a decrease in the Common-Mode Reduction Ratio (CMRR) at the common-mode switching point, failing to meet the requirement of 140dB across the entire common-mode range of the rail-to-rail input.

[0004] For precision matching resistor trimming networks, common methods include thin-film resistor matching technology, pre-package trimming technology, and E-TRIM technology. Thin-film resistors are widely used in the design of differential amplifiers and current sense amplifiers due to their low temperature drift and high matching performance. However, achieving a CMRR of 140dB through matching would result in significant waste of chip area. For pre-package trimming, the accuracy of the trimming module can decrease due to post-package stress and external environmental factors, thus reducing the post-package CMRR. Therefore, the best approach is to package first and then trim. However, post-package trimming typically requires a trimming switch. For different power supply voltages and common-mode levels on both sides of the switch, the switch's on-resistance cannot maintain a constant value, leading to a decrease in trimming accuracy.

[0005] Therefore, the intrinsic CMRR and tuning logic accuracy of precision differential amplifiers need further research in order to achieve a CMRR of 140dB. Summary of the Invention

[0006] The problem to be solved by this invention is to provide a high common-mode rejection ratio precision current sense amplifier to solve the problems of rail-to-rail input stage offset voltage drift, resistor network mismatch and insufficient common-mode rejection ratio in the prior art.

[0007] This invention adopts the following technical solution: a high common-mode rejection ratio precision current sensing amplifier, comprising:

[0008] High common-mode rejection ratio input stage circuit: The input common-mode voltage signals VINN and VINP are sampled by the first common-mode voltage sampling charge pump VCMCP1, and the output drive voltage Vboost is sent to the first chopper switch CHOP1 and the PMOS input pair to provide the input stage power supply potential;

[0009] Transconductance amplifier circuit: adopts a chopper architecture and is connected to the high common-mode rejection ratio input stage circuit, including: second chopper switch CHOP2, second amplifier GM2, third amplifier GM3 and ripple suppression loop, used to reduce offset voltage and output ripple, and generate output voltage VOUT;

[0010] The precision resistor adjustment network includes: a common-mode rejection ratio (CMRR) adjustment circuit and a second common-mode voltage sampling charge pump (VCMCP2). The CMRR adjustment circuit is used to adjust the resistor mismatch of the current sensing amplifier, and the second common-mode voltage sampling charge pump (VCMCP2) provides a control voltage for the adjustment logic to keep the on-resistance of the adjustment switch constant.

[0011] The voltage signal VINP is input to the high common-mode rejection ratio input stage circuit through the first resistor R1, and then input to the precision resistor adjustment network through the second resistor R2.

[0012] The voltage signal VINN is input to the high common-mode rejection ratio input stage circuit through the third resistor R3, and then connected to the output voltage VOUT through the fourth resistor R4.

[0013] Preferably, the high common-mode rejection ratio input stage circuit includes: a first common-mode voltage sampling charge pump VCMCP1, a first chopper switch CHOP1, a first amplifier GM1, and a fourth amplifier GM4;

[0014] The common-mode voltage signals VINN and VINP are simultaneously connected to the two input terminals of the first common-mode voltage sampling charge pump VCMCP1, the first chopper switch CHOP1, and the fourth amplifier GM4.

[0015] The first common-mode voltage sampling charge pump VCMCP1 has its output terminal simultaneously input to the first chopper switch CHOP1, the first amplifier GM1, and the fourth amplifier GM4 to ensure that the on-resistance of the input to the first chopper switch CHOP1 remains constant.

[0016] The two output terminals of the first chopper switch CHOP1 are respectively connected to the two input terminals of the first amplifier GM1, serving as the input signals of the first amplifier GM1;

[0017] The two output terminals of the first amplifier GM1 are simultaneously connected to the input terminal of the second chopper switch CHOP2 and the output terminal of the ripple suppression loop to suppress the offset voltage and ripple of the first amplifier GM1.

[0018] The two output terminals of the fourth amplifier GM4 are connected to the input terminals of the subsequent third amplifier GM3 to improve the bandwidth and high-frequency response stability of the operational amplifier.

[0019] Preferably, in the transconductance amplifier circuit, the input terminal of the second chopper switch CHOP2 is connected to the output terminal of the first amplifier GM1, and the output terminal is connected in sequence to the second amplifier GM2 and the third amplifier GM3;

[0020] The ripple suppression loop is connected in parallel to the second chopper switch CHOP2, with its output terminal connected to the output terminal of the first amplifier GM1 and its input terminal connected to the input terminal of the second amplifier GM2, in order to reduce offset voltage and output ripple.

[0021] Preferably, the first common-mode voltage sampling charge pump VCMCP1 and the second common-mode voltage sampling charge pump VCMCP2 have the same structure, both including: a common-mode voltage buffer, a control LDO, a charge pump, and control logic, with the rear end connected to a trim switch;

[0022] The control LDO is connected to the power supply VDD and outputs a stable power supply LVDD to the charge pump and control logic.

[0023] The buffer buffers the input common-mode voltage signal, enhances the signal driving capability, and outputs the common-mode voltage VCM to the charge pump.

[0024] The charge pump utilizes the charging and discharging characteristics of a capacitor to boost and convert the input common-mode voltage VCM, generating a drive voltage Vboost to drive the adjustment switch connected to the back end.

[0025] The control logic performs logical control on the charging and discharging process of the charge pump according to the clock input signal, and adjusts the voltage value of the drive voltage Vboost.

[0026] Preferably, the adjustment switch includes: an LS logic selection module and a first NMOS transistor MN1. The LS logic selection module controls the stable on-resistance of the first NMOS transistor MN1 to improve the accuracy of the adjustment logic.

[0027] The charge pump samples and processes the input common-mode voltages VIP1 and VIP2 to generate a common-mode voltage VCM and a drive voltage Vboost, which are then input to the LS logic selection module. The drive voltage Vboost = VCM + 1.5V.

[0028] The LS logic selection module has two parts. The output terminal is connected to the gate of the first NMOS transistor MN1. It selects whether to pass the VCM voltage to the gate of the first NMOS transistor MN1 according to the control logic signal, so as to drive the first NMOS transistor MN1.

[0029] The source of the first NMOS transistor MN1 is connected to the input common-mode voltage, and the drain is connected to the output voltage OUT.

[0030] Preferably, the high common-mode rejection ratio input stage circuit further includes: a trimming switch circuit, a PMOS input pair, an NMOS transistor group, a PMOS transistor group, and a folded common-source common-gate module;

[0031] The PMOS input pair includes: a first PMOS transistor MP1 and a second PMOS transistor MP2;

[0032] The first common-mode voltage sampling charge pump VCMCP1 takes in the common-mode voltage signal, and outputs the voltage VCM and the driving voltage Vboost after being boosted by the charge pump at its two output terminals respectively. After being selected by two LS logic selection modules, the output voltage OUT is sent to the switch groups CH1 and CH2.

[0033] The switch group CH1 and CH2 output two voltages, one of which is input to the gate of the first PMOS transistor MP1 and the gate of the third PMOS transistor MP3 in the PMOS transistor group, and the other of which is input to the gate of the second PMOS transistor MP2 and the gate of the fourth PMOS transistor MP4 in the PMOS transistor group.

[0034] The drain of the first PMOS transistor MP1 is connected to the source of the third PMOS transistor MP3, and the drain of the second PMOS transistor MP2 is connected to the source of the fourth PMOS transistor MP4; the drains of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the folded common source and common gate module.

[0035] The folded common source and common gate module is also connected to power supply VDD and ground GND to provide it with power and ground potential during normal operation.

[0036] Preferably, in the high common-mode rejection ratio input stage circuit, the PMOS transistor group is used to provide mirror current and cascode protection;

[0037] The driving voltage Vboost is input to the source of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 in the PMOS transistor group;

[0038] The drain of the fifth PMOS transistor MP5 is connected to the source of the seventh PMOS transistor MP7, and the drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP8.

[0039] The gate of the fifth PMOS transistor MP5 is connected to the gates of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7. The gate of the sixth PMOS transistor MP6 is connected to the gate of the eighth PMOS transistor MP8 and then to the drain of the eighth PMOS transistor MP8.

[0040] The drain of the seventh PMOS transistor MP7 is connected to the source of the first PMOS transistor MP1 and the second PMOS transistor MP2, and the drain of the eighth PMOS transistor MP8 is connected to the source of the fourth NMOS transistor MN4 in the NMOS transistor group.

[0041] Preferably, in the high common-mode rejection ratio input stage circuit, the NMOS transistor group is used as a current mirror;

[0042] The first NMOS transistor MN1, the second NMOS transistor MN2, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 in the NMOS transistor group share a common gate and are connected to the drain of the fifth NMOS transistor MN5;

[0043] The power supply VDD is connected to the current mirror input, the current mirror output is connected to the drain of the fifth NMOS transistor MN5, the source of the fifth NMOS transistor MN5 is connected to the drain of the first NMOS transistor MN1, the source of the fourth NMOS transistor MN4 is connected to the drain of the second NMOS transistor MN2, and the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are grounded.

[0044] Preferably, in the precision resistor adjustment network, the common-mode rejection ratio adjustment circuit includes: a resistor array, a switch array, and an adjustment logic module;

[0045] The resistor array includes resistors RT, ..., RTN+1, RTN, ..., RT1 connected in series, with the input terminal connected to the input signal;

[0046] Among them, resistors RTN+1*, RTN*, ..., RT1 are connected in parallel with resistors RTN+1, RTN, ..., RT1 respectively;

[0047] The switch array includes switches: SWN+1, SWN, ..., SW1, which are connected after resistors RTN+1*, RTN*, ..., RT1*, respectively. Each switch is controlled by adjustment bits bitn+1, bitn, ..., bit1 in the adjustment logic module to selectively connect or disconnect the resistors to adjust the total resistance value of the resistor array and output it at the output terminal of the resistor array.

[0048] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0049] 1. High CMRR: The high common-mode rejection ratio input stage circuit of this invention improves the intrinsic CMRR of the precision operational amplifier core through the design of VCMCP circuit and PMOS input pair, which is significantly better than the prior art.

[0050] 2. Low offset voltage and low noise: This invention reduces amplifier noise and offset voltage through the use of chopper structure and loop ripple suppression structure, making it suitable for high-precision applications.

[0051] 3. Wide power supply voltage range: The precision current sensing amplifier of this invention can operate with a power supply voltage of 1.8V to 5.5V, making it suitable for a variety of low-voltage applications. Attached Figure Description

[0052] Figure 1 This is a schematic diagram of the precision current detection amplifier structure of the present invention;

[0053] Figure 2 This is a schematic diagram of the VCMCP circuit of the present invention;

[0054] Figure 3 This is a schematic diagram of the adjustment switch of the present invention;

[0055] Figure 4 This is a schematic diagram of the high common-mode rejection ratio input stage circuit of the present invention;

[0056] Figure 5 This is a schematic diagram of the precision resistor adjustment network of the present invention. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the application will be further described in detail below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments involved in this invention. All non-innovative embodiments based on these embodiments by other researchers in the art are within the protection scope of this invention. Furthermore, the step numbers in the embodiments of this invention are only set for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0058] In one embodiment of the present invention, a high common-mode rejection ratio precision current-sensing amplifier, such as... Figure 1 As shown, it mainly includes: a high common-mode rejection ratio input stage circuit, a precision resistor adjustment network, and a transconductance amplifier circuit.

[0059] To improve the intrinsic CMRR of the precision operational amplifier core, this embodiment designs a high common-mode rejection ratio input stage circuit. The first common-mode voltage sampling charge pump VCMCP1 samples the input common-mode signals VINN and VINP of the operational amplifier and outputs a potential Vboost to provide the input stage power supply potential for the first chopper switch CHOP1 and amplifiers GM1 and GM4. This ensures that the operating state of the input pair transistors and the chopper switch transistors remains unchanged with the input common-mode voltage, thereby improving the intrinsic CMRR of the operational amplifier.

[0060] Among them, the common-mode voltage signals VINN and VINP are simultaneously connected to the two input terminals of the first common-mode voltage sampling charge pump VCMCP1, the first chopper switch CHOP1, and the fourth amplifier GM4.

[0061] Specifically, the output of the first common-mode voltage sampling charge pump VCMCP1 is simultaneously input to the first chopper switch CHOP1, the first amplifier GM1, and the fourth amplifier GM4 to ensure that the on-resistance of the input to the first chopper switch CHOP1 remains constant.

[0062] The two output terminals of the first chopper switch CHOP1 are connected to the two input terminals of the first amplifier GM1, respectively, as the input signals of the first amplifier GM1.

[0063] The two output terminals of the first amplifier GM1 are simultaneously connected to the input terminal of the second chopper switch CHOP2 and the output terminal of the ripple suppression loop to suppress the offset voltage and ripple of the first amplifier GM1.

[0064] The two output terminals of the fourth amplifier GM4 are connected to the input terminals of the subsequent third amplifier GM3 to improve the bandwidth and high-frequency response stability of the op-amp.

[0065] Furthermore, to reduce noise and improve power efficiency, the transconductance amplifier circuit uses a chopper architecture and a ripple suppression loop to reduce the operational amplifier's offset voltage and output ripple.

[0066] In this embodiment, the transconductance amplifier circuit is connected to the high common-mode rejection ratio input stage circuit, including: a second chopper switch CHOP2, a second amplifier GM2, a third amplifier GM3, and a ripple suppression loop, which are used to reduce offset voltage and output ripple and generate output voltage VOUT.

[0067] The input terminal of the second chopper switch CHOP2 is connected to the output terminal of the first amplifier GM1, and the output terminal is connected to the second amplifier GM2 and the third amplifier GM3 in turn.

[0068] The ripple suppression loop is connected in parallel to the second chopper switch CHOP2. Its output is connected to the output of the first amplifier GM1, and its input is connected to the input of the second amplifier GM2. This is used to reduce offset voltage and output ripple.

[0069] Furthermore, to improve the accuracy of the resistor adjustment network, this embodiment uses a voltage sampling charge pump again through a precision resistor adjustment network to provide the adjustment module switch with a stable on-resistance that changes with the REF voltage. Combined with the precision matching resistor adjustment network, the CMRR of the differential operational amplifier can be tuned by 140dB.

[0070] In this embodiment, the precision resistor adjustment network specifically includes: a common-mode rejection ratio (CMRR) adjustment circuit and a second common-mode voltage sampling charge pump (VCMCP2). The current detection amplifier adjusts the resistor mismatch through the CMRR adjustment circuit and provides control voltage to the adjustment logic through the second common-mode voltage sampling charge pump (VCMCP2) to keep the on-resistance of the adjustment switch constant.

[0071] The voltage signal VINP is input to the high common-mode rejection ratio input stage circuit through the first resistor R1, and then input to the precision resistor adjustment network through the second resistor R2; the voltage signal VINN is input to the high common-mode rejection ratio input stage circuit through the third resistor R3, and then connected to the output voltage VOUT through the fourth resistor R4.

[0072] Specifically, this embodiment combines a common-mode voltage sampling buffer and a charge pump to design a circuit in which the driving voltage changes with the sampling voltage, ensuring the stability of the on-resistance of the adjustment switch.

[0073] In this embodiment, the first common-mode voltage sampling charge pump VCMCP1 and the second common-mode voltage sampling charge pump VCMCP2 have the same structure, such as... Figure 2 As shown, each component includes: a common-mode voltage buffer, a control LDO, a charge pump, and control logic, with the back end connected to a trim switch.

[0074] The LDO input is VDD and the output is LVDD, providing a stable power supply for the entire circuit. The buffer buffers the input common-mode voltage signals VIP1 and VIP2 to enhance the signal driving capability and outputs the common-mode voltage VCM to the charge pump. The charge pump uses the charging and discharging characteristics of the capacitor to boost and convert the input common-mode voltage VCM to generate the driving voltage Vboost, which drives the adjustment switch connected to the back end.

[0075] The control logic inputs a clock CLK signal, which controls the charging and discharging process of the charge pump based on the clock CLK signal. The output control signal is then sent to the charge pump to adjust the voltage value of the drive voltage Vboost.

[0076] Specifically, in this embodiment, the structure of the adjustment switch is as follows: Figure 3 As shown, it includes: an LS logic selection module and a first NMOS transistor MN1. The LS logic selection module controls the stable on-resistance of the first NMOS transistor MN1 to improve the accuracy of the tuning logic.

[0077] The charge pump VCMCP samples and processes the input common-mode voltages VIP1 and VIP2 to generate the common-mode voltage VCM and the drive voltage Vboost, which are then input to the LS logic selection module.

[0078] Specifically, in this embodiment, the driving voltage Vboost = VCM + 1.5V.

[0079] There are two LS logic selection modules, both of which have their outputs connected to the gate of the first NMOS transistor MN1. The control logic signal determines whether to pass the VCM voltage to the gate of the first NMOS transistor MN1 to drive it. The source of the first NMOS transistor MN1 is connected to the input common-mode voltage, and the drain is connected to the output voltage OUT.

[0080] Specifically, in this embodiment, the high common-mode rejection ratio input stage circuit is as follows: Figure 4 As shown, it also includes: a tuning switch circuit, a PMOS input pair, an NMOS transistor group, a PMOS transistor group, and a folded cascode module.

[0081] The PMOS input pair includes: a first PMOS transistor MP1 and a second PMOS transistor MP2;

[0082] The NMOS transistor group is used as a current mirror, including: first NMOS transistor MN1, second NMOS transistor MN2, fourth NMOS transistor MN4, and fifth NMOS transistor MN5, which are used as current mirrors;

[0083] The PMOS transistor group is used to provide mirror current and cascode protection, including: the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, and the eighth PMOS transistor MP8.

[0084] Specifically, the first common-mode voltage sampling charge pump VCMCP1 inputs the common-mode voltage signal, and the two output terminals output the voltage VCM and the Vboost voltage VCM+1.5V after being boosted by the charge pump, respectively. After being selected by two LS logic selection modules, the output voltage OUT is sent to the switch group CH1 and CH2.

[0085] The switch group CH1 and CH2 output two voltages, one of which is input to the gate of the first PMOS transistor MP1 and the gate of the third PMOS transistor MP3 in the PMOS transistor group, and the other of which is input to the gate of the second PMOS transistor MP2 and the gate of the fourth PMOS transistor MP4 in the PMOS transistor group.

[0086] The drain of the first PMOS transistor MP1 is connected to the source of the third PMOS transistor MP3, and the drain of the second PMOS transistor MP2 is connected to the source of the fourth PMOS transistor MP4; the drains of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the folded common source and common gate module.

[0087] The folded common source and common gate module is connected to the power supply VDD and ground GND, providing them with power and ground potential during normal operation.

[0088] Furthermore, the boosted Vboost voltage VCM+1.5V is input to the source of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 in the PMOS transistor group;

[0089] The drain of the fifth PMOS transistor MP5 is connected to the source of the seventh PMOS transistor MP7, and the drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP8.

[0090] The gate of the fifth PMOS transistor MP5 is connected to the gates of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7. The gate of the sixth PMOS transistor MP6 is connected to the gate of the eighth PMOS transistor MP8 and then to the drain of the eighth PMOS transistor MP8.

[0091] The drain of the seventh PMOS transistor MP7 is connected to the source of the first PMOS transistor MP1 and the second PMOS transistor MP2, and the drain of the eighth PMOS transistor MP8 is connected to the drain of the fourth NMOS transistor MN4 in the NMOS transistor group.

[0092] Furthermore, the first NMOS transistor MN1, the second NMOS transistor MN2, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 in the NMOS transistor group share a common gate and are connected to the drain of the fifth NMOS transistor MN5;

[0093] The power supply VDD is connected to the input terminal of the current mirror, and the output port is connected to the drain of the fifth NMOS transistor MN5. The source of the fifth NMOS transistor MN5 is connected to the drain of the first NMOS transistor MN1, and the source of the fourth NMOS transistor MN4 is connected to the drain of the second NMOS transistor MN2. The sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are grounded.

[0094] Specifically, in this embodiment, the precision resistor adjustment network adjusts resistor mismatch using E-TRIM technology and provides control voltage to the adjustment logic through VCMCP2, ensuring that the on-resistance of the adjustment switch remains constant and improving the accuracy of the resistor matching network.

[0095] Common-mode rejection ratio adjustment circuit, such as Figure 5 As shown, it includes: a resistor array, a switch array, and a tuning logic module.

[0096] The resistor array includes resistors RT, ..., RTN+1, RTN, ..., RT1 connected in series. The input terminal is connected to the input signal. The number of resistors in the array is selected according to the accuracy. Resistors RTN+1*, RTN*, ..., RT1 are connected in parallel with resistors RTN+1, RTN*, ..., RT1, respectively.

[0097] In this embodiment, N is 9.

[0098] The switch array includes switches: SWN+1, SWN, ..., SW1, which are connected after resistors RTN+1*, RTN*, ..., RT1*, respectively. Each switch is controlled by adjustment bits bitn+1, bitn, ..., bit1 in the adjustment logic module to selectively connect or disconnect the resistors to adjust the total resistance value of the resistor array, which is output at the output terminal of the resistor array.

[0099] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A high common-mode rejection ratio precision current sensing amplifier, characterized in that, include: High common-mode rejection ratio input stage circuit: The input common-mode voltage signals VINN and VINP are sampled by the first common-mode voltage sampling charge pump VCMCP1, and the output drive voltage Vboost is sent to the first chopper switch CHOP1 and the PMOS input pair to provide the input stage power supply potential; Transconductance amplifier circuit: adopts a chopper architecture and is connected to the high common-mode rejection ratio input stage circuit, including: second chopper switch CHOP2, second amplifier GM2, third amplifier GM3 and ripple suppression loop, used to reduce offset voltage and output ripple, and generate output voltage VOUT; The precision resistor adjustment network includes: a common-mode rejection ratio (CMRR) adjustment circuit and a second common-mode voltage sampling charge pump (VCMCP2). The CMRR adjustment circuit is used to adjust the resistor mismatch of the current sensing amplifier, and the second common-mode voltage sampling charge pump (VCMCP2) provides a control voltage for the adjustment logic to keep the on-resistance of the adjustment switch constant. The high common-mode rejection ratio input stage circuit includes: a first common-mode voltage sampling charge pump VCMCP1, a first chopper switch CHOP1, a first amplifier GM1, and a fourth amplifier GM4; The common-mode voltage signals VINN and VINP are simultaneously connected to the two input terminals of the first common-mode voltage sampling charge pump VCMCP1, the first chopper switch CHOP1, and the fourth amplifier GM4. The first common-mode voltage sampling charge pump VCMCP1 has its output terminal simultaneously input to the first chopper switch CHOP1, the first amplifier GM1, and the fourth amplifier GM4 to ensure that the on-resistance of the input to the first chopper switch CHOP1 remains constant. The two output terminals of the first chopper switch CHOP1 are respectively connected to the two input terminals of the first amplifier GM1; The two output terminals of the first amplifier GM1 are simultaneously connected to the input terminal of the second chopper switch CHOP2 and the output terminal of the ripple suppression loop to suppress the offset voltage and ripple of the first amplifier GM1. The two output terminals of the fourth amplifier GM4 are connected to the input terminals of the subsequent third amplifier GM3.

2. The high common-mode rejection ratio precision current sensing amplifier according to claim 1, characterized in that, The voltage signal VINP is input to the high common-mode rejection ratio input stage circuit through the first resistor R1, and then input to the precision resistor adjustment network through the second resistor R2. The voltage signal VINN is input to the high common-mode rejection ratio input stage circuit through the third resistor R3, and then connected to the output voltage VOUT through the fourth resistor R4.

3. The high common-mode rejection ratio precision current sensing amplifier according to claim 2, characterized in that, In the transconductance amplifier circuit, the input terminal of the second chopper switch CHOP2 is connected to the output terminal of the first amplifier GM1, and the output terminal is connected to the second amplifier GM2 and the third amplifier GM3 in sequence. The ripple suppression loop is connected in parallel to the second chopper switch CHOP2, with its output terminal connected to the output terminal of the first amplifier GM1 and its input terminal connected to the input terminal of the second amplifier GM2, in order to reduce offset voltage and output ripple.

4. The high common-mode rejection ratio precision current sensing amplifier according to claim 3, characterized in that, The first common-mode voltage sampling charge pump VCMCP1 and the second common-mode voltage sampling charge pump VCMCP2 have the same structure, both including: a common-mode voltage buffer, a control LDO, a charge pump, and control logic, with the back end connected to a trim switch; The control LDO is connected to the power supply VDD and outputs a stable power supply LVDD to the charge pump and control logic. The buffer buffers the input common-mode voltage signal, enhances the signal driving capability, and outputs the common-mode voltage VCM to the charge pump. The charge pump utilizes the charging and discharging characteristics of a capacitor to boost and convert the input common-mode voltage VCM, generating a drive voltage Vboost to drive the adjustment switch connected to the back end. The control logic performs logical control on the charging and discharging process of the charge pump according to the clock input signal, and adjusts the voltage value of the drive voltage Vboost.

5. The high common-mode rejection ratio precision current sensing amplifier according to claim 4, characterized in that, The adjustment switch includes: an LS logic selection module and a first NMOS transistor MN1. The LS logic selection module controls the stable on-resistance of the first NMOS transistor MN1 to improve the accuracy of the adjustment logic. The charge pump samples and processes the input common-mode voltages VIP1 and VIP2 to generate a common-mode voltage VCM and a drive voltage Vboost, which are then input to the LS logic selection module. The drive voltage Vboost = VCM + 1.5V. The LS logic selection module has two parts. The output terminal is connected to the gate of the first NMOS transistor MN1. It selects whether to pass the VCM voltage to the gate of the first NMOS transistor MN1 according to the control logic signal, so as to drive the first NMOS transistor MN1. The source of the first NMOS transistor MN1 is connected to the input common-mode voltage, and the drain is connected to the output voltage OUT.

6. The high common-mode rejection ratio precision current sensing amplifier according to claim 5, characterized in that, The high common-mode rejection ratio input stage circuit further includes: a trimming switch circuit, a PMOS input pair, an NMOS transistor group, a PMOS transistor group, and a folded common-source common-gate module; The PMOS input pair includes: a first PMOS transistor MP1 and a second PMOS transistor MP2; The first common-mode voltage sampling charge pump VCMCP1 takes in the common-mode voltage signal, and outputs the voltage VCM and the driving voltage Vboost after being boosted by the charge pump at its two output terminals respectively. After being selected by two LS logic selection modules, the output voltage OUT is sent to the switch groups CH1 and CH2. The switch group CH1 and CH2 output two voltages, one of which is input to the gate of the first PMOS transistor MP1 and the gate of the third PMOS transistor MP3 in the PMOS transistor group, and the other of which is input to the gate of the second PMOS transistor MP2 and the gate of the fourth PMOS transistor MP4 in the PMOS transistor group. The drain of the first PMOS transistor MP1 is connected to the source of the third PMOS transistor MP3, and the drain of the second PMOS transistor MP2 is connected to the source of the fourth PMOS transistor MP4; the drains of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to a folded common source and common gate module; the folded common source and common gate module is also connected to power supply VDD and ground GND.

7. The high common-mode rejection ratio precision current sensing amplifier according to claim 6, characterized in that, In the high common-mode rejection ratio input stage circuit, the PMOS transistor group is used to provide mirror current and cascode protection; The driving voltage Vboost is input to the source of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 in the PMOS transistor group; The drain of the fifth PMOS transistor MP5 is connected to the source of the seventh PMOS transistor MP7, and the drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP8. The gate of the fifth PMOS transistor MP5 is connected to the gates of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7. The gate of the sixth PMOS transistor MP6 is connected to the gate of the eighth PMOS transistor MP8 and then to the drain of the eighth PMOS transistor MP8. The drain of the seventh PMOS transistor MP7 is connected to the source of the first PMOS transistor MP1 and the second PMOS transistor MP2, and the drain of the eighth PMOS transistor MP8 is connected to the drain of the fourth NMOS transistor MN4 in the NMOS transistor group.

8. The high common-mode rejection ratio precision current sensing amplifier according to claim 7, characterized in that, In the high common-mode rejection ratio input stage circuit, the NMOS transistor group is used as a current mirror. The first NMOS transistor MN1, the second NMOS transistor MN2, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 in the NMOS transistor group share a common gate and are connected to the drain of the fifth NMOS transistor MN5; The power supply VDD is connected to the input of the current mirror, the output of the current mirror is connected to the drain of the fifth NMOS transistor MN5, the source of the fifth NMOS transistor MN5 is connected to the drain of the first NMOS transistor MN1, the source of the fourth NMOS transistor MN4 is connected to the drain of the second NMOS transistor MN2, and the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are grounded.

9. The high common-mode rejection ratio precision current sensing amplifier according to claim 1, characterized in that, In the precision resistor adjustment network, the common-mode rejection ratio adjustment circuit includes: a resistor array, a switch array, and an adjustment logic module; The resistor array includes resistors RT, ..., RTN+1, RTN, ..., RT1 connected in series, with the input terminal connected to the input signal; Among them, resistors RTN+1*, RTN*, ..., RT1 are connected in parallel with resistors RTN+1, RTN, ..., RT1 respectively; The switch array includes switches: SWN+1, SWN, ..., SW1, which are connected after resistors RTN+1*, RTN*, ..., RT1*, respectively. Each switch is controlled by adjustment bits bitn+1, bitn, ..., bit1 in the adjustment logic module to selectively connect or disconnect the resistors to adjust the total resistance value of the resistor array and output it at the output terminal of the resistor array.

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