Method for forming pore structure

Abstract

A hole structure forming method comprises the following steps: providing a substrate, and sequentially forming a hard mask layer and a photoresist mask layer on the substrate; the method comprises the following steps of: etching a hard mask layer by using a photoresist mask layer to form a groove which at least penetrates through the hard mask layer, carrying out in-situ thermal chemical reaction treatment on the side wall of the groove so as to form a protective layer of which the compactness is higher than that of the hard mask layer on the side wall of the hard mask layer, and then taking the residual hard mask layer as a mask, and etching the substrate by adopting a dry etching process to form the deep hole. The protection layer is formed through in-situ thermal chemical reaction growth, and the structure of the protection layer is compact, so that in the process of performing dry etching on the substrate to form the deep hole, the protection layer can effectively resist the damage of etching plasma to the side wall of the hard mask layer in the dry etching process, the deep hole with better side wall morphology can be formed, and the service life of the deep hole is prolonged. The consistency of the width sizes of the top and the bottom of the deep hole is improved, and the electrical performance and the reliability of the finally formed semiconductor structure are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for forming a pore structure. Background Art

[0002] As semiconductor technology continues to advance, electronic devices continue to move towards miniaturization and higher performance, and packaging technology is also evolving accordingly. In the pursuit of higher integration and better performance, three-dimensional packaging structures have emerged and become a research hotspot.

[0003] As one of the key technologies for achieving three-dimensional packaging, Through Silicon Via (TSV) etching technology is becoming increasingly important. This technology forms deep holes with high aspect ratios in silicon substrates, providing an effective physical channel for interconnection between different metal layers or chips.

[0004] In the practical application of TSV etching technology, the front-layer multilayer mask material is used as a hard mask (HM). The hard mask plays a crucial role in the etching process. It not only guides the precise etching process but also ensures that the through-hole is formed according to the desired shape and size, thus providing a high-quality substrate for subsequent process steps such as metal filling. However, under existing technical conditions, the deep hole (i.e., TSV) etching process faces many challenges. Summary of the Invention

[0005] The problem solved by the present invention is to provide a method for forming a hole structure, which is used to improve the formation quality of deep holes and improve the electrical performance and reliability of semiconductor structures.

[0006] To solve the above problems, the present invention provides a method for forming a hole structure, comprising: providing a substrate, on which a hard mask layer and a photoresist mask layer are sequentially formed; wherein the hard mask layer comprises at least two sub-mask layers stacked in sequence, and the materials of two adjacent sub-mask layers are different, and the photoresist mask layer comprises a mask pattern; dry-etching the hard mask layer using the photoresist mask layer as a mask and the substrate as an etch stop layer to form a groove that at least penetrates the hard mask layer; removing the photoresist mask layer, and performing an in-situ thermochemical reaction treatment on the sidewalls of the hard mask layer exposed by the groove to form a protective layer with a higher density than the hard mask layer, and the protective layer at least covers the sidewalls of the remaining hard mask layer; using the remaining hard mask layer as a mask, dry-etching the substrate to form a deep hole.

[0007] Optionally, a stripping machine is used to remove the photoresist mask layer while performing the in-situ thermochemical reaction treatment, and a reaction gas is input into a processing chamber of the stripping machine during the treatment process.

[0008] Optionally, the material of each of the sub-mask layers is independently selected from one of silicon oxide, silicon nitride, polysilicon and amorphous silicon.

[0009] Optionally, the in-situ thermochemical reaction treatment is an in-situ thermal oxidation treatment, and the reaction gas input into the processing chamber of the debonding machine includes an oxygen source gas.

[0010] Optionally, the oxygen source gas includes oxygen, and the process parameters of the in-situ thermal oxidation treatment are: chamber pressure between 300mTorr and 1000mTorr, process time between 50 seconds and 2000 seconds, RF power between 1500W and 5000W, temperature controlled between 100°C and 300°C, and oxygen gas flow rate between 5000sccm and 30000sccm.

[0011] Optionally, the in-situ thermal chemical reaction treatment is an in-situ thermal nitridation treatment, and the reaction gas input into the processing chamber of the debonding machine includes a nitrogen source gas.

[0012] Optionally, the nitrogen source gas includes nitrogen, and the process parameters of the in-situ thermal nitridation treatment are: chamber pressure between 300mTorr and 1000mTorr, process time between 50 seconds and 2000 seconds, RF power between 1500W and 5000W, temperature controlled between 100°C and 300°C, and nitrogen gas flow rate between 5000sccm and 30000sccm.

[0013] Optionally, the material of the substrate includes silicon; in the step of performing in-situ thermal chemical reaction treatment on the side walls of the hard mask layer exposed by the groove, the top of the substrate is also subjected to in-situ thermal chemical reaction treatment, and the protective layer also covers the surface of the remaining portion of the substrate exposed by the groove.

[0014] Optionally, the step of dry-etching the substrate to form deep holes further includes: dry-etching and removing the remaining portion of the protective layer covering the upper surface of the substrate.

[0015] Optionally, the sidewalls of the groove are vertical or approximately vertical to the bottom wall of the groove; wherein: the groove exposes a portion of the upper surface of the substrate; or, the bottom of the groove is located within the substrate, that is, part of the substrate is removed by dry etching when the groove is formed.

[0016] Optionally, the difference between the top critical dimension and the bottom critical dimension of the deep hole is less than or equal to 50 nm.

[0017] Optionally, the method further includes: filling the deep hole with a conductive material.

[0018] Compared with the prior art, the technical solution of the present invention has the following advantages: The hole structure formation method provided by an embodiment of the present invention, after forming a groove that at least penetrates the hard mask layer, removes the photoresist mask layer and performs an in-situ thermochemical reaction treatment on the groove sidewalls before etching the substrate to form a deep hole using the remaining hard mask layer as a mask using a dry etching process. This forms a protective layer on the sidewalls of the hard mask layer that is denser than the hard mask layer itself. Because the protective layer is grown through an in-situ thermochemical reaction, the protective layer has a dense structure. Therefore, during the process of dry etching the substrate to form the deep hole, the protective layer can effectively resist damage to the sidewalls of the hard mask layer caused by the plasma during the dry etching process, avoiding damage to the groove sidewall morphology or indentation, and expanding the process window for etching the substrate using the hard mask layer as a mask. This allows the hard mask layer to serve as an ideal mask for etching the substrate, forming a deep hole with a better sidewall morphology, and improving the consistency of the width dimensions of the deep hole top and bottom, which helps to improve the electrical performance and reliability of the resulting semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1 to 3 It is a method for forming a pore structure; Figures 4 to 9 It is a structural schematic diagram of each step of a pore structure forming method of the present invention. DETAILED DESCRIPTION

[0020] The current methods for forming pore structures have poor performance. The reasons for the poor performance are analyzed by combining a method for forming a pore structure.

[0021] like Figures 1 to 3 As shown, a schematic structural diagram corresponding to each step in a method for forming a hole structure is shown.

[0022] refer to Figure 1 , providing a substrate 1, and sequentially forming a hard mask layer 2 on the substrate 1, and a groove 3 penetrating the hard mask layer 2.

[0023] refer to Figure 2 , using the hard mask layer 2 as a mask, dry-etching the substrate 1 to form a deep hole 4.

[0024] refer to Figure 3 , the deep hole 4 is filled with a conductive material 6 .

[0025] Because the hard mask layer 2 typically includes multiple sub-mask layers 21, and each sub-mask layer 21 is made of a different material, including but not limited to silicon nitride, polysilicon, and amorphous silicon, during etching of the substrate 1 using the hard mask layer 2 as a mask, the different materials of each sub-mask layer 21 result in different etching rates in the same dry etching process. This can easily lead to concavities 21a on the sidewalls of the sub-mask layer 21 with a faster etching rate. This can cause problems such as loose filling during the subsequent filling of the conductive material 6, and can easily lead to voids 5 in the conductive material, ultimately affecting the overall electrical performance of the semiconductor structure.

[0026] To address the technical problem, embodiments of the present invention provide a method for forming a pore structure. After forming a recess that at least penetrates the hard mask layer, the photoresist mask layer is removed and the recess sidewalls are subjected to an in-situ thermochemical reaction treatment before the substrate is dry-etched using the remaining hard mask layer as a mask to form a deep hole. This method forms a protective layer on the sidewalls of the hard mask layer that is denser than the hard mask layer itself. Because the protective layer is grown through an in-situ thermochemical reaction, the protective layer has a dense structure. Therefore, during the dry-etching process of the substrate to form the deep hole, the protective layer can effectively resist damage to the sidewalls of the hard mask layer caused by the etching plasma during the dry-etching process. This prevents damage to the sidewalls of the recess, or concavities, and increases the process window for etching the substrate using the hard mask layer as a mask. This allows the hard mask layer to serve as an ideal mask for etching the substrate, forming a deep hole with a better sidewall morphology and improving the consistency of the width between the top and bottom of the deep hole, thereby contributing to improved electrical performance and reliability of the resulting semiconductor structure.

[0027] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] Accordingly, the present invention provides a method for forming a pore structure. Figures 4 to 9 It is a structural schematic diagram corresponding to the key steps in the pore structure forming method of the present invention.

[0029] refer to Figure 4 A substrate 100 is provided, on which a hard mask layer 101 and a photoresist mask layer 102 are sequentially formed; wherein the hard mask layer 101 includes at least two sub-mask layers 1011 stacked in sequence, and the materials of the two adjacent sub-mask layers 1011 are different, and the photoresist mask layer 102 includes a mask pattern 1021.

[0030] By forming a stacked structure consisting of a photoresist mask layer 102 , a multi-layer composite hard mask layer 101 and a substrate 100 , the photoresist mask layer 102 includes a mask pattern 1021 , which provides a basis for subsequently transferring a pattern into the substrate 100 .

[0031] In some embodiments, the substrate 100 is made of silicon. Silicon is a commonly used material in semiconductor manufacturing processes and is compatible with many other materials and mainstream semiconductor manufacturing processes. In other embodiments, the substrate may also be made of germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0032] In some embodiments, the hard mask layer 101 includes at least two sub-mask layers 1011 stacked in sequence, and the materials of the two adjacent sub-mask layers 1011 are different, so that in the subsequent process of etching the substrate 100 using the hard mask layer 101 as a mask, the mask pattern 1021 can be more accurately transferred to the substrate 100.

[0033] In some embodiments, the material of each sub-mask layer 1011 is independently selected from one of silicon oxide, silicon nitride, polysilicon (poly), and amorphous silicon (A-Si).

[0034] As an example, the hard mask layer 101 includes a stacked structure of a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer stacked in sequence.

[0035] It should be noted that, in the step of providing the substrate 100 , an intermediate mask layer 107 is further formed between the hard mask layer 101 and the photoresist mask layer 102 .

[0036] The mask pattern 1021 in the photoresist mask layer is formed through exposure and development. If the photoresist mask layer 102 is subsequently used directly as a mask to etch the underlying hard mask layer 101, since etching the hard mask layer 101 is difficult and generally requires high-energy, highly chemically active plasma, this etching environment consumes a lot of energy from the relatively "fragile" photoresist mask layer 102. Therefore, if the photoresist mask layer 102 is directly used as a mask to etch the hard mask layer 101, the photoresist mask layer 102 is likely to be prematurely consumed before the hard mask layer 101 is etched through. Therefore, the intermediate mask layer 107 serves as a process auxiliary layer, first receiving the mask pattern 1021 from the photoresist mask layer 102, and then accurately transferring the mask pattern 1021 to the hard mask layer 101.

[0037] refer to Figure 5 The hard mask layer 101 is dry-etched using the photoresist mask layer 102 as a mask and the substrate 100 as an etch stop layer to form a groove 103 that at least penetrates the hard mask layer 101 .

[0038] The pattern of the photoresist mask layer 102 is transferred to the underlying hard mask layer 101 by dry etching, and a groove 103 having the same pattern as the mask pattern 1021 is formed in the hard mask layer 101, thereby defining a precise mask opening for subsequent deep hole etching; moreover, during the etching process, the substrate 100 is used as an etch stop layer to ensure that the bottom of the groove 103 is exposed to the surface of the substrate 100, and the sidewalls of the hard mask layer 101 to be formed as a protective layer are formed, so that the subsequent in-situ thermal chemical reaction treatment can at least form a protective layer on the sidewalls of the groove 103.

[0039] In some embodiments, the sidewalls of the groove 103 are perpendicular or approximately perpendicular to the bottom wall of the groove 103 .

[0040] The side walls of the groove 103 are perpendicular or approximately perpendicular to the bottom wall of the groove 103, which ensures the graphic transfer accuracy of the hard mask layer 101 as a mask when the hard mask layer 101 is subsequently used as a mask, and is beneficial for making the side walls of the deep hole formed by the subsequent etching of the substrate 100 perpendicular or approximately perpendicular to the bottom wall of the deep hole, so that the deep hole has a good morphology.

[0041] In some embodiments, the groove 103 exposes a portion of the upper surface of the substrate 100; or, the bottom of the groove 103 is located within the substrate 100, that is, the dry etching removes a portion of the substrate 100 when the groove 103 is formed. This allows the bottom of the groove 103 to expose the top of the substrate 100 or to etch a portion of the thickness of the substrate 100, ensuring that the hard mask layer 101 is completely etched through, allowing the hard mask layer 101 to serve as a good mask in subsequent processes.

[0042] It should be noted that, before the hard mask layer 101 is etched using a dry etching process to form the groove 103 , the intermediate mask layer 107 is first etched through.

[0043] refer to Figure 6 and Figure 7 , remove the photoresist mask layer 102, and perform in-situ thermal chemical reaction treatment on the sidewall of the hard mask layer 101 exposed by the groove 103 to form a protective layer 104 (such as Figure 7 As shown in FIG, the protective layer 104 at least covers the sidewalls of the remaining hard mask layer 101.

[0044] Since the protective layer 104 is grown through an in-situ thermochemical reaction, the structure of the protective layer 104 is dense. Therefore, during the process of dry etching the substrate 100 to form a deep hole, the protective layer 104 can effectively resist the damage caused by the plasma to the side wall of the hard mask layer 101 during the dry etching process, thereby avoiding the destruction or concavity of the side wall morphology of the groove 103, and increasing the process window for etching the substrate 100 using the hard mask layer 101 as a mask, so that the hard mask layer 101 can be used as an ideal mask to etch the substrate 100, forming a deep hole with better side wall morphology, improving the consistency of the width dimensions of the top and bottom of the deep hole, and helping to improve the electrical performance and reliability of the finally formed semiconductor structure.

[0045] Specifically, a stripping machine (Asher) is used to remove the photoresist mask layer 102 and simultaneously perform an in-situ thermochemical reaction treatment. During the treatment process, a reaction gas is input into the processing chamber of the stripping machine.

[0046] The photoresist removal and protective layer 104 formation steps are integrated into one step by the degumming machine, which simplifies the process flow and avoids wafer transfer between different devices. While improving production efficiency, it also avoids possible contamination caused by exposure of the wafer to the environment outside the chamber.

[0047] In some embodiments, during the step of performing in-situ thermal chemical reaction treatment on the sidewalls of the hard mask layer 101 exposed by the groove 103, an in-situ thermal chemical reaction treatment is also performed on the top of the substrate 100, and the protective layer 104 also covers the surface of the remaining portion of the substrate 100 exposed by the groove 103.

[0048] While forming the protective layer 104 on the hard mask layer 101 on the sidewall of the groove 103, since the material of the substrate 100 is silicon, the protective layer 104 is also formed on the surface of the substrate 100 at the bottom of the groove 103, that is, the protective layer 104 is formed on the surface of the substrate 100 exposed by the groove 103.

[0049] In some embodiments, the in-situ thermochemical reaction process includes an in-situ thermal oxidation process, and the reaction gas input into the processing chamber of the stripping machine includes an oxygen source gas.

[0050] During the in-situ thermal oxidation process, oxygen source gas is introduced into the processing chamber to cause an oxidation reaction at high temperature on the sidewalls of the hard mask layer 101 and the bottom of the recess 103, thereby generating a dense oxide (e.g., silicon oxide) protective layer 104. This in-situ grown oxide protective layer 104 has excellent chemical stability and tolerance to plasma in the subsequent silicon etching process, which is conducive to achieving effective protection of the sidewalls.

[0051] As an example, the oxygen source gas includes oxygen.

[0052] Specifically, the process parameters of the in-situ thermal oxidation treatment are: chamber pressure between 300mTorr and 1000mTorr, process time between 50 seconds and 2000 seconds, RF power between 1500W and 5000W, temperature control between 100℃ and 300℃, and oxygen gas flow rate between 5000sccm and 30000sccm.

[0053] By coordinating the control of pressure, time, power, temperature, and gas flow, the rate and process of the oxidation reaction are precisely regulated, and a sufficiently dense but not too thick oxide protective layer 104 is formed on the sidewalls of the hard mask layer 101. This allows the protective layer 104 to fully protect the sidewalls of the recess 103 without significantly changing the critical dimension (CD) of the deep hole to be formed subsequently, which is conducive to achieving stability and repeatability of the process results.

[0054] In some embodiments, the in-situ thermal chemical reaction process is an in-situ thermal nitridation process, and the reaction gas input into the processing chamber of the stripping machine includes a nitrogen source gas.

[0055] By introducing nitrogen source gas into the processing chamber, a nitridation reaction occurs on the sidewalls of the hard mask and the bottom of the recess 103 at high temperature, thereby generating a dense nitride (such as silicon nitride) protective layer 104. The in-situ grown nitride protective layer 104 has high density and high chemical stability, so that the protective layer 104 can fully protect the sidewalls of the recess 103 without significantly changing the critical dimension (CD) of the deep hole to be formed subsequently, which is conducive to achieving stability and repeatability of the process results.

[0056] As an example, the nitrogen source gas includes nitrogen.

[0057] Specifically, the process parameters of the in-situ thermal nitridation treatment are: chamber pressure between 300mTorr and 1000mTorr, process time between 50 seconds and 2000 seconds, RF power between 1500W and 5000W, temperature control between 100℃ and 300℃, and nitrogen gas flow rate between 5000sccm and 30000sccm.

[0058] By coordinating the control of pressure, time, power, temperature, and gas flow, the rate and process of the nitridation reaction are precisely regulated to form a sufficiently dense but not too thick nitride protection layer 104 on the sidewalls of the hard mask layer 101. This allows the protection layer 104 to fully protect the sidewalls of the recess 103 without significantly changing the critical dimension (CD) of the deep hole to be formed subsequently, thereby facilitating the stability and repeatability of the process results.

[0059] Specifically, during the in-situ thermal nitridation process, the nitrogen source gas input into the processing chamber of the stripping machine includes a mixed gas of nitrogen and hydrogen.

[0060] By utilizing the reducing and catalytic effects of hydrogen, more active nitrogen species (such as NH x free radicals), thereby improving the efficiency of the nitridation reaction or improving the quality of the formed protective layer 104, making the generated nitride protective layer 104 denser or having a stronger bonding force with the substrate, thereby achieving a better protection effect.

[0061] refer to Figure 8 , using the remaining hard mask layer 101 as a mask, the substrate 100 is dry-etched to form a deep hole 105 (through silicon via).

[0062] After forming a protective layer 104 on the hard mask layer 101 on the side wall of the groove 103, the substrate 100 is dry-etched to transfer the pattern in the hard mask to the substrate 100. Because the protective layer 104 is grown by an in-situ thermochemical reaction, the structure of the protective layer 104 is dense. Therefore, in the process of dry-etching the substrate 100 to form the deep hole 105, the protective layer 104 can effectively resist the damage caused to the side wall of the hard mask layer 101 by the etching plasma during the dry etching process, avoiding the destruction or concavity of the side wall morphology of the groove 103, so that the hard mask layer 101 can be used as an ideal mask to etch the substrate 100, forming a deep hole 105 with a better side wall morphology, improving the consistency of the width dimensions of the top and bottom of the deep hole 105, and helping to improve the electrical performance and reliability of the finally formed semiconductor structure.

[0063] In some embodiments, the step of dry etching the substrate 100 to form the deep hole 105 further includes dry etching to remove a portion of the protective layer 104 covering the remaining upper surface of the substrate 100. The protective layer 104 at the bottom of the groove 103 is removed before the main etching begins, thereby exposing the underlying substrate 100 material and opening a channel for subsequent etching of the substrate 100.

[0064] As an example, the deep hole 105 is formed by dry etching the substrate 100 using the remaining hard mask layer 101 as a mask using inductively coupled plasma (ICP).

[0065] By utilizing the characteristic of inductively coupled plasma (ICP) that can generate high-density, low-energy ions, high-rate, high-anisotropy etching of the substrate 100 is achieved, thereby meeting the process requirements for forming deep holes 105 with a high aspect ratio.

[0066] In some embodiments, the difference between the top critical dimension and the bottom critical dimension of the deep hole 105 is less than or equal to 50 nm.

[0067] The difference between the top critical dimension and the bottom critical dimension of the deep hole 105 is less than or equal to 50 nm, so that the side wall of the deep hole 105 and the bottom wall of the deep hole 105 are in an approximately vertical state, providing a geometric cavity with a uniform cross-section and nearly vertical side walls for the subsequent conductive material filling process, so that the subsequent conductive material can be seamlessly and densely filled during deposition.

[0068] refer to Figure 9 The method for forming the hole structure further includes: filling the deep hole 105 with a conductive material 106 .

[0069] By filling deep holes 105 with conductive material 106, vertical conductive pathways are established between metal interconnects on different layers, enabling signal transmission and power distribution between multiple metal layers or between multiple chips. This is the core function of the through-silicon via (TSV) structure. Because the top and bottom widths of deep holes 105 are highly consistent, the filling process of conductive material 106 is smoother and more consistent, resulting in a dense, void-free conductive column. This fundamentally ensures that the TSV possesses the electrical properties of low resistance and high current carrying capacity.

[0070] In some embodiments, the conductive material 106 filled in the deep hole 105 includes tungsten or copper.

[0071] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a pore structure, characterized in that: include: Providing a substrate, on which a hard mask layer and a photoresist mask layer are sequentially formed; wherein the hard mask layer includes at least two sub-mask layers stacked in sequence, and two adjacent sub-mask layers are made of different materials; and the photoresist mask layer includes a mask pattern; dry-etching the hard mask layer using the photoresist mask layer as a mask and the substrate as an etch stop layer to form a groove at least penetrating the hard mask layer; removing the photoresist mask layer, and performing an in-situ thermochemical reaction treatment on the sidewalls of the hard mask layer exposed by the groove to form a protective layer having a higher density than that of the hard mask layer, wherein the protective layer at least covers the remaining sidewalls of the hard mask layer; The substrate is dry-etched using the remaining hard mask layer as a mask to form deep holes.

2. The method for forming a pore structure according to claim 1, wherein: A stripping machine is used to remove the photoresist mask layer while performing the in-situ thermal chemical reaction treatment. During the treatment process, a reaction gas is input into the processing chamber of the stripping machine.

3. The method for forming a pore structure according to claim 1 or 2, wherein: The material of each of the sub-mask layers is independently selected from one of silicon oxide, silicon nitride, polysilicon and amorphous silicon.

4. The method for forming a pore structure according to claim 2, wherein: The in-situ thermochemical reaction treatment is an in-situ thermal oxidation treatment, and the reaction gas input into the processing chamber of the debonding machine includes an oxygen source gas.

5. The method for forming a pore structure according to claim 4, wherein: The oxygen source gas includes oxygen, and the process parameters of the in-situ thermal oxidation treatment are: chamber pressure between 300mTorr and 1000mTorr, process time between 50 seconds and 2000 seconds, RF power between 1500W and 5000W, temperature controlled between 100°C and 300°C, and oxygen gas flow rate between 5000sccm and 30000sccm.

6. The method for forming a pore structure according to claim 2, wherein: The in-situ thermal chemical reaction treatment is an in-situ thermal nitridation treatment, and the reaction gas input into the processing chamber of the stripping machine includes a nitrogen source gas.

7. The method for forming a pore structure according to claim 6, wherein: The nitrogen source gas includes nitrogen, and the process parameters of the in-situ thermal nitridation treatment are: chamber pressure between 300mTorr and 1000mTorr, process time between 50 seconds and 2000 seconds, RF power between 1500W and 5000W, temperature controlled between 100°C and 300°C, and nitrogen gas flow rate between 5000sccm and 30000sccm.

8. The method for forming a pore structure according to claim 1, wherein: The material of the substrate includes silicon; In the step of performing in-situ thermochemical reaction treatment on the sidewalls of the hard mask layer exposed by the groove, an in-situ thermochemical reaction treatment is also performed on the top of the substrate, and the protection layer also covers the surface of the remaining portion of the substrate exposed by the groove.

9. The method for forming a pore structure according to claim 8, wherein: The step of dry etching the substrate to form deep holes further includes: dry etching to remove the remaining portion of the protective layer covering the upper surface of the substrate.

10. The method for forming a pore structure according to claim 1, wherein: The sidewalls of the groove are perpendicular or approximately perpendicular to the bottom wall of the groove; wherein: the groove exposes a portion of the upper surface of the substrate; or, the bottom of the groove is located within the substrate, that is, a portion of the substrate is removed by dry etching when the groove is formed.

11. The method for forming a pore structure according to claim 1, wherein: The difference between the top critical dimension and the bottom critical dimension of the deep hole is less than or equal to 50 nm.

12. The method for forming a pore structure according to claim 1, wherein: Also includes: The deep holes are filled with a conductive material.

Images