LDMOS device and manufacturing method thereof
By forming an LDD region as the source in the well region of the LDMOS device and short-connecting it to the body electrode, the problem of floating body effect is solved, and the reliability of the device and the flexibility of SOI chip design are improved.
Patent Information
- Application Number
- CN202510708490.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-09-05
AI Technical Summary
When the SOI LDMOS device is partially exhausted and the voltage is not connected to, resulting in floating body effect, resulting in leakage, affecting device reliability.
The LDD region is formed as a source in the well region of the LDMOS device and is brought into contact with the second heavily doped region of the body electrode to ensure that the source and the body electrode are shorted during operation, and the floating body region is connected to the same potential, thereby improving the floating body effect.
By improving the floating body effect, the reliability of the device is improved and the flexibility of SOI chip design is enhanced.
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Figure CN120603290A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to an LDMOS device and a manufacturing method thereof. Background Art
[0002] With the development of radio frequency (RF) technology (for example, envelope tracking technology and predistortion technology), silicon-on-insulator lateral double-diffused metal-oxide-semiconductor field-effect transistor (SOI LDMOSFET, referred to as "SOI LDMOS" in this application) devices have become a common choice for RF amplifiers. At the same time, due to their ease of switch device integration, they have been widely used.
[0003] refer to Figure 1 , which shows a schematic top view of a SOI LDMOS device provided in the related art; Figure 2 , which shows the SOI LDMOS device provided in the related art along Figure 1 A schematic cross-sectional view of the AA' direction is shown, for example, Figure 1 As shown, a gate dielectric layer 120 is formed on an SOI substrate (which includes a silicon (Si) substrate and an insulating layer 100 formed therein, wherein the insulating layer 100 isolates the silicon substrate into a bottom substrate 111 located therebelow and a top substrate 112 located thereover). A gate 130 is formed on the gate dielectric layer 120. A first heavily doped region 1121 and a second heavily doped region 1122 are formed in the top substrate 112 on both sides of the gate 130. A drift region 114 and a well region 113 are formed in the top substrate 112 between the first heavily doped region 1121 and the second heavily doped region 1122. Figure 2 As shown, a third heavily doped region 115 is formed in the top substrate 112 outside the gate 130. When the LDMOS device is working, the first heavily doped region 1121 and the second heavily doped region 1122 can serve as the source and drain of the device, and the third heavily doped region 115 can serve as the body electrode of the device.
[0004] However, when the SOI LDMOS device provided in the related art is operating, the well region 113 is partially depleted and not connected to a voltage, and is in an electrically suspended state. The charge generated by impact ionization cannot be discharged, resulting in a floating body effect, which causes leakage and affects the reliability of the device. Summary of the Invention
[0005] The present application provides an LDMOS device and a manufacturing method thereof, which can solve the problem that the LDMOS device provided in the related art is prone to generating a floating body effect.
[0006] In one aspect, an embodiment of the present application provides an LDMOS device, including:
[0007] An SOI substrate, the SOI substrate comprising a silicon substrate and an insulating layer formed in the silicon substrate, the insulating layer isolating the silicon substrate into a top substrate located above and a bottom substrate located below;
[0008] a gate dielectric layer formed on the top substrate;
[0009] a gate formed on the gate dielectric layer;
[0010] A well region and a drift region are formed in the top substrate, a first heavily doped region is formed in the drift region, a second heavily doped region is formed in the well region, and an LDD region is formed in the well region between the second heavily doped region and the gate in a lateral direction, the LDD region being in contact with the second heavily doped region;
[0011] When the LDMOS device is in operation, the first heavily doped region serves as a drain, the LDD region serves as a source, and the second heavily doped region serves as a body electrode.
[0012] In some embodiments, a sidewall spacer is formed around the gate.
[0013] In some embodiments, a SAB layer is formed on the other side of the gate, and the SAB layer is in contact with the drift region on the other side of the gate and a predetermined area on the top of the gate respectively.
[0014] On the other hand, an embodiment of the present application provides a method for manufacturing an LDMOS device, comprising:
[0015] Providing an SOI substrate, the SOI substrate comprising a silicon substrate and an insulating layer formed in the silicon substrate, the insulating layer isolating the silicon substrate into a top substrate located above and a bottom substrate located below, a gate dielectric layer formed on an upper surface of the top substrate, a well region and a drift region formed in the top substrate, and a first heavily doped region formed in the drift region;
[0016] forming a gate on the gate dielectric layer;
[0017] forming an LDD region in a well region on one side of the gate;
[0018] forming a second heavily doped region in a well region on one side of the LDD region, wherein the second heavily doped region is in contact with the LDD region;
[0019] When the LDMOS device is in operation, the first heavily doped region serves as a drain, the LDD region serves as a source, and the second heavily doped region serves as a body electrode.
[0020] In some embodiments, after forming the second heavily doped region in the well region on one side of the LDD region, the method further includes:
[0021] forming a SAB layer on the other side of the gate, wherein the SAB layer is in contact with the drift region on the other side of the gate and a predetermined area on the top of the gate;
[0022] forming an ILD layer on the top substrate;
[0023] A first contact hole and a second contact hole are formed in the ILD layer, wherein the bottom of the first contact hole contacts the first heavily doped region, and the bottom of the second contact hole contacts the LDD region or the second heavily doped region.
[0024] In some embodiments, forming a gate on the gate dielectric layer includes:
[0025] forming a polysilicon layer on the gate dielectric layer;
[0026] Performing etching to remove the polysilicon layer and the gate dielectric layer in areas other than the target area, where the polysilicon layer in the target area forms the gate;
[0027] A sidewall spacer is formed on the periphery of the gate.
[0028] The technical solution of this application has at least the following advantages:
[0029] By forming an LDD region in the well region of the LDMOS device as the source of the device, and making the LDD region contact the second heavily doped region as the body electrode of the device, when the device is working, the source and the body electrode region are short-circuited, and the body electrode region can pass through the lower layer of the source to connect with the floating body region of the well region, so that the floating body region of the well region is led out to have the same potential as the source, thereby improving the floating body effect, while lengthening the channel of the device and improving the flexibility of SOI chip design. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0031] Figure 1 1 is a schematic top view of a SOILDMOS device provided in the related art;
[0032] Figure 2 The SOI LDMOS device provided in the related art is Figure 1 Schematic diagram of the cross section along the AA' direction;
[0033] Figure 3 is a flow chart of a method for manufacturing an LDMOS device provided by an exemplary embodiment of the present application;
[0034] Figure 4 As for Figure 9 This is a schematic diagram of the manufacturing process of an LDMOS device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0035] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0036] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0037] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0038] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0039] refer to Figure 3 , which shows a flow chart of a method for manufacturing an LDMOS device provided by an exemplary embodiment of the present application, as shown in FIG. Figure 3 As shown, the method includes:
[0040] Step S1, providing an SOI substrate, which includes a silicon substrate and an insulating layer formed in the silicon substrate, the insulating layer isolates the silicon substrate into a top substrate located above and a bottom substrate located below, a gate dielectric layer is formed on the upper surface of the top substrate, a well region and a drift region are formed in the top substrate, and a first heavily doped region is formed in the drift region.
[0041] refer to Figure 4 , which shows a cross-sectional schematic diagram before forming a gate on the gate dielectric layer. Figure 4 As shown, the SOI substrate includes a silicon substrate and an insulating layer 200 formed in the silicon substrate. The insulating layer 200 isolates the silicon substrate into a top substrate 212 located above and a bottom substrate 211 located below. A gate dielectric layer 220 is formed on the upper surface of the top substrate 212. A well region 213 and a drift region 214 are formed in the top substrate 212. A first heavily doped region 212 is formed in the drift region 214.
[0042] Among them, the gate dielectric layer 220 can be formed by generating a silicon dioxide (SiO2) layer on the surface of the top substrate 212 through a thermal oxidation process, the well region 213 is doped with impurities of the first conductive type, and the drift region 214 and the first heavily doped region 212 are doped with impurities of the second conductive type.
[0043] Step S2: forming a gate on the gate dielectric layer.
[0044] refer to Figure 5 , which shows a cross-sectional schematic diagram after the gate is formed. For example, Figure 5As shown, a sidewall 231 is formed on the periphery of the gate 230. Step S2 includes but is not limited to: forming a polysilicon (poly) layer ( Figure 5 (not shown), etching is performed (by photolithography process) to remove the polysilicon layer and the gate dielectric layer 220 in other areas except the first target area, the polysilicon layer in the first target area forms a gate 230, and a sidewall 231 is formed on the side of the gate 230 (a silicon dioxide layer can be deposited first, and then the silicon dioxide layer in other areas except the side of the gate is removed by etching to form a sidewall).
[0045] In step S3 , an LDD region is formed in the well region on one side of the gate.
[0046] refer to Figure 6 , which shows a cross-sectional schematic diagram after the LDD region is formed in the well region on one side of the gate. Figure 6 As shown, step S3 includes but is not limited to: covering the top substrate 212 with a photoresist ( Figure 6 (not shown), the photoresist in the second target area (located in the well area 213 on one side of the gate 230) is removed by exposure and development in sequence, and a lightly doped drain (LDD) area 216 is formed in the second target area by ion implantation, where the LDD area 216 is doped with impurities of the second conductivity type.
[0047] Step S4 , forming a second heavily doped region in the well region on one side of the LDD region, wherein the second heavily doped region contacts the LDD region.
[0048] refer to Figure 7 , which shows a cross-sectional schematic diagram after forming the third heavily doped region; Figure 8 , which shows a top view schematic diagram after the third heavily doped region is formed, Figure 7 for Figure 8 Schematic diagram of the cross section along the BB' direction. For example, Figure 7 and Figure 8 As shown, step S4 includes but is not limited to: covering the top substrate 212 with a photoresist ( Figure 7 (not shown in the figure), the photoresist in the third target area (located in the well area 213 on one side of the LDD area 216) is removed by exposure and development in sequence, and a second heavily doped area 215 is formed in the third target area by ion implantation. The second heavily doped area 215 is doped with impurities of the first conductive type, and the impurity concentrations in the first heavily doped area 212 and the second heavily doped area 215 are greater than the impurity concentrations in other doping areas.
[0049] When the LDMOS device is operating, the first heavily doped region serves as the drain 212, the LDD region 216 serves as the source, and the second heavily doped region 215 serves as the body electrode. It should be noted that the present embodiment uses a structure in which two adjacent LDMOS devices share a common body electrode (a top-view gate shape of a U-shaped gate is also an exemplary structure) for illustrative purposes. In actual applications, various configurations can be employed as needed.
[0050] Optionally, after step S4, the method further includes: forming a self-aligned silicide block (SAB) layer on the other side of the gate; forming an interlayer dielectric (ILD) layer on the top substrate; and forming a first contact hole and a second contact hole in the ILD layer.
[0051] refer to Figure 9 , which shows a cross-sectional schematic diagram after forming the SAB layer and the contact hole. Figure 9 As shown, the SAB layer 240 contacts the drift region 214 on the other side of the gate 230 and a predetermined area on the top of the gate 230, respectively. The bottom of the first contact hole 2511 in the ILD layer 250 contacts the first heavily doped region 212, and the bottom of the second contact hole 2511 in the ILD layer 250 contacts the LDD region 216 or the second heavily doped region 215.
[0052] refer to Figure 9 , which shows a cross-sectional schematic diagram of an LDMOS device provided by an exemplary embodiment of the present application. The LDMOS device can be manufactured by the above-mentioned manufacturing method. For example, Figure 9 As shown, the device includes:
[0053] The SOI substrate includes a silicon substrate and an insulating layer 200 formed in the silicon substrate. The insulating layer 200 isolates the silicon substrate into a top substrate 212 located above and a bottom substrate 211 located below.
[0054] A gate dielectric layer 220 is formed on the top substrate 212 .
[0055] The gate 230 is formed on the gate dielectric layer 220. A sidewall spacer 231 is formed around the gate 230. A SAB layer 240 is formed on the other side of the gate 230. The SAB layer 240 contacts the drift region 214 on the other side of the gate 230 and a predetermined area on the top of the gate 230.
[0056] A well region 213 and a drift region 214 are formed in the top substrate 212, a first heavily doped region 212 is formed in the drift region 214, a second heavily doped region 215 is formed in the well region 213, and laterally, an LDD region 216 is formed in the well region 213 between the second heavily doped region 215 and the gate 230, and the LDD region 216 is in contact with the second heavily doped region 215.
[0057] The well region 213 and the second heavily doped region 215 are doped with impurities of the first conductive type, the drift region 214, the LDD region 216 and the first heavily doped region 212 are doped with impurities of the first conductive type, and the impurity concentrations in the first heavily doped region 212 and the second heavily doped region 215 are greater than the impurity concentrations in other doped regions.
[0058] In the embodiment of the present application, if the first conductivity type impurity is an N (negative) type impurity, the second conductivity type impurity is a P (positive) type impurity; if the second conductivity type impurity is a P type impurity, the second conductivity type impurity is an N type impurity.
[0059] When the LDMOS device is in operation, the first heavily doped region 212 serves as a drain, the LDD region 216 serves as a source, and the second heavily doped region 215 serves as a body electrode.
[0060] To sum up, in the embodiments of the present application, an LDD region is formed in the well region of the LDMOS device as the source of the device, and the LDD region is contacted with the second heavily doped region serving as the body electrode of the device. When the device is working, the source and the body electrode region are short-circuited, and the body electrode region can pass through the lower layer of the source and be connected to the floating body region of the well region, so that the floating body region of the well region is led out so that it has the same potential as the source, thereby improving the floating body effect, while lengthening the channel of the device and improving the flexibility of SOI chip design.
[0061] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.
Claims
1. An LDMOS device, characterized in that: include: An SOI substrate, the SOI substrate comprising a silicon substrate and an insulating layer formed in the silicon substrate, the insulating layer isolating the silicon substrate into a top substrate located above and a bottom substrate located below; a gate dielectric layer formed on the top substrate; a gate formed on the gate dielectric layer; A well region and a drift region are formed in the top substrate, a first heavily doped region is formed in the drift region, a second heavily doped region is formed in the well region, and an LDD region is formed in the well region between the second heavily doped region and the gate in a lateral direction, the LDD region being in contact with the second heavily doped region; When the LDMOS device is in operation, the first heavily doped region serves as a drain, the LDD region serves as a source, and the second heavily doped region serves as a body electrode.
2. The device according to claim 1, characterized in that A sidewall is formed around the gate.
3. The device according to claim 2, characterized in that A SAB layer is formed on the other side of the gate, and the SAB layer is in contact with the drift region on the other side of the gate and a predetermined region on the top of the gate respectively.
4. A method for manufacturing an LDMOS device, characterized in that: include: Providing an SOI substrate, the SOI substrate comprising a silicon substrate and an insulating layer formed in the silicon substrate, the insulating layer isolating the silicon substrate into a top substrate located above and a bottom substrate located below, a gate dielectric layer formed on an upper surface of the top substrate, a well region and a drift region formed in the top substrate, and a first heavily doped region formed in the drift region; forming a gate on the gate dielectric layer; forming an LDD region in a well region on one side of the gate; forming a second heavily doped region in a well region on one side of the LDD region, wherein the second heavily doped region is in contact with the LDD region; When the LDMOS device is in operation, the first heavily doped region serves as a drain, the LDD region serves as a source, and the second heavily doped region serves as a body electrode.
5. The method according to claim 4, characterized in that After forming the second heavily doped region in the well region on one side of the LDD region, the method further includes: forming a SAB layer on the other side of the gate, wherein the SAB layer is in contact with the drift region on the other side of the gate and a predetermined area on the top of the gate; forming an ILD layer on the top substrate; A first contact hole and a second contact hole are formed in the ILD layer, wherein the bottom of the first contact hole contacts the first heavily doped region, and the bottom of the second contact hole contacts the LDD region or the second heavily doped region.
6. The method according to claim 5, characterized in that The step of forming a gate on the gate dielectric layer includes: forming a polysilicon layer on the gate dielectric layer; Performing etching to remove the polysilicon layer and the gate dielectric layer in areas other than the target area, where the polysilicon layer in the target area forms the gate; A sidewall spacer is formed on the periphery of the gate.