Direct current charging pile bridging power distribution system

Abstract

The invention provides a direct-current charging pile bridging power distribution system, and belongs to the technical field of direct-current charging piles. The direct-current charging pile bridging power distribution system is characterized in that three-phase voltage and dual-port current data of a power grid are acquired firstly, and an initial virtual impedance matrix is established; secondly, dividing load requirements into three modes, correcting initial virtual impedance by adopting a floating weight index and an impedance optimization mechanism equation, and outputting optimized virtual impedance parameters; then, a current shunting path is established through bridge switch matrix conduction time sequence control, then the dual-port current balance degree is calculated in real time, a current balance contribution degree evaluation system is constructed, and a duty ratio distribution scheme is optimized; then establishing a current distribution bridge matrix, and dynamically updating matrix parameters to realize accurate power control; optimizing the switching frequency and the dead time by adopting an efficiency improvement algorithm; and finally, outputting the optimized parameters to a bridge switch matrix, generating a new PWM driving signal, and realizing dynamic balance distribution of power of double output ports.

Description

Technical Field

[0001] The present invention belongs to the technical field of DC charging piles, and in particular relates to a DC charging pile bridging power distribution system. Background Art

[0002] DC charging piles, the core equipment for fast charging of electric vehicles, typically utilize a single power conversion unit (PCU) in conjunction with a switch matrix to achieve multi-port output. Traditionally, the PCU converts AC power into DC power using a three-phase rectifier bridge, which is then distributed to each charging port via a fixed-parameter switch matrix. This approach can achieve basic power output under ideal grid conditions. Existing charging pile systems are widely used in locations such as highway service areas, urban charging stations, and commercial complexes, providing fast charging services for electric vehicles. However, traditional power distribution systems have significant drawbacks. First, the fixed-parameter switch control strategy cannot adapt to unbalanced three-phase grid voltages. When grid voltage fluctuates, differences in voltage amplitude and phase between phases lead to reduced power conversion efficiency. Second, when the loads on the two output ports differ, traditional systems lack a dynamic power redistribution mechanism, making it impossible to adjust the power output ratio based on actual load demand. Furthermore, circulating currents are prone to occur within the switch matrix, increasing system losses and affecting charging stability. The core problem that traditional technology is difficult to solve is that when the power grid status changes and the dual-port load is uneven, the system cannot achieve dynamic balanced power distribution, resulting in reduced charging efficiency and insufficient equipment utilization, which seriously affects the actual application effect of the charging pile. Summary of the Invention

[0003] In view of this, the present invention provides a DC charging pile bridge power distribution system, which can solve the technical problem in the prior art that the dual output ports of the DC charging pile have unbalanced power distribution under conditions of grid voltage imbalance and load difference, resulting in reduced charging efficiency.

[0004] The present invention is implemented as follows: The present invention provides a DC charging pile bridge power distribution system, in which the power conversion unit adopts a three-phase rectifier bridge structure, which is composed of six power diodes and six IGBT switch tubes. The AC input end of the power conversion unit is connected to the three-phase power supply of the power grid, and the DC output end is connected to the common input end of the bridge switch matrix; the bridge switch matrix adopts an H-bridge topology structure, including eight bidirectional power switch tubes, forming two independent H-bridge units, and each H-bridge unit corresponds to an output port; the control chip adopts a 32-bit ARM architecture processor, and communicates data with the voltage acquisition unit and the current detection unit through the CAN bus. A dynamic impedance balancing control module is provided in the control chip, which realizes the dynamic balanced distribution of the power of the dual output ports by establishing a virtual impedance matrix and a current distribution bridge matrix, thereby solving the core problem of reduced charging efficiency caused by unbalanced power distribution under conditions of unbalanced grid voltage and load difference.

[0005] Among them, the dynamic impedance balancing control module specifically performs the following steps: collecting the instantaneous values ​​of the three-phase voltage of the power grid and the instantaneous values ​​of the current of the dual output ports, establishing a hierarchical evaluation system according to the voltage imbalance, and establishing an initial virtual impedance matrix through the virtual impedance contribution; dividing the load demand into three modes of synchronous load, asynchronous load, and polarized load based on the load difference of the dual output ports, adopting the impedance optimization mechanism equation when correcting the initial virtual impedance based on the floating weight index, and outputting the optimized virtual impedance parameters; establishing a current diversion path through the conduction timing control of the bridge switch matrix, monitoring the circulating current effect coefficient and starting the circulating current suppression algorithm; calculating the current balance of the dual output ports in real time and constructing a current balance contribution evaluation system, solving the optimal duty cycle distribution scheme through the least squares optimization problem; establishing a current distribution bridge matrix, and dynamically updating the matrix parameters according to load changes; monitoring the overall power density of the system and starting the efficiency improvement algorithm; outputting the optimized virtual impedance parameters and the current distribution bridge matrix to the bridge switch matrix to generate a new PWM drive signal.

[0006] Among them, the steps of establishing the initial virtual impedance matrix are to collect the instantaneous value of the three-phase voltage of the power grid through the voltage acquisition unit, and collect the instantaneous value of the current of the dual output ports through the current detection unit. The voltage imbalance is divided into three levels: mild imbalance, moderate imbalance, and severe imbalance according to the voltage imbalance degree. The influence of each level on the power transmission efficiency is evaluated through the virtual impedance contribution, and the initial virtual impedance matrix is ​​established as a benchmark reference for power distribution.

[0007] Among them, the initial virtual impedance is specifically based on the equivalent impedance reference value set under the rated operating conditions of the system, which is used to describe the ideal transmission characteristics between the power conversion unit and the dual output ports, and the reference impedance matrix is ​​determined by mathematical modeling of the voltage and current ratio.

[0008] Among them, the virtual impedance contribution is a quantitative indicator that measures the contribution of virtual impedance to power transmission efficiency under different grid conditions. It is calculated by multiplying the voltage imbalance level and the corresponding power transmission success rate. The higher the virtual impedance contribution, the more stable the power transmission efficiency under the said state.

[0009] Among them, the step of outputting the optimized virtual impedance parameters is specifically based on the load current difference and voltage difference of the dual output ports, dividing the load demand difference into three modes: synchronous load, asynchronous load, and polarized load. When correcting the initial virtual impedance based on the floating weight index, the impedance optimization mechanism equation is used to output the optimized virtual impedance parameters.

[0010] Among them, the optimized virtual impedance parameters are dynamic impedance parameters that are modified based on the initial virtual impedance according to the real-time grid status and load changes. The impedance matrix elements are adjusted in real time through an adaptive algorithm to compensate for the impact of grid imbalance on power transmission.

[0011] The floating weight index is a dynamic coefficient that reflects the degree of load difference between the two output ports. Its value range is 0.1 to 2.0. When the loads on the two ports are equal, the floating weight index is 1.0. When the load difference increases, the floating weight index is adjusted accordingly to dynamically correct the power allocation ratio.

[0012] Among them, the step of starting the circulating current suppression algorithm is to establish a current shunt path between the two H-bridge units through the conduction timing control of the bridge switch matrix, monitor and calculate the circulating current effect coefficient based on the detection data of the current detection unit, and start the circulating current suppression algorithm when the circulating current effect coefficient exceeds the set threshold.

[0013] Among them, the circulation effect coefficient is a quantitative parameter that describes the degree of current circulation within the bridge switch matrix. It is calculated by measuring the correlation between the current of each switch tube and the total output current. The larger the circulation effect coefficient, the more serious the invalid circulation, which affects the system efficiency.

[0014] Among them, the steps for solving the optimal duty cycle distribution scheme are to calculate the current balance of the dual output ports in real time based on the instantaneous current values ​​of the dual output ports and construct a current balance contribution evaluation system, and divide the current distribution state into three ranges: excellent balance, general balance, and imbalance. When the current balance contribution is lower than 0.6, the optimal duty cycle distribution scheme is solved by the least squares optimization problem.

[0015] The current balance is specifically an indicator of the uniformity of the current distribution at the dual output ports. It is determined by calculating the ratio of the standard deviation to the average value of the effective current values ​​of the two ports. The closer the current balance is to 1, the more uniform the current distribution is.

[0016] Among them, the current balancing contribution is a comprehensive indicator that evaluates the contribution of the current distribution uniformity of the dual output ports to the overall system performance. It is calculated by weighted summation of the current distribution state ratio and the corresponding system stability coefficient. The higher the current balancing contribution, the more conducive the current distribution is to the long-term stable operation of the system.

[0017] Among them, the step of establishing a current distribution bridge matrix is ​​to establish a current distribution bridge matrix based on optimizing virtual impedance parameters and current balance. The matrix elements represent the current distribution coefficients corresponding to each switch tube. The matrix parameters are dynamically updated according to load changes to achieve precise power control.

[0018] Among them, the current distribution bridge matrix is ​​specifically a mathematical matrix that describes the current distribution relationship of each power switch tube in the bridge switch matrix. The matrix dimension is 8×2, each row corresponds to a switch tube, and each column corresponds to an output port. The matrix element value represents the current contribution coefficient of the switch tube to the corresponding port.

[0019] Among them, the impedance optimization mechanism equation is used to dynamically adjust the virtual impedance parameters according to the load characteristics and grid status. The input includes the load conversion rate coefficient, the grid voltage imbalance factor, the floating weight index, the delay compensation coefficient, and the temperature correction parameter. The output is the optimized virtual impedance parameters. The impedance optimization mechanism equation solves the optimal impedance configuration scheme through a multivariable nonlinear optimization algorithm.

[0020] This invention achieves adaptive and balanced power distribution at dual output ports by establishing a virtual impedance matrix and a current distribution bridge matrix. This method first collects grid three-phase voltage and dual-port current data, establishes a graded evaluation system based on the degree of voltage imbalance, and quantifies the impact of each grade on power transmission using virtual impedance contribution metrics. To address grid voltage imbalance, the virtual impedance parameters are dynamically adjusted to compensate for the impact of grid fluctuations on power transmission, ensuring stable system operation in complex grid environments. To address load differences at the dual output ports, a floating weight index and an impedance optimization mechanism equation are used to adjust the power distribution ratio in real time, ensuring that each port receives the appropriate power output according to actual needs. To address the circulating current effect, the circulating current coefficient is monitored and a suppression algorithm is activated to effectively reduce internal inefficient circulating current. By constructing a multi-dimensional control parameter system, static switch control is transformed into dynamic, adaptive control, enabling the system to optimize power distribution strategies in real time based on grid conditions and load changes. The establishment of the current distribution bridge matrix enables precise control of the current contribution coefficient of each switch. Ultimately, balanced power distribution is achieved through dynamic adjustment of the PWM signal, resolving the core issue of unbalanced power distribution and significantly improving the charging efficiency of the dual output ports and overall system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the structure of the system of the present invention.

[0022] Figure 2 This is a flow chart of the steps executed by the dynamic impedance balancing control module in the present invention.

[0023] Figure 3 Schematic diagram of the hardware composition in Example 2.

[0024] Figure 4 Schematic diagram of the principle of the bridge switch matrix H bridge in Example 2.

[0025] Figure 5 This is a schematic diagram of the composition of the dynamic impedance balance control in Example 2. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0027] like Figure 1 As shown, it is a structural diagram of a DC charging pile bridge power distribution system provided by the present invention. The system includes: a power conversion unit, a voltage acquisition unit, a current detection unit, a bridge switch matrix, a dual output port, a filter capacitor group, a protection circuit breaker and a control chip, wherein the power conversion unit adopts a three-phase rectifier bridge structure, which is composed of six power diodes and six IGBT switch tubes. The AC input end of the power conversion unit is connected to the three-phase power supply of the power grid, and the DC output end is electrically connected to the common input end of the bridge switch matrix; the voltage acquisition unit includes eight voltage sensors, which are respectively arranged at the three-phase input end of the power grid, the DC output end of the power conversion unit and the dual output port, for real-time monitoring of the voltage value of each node; the current detection unit includes four current sensors, which are respectively set In the DC output bus of the power conversion unit and the positive and negative lines of the dual output ports, it is used to detect real-time current data; the bridge switch matrix adopts an H-bridge topology, including eight bidirectional power switch tubes, forming two independent H-bridge units, each H-bridge unit corresponding to an output port; the dual output ports are respectively a first charging gun interface and a second charging gun interface, and the two interfaces are 180 degrees symmetrically distributed in the physical structure, and each interface includes a positive terminal, a negative terminal and a communication terminal; the filter capacitor group includes six electrolytic capacitors, four of which are connected in parallel to the input end of the bridge switch matrix, and two are respectively connected to the dual output ports for filtering ripple current; the protective circuit breaker is arranged between the power conversion unit and the bridge switch matrix, and automatically disconnects the circuit connection when an overcurrent or short circuit fault is detected.

[0028] The control chip uses a 32-bit ARM architecture processor and is installed on a printed circuit board inside the system control cabinet. The control chip communicates data with the voltage acquisition unit and current detection unit via the CAN bus, is electrically connected to the IGBT drive circuit of the power conversion unit and the power switch tube drive circuit of the bridge switch matrix via a PWM signal output port, and is electrically connected to the control coil of the protective circuit breaker via a digital IO port. The control chip has an integrated AD converter for processing analog sensor signals and an integrated timer for generating accurate PWM control signals.

[0029] The control chip is provided with a dynamic impedance balancing control module for dynamically adjusting the conduction strategy and power distribution ratio of the bridge switch matrix according to grid voltage fluctuations and three-phase imbalance, thereby achieving stable power output of the dual output ports.

[0030] like Figure 2 As shown, the dynamic impedance balancing control module is used to perform the following steps: S01. The voltage acquisition unit is used to collect instantaneous values ​​of the three-phase voltage of the power grid, and the current detection unit is used to collect instantaneous values ​​of the current at the dual output ports. The voltage imbalance is divided into three levels: mild imbalance, moderate imbalance, and severe imbalance according to the degree of voltage imbalance. A mild imbalance of 60% corresponds to a contribution rate of 0.85, a moderate imbalance of 30% corresponds to a contribution rate of 0.65, and a severe imbalance of 10% corresponds to a contribution rate of 0.35. The virtual impedance contribution is used to evaluate the impact of each level on power transmission efficiency, and an initial virtual impedance matrix is ​​established as a reference for power distribution. S02. Based on the load current difference and voltage difference of the dual output ports, the load demand difference is divided into three modes: synchronous load, asynchronous load, and polarized load. The synchronous load conversion rate of 0.92 corresponds to a delay rate of 15 milliseconds, the asynchronous load conversion rate of 0.78 corresponds to a delay rate of 35 milliseconds, and the polarized load conversion rate of 0.56 corresponds to a delay rate of 65 milliseconds. When correcting the initial virtual impedance based on the floating weight index, an impedance optimization mechanism equation is used to output the optimized virtual impedance parameters; S03, establishing a current shunt path between the two H-bridge units by controlling the conduction timing of the bridge switch matrix, monitoring and calculating a circulating current effect coefficient based on detection data of the current detection unit, and starting a circulating current suppression algorithm when the circulating current effect coefficient exceeds a set threshold; S04. Calculate the current balance of the dual output ports in real time based on the instantaneous current values ​​of the dual output ports and establish a current balance contribution evaluation system. The current distribution state is divided into three ranges: excellent balance, general balance, and imbalance. An excellent balance ratio of 45% corresponds to a contribution of 0.95, a general balance ratio of 40% corresponds to a contribution of 0.75, and an imbalance ratio of 15% corresponds to a contribution of 0.45. When the current balance contribution is lower than 0.6, solve the optimal duty cycle distribution scheme through the least squares optimization problem, adjust the duty cycle of each power switch tube in the bridge switch matrix, and redistribute the current flow. S05. Establishing a current distribution bridge matrix based on the optimized virtual impedance parameters and current balance, where matrix elements represent current distribution coefficients corresponding to respective switches, and dynamically updating matrix parameters according to load changes to achieve precise power control; S06. Based on the output power of the power conversion unit and the overall power density of the physical volume monitoring system, the efficiency loss is divided into three categories according to the source of conduction loss, switching loss, and magnetic loss. When conduction loss accounts for 55% of the total loss, the corresponding attenuation rate is 0.15; when switching loss accounts for 30% of the total loss, the corresponding attenuation rate is 0.25; and when magnetic loss accounts for 15% of the total loss, the corresponding attenuation rate is 0.35. When the power density drops by more than 8%, the efficiency improvement algorithm is activated to reduce the negative impact of switching loss by adjusting the switching frequency, optimize the dead time to reduce conduction loss, and adjust the working state of the filter capacitor group to suppress magnetic loss. S07: Output the optimized virtual impedance parameters and the current distribution bridge matrix to the bridge switch matrix to generate a new PWM drive signal, thereby achieving dynamic balanced distribution of power at the dual output ports.

[0031] Among them, the initial virtual impedance is specifically based on the equivalent impedance reference value set under the rated operating conditions of the system, which is used to describe the ideal transmission characteristics between the power conversion unit and the dual output ports, and the reference impedance matrix is ​​determined by mathematical modeling of the voltage and current ratio.

[0032] Among them, the optimized virtual impedance parameters are dynamic impedance parameters that are modified based on the initial virtual impedance according to the real-time grid status and load changes. The impedance matrix elements are adjusted in real time through an adaptive algorithm to compensate for the impact of grid imbalance on power transmission.

[0033] The floating weight index is a dynamic coefficient that reflects the degree of load difference between the two output ports. Its value range is 0.1 to 2.0. When the loads on the two ports are equal, the floating weight index is 1.0. When the load difference increases, the floating weight index is adjusted accordingly to dynamically correct the power allocation ratio.

[0034] Among them, the circulation effect coefficient is a quantitative parameter that describes the degree of current circulation within the bridge switch matrix. It is calculated by measuring the correlation between the current of each switch tube and the total output current. The larger the circulation effect coefficient, the more serious the invalid circulation, which affects the system efficiency.

[0035] The current balance is specifically an indicator of the uniformity of the current distribution at the dual output ports. It is determined by calculating the ratio of the standard deviation to the average value of the effective current values ​​of the two ports. The closer the current balance is to 1, the more uniform the current distribution is.

[0036] Among them, the current distribution bridge matrix is ​​specifically a mathematical matrix that describes the current distribution relationship of each power switch tube in the bridge switch matrix. The matrix dimension is 8×2, each row corresponds to a switch tube, and each column corresponds to an output port. The matrix element value represents the current contribution coefficient of the switch tube to the corresponding port.

[0037] Among them, the virtual impedance contribution is a quantitative indicator that measures the contribution of virtual impedance to power transmission efficiency under different grid conditions. It is calculated by multiplying the voltage imbalance level and the corresponding power transmission success rate. The higher the virtual impedance contribution, the more stable the power transmission efficiency under the said state.

[0038] Among them, the current balancing contribution is a comprehensive indicator that evaluates the contribution of the current distribution uniformity of the dual output ports to the overall system performance. It is calculated by weighted summation of the current distribution state ratio and the corresponding system stability coefficient. The higher the current balancing contribution, the more conducive the current distribution is to the long-term stable operation of the system.

[0039] Among them, power density is specifically the power conversion capacity per unit volume, which is calculated by the ratio of the total output power of the system to the physical volume of the power conversion unit, reflecting the power conversion efficiency and compact design level of the system.

[0040] The impedance optimization mechanism equation is used to dynamically adjust the virtual impedance parameters according to the load characteristics and grid status. The input includes the load conversion rate coefficient, the grid voltage imbalance factor, the floating weight index, the delay compensation coefficient, and the temperature correction parameter. The output is the optimized virtual impedance parameter. The impedance optimization mechanism equation solves the optimal impedance configuration scheme through a multivariable nonlinear optimization algorithm, wherein the load conversion rate coefficient is derived from the synchronous load conversion rate, the asynchronous load conversion rate, and the polarized load conversion rate; the grid voltage imbalance factor is derived from the contribution rate of mild imbalance, moderate imbalance, and severe imbalance; the delay compensation coefficient is derived from the synchronous load delay rate, the asynchronous load delay rate, and the polarized load delay rate; the temperature correction parameter is derived from the operating temperature detection value of the power conversion unit; the optimized virtual impedance parameters are used to establish the current distribution bridge matrix in step S05 and generate the PWM drive signal in step S07.

[0041] The specific implementation of the above steps is described in detail below.

[0042] The power conversion unit adopts a three-phase rectifier bridge topology, including 6 power diodes and 6 insulated gate bipolar transistor switches. The power diodes use 1200V / 200A silicon carbide Schottky diodes, and the insulated gate bipolar transistor switches use 1200V / 300A devices. The three-phase rectifier bridge circuit converts the 380V AC power supply into a 750V DC power supply. The AC input of the power conversion unit is connected to the three-phase power supply of the power grid through a contactor, and the DC output is connected to the common input of the bridge switch matrix through a copper busbar with a cross-sectional area of ​​150 , the current carrying capacity reaches 400A.

[0043] The voltage acquisition unit contains 8 Hall voltage sensors with a rated measurement range of 0-1000V, an accuracy level of 0.5, and a response time of less than 1ms. Three voltage sensors are respectively set at the three-phase input terminals A, B, and C of the power grid to monitor the amplitude and phase relationship of the power grid voltage. One voltage sensor is set between the positive and negative poles of the DC output terminal of the power conversion unit to monitor the DC bus voltage. Four voltage sensors are respectively set between the positive and negative poles of the dual output ports to monitor the output voltage of each charging port. The voltage sensor is connected to the analog input port of the control chip through a shielded cable, and the signal transmission distance is controlled within 3m.

[0044] The current detection unit contains four Hall current sensors with a rated measurement range of 0 to 500A, an accuracy level of 0.5, and a response time of less than 0.5ms. One current sensor is set in the positive circuit of the DC output bus of the power conversion unit to monitor the total output current. One current sensor is set in the negative circuit of the DC output bus of the power conversion unit to monitor the total return current. Two current sensors are set in the positive lines of the dual output ports to monitor the output current of each charging port. The current sensor is connected to the analog input port of the control chip via a shielded twisted pair cable.

[0045] The bridge switch matrix uses a dual H-bridge topology and includes eight bidirectional power switches. Each switch is composed of two anti-parallel metal-oxide semiconductor field-effect transistors with a device specification of 1200V / 200A. The eight switches are divided into two groups, with four switches in each group forming a complete H-bridge unit. The first H-bridge unit corresponds to the first charging gun interface, and the second H-bridge unit corresponds to the second charging gun interface. The common input of the bridge switch matrix is ​​connected to the DC output of the power conversion unit via a copper busbar. The outputs of the two H-bridge units are connected to the corresponding charging gun interfaces via copper busbars.

[0046] The dual output ports include a primary charging gun connector and a secondary charging gun connector. The two connectors are symmetrically spaced 180 degrees on the front panel of the control cabinet, with a spacing of 1.2 meters. Each charging gun connector includes a positive terminal, a negative terminal, and a communication terminal. The positive and negative terminals are made of copper alloy and rated at 250A. The communication terminal is used for communication protocol interaction with the electric vehicle. The charging gun connector housing is made of flame-retardant polycarbonate and has an IP54 protection rating.

[0047] The filter capacitor bank consists of six electrolytic capacitors, each with a capacity of 4700μF, a rated voltage of 450V, and an operating temperature range of -25°C to 85°C. Four electrolytic capacitors are connected in parallel at the common input of the bridge switch matrix to filter the ripple current output by the power conversion unit. Two electrolytic capacitors are connected between the positive and negative terminals of the dual output ports to filter high-frequency ripple at the output ports. The electrolytic capacitors are bolted to the heat sink, which is made of extruded aluminum alloy and has a natural convection heat dissipation capacity of 50W.

[0048] The protective circuit breaker, located on the DC bus between the power conversion unit and the bridge switch matrix, utilizes a vacuum circuit breaker structure with a rated current of 400A, a breaking capacity of 20kA, and an operating time of less than 10ms. The control coil of the protective circuit breaker is rated at 24V and 15W and is connected to the digital output port of the control chip via a relay. When an overcurrent, short circuit, or ground fault is detected, the control chip outputs a disconnect signal, actuating the relay and disconnecting the power to the protective circuit breaker control coil, quickly disconnecting the circuit.

[0049] The control chip utilizes a 32-bit ARM Cortex-M4 architecture microcontroller with a main frequency of 168MHz. It features 512KB of flash memory and 192KB of random access memory, an integrated 12-bit analog-to-digital converter, and a high-precision timer. The control chip is mounted on a four-layer printed circuit board (PCB) measuring 200mm x 150mm and constructed from FR-4 epoxy resin within the system control cabinet. The control chip communicates with the voltage acquisition unit and current detection unit via a CAN bus interface. The CAN bus baud rate is set to 500kbps, allowing for a maximum communication distance of 100m. The control chip connects to the insulated gate bipolar transistor (IGBT) driver circuits of the power conversion unit and the power switch driver circuits of the bridge switch matrix via 12 pulse-width modulation (PWM) output ports. The PWM signal frequency is 20kHz and the amplitude is 15V. The control chip also connects to peripheral devices such as the circuit breaker's control coil, status indicator, and alarm buzzer via 8 digital input and output ports.

[0050] The specific implementation of the steps executed by the dynamic impedance balancing control module is described in detail below.

[0051] Step S01 is implemented by using a voltage acquisition unit to collect instantaneous values ​​of the three-phase grid voltages. The sampling frequency is set to 10kHz, and the sampling window length is 20ms, covering a complete power frequency cycle. The analog-to-digital converter built into the control chip converts the analog voltage signals into digital values ​​with a 12-bit resolution, corresponding to a voltage measurement accuracy of 0.24V. A fast Fourier transform algorithm is used to analyze the amplitude and phase relationship of the three-phase voltages and calculate the voltage imbalance index. The voltage imbalance is calculated using the symmetrical component method, extracting the ratio of the negative-sequence component to the positive-sequence component to determine the degree of imbalance. When the voltage imbalance is less than 2%, it is considered mild, with a contribution ratio of 60% and a corresponding contribution ratio of 0.85. When the voltage imbalance is between 2% and 5%, it is considered moderate, with a contribution ratio of 30% and a corresponding contribution ratio of 0.65. When the voltage imbalance is greater than 5%, it is considered severe, with a contribution ratio of 10% and a corresponding contribution ratio of 0.35. The virtual impedance contribution is calculated by multiplying the voltage imbalance level by the corresponding contribution rate. This is used to assess the impact of each level on power transmission efficiency. The initial virtual impedance matrix is ​​established based on the equivalent impedance reference value under the system's rated operating conditions. The matrix dimensions are 2×2, with the diagonal elements representing the baseline impedance value of each output port, and the off-diagonal elements representing the coupling impedance value between ports.

[0052] The specific implementation of step S02 involves using a current detection unit to collect instantaneous current values ​​at both output ports, with a sampling frequency consistent with voltage acquisition, set at 10kHz. The control chip calculates the load current and voltage difference between the two output ports, employing a sliding average filter algorithm to eliminate high-frequency noise interference. The filter window length is set to 100 sampling points. The load demand difference mode is determined based on the ratio of the load current difference to the average current. When the ratio is less than 10%, the load demand difference mode is determined. The transition rate is set to 0.92, and the corresponding delay rate is set to 15ms. When the ratio is between 10% and 30%, the load demand difference mode is determined. The transition rate is set to 0.78, and the corresponding delay rate is set to 35ms. When the ratio is greater than 30%, the load demand difference mode is determined. The transition rate is set to 0.56, and the corresponding delay rate is set to 65ms. A floating weight index is calculated based on the ratio of the load current difference to the total load current. The value range is limited to 0.1 to 2.0, and the floating weight index is 1.0 when the loads on both ports are equal. The impedance optimization mechanism equation utilizes a multivariable nonlinear optimization algorithm. Input parameters include the load conversion coefficient, grid voltage imbalance factor, floating weight index, delay compensation coefficient, and temperature correction parameter. The optimization algorithm uses a gradient descent method to solve the optimal impedance configuration. The number of iterations is limited to 50, and the convergence accuracy is set to 0.01%. The optimized virtual impedance parameters are obtained by modifying the diagonal and off-diagonal elements of the initial virtual impedance matrix. The correction coefficients are dynamically adjusted based on load characteristics and grid status.

[0053] The specific implementation of step S03 is to establish a current shunt path by controlling the conduction timing of the bridge switch matrix, and to implement a phase-shifted full-bridge control strategy to achieve power transfer between the two H-bridge units. The control chip generates eight pulse-width modulated drive signals with a phase difference of 45 degrees, which respectively control the eight power switches in the bridge switch matrix. The circulating current effect coefficient is calculated by measuring the correlation between the current of each switch and the total output current, and the similarity of the current waveforms is analyzed using the Pearson correlation coefficient algorithm. The calculation cycle of the circulating current effect coefficient is 1ms. When the average value of the circulating current effect coefficient for 10 consecutive calculation cycles exceeds 0.15, the circulating current suppression algorithm is activated. The circulating current suppression algorithm uses a zero-voltage switching control strategy to achieve soft switching by adjusting the conduction time difference between adjacent switches, reducing current surges during the switching process. The response time of the circulating current suppression algorithm is set to 5ms, and the suppression effect is evaluated by monitoring the decline in the circulating current effect coefficient, with the goal of reducing the circulating current effect coefficient to below 0.1.

[0054] The specific implementation of step S04 involves real-time calculation of current balance based on the instantaneous current values ​​of the dual output ports, using the ratio of the standard deviation to the average value as the balance indicator. The current balance calculation cycle is 10ms, and a sliding window algorithm is used to collect statistics on the current data of the most recent 100 sampling points. When the current balance is greater than 0.9, it is determined to be in an excellent balance state, with a contribution of 45% and a corresponding contribution of 0.95. When the current balance is between 0.7 and 0.9, it is determined to be in a fair balance state, with a contribution of 40% and a corresponding contribution of 0.75. When the current balance is less than 0.7, it is determined to be unbalanced, with a contribution of 15% and a corresponding contribution of 0.45. The current balance contribution is calculated by taking the weighted sum of the contribution of each state and the corresponding contribution. When the current balance contribution falls below 0.6, the duty cycle optimization algorithm is activated. The duty cycle optimization algorithm uses the least squares method to solve the optimal duty cycle allocation scheme, with the objective function being to minimize the sum of the squares of the current differences between the dual output ports. The optimization algorithm's constraints include upper and lower limits on the duty cycle of each switch, total power balance constraints, and switching frequency limits. The duty cycle adjustment step size is set to 1%, the adjustment period is 50ms, and the maximum adjustment range is limited to 20%.

[0055] The specific implementation of step S05 is to establish a current distribution bridge matrix based on optimizing virtual impedance parameters and current balance. The matrix dimension is 8×2, corresponding to 8 power switch tubes and 2 output ports. The matrix element value represents the current contribution coefficient of each switch tube to the corresponding output port, and the value range is 0 to 1. The process of establishing the current distribution bridge matrix adopts a linear programming algorithm. The constraints include the normalization condition of the current distribution coefficient of each switch tube and the power balance condition. The update cycle of the matrix parameters is 100ms. The exponential smoothing filter algorithm is used to reduce parameter fluctuations, and the smoothing coefficient is set to 0.8. The effectiveness of the current distribution bridge matrix is ​​evaluated by comparing the deviation between the expected current distribution and the actual current distribution. The deviation threshold is set to 5%. When the deviation exceeds the threshold, the control chip recalculates the matrix parameters to ensure the accuracy of the current distribution. The storage of the matrix parameters adopts a double buffering mechanism to ensure the continuous operation of the system during the parameter update process.

[0056] The specific implementation of step S06 is to monitor the overall power density of the system based on the output power and physical volume of the power conversion unit. The power density calculation period is 1s. The total output power of the system is obtained by multiplying the voltage and current of the dual output ports. The physical volume of the power conversion unit is determined to be 0.5 according to the equipment size specifications. Efficiency loss analysis uses a power balance equation to decompose total losses into three components: conduction loss, switching loss, and magnetic loss. Conduction loss accounts for 55% of total losses, with a corresponding attenuation factor set to 0.15. This is primarily due to the proportional relationship between the on-resistance of the power device and the square of the current. Switching loss accounts for 30% of total losses, with a corresponding attenuation factor set to 0.25. This is primarily due to the switching frequency multiplied by the voltage and current. Magnetic loss accounts for 15% of total losses, with a corresponding attenuation factor set to 0.35. This is primarily due to the core loss of the transformer and inductor. When the power density drops by more than 8%, the efficiency improvement algorithm is activated. The algorithm includes three submodules: switching frequency optimization, dead-time adjustment, and filter capacitor operating state optimization. Switching frequency optimization uses a variable frequency control strategy to dynamically adjust the switching frequency based on the load size, reducing the switching frequency at light loads to reduce switching losses. Dead-time optimization uses an adaptive dead-time control algorithm to dynamically adjust the dead-time based on the switching characteristics of the power device to reduce conduction losses. Filter capacitor operating state optimization reduces the equivalent series resistance loss of the capacitor by adjusting the charge and discharge timing of the capacitor.

[0057] The specific implementation of step S07 is to output the optimized virtual impedance parameters and the current distribution bridge matrix to the bridge switch matrix to generate a new pulse width modulation drive signal. The pulse width modulation signal is generated using a carrier comparison method, with the carrier frequency set to 20kHz and the carrier amplitude set to 5V. The control chip calculates the duty cycle of each power switch tube based on the current distribution bridge matrix, with a duty cycle accuracy of 0.1%. The pulse width modulation drive signal is connected to the power switch tube drive circuit via an optoelectronic isolator, with an isolation voltage of 2500V and a transmission delay time of less than 100ns. The rise time and fall time of the drive signal are set to 50ns and 30ns, respectively, to ensure fast switching of the power switch tube. The synchronous control of the pulse width modulation drive signal adopts a master-slave clock architecture, with the master clock frequency of 80MHz and the slave clock synchronized via a phase-locked loop, with a phase error of less than 1 degree. The new pulse width modulation drive signal achieves dynamic balanced power distribution of the dual output ports, with a power distribution accuracy of 2% and a response time of less than 20ms. The system realizes automatic adjustment of power distribution through closed-loop control. The controller adopts proportional-integral-differential algorithm with the proportional coefficient set to 0.5, the integral coefficient set to 0.1, and the differential coefficient set to 0.05.

[0058] It should be noted that the virtual impedance dynamic adjustment technology of the present invention realizes active compensation for grid voltage imbalance by establishing an initial virtual impedance matrix and correcting it in real time according to the grid state. The traditional charging pile system adopts a fixed-parameter switch control strategy, which cannot adapt to the dynamic changes in the amplitude and phase of the three-phase voltage of the grid, resulting in a significant decrease in power conversion efficiency with grid fluctuations. The present invention divides the voltage imbalance into three levels: mild, moderate, and severe, and introduces the concept of virtual impedance contribution to convert the complex grid state into quantifiable control parameters, so that the system can dynamically adjust the transmission impedance characteristics according to the actual grid conditions, thereby maintaining stable power transmission efficiency in a grid fluctuation environment, and significantly improving the system's adaptability and robustness to changes in the grid environment.

[0059] The current distribution bridge matrix optimization technology achieves precise power control by constructing a mathematical matrix of eight rows and two columns to describe the current contribution relationship of each power switch tube to the dual output ports. The traditional switch matrix control method lacks precise quantitative management of the current distribution of each switch tube, and cannot achieve optimal power distribution when the dual-port load requirements are different. The present invention monitors the current balance of the dual ports in real time and constructs a current balance contribution evaluation system. When an imbalance in current distribution is detected, the least squares method is used to optimize and solve the optimal duty cycle distribution scheme, and the conduction time ratio of each switch tube is dynamically adjusted to ensure that the current is accurately distributed according to the actual load requirements. This mathematical matrix-based control method transforms empirical switch control into precise control guided by theory, greatly improving the accuracy and response speed of power distribution.

[0060] The circulation effect suppression technology effectively solves the problem of internal circulating current in the H-bridge topology by monitoring the circulation effect coefficient and starting an adaptive suppression algorithm. Traditional dual-output port charging systems are prone to generating invalid circulation losses during the operation of the bridge switch matrix. These circulating currents not only reduce system efficiency, but also affect the charging stability and equipment life. The present invention quantifies the degree of circulation by measuring the correlation between the current of each switch tube and the total output current. When the circulation effect coefficient exceeds the set threshold, the switch timing control is automatically optimized. By adjusting the conduction strategy between the H-bridge units, a reasonable current shunt path is established, which fundamentally reduces the generation of internal invalid circulating current, significantly reduces the power loss of the system and improves the stability of the charging process.

[0061] The synergistic effect of the above three technologies forms a complete dynamic power balance control system, which has significant comprehensive advantages over traditional single control methods. Virtual impedance dynamic adjustment technology solves the impact of grid fluctuations on power transmission from the source, providing a stable basic condition for subsequent precise control; current distribution bridge matrix optimization technology realizes precise power distribution between dual ports on this basis, ensuring that each port obtains the appropriate charging power according to actual needs; circulation effect suppression technology reduces invalid losses from the perspective of internal system optimization, ensuring the efficient execution of the overall control strategy. The three technologies are unified and coordinated through the impedance optimization mechanism equation, organically combining grid state compensation, load adaptation control and internal loss suppression, forming a complete closed-loop control system from external adaptation to internal optimization, so that the charging pile can still maintain efficient and stable dual-port power output performance in complex working environments.

[0062] Specifically, the core principle of the present invention's technical solution for addressing unbalanced power distribution lies in the establishment of a dynamic control mechanism based on virtual impedance. Traditional switch matrices employ a fixed conduction strategy, making them incapable of responding to changes in external conditions. By introducing the concept of virtual impedance, the present invention abstracts the power transmission path into an adjustable equivalent impedance network, providing a theoretical basis for dynamic control.

[0063] The logical basis of virtual impedance balancing control is to convert grid imbalances and load differences into quantifiable control parameters. The system first establishes an initial virtual impedance matrix as a baseline reference, which reflects the power transmission characteristics under ideal conditions. When a three-phase voltage imbalance is detected in the grid, the degree of imbalance is determined through a graded assessment and the corresponding virtual impedance contribution is calculated. This quantification method enables complex grid conditions to be accurately described using a mathematical model.

[0064] Load adaptability control is achieved through a floating weight index. When the load demands on the two output ports differ, the system determines the load mode based on the current and voltage differences and calculates the corresponding transition rate and delay rate parameters. The impedance optimization mechanism equation integrates multiple influencing factors, including the load transition rate coefficient, the grid voltage imbalance factor, and the delay compensation coefficient. A multivariable nonlinear optimization algorithm is used to determine the optimal impedance configuration, ensuring that the power allocation strategy matches actual demand.

[0065] Current balancing control achieves precise regulation by establishing a current distribution bridge matrix. This matrix describes the current contribution of the eight switches to the two output ports, with each matrix element representing the distribution coefficient for the corresponding switch. The system monitors the current balance between the two ports in real time. When an imbalance is detected, it uses the least squares method to optimize the optimal duty cycle distribution, dynamically adjusting the on-time of each switch and redistributing the current flow.

[0066] The circulating current suppression mechanism achieves adaptive control by monitoring the circulating current effect coefficient. The H-bridge topology of the bridge switch matrix is ​​prone to internal circulating current under improper control. The system quantifies the degree of circulating current by calculating the correlation between the current of each switch and the total output current. When the circulating current effect exceeds the threshold, the suppression algorithm is automatically activated to optimize the switch timing control and reduce ineffective losses.

[0067] The entire control strategy relies on the high-speed computing capabilities of a 32-bit ARM processor and precise control of PWM signals. The processor collects sensor data in real time via the CAN bus, executes complex optimization algorithms, and converts the results into PWM drive signals that are output to the switch matrix, forming a closed-loop control system to ensure dynamic balance in power distribution.

[0068] A specific embodiment 1 of the present invention is provided below. The specific implementation of each step in this embodiment 1 is described in detail as follows.

[0069] The specific implementation of step S01 is the same as above, and the calculation process involved is described in detail as follows: The voltage unbalance is calculated using the symmetrical component method, which is specifically expressed as: ; Where, is the voltage unbalance; is the negative sequence voltage component, which is extracted from the three-phase voltage by the fast Fourier transform algorithm; is the positive sequence voltage component, which represents the balanced component of the three-phase voltage.

[0070] The calculation of virtual impedance contribution is specifically expressed as: ; Where, is the virtual impedance contribution; For the The proportion of level voltage imbalance, including , , ; For the The contribution rate corresponding to the level, where , , ; The values ​​1, 2, and 3 correspond to mild, moderate, and severe imbalance, respectively.

[0071] The initial virtual impedance matrix is ​​specifically expressed as: ; Where, is the initial virtual impedance matrix; 、 The reference impedance value of each output port is determined based on the voltage-to-current ratio under the rated operating conditions of the system; 、 The coupling impedance between the two ports indicates the degree of electrical coupling between the two output ports.

[0072] The mathematical modeling of the voltage to current ratio is specifically expressed as: ; Where, is the baseline impedance value; is the system rated voltage; is the rated power of the system.

[0073] The specific implementation of step S02 is the same as above, and the calculation process involved is described in detail as follows: The calculation of load demand difference mode determination is specifically expressed as: ; Where, is the load current difference ratio; 、 They are the load currents of the first and second output ports, respectively, which are collected in real time by the current detection unit.

[0074] The calculation of the floating weight index is specifically expressed as follows: ; Where, is a floating weight index with a value range of 0.1 to 2.0; It is an adjustment coefficient with a value range of 0.5 to 2.0, which is used to control the sensitivity of the weight index.

[0075] The calculation of the load transfer rate coefficient is specifically expressed as: ; Where, is the load conversion coefficient; For the Weight factors for different load patterns; For the The transition rate of the load mode, where , , Corresponding to synchronous, asynchronous and polarized loads respectively.

[0076] The calculation of the delay compensation coefficient is specifically expressed as: ; Where, is the delay compensation coefficient; For the The delay rate of the load pattern, where millisecond, millisecond, millisecond.

[0077] The impedance optimization mechanism equation is specifically expressed as: ; Where, To optimize the virtual impedance parameters; is the impedance correction; is the grid voltage unbalance factor; is the temperature correction parameter, which comes from the operating temperature detection value of the power conversion unit; It is a multivariable nonlinear optimization function and is solved by gradient descent method.

[0078] The iterative formula of the gradient descent method is specifically expressed as: ; Where, For the Impedance parameter of the iteration; is the learning rate, the value is 0.01; is the gradient of the objective function; is the number of iterations, the maximum value is 50.

[0079] The specific implementation of step S03 is the same as above, and the calculation process involved is described in detail as follows: The calculation of the circulation effect coefficient is specifically expressed as: ; Where, is the circulation effect coefficient; For the The current of a switching tube; is the average switching current, and the calculation formula is ; is the total output current; The switch tube number ranges from 1 to 8.

[0080] The calculation of the Pearson correlation coefficient is specifically expressed as: ; Where, For the Correlation coefficient between the current of each switch tube and the total output current; is the number of sampling points; is the time serial number; and are the average values ​​of the corresponding currents.

[0081] The specific implementation of step S04 is the same as above, and the calculation process involved is described in detail as follows: The calculation of current balance is specifically expressed as: ; Where, is the current balance; is the standard deviation of the dual output port current, and the calculation formula is ; is the average value of the dual output port current, and the calculation formula is .

[0082] The calculation of current balancing contribution is specifically expressed as: ; Where, Current balancing contribution; For the The proportion of current distribution states, among which , , ; For the The contribution corresponding to the state, , , ; The values ​​1, 2, and 3 correspond to excellent equilibrium, general equilibrium, and imbalance states, respectively.

[0083] The objective function of the least squares method to optimize the duty cycle is specifically expressed as: ; Where, is the objective function; For the The target current of each output port; For the The actual current of each output port; Output port number, value 1 or 2.

[0084] The specific implementation of step S05 is the same as above, and the calculation process involved is described in detail as follows: The current distribution bridge matrix is ​​specifically expressed as: ; Where, for current distribution bridge matrix; For the The switch tube is The current contribution coefficient of each output port ranges from 0 to 1; The switch tube number ranges from 1 to 8; Output port number, value 1 or 2.

[0085] The normalization condition of matrix elements is specifically expressed as: ; In the formula, the sum of the current contribution coefficients of each switch tube to the two output ports is equal to 1.

[0086] The exponential smoothing filter algorithm for matrix parameter update is specifically expressed as: ; Where, is the updated matrix element; is the historical matrix element; is the matrix element currently being calculated; is the smoothing coefficient, and its value is 0.8.

[0087] The specific implementation of step S06 is the same as above, and the calculation process involved is described in detail as follows: The calculation of power density is specifically expressed as: ; Where, is the power density; is the total output power of the system, and the calculation formula is ; is the physical volume of the power conversion unit, and its value is ; 、 are the voltages of the two output ports respectively.

[0088] The calculation of efficiency loss decomposition is specifically expressed as: ; Where, is the total loss; is the conduction loss; is the switching loss; is the magnetic loss.

[0089] The specific calculation of each loss component is: ; ; ; Where 0.55, 0.30, and 0.15 are the proportions of conduction loss, switching loss, and magnetic loss to total loss, respectively; 0.15, 0.25, and 0.35 are the corresponding attenuation rates, respectively.

[0090] The specific implementation of step S07 is the same as above, and the calculation process involved is described in detail as follows: The calculation of pulse width modulation duty cycle is specifically expressed as: ; Where, For the The duty cycle of each switch; Assign bridge matrix elements to currents; For the The reference voltage of each output port; is the carrier voltage amplitude, which is 5V; The output port number.

[0091] The comparison function of the carrier comparison method is specifically expressed as: ; Where, For the The pulse width modulation signal of the switching tube; is the carrier frequency, which is 20kHz; is the time variable.

[0092] The transfer function of the proportional-integral-derivative controller is specifically expressed as: ; Where, Pass a function to the controller; is the proportional coefficient, which takes a value of 0.5; is the integral coefficient, which takes a value of 0.1; is the differential coefficient, with a value of 0.05; is the Laplace variable.

[0093] The calculation of power allocation error is specifically expressed as: ; Where, Allocate error for power; 、 The set power for the two output ports; 、 is the actual power of the two output ports, which is obtained by real-time calculation of the product of voltage and current.

[0094] In order to better understand and implement the present invention, the following provides a specific application scenario of the present invention, Example 2: A researcher built a DC charging pile bridge power distribution system with a rated power of 120kW to verify the effectiveness of the dynamic impedance balance control method. The system includes hardware and software parts, such as Figure 3 As shown in the figure, the hardware part adopts a three-phase rectifier bridge structure power conversion unit with a DC output voltage range of 200V to 750V and a maximum output current of 160A. The power conversion unit consists of six IGBT switches with a rated current of 50A and six power diodes with a reverse recovery time of 35ns. The switching frequency is set to 20kHz. Figure 4 The bridge switch matrix shown uses an H-bridge topology and includes eight bidirectional power switches (S1-S8). Each switch has an on-resistance of 8mΩ and a turn-off time of 120ns. The dual output ports are configured as the first and second charging connectors, respectively, with a 180-degree symmetrical physical structure. Each port has a rated output power of 60kW.

[0095] The voltage acquisition unit is equipped with eight 0.2-class voltage sensors, installed at the three-phase grid input, the DC output of the power conversion unit, and the dual output ports. They have a measurement range of 0V to 1000V and a response time of 2ms. The current sensing unit includes four 0.5-class Hall-effect current sensors with a rated measurement range of 0A to 200A, a linearity error of less than 0.1%, and a temperature coefficient of 50ppm / °C. The filter capacitor bank consists of six 4700μF electrolytic capacitors, four of which are connected in parallel at the input of the bridge switch matrix with an equivalent series resistance of 12mΩ, and two of which are connected at each of the dual output ports. The protective circuit breaker uses an electronic fast-acting circuit breaker with an operating time of less than 5ms and a breaking capacity of 10kA.

[0096] The control chip uses a 32-bit processor based on the ARM Cortex-M4 core, running at 168MHz. It features a built-in 12-bit A / D converter and 16 PWM output channels. The control chip communicates with the sensor unit via the CAN bus, with a baud rate of 500kbps and a communication cycle of 1ms. The PWM signal output port is connected to the IGBT driver circuit, with a drive voltage of 15V and a dead time of 2μs. The digital I / O port is connected to the circuit breaker control coil, with an output voltage of 24V and a drive current of 50mA.

[0097] The dynamic impedance balance control module of the software is the core component of the system. Its connection and composition are as follows: Figure 5 As shown. In actual operation, researchers collected the instantaneous value of the three-phase voltage of the power grid through the voltage acquisition unit at a sampling frequency of 10kHz, and the sampling window length was set to 20ms. In a certain test, the voltage of phase A of the power grid was 218V, the voltage of phase B was 215V, and the voltage of phase C was 220V. The positive sequence voltage component was obtained by fast Fourier transform algorithm analysis. 217.7V, negative sequence voltage component is 2.1V. The voltage imbalance is calculated according to the formula , it is judged to be a slightly unbalanced state. The calculation result of virtual impedance contribution is .

[0098] The results of the dual output port load current detection show that the first output port current The second output port current is 85A. is 78A, the load current difference ratio , it is determined to be synchronous load mode. The floating weight index calculation result is Load transfer rate coefficient The temperature sensor detects that the operating temperature of the power conversion unit is 65℃, and the temperature correction parameter is Set to 1.08.

[0099] As shown in Table 1, the system operating parameters under different grid conditions are shown: Table 1 System operating parameters under different grid conditions

[0100] The impedance optimization mechanism equation is solved by gradient descent method, and the learning rate is set , converged after 25 iterations. The results of optimizing the virtual impedance parameters show that the diagonal elements of the initial virtual impedance matrix are adjusted from the baseline value of 1.2Ω to 1.08Ω, and the off-diagonal elements are adjusted from 0.15Ω to 0.12Ω.

[0101] Monitoring of the circulating current coefficient of the bridge switch matrix showed that under normal operation, the coefficient was 0.087, below the set threshold of 0.15. However, when the load suddenly changed, the coefficient instantly rose to 0.168, triggering the circulating current suppression algorithm. By adjusting the on-time differences between adjacent switches, the coefficient was reduced to 0.094 within 5ms, achieving effective circulating current suppression.

[0102] The real-time calculation results of current balance show that the standard deviation of the current of the dual output ports is ,average value , current balance , it is determined to be an excellent balance state. The calculation result of current balance contribution is , which is higher than the set threshold of 0.6, and there is no need to start the duty cycle optimization algorithm.

[0103] As shown in Table 2, the specific values ​​of the current distribution bridge matrix are shown: Table 2 Current distribution bridge matrix parameters

[0104] The power density monitoring results show that the total output power of the system , power density The results of efficiency loss analysis show that the total loss is 3.2kW, of which the conduction loss is 1.49kW, the switching loss is 0.72kW, and the magnetic loss is 0.33kW. When the system load increases to full load operation, the power density rises to 240kW / , various losses increase accordingly but the proportion remains stable.

[0105] During the pulse width modulation drive signal generation process, the control chip calculates the duty cycle of each switch tube according to the current distribution bridge matrix. Taking the first switch tube as an example, the duty cycle The carrier comparison method generates a PWM signal with a frequency of 20kHz and a duty cycle accuracy of 0.1%. Test results of the proportional-integral-derivative controller's response characteristics show that the system responds to load changes in 18ms and maintains a steady-state error of less than 1.5%.

[0106] As shown in Table 3, the performance parameters of the system under different load conditions are shown: Table 3 System performance parameters under different load conditions

[0107] Long-term test results show that the system maintained stable performance after 72 hours of continuous operation. Power distribution accuracy remained within 2.5%, and current balance remained above 0.92. Temperature monitoring data showed that the maximum operating temperature of the power devices was 78°C, well below the rated operating temperature limit of 105°C.

[0108] To verify the superiority of the dynamic impedance balancing control method, researchers conducted a comparative test against a traditional static power allocation method. This traditional method uses a fixed duty cycle control strategy, disregarding grid state variations and load variations, and relies solely on preset parameters for power allocation. The comparative test was conducted on the same hardware platform for 24 hours, with system performance data recorded every 30 minutes.

[0109] Test results of the traditional static power allocation method show that under conditions of mild grid voltage imbalance, the power allocation error is 3.8%, the current balance is 0.82, and the response time is 35ms. When the grid experiences moderate imbalance, the power allocation error increases to 6.2%, the current balance drops to 0.74, and system stability is significantly reduced. Under conditions of dynamic load fluctuations, the traditional method has poor adaptability, and the power allocation accuracy fluctuates greatly, with a maximum error of 8.1%.

[0110] In contrast, the system using dynamic impedance balancing control demonstrated significant technical advantages under the same test conditions. Under conditions of mild grid voltage imbalance, the power allocation error was reduced to 1.8%, a 15.8% improvement over the traditional method. Current balance increased to 0.957, a 16.7% improvement. Response time was shortened to 18ms, a 17.4% increase in response speed. Under conditions of moderate grid imbalance, the power allocation error of the dynamic control method was only 2.6%, far lower than the 6.2% of the traditional method, demonstrating significant technical improvements.

[0111] Comparative system efficiency tests show that the average efficiency of the traditional static power distribution method is 94.2%, while the average efficiency of the dynamic impedance balancing control method reaches 96.8%, an efficiency improvement of 2.6 percentage points. Under full-load operating conditions, the dynamic control method reduces power loss by 18.3% compared to the traditional method, primarily due to optimized switch timing control and circulating current suppression algorithms. This improved current balancing performance results in more uniform thermal stress distribution in power devices during long-term operation, effectively extending the equipment's service life.

[0112] The dynamic impedance balancing control method monitors grid status and load changes in real time, adaptively adjusting virtual impedance parameters and power allocation strategies. This fundamentally addresses the technical challenges of traditional static control methods, which are unable to adapt to changing operating conditions. This method significantly improves key technical indicators such as power allocation accuracy, current balancing performance, and system response speed, providing a reliable technical guarantee for the efficient and stable operation of DC charging piles.

[0113] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed by the present invention, which should be covered by the scope of protection of the present invention.

Claims

1. A DC charging pile bridge power distribution system, comprising a power conversion unit, a voltage acquisition unit, a current detection unit, a bridge switch matrix, dual output ports, a filter capacitor bank, a protective circuit breaker, and a control chip, characterized in that: The AC input of the power conversion unit is connected to the three-phase power supply of the power grid, and the DC output is connected to the common input of the bridge switch matrix; the bridge switch matrix includes two independent H-bridge units, each H-bridge unit corresponds to an output port; the control chip communicates data with the voltage acquisition unit and the current detection unit through the CAN bus. The control chip is equipped with a dynamic impedance balancing control module, which realizes dynamic balanced distribution of power at the dual output ports by establishing a virtual impedance matrix and a current distribution bridge matrix.

2. The system according to claim 1, wherein: The dynamic impedance balance control module specifically performs the following steps: collecting the instantaneous values ​​of the three-phase voltage of the power grid and the instantaneous values ​​of the current at the dual output ports, establishing a hierarchical evaluation system based on the voltage imbalance, and establishing an initial virtual impedance matrix based on the virtual impedance contribution; dividing the load demand into three modes based on the load difference of the dual output ports: synchronous load, asynchronous load, and polarized load; using the impedance optimization mechanism equation to correct the initial virtual impedance based on the floating weight index, and outputting the optimized virtual impedance parameters; establishing a current shunt path through the conduction timing control of the bridge switch matrix, monitoring the circulating current effect coefficient, and initiating the circulating current suppression algorithm; The current balance of the dual output ports is calculated in real time, and a current balance contribution evaluation system is constructed. The optimal duty cycle distribution scheme is solved through the least squares optimization problem. A current distribution bridge matrix is ​​established, and the matrix parameters are dynamically updated according to load changes. The overall power density of the system is monitored and the efficiency improvement algorithm is activated. The optimized virtual impedance parameters and the current distribution bridge matrix are output to the bridge switch matrix to generate a new PWM drive signal.

3. The system according to claim 2, characterized in that The steps for establishing the initial virtual impedance matrix are as follows: collecting the instantaneous values ​​of the three-phase voltage of the power grid through the voltage acquisition unit, collecting the instantaneous values ​​of the current of the dual output ports through the current detection unit, and dividing the voltage imbalance into three levels: mild imbalance, moderate imbalance, and severe imbalance according to the voltage imbalance. The influence of each level on the power transmission efficiency is evaluated through the virtual impedance contribution, and the initial virtual impedance matrix is ​​established as a benchmark reference for power distribution.

4. The system according to claim 3, characterized in that The initial virtual impedance is specifically based on the equivalent impedance reference value set under the rated operating conditions of the system, which is used to describe the ideal transmission characteristics between the power conversion unit and the dual output ports. The reference impedance matrix is ​​determined by mathematical modeling of the voltage-current ratio.

5. The system according to claim 4, characterized in that The virtual impedance contribution is a quantitative indicator that measures the contribution of virtual impedance to power transmission efficiency under different grid conditions. It is calculated by multiplying the voltage imbalance level by the corresponding power transmission success rate. A higher virtual impedance contribution indicates a more stable power transmission efficiency under the stated conditions.

6. The system according to claim 5, characterized in that The steps of outputting optimized virtual impedance parameters are as follows: based on the load current difference and voltage difference of the dual output ports, the load demand difference is divided into three modes: synchronous load, asynchronous load, and polarized load. When correcting the initial virtual impedance based on the floating weight index, the impedance optimization mechanism equation is used to output the optimized virtual impedance parameters.

7. The system according to claim 6, characterized in that The optimized virtual impedance parameters are dynamic impedance parameters that are modified based on the initial virtual impedance according to the real-time grid status and load changes. The impedance matrix elements are adjusted in real time through an adaptive algorithm to compensate for the impact of grid imbalance on power transmission.

8. The system according to claim 7, characterized in that The floating weight index is a dynamic coefficient that reflects the degree of load difference between the two output ports. Its value range is 0.1 to 2.

0. When the loads on the two ports are equal, the floating weight index is 1.

0. When the load difference increases, the floating weight index is adjusted accordingly to dynamically correct the power allocation ratio.

9. The system according to claim 8, characterized in that The steps for starting the circulating current suppression algorithm are to establish a current shunt path between the two H-bridge units through the conduction timing control of the bridge switch matrix, monitor and calculate the circulating current effect coefficient based on the detection data of the current detection unit, and start the circulating current suppression algorithm when the circulating current effect coefficient exceeds the set threshold.

10. The system according to claim 9, characterized in that The circulation effect coefficient is a quantitative parameter that describes the degree of current circulation within the bridge switch matrix. It is calculated by measuring the correlation between the current of each switch tube and the total output current. The larger the circulation effect coefficient, the more serious the invalid circulation, which affects the system efficiency.

Images