Test method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a test method and device, a storage medium and electronic equipment, and relates to the technical field of computers.The method comprises the steps that a test parameter set is obtained, and the test parameter set comprises test parameters of at least one temperature condition; loss test is carried out by using the test parameter set and a first test board to obtain a limit value of link loss, and the limit value of link loss is at least used for reflecting the driving capability of a sending end chip; carrying out loss test by using the test parameter set and a first test board, comprising the following steps: adjusting the temperature of the first PCB, and determining the target temperature of the adjusted first PCB; and determining test parameters matched with the target temperature, and performing loss test by using the matched test parameters. Therefore, the link loss characteristic is changed by adopting the test parameters matched with each temperature and controlling the measurement temperature, and then the limit value of the link loss is obtained to reflect the driving capability of the sending end chip.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a testing method, device, storage medium, and electronic equipment. Background Art

[0002] In traditional digital system design, high-speed interconnects are often ignored because they have minimal impact on system performance. However, with the continuous advancement of computer technology, high-speed interconnects are becoming a dominant factor in determining system performance, often leading to unforeseen issues and significantly increasing the complexity of system design. Therefore, in high-speed link design verification, it is important to comprehensively consider the interactions between various modules. High-speed signal link stability should be assessed through testing and evaluation methods to improve the success rate of overall system design and shorten the R&D cycle.

[0003] During the server system design process, high-speed solutions need to be designed based on the actual signal driving capabilities of the CPU chip, including PCB board selection, chip layout and wiring, etc. For example, Figure 1 In the design diagram shown, the high-speed signal loss between CPU0 and CPU1 must not exceed the CPU's drive capability limit. The longer the signal transmission distance and the lower the PCB material grade, the greater the signal loss. When the loss exceeds the chip's limit, signal distortion will occur, leading to system failure. Therefore, before system design, it is important to clearly define the CPU chip's drive capability and design accordingly. Failure to assess the chip's limit significantly increases the risk of product design failure.

[0004] To evaluate the CPU's driving capabilities, traditional testing is typically performed on the designed link. This involves using the CPU's default signal parameters. As the link degrades, the test results gradually deteriorate. When the test results exceed a certain threshold, the CPU's limits are identified. Currently, there are two main design approaches for testing links.

[0005] Solution 1: Design multiple verification boards, each with a different trace length. By varying the trace length, the link loss between CPU0 and CPU1 is adjusted while simultaneously testing the signal. As the trace length increases, the signal deteriorates. When the trace length reaches a certain limit, the signal deteriorates to its limit, allowing evaluation of the CPU's driving capability.

[0006] Solution 2: Design multiple verification boards with consistent trace lengths. Each verification board has a different PCB material grade. Lower PCB grades correspond to greater losses. Signal testing is performed from high to low PCB grade. As the PCB grade decreases, the signal deteriorates. When the PCB grade drops to a certain level, the signal deteriorates to the limit, at which point the CPU drive capability can be assessed.

[0007] Although both of the above solutions can find the chip's driving capability limit, the test process is based on the CPU's default parameters and no parameter optimization is performed. Therefore, the results obtained cannot truly reflect the CPU's actual driving capability. In addition, the current solution is costly because it requires the design and proofing of multiple samples. Solution 1 requires the design of PCB versions of multiple lengths, which increases verification costs. Solution 2 also increases verification costs by designing verification boards of multiple different PCB grades. At the same time, because the differences between boards of different grades are not small, when the limit capability approaches the limit between the two boards, it is necessary to use the design of Solution 1 to further refine the link characteristics, further increasing the design cost. Summary of the Invention

[0008] The present application provides a testing method, device, storage medium and electronic device to at least solve the above technical problems existing in the prior art.

[0009] The technical solution of the embodiment of the present application is implemented as follows: In a first aspect, an embodiment of the present application provides a testing method, the method comprising: Acquire a test parameter set, wherein the test parameter set includes a test parameter of at least one temperature condition; Performing a loss test using the test parameter set and the first test board to obtain a limit value of link loss, wherein the limit value of link loss is used to at least reflect a driving capability of a transmitting end chip; The first test board includes: a first PCB board, and a transmitting end chip and a receiving end chip arranged on the first PCB board; The performing a loss test using the test parameter set and the first test board includes: Adjusting the temperature of the first PCB board and determining the adjusted target temperature of the first PCB board; Determine test parameters that match the target temperature, and perform a loss test using the matched test parameters.

[0010] In the above solution, obtaining the test parameter set includes: For a second test board, a plurality of first parameters of the first test chip and a plurality of second parameters of the second test chip are set; the second test board comprises: a second PCB board, a first test chip and a second test chip arranged on the second PCB board; Performing a pre-test based on the plurality of first parameters and the plurality of second parameters to obtain a test parameter set; The pre-test is performed based on the plurality of first parameters and the plurality of second parameters to obtain a test parameter set, including: At a first temperature, performing signal quality detection on a plurality of parameter combinations according to the plurality of first parameters and the plurality of second parameters, and determining the first parameter and the second parameter corresponding to the optimal signal quality result according to the plurality of signal quality results; adjusting the temperature, performing signal quality detection on a plurality of parameter combinations according to the plurality of first parameters and the plurality of second parameters at the adjusted second temperature, and determining the first parameter and the second parameter corresponding to the optimal signal quality result according to the plurality of signal quality results; By analogy, the first parameter and the second parameter corresponding to the optimal signal quality results under multiple temperatures are obtained as the test parameter set; The test parameter set is saved to the transmitting end chip and the receiving end chip.

[0011] In the above solution, the test parameters include: a first parameter and a second parameter; The first parameter is used by the transmitting end chip to adjust the preset value of the signal; The second parameter is used by the receiving end chip to perform signal equalization to increase the clarity of the received signal.

[0012] In the above solution, pre-testing is performed based on the plurality of first parameters and the plurality of second parameters to obtain a test parameter set, which further includes: Performing temperature zoning on the second test plate to obtain at least one temperature zone; Using a temperature sensor to collect the temperature of each temperature sensor; The temperature of the second PCB is determined according to the temperature of each temperature sensor and the coefficient of the temperature zone where the temperature sensor is located.

[0013] In the above solution, determining the adjusted test parameters for the temperature matching of the first PCB board and performing a signal test using the matching test parameters includes: determining the temperature of the first PCB board according to a temperature sensor provided on the first PCB board; Triggering the transmitting chip to select a first parameter according to the temperature of the first PCB board and to send a test signal according to the first parameter; triggering the receiving chip to select a second parameter according to the temperature of the first PCB board and to adjust the received test signal according to the second parameter; determining a number of bit errors based on the sent test signal and the received test signal; If the number of bit errors exceeds the threshold, the limit value of the link loss is determined; If the number of bit errors does not exceed the threshold, the temperature of the first PCB board is readjusted to determine the adjusted temperature of the first PCB board; a test parameter matching the adjusted temperature is determined, and a signal test is performed using the matching test parameter.

[0014] In the above solution, determining the limit value of the link loss includes: Determine the loss per unit length corresponding to the temperature at which the number of bit errors exceeds a threshold; A limit value of the link loss is determined based on the link length and unit length loss of the first PCB board.

[0015] In the above solution, there are multiple temperature sensors; each temperature sensor is used to test the temperature in a different temperature zone; The step of determining the adjusted target temperature of the first PCB board includes: Determine the weight coefficient corresponding to the temperature zone to which each temperature sensor belongs; A target temperature of the first PCB board is determined according to each temperature sensor and the weight coefficient.

[0016] In the above solution, determining the weight coefficient corresponding to the temperature zone to which each temperature sensor belongs includes: Assign a weight coefficient to each temperature zone based on the link length within each temperature zone. The longer the link, the greater the weight coefficient. or, A weight coefficient is assigned to each temperature zone based on the link loss corresponding to the link routing length and temperature in each temperature zone.

[0017] In the above solution, if the first PCB board is divided into a plurality of temperature zones, determining the link length of the first PCB board includes: determining the link length in each temperature zone; Determining the unit length loss corresponding to the temperature when the number of bit errors exceeds the threshold, including: determining the unit length loss in each temperature region; Accordingly, determining a limit value of the link loss based on the link length and the loss per unit length of the first PCB board includes: Determine the link loss in each temperature zone based on the link length in each temperature zone and the unit length loss corresponding to each temperature zone; Based on the link loss in each temperature zone, the limit value of the link loss is determined.

[0018] In the above solution, if the transmission paths of the link are distributed on different layers of the PCB board, determining the link length in each temperature zone includes: determining the trace length of the layers involved in each temperature zone; Determining the unit length loss in each temperature region includes: determining the unit length loss corresponding to each layer in each temperature region; Determining the link loss in each temperature zone according to the link length in each temperature zone and the unit length loss corresponding to each temperature zone includes: Determine the link loss of each layer based on the trace length of the layers involved in each temperature zone and the unit length loss corresponding to each layer; The link loss of each temperature zone is determined based on the link losses of the layers involved in each temperature zone.

[0019] In the above solution, the method further includes: A loss test connector is used to detect the unit length loss value of at least one PCB board at different temperatures; the at least one PCB board includes: a first PCB board.

[0020] In the above solution, adjusting the temperature of the first PCB board includes: The fan controller is used to control the fan speed to adjust the temperature of the first PCB board.

[0021] In a second aspect, an embodiment of the present application provides a testing device, the device comprising: An acquisition module, configured to acquire a test parameter set, wherein the test parameter set includes a test parameter of at least one temperature condition; a testing module, configured to perform a loss test using the test parameter set and the first test board to obtain a limit value of link loss, wherein the limit value of link loss is used to at least reflect a driving capability of a transmitting end chip; The first test board includes: a first PCB board, and a transmitting end chip and a receiving end chip arranged on the first PCB board; The performing a loss test using the test parameter set and the first test board includes: Adjusting the temperature of the first PCB board and determining the adjusted target temperature of the first PCB board; Determine test parameters that match the target temperature, and perform a loss test using the matched test parameters.

[0022] In a third aspect, an embodiment of the present application provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any one of the test methods described.

[0023] In a fourth aspect, an embodiment of the present application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute any one of the test methods described.

[0024] The embodiments of the present application have the following beneficial effects: The test method, device, storage medium, and electronic device provided in the embodiments of the present application are applied to obtain a test parameter set, wherein the test parameter set includes a test parameter for at least one temperature condition; a loss test is performed using the test parameter set and a first test board to obtain a limit value of link loss, wherein the limit value of link loss is used to at least reflect the driving capability of the transmitting chip; wherein the first test board includes: a first PCB board, and a transmitting chip and a receiving chip arranged on the first PCB board; performing the loss test using the test parameter set and the first test board includes: adjusting the temperature of the first PCB board, determining a target temperature of the adjusted first PCB board; determining test parameters that match the target temperature, and performing a loss test using the matched test parameters. In this way, the temperature-dependent characteristics of the PCB board are utilized to change the link loss characteristics by adopting test parameters that match each temperature and controlling the measurement temperature, thereby obtaining a limit value of link loss to reflect the driving capability of the transmitting chip.

[0025] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a CPU interconnection provided in an embodiment of the present application; Figure 2 A flow chart of a testing method provided in an embodiment of the present application; Figure 3 A schematic diagram of a testing method provided in an embodiment of the present application; Figure 4 A schematic diagram of a loss test provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of a testing device provided in an embodiment of the present application; Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, features, and advantages of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0028] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0029] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0031] Figure 2 A flow chart of a test method provided in an embodiment of the present application is shown as follows: Figure 2 As shown, the test method includes: Step 201: Acquire a test parameter set, where the test parameter set includes at least one test parameter of a temperature condition; Step 202: Perform a loss test using the test parameter set and the first test board to obtain a link loss limit value; the link loss limit value is used to at least reflect the driving capability of the transmitting end chip; The first test board includes: a first PCB board and a transmitting end chip and a receiving end chip arranged on the first PCB board; The performing a loss test using the test parameter set and the first test board includes: Adjusting the temperature of the first PCB board and determining the adjusted target temperature of the first PCB board; Determine test parameters that match the target temperature, and perform a loss test using the matched test parameters.

[0032] Here, the transmitting chip refers to the CPU chip that generates and sends signals, while the receiving chip refers to the CPU chip that receives signals, which is used to receive and process signals.

[0033] The test parameter set includes test parameters for at least one temperature condition, each temperature condition corresponds to a different test parameter, and the test parameter is the optimal test parameter under the corresponding temperature adjustment.

[0034] The link loss limit refers to the maximum attenuation a signal can withstand during transmission, reflecting the upper limit of signal quality degradation from the transmitter chip to the receiver chip. The drive capability of the transmitter chip refers to the signal strength and driving force it can provide.

[0035] The link loss limit is related to the drive capability of the transmitter chip, as this determines the signal strength it can output. If signal attenuation is excessive and the transmitter chip's drive capability is insufficient, communication quality may be degraded or signal loss may occur. Therefore, the link loss limit reflects the chip's drive capability; a larger limit indicates a stronger drive capability.

[0036] In the embodiment of the present application, by pre-obtaining the optimal test parameters under different temperature conditions, it is ensured that the test parameters used by the transmitting chip and the receiving chip during the test are optimal, that is, the use of the test parameters under the same temperature conditions can best reflect the optimal performance of the transmitting chip (such as a CPU chip) and the receiving chip (such as a CPU chip). By utilizing the temperature-dependent characteristics of the PCB board, the link loss is changed by precisely controlling the measured temperature. At the same time, the performance of the transmitting chip and the receiving chip is maximized by applying the optimal parameters. In this way, the ultimate capability of the transmitting chip can be accurately determined, thereby improving the accuracy of the test. In addition, this method does not require the design of multiple cables or multiple grades of PCB boards, nor does it require the design of multiple cables or multiple grades of PCB boards, greatly reducing the verification cost. In addition, for chips with the same pins, a single PCB board can be used for testing, and it only needs to be installed on the first PCB board as described above.

[0037] In some embodiments, obtaining the test parameter set includes: For a second test board, a plurality of first parameters of the first test chip and a plurality of second parameters of the second test chip are set; the second test board comprises: a second PCB board, a first test chip and a second test chip arranged on the second PCB board; Performing a pre-test based on the plurality of first parameters and the plurality of second parameters to obtain a test parameter set; The pre-test is performed based on the plurality of first parameters and the plurality of second parameters to obtain a test parameter set, including: At a first temperature, performing signal quality detection on a plurality of parameter combinations according to the plurality of first parameters and the plurality of second parameters, and determining the first parameter and the second parameter corresponding to the optimal signal quality result according to the plurality of signal quality results; adjusting the temperature, performing signal quality detection on a plurality of parameter combinations according to the plurality of first parameters and the plurality of second parameters at the adjusted second temperature, and determining the first parameter and the second parameter corresponding to the optimal signal quality result according to the plurality of signal quality results; By analogy, the first parameter and the second parameter corresponding to the optimal signal quality results under multiple temperatures are obtained as the test parameter set; The test parameter set is saved to the transmitting end chip and the receiving end chip.

[0038] Here, the signal quality result can be measured by the eye diagram of the received signal. During testing, the optimal signal quality result can be the signal with the largest eye opening and no significant noise or distortion. Specifically, at each temperature, the optimal test parameters are selected for signal testing. The test parameters corresponding to the largest eye opening, the most stable signal waveform, and the least noise and interference are selected as the optimal test parameters.

[0039] Here, the second test board may include a second PCB board, a first test chip and a second test chip. The purpose of the second test board is to evaluate test parameters.

[0040] It should be noted that different PCB materials may have varying effects on temperature, signal transmission speed, and loss. Different materials can lead to variations in signal loss, delay, and other factors during testing. This is particularly true for high-frequency signal transmission, where the material's characteristics can affect signal quality and stability. Therefore, the first and second PCBs can be made of the same material. However, if the materials are similar and the impact is minimal, the first and second PCBs can be made of different materials.

[0041] In some embodiments, the test parameters include: a first parameter and a second parameter; The first parameter is used by the transmitting end chip to adjust the preset value of the signal; The second parameter is used by the receiving end chip to perform signal equalization to increase the clarity of the received signal.

[0042] Here, the first parameter can be a transmitter (TX) preset parameter. This is a preset value used by the transmitter chip to adjust the signal and control the initial state of the signal. By setting the first parameter, the transmitter chip can pre-process or pre-condition the signal to ensure that the signal is in a suitable state before transmission. This preset value can involve adjustments to the signal's amplitude, frequency, waveform, and other aspects to ensure stable and clear signal transmission and adapt to different transmission conditions (such as temperature and interference), thereby optimizing signal transmission.

[0043] The second parameter can be a CTLE (Continuous-Time Linear Equalizer) parameter, which is used by the receiver chip for signal equalization. The receiver chip uses the second parameter for signal equalization to improve received signal quality, enhance the receiver chip's decoding capabilities, and improve signal clarity.

[0044] CTLE is an analog signal equalization technology that improves signal quality by adjusting the received signal to compensate for attenuation and distortion during transmission. Its purpose is to make the received signal clearer in the time and frequency domains, reduce noise and interference, and enable more accurate signal decoding and processing at the receiver.

[0045] In some embodiments, performing a pre-test based on the plurality of first parameters and the plurality of second parameters to obtain a test parameter set further includes: Performing temperature zoning on the second test plate to obtain at least one temperature zone; Using a temperature sensor to collect the temperature of each temperature sensor; The temperature of the second PCB is determined according to the temperature of each temperature sensor and the coefficient of the temperature zone where the temperature sensor is located.

[0046] Here, the second test board can be placed in the test chassis. Considering that the temperature distribution inside the test chassis may be uneven, generally speaking, the closer to the chip, the higher the temperature, it is proposed to divide the second test board into temperature zones, for example, high temperature zone, medium temperature zone, and low temperature zone, and set a temperature sensor in each temperature zone, such as Figure 3 Wherein, CPU0 represents the first test chip or the transmitting end chip, and CPU1 represents the second test chip or the receiving end chip.

[0047] Multiple temperature sensors can be arranged on the second PCB board to monitor the temperature of different areas on the board in real time. At the same time, correction or compensation can be performed in combination with the coefficients of the temperature areas to ultimately obtain the accurate temperature of the entire second PCB board.

[0048] In one example, the sum of the coefficients of each temperature zone is 1. The temperature of each temperature zone is multiplied by the coefficient and then added together, and the result obtained is used as the accurate temperature of the entire second PCB board.

[0049] In some embodiments, determining the test parameters that match the adjusted temperature of the first PCB board, and performing a signal test using the matched test parameters, includes: determining the temperature of the first PCB board according to a temperature sensor provided on the first PCB board; Triggering the transmitting chip to select a first parameter according to the temperature of the first PCB board and to send a test signal according to the first parameter; triggering the receiving chip to select a second parameter according to the temperature of the first PCB board and to adjust the received test signal according to the second parameter; determining a number of bit errors based on the sent test signal and the received test signal; If the number of bit errors exceeds the threshold, the limit value of the link loss is determined; If the number of bit errors does not exceed the threshold, the temperature of the first PCB board is readjusted to determine the adjusted temperature of the first PCB board; a test parameter matching the adjusted temperature is determined, and a signal test is performed using the matching test parameter.

[0050] Here, the method can be applied to a test device or a test platform. In addition to the first test board and the second test board, the device or platform can also have a dedicated test device that can trigger each device to perform a corresponding operation.

[0051] The transmitting chip and the receiving chip can independently read or obtain the test parameter set, or pre-save the test parameter set to the transmitting chip and the receiving chip. During testing, the controller can trigger the transmitting chip and the receiving chip to determine the temperature of the first PCB board based on the temperature detected by the temperature sensor, and each chip can determine the test parameters based on the temperature of the first PCB board (i.e., the transmitting chip selects the first parameter corresponding to the current temperature to adjust the signal transmission state, and the receiving chip selects the second parameter corresponding to the current temperature to equalize and adjust the received signal). Then, the controller compares the test signal sent by the transmitting end with the signal received by the receiving end, and counts the number of bit errors (Bit Error Rate, BER) that occur. Here, the number of bit errors is an important indicator of link signal quality.

[0052] If the number of bit errors exceeds the threshold, it indicates poor link signal quality and has reached its performance limit. The link loss limit can then be determined. If the number of bit errors does not exceed the threshold, link performance is within an acceptable range. The test process then continues by adjusting the PCB temperature and resetting the target environmental conditions (i.e., resetting the temperature environment). For this new temperature, the transmitter and receiver chips each re-determine their matching test parameters (first and second parameters). Using these matching parameters, a new signal test is performed. This cycle repeats until the number of bit errors exceeds the threshold. If the number of bit errors remains within the threshold, the temperature at which the maximum number of bit errors occurs can be selected.

[0053] For example, it is assumed that the test parameter set includes test parameters for 10 temperature conditions, which are test parameters corresponding to 10 degrees, 20 degrees, 30 degrees, 40 degrees, 50 degrees, 60 degrees, 70 degrees, 80 degrees, 90 degrees, and 95 degrees, respectively.

[0054] At 10 degrees, determine the test parameters that match 10 degrees, and use the matching test parameters to perform signal testing; if the number of bit errors obtained does not exceed the threshold, adjust the temperature to 20 degrees, determine the test parameters that match 20 degrees, and use the matching test parameters to perform signal testing; if the number of bit errors obtained still does not exceed the threshold, test at 30 degrees, 40 degrees, 50 degrees, 60 degrees, 70 degrees, 80 degrees, 90 degrees, and 95 degrees in sequence until the temperature at which the number of bit errors exceeds the threshold is obtained.

[0055] It's important to note that as temperature rises, the electrical properties of PCB materials change, leading to decreased signal transmission quality and increased link loss. This is because as temperature rises, the material's conductivity, dielectric constant, and other physical properties change, potentially leading to greater signal attenuation, increased noise, or increased bit error rates. Based on these PCB characteristics, temperature adjustment can be performed from low to high temperatures, determining the lowest temperature at which the number of bit errors exceeds a threshold.

[0056] Comparing the test signal sent by the transmitter with the signal received by the receiver and counting the number of bit errors can be accomplished using a dedicated measurement program, which can be installed on the receiver chip or dedicated test equipment. For example, after receiving the test signal, the receiver chip decodes it, and the measurement program compares the decoded result with the original signal from the transmitter chip to count the number of bit errors. Alternatively, dedicated test equipment (such as a bit error rate tester, or BER tester) can be used to process the signal and output bit error rate data.

[0057] In some embodiments, determining the limit value of the link loss includes: Determining a link length of the first PCB board and a unit length loss corresponding to a temperature when the number of bit errors exceeds a threshold; A limit value of the link loss is determined based on the link length and unit length loss of the first PCB board.

[0058] Here, when the temperature changes, the signal quality will also be affected, which will lead to a change in the number of bit errors. If the number of bit errors exceeds a preset threshold, it means that the signal quality has deteriorated to an unacceptable level and the link performance has reached a limit.

[0059] On this basis, the loss per unit length at a specific temperature is determined when the number of bit errors exceeds a threshold. Based on the link length of the first PCB board (i.e., the actual physical length of the signal transmission) and the determined loss per unit length, the loss limit of the entire link can be calculated.

[0060] It should be noted that the performance of a link is affected by its length. Long links have higher losses. Therefore, by calculating the loss per unit length, the maximum total link loss can be inferred.

[0061] In this way, the limit value of link loss can be determined, and the driving capability of the transmitting chip can be evaluated. During system design, the maximum effective transmission range and performance boundary of the signal link can also be reflected, helping to optimize the stability and reliability of the system.

[0062] It should be noted that if a PCB board including two chips is designed, the test method provided in the embodiment of this application can also be used to test the system performance. It can take into account the driving capability of the transmitting chip and the influence of the link length to evaluate the system performance.

[0063] In some embodiments, there are multiple temperature sensors; each temperature sensor is used to test the temperature in a different temperature zone; The step of determining the adjusted target temperature of the first PCB board includes: Determine the weight coefficient corresponding to the temperature zone to which each temperature sensor belongs; A target temperature of the first PCB board is determined according to each temperature sensor and the weight coefficient.

[0064] Here, the first test board can be placed in the test chassis. Considering that the temperature distribution inside the test chassis may be uneven, generally speaking, the closer to the chip, the higher the temperature, it is proposed to divide the first test board into temperature zones, for example, high temperature zone, medium temperature zone, and low temperature zone, and set a temperature sensor in each temperature zone, such as Figure 3 Wherein, CPU0 represents the first test chip or the transmitting end chip, and CPU1 represents the second test chip or the receiving end chip.

[0065] Multiple temperature sensors can be arranged on the first PCB board to monitor the temperature of different areas on the board in real time. At the same time, correction or compensation can be performed in combination with the coefficients of the temperature areas to ultimately obtain the accurate temperature of the entire first PCB board.

[0066] In one example, the sum of the coefficients of each temperature zone is 1, and the temperature of each temperature zone is multiplied by the coefficient and then added together, and the result obtained is used as the accurate temperature of the entire first PCB board.

[0067] In some embodiments, determining the weight coefficient corresponding to the temperature zone to which each temperature sensor belongs includes: Assign a weight coefficient to each temperature zone based on the link length within each temperature zone. The longer the link, the greater the weight coefficient. or, A weight coefficient is assigned to each temperature zone based on the link loss corresponding to the link routing length and temperature in each temperature zone.

[0068] Here, within a temperature zone, if the link trace is long, the weight coefficient of that zone should be relatively large. Therefore, generally, the longer the link trace, the larger the weight coefficient. By assigning higher weight coefficients to long link areas, you can ensure that the temperature in these areas receives sufficient attention.

[0069] In addition to link length, the impact of link loss can also be considered. Link transmission loss varies under different temperature environments, potentially affecting signal quality. In high-temperature environments, the link's electrical performance may degrade, resulting in greater signal loss. In low-temperature environments, link loss may be lower, but it may still affect some transmission characteristics. Weighting factors are assigned to each region based on the temperature-dependent loss characteristics and in conjunction with link length. Therefore, temperature regions with higher loss generally receive higher weights to ensure that the impact of temperature is fully accounted for.

[0070] In some embodiments, if the first PCB board is divided into a plurality of temperature zones, determining the link length of the first PCB board includes: determining the link length within each temperature zone; Determining the unit length loss corresponding to the temperature when the number of bit errors exceeds the threshold, including: determining the unit length loss in each temperature region; Accordingly, determining a limit value of the link loss based on the link length and the loss per unit length of the first PCB board includes: Determine the link loss in each temperature zone based on the link length in each temperature zone and the unit length loss corresponding to each temperature zone; Based on the link loss in each temperature zone, the limit value of the link loss is determined.

[0071] Here, if the first PCB board is divided into multiple temperature zones, the link length within each temperature zone (ie, the physical length of the signal transmission line within the temperature zone) is first determined.

[0072] When the number of bit errors detected increases and exceeds the set threshold, the link loss is calculated for each temperature zone according to the following formula: Link loss = Link length in that temperature zone × Loss per unit length in that temperature zone.

[0073] In this way, combining the link length and temperature-dependent loss characteristics, the actual signal loss in each temperature region can be determined. Finally, the link loss in all regions is comprehensively considered to determine the limit value of the link loss on the entire PCB board.

[0074] Thus, the link loss limit value represents the maximum loss that the signal transmission can withstand under the current temperature conditions and link layout.

[0075] For example, assuming the link length in the high-temperature range is L1 and the loss per unit length is D1, then the link loss in the high-temperature range is R1 = L1 × D1, where × represents the multiplication sign. Assuming the link length in the medium-temperature range is L2 and the loss per unit length is D2, then the link loss in the medium-temperature range is R2 = L2 × D2. Assuming the link length in the low-temperature range is L3 and the loss per unit length is D3, then the link loss in the medium-temperature range is R3 = L3 × D3. The total link loss is R = R1 + R2 + R3, which gives the limit value.

[0076] In some embodiments, if the transmission paths of the link are distributed on different layers of the PCB board, determining the link length in each temperature zone includes: determining the trace length of the layers involved in each temperature zone; Determining the unit length loss in each temperature region includes: determining the unit length loss corresponding to each layer in each temperature region; Determining the link loss in each temperature zone according to the link length in each temperature zone and the unit length loss corresponding to each temperature zone includes: Determine the link loss of each layer based on the trace length of the layers involved in each temperature zone and the unit length loss corresponding to each layer; The link loss of each temperature zone is determined based on the link losses of the layers involved in each temperature zone.

[0077] Here, if the signal transmission paths within the temperature region are distributed on different layers of the PCB, the losses of each part can be calculated separately and summed.

[0078] For example, the length of the link in the high-temperature area on the surface is L11, the loss per unit length of the surface is D11, the length of the link in the high-temperature area on the inner layer is L12, and the loss per unit length of the inner layer is D12. Then the link loss in the high-temperature area is R1=L11×D11+L12×D12.

[0079] In some embodiments, the method further comprises: A loss test connector is used to detect the unit length loss value of at least one PCB board at different temperatures; the at least one PCB board includes: a PCB board made of the same material as the first PCB board.

[0080] Here, a special loss test connector can be used in advance to test the loss per unit length, such as Figure 4As shown, a loss measurement board is designed (typically made of the same material as the first PCB, so the measurement results can be applied to the first PCB). This board is equipped with a loss test connector and placed in a constant temperature chamber (ensuring consistent temperature across the link). The link loss is measured at various temperatures to obtain a loss baseline at each temperature. During the testing phase, the board is heated to multiple temperatures, and the link on the board is measured.

[0081] If different layers of the PCB are involved in the actual testing phase, the unit length loss values ​​of different layers at different temperatures can also be measured here.

[0082] In some embodiments, adjusting the temperature of the first PCB board includes: The fan controller is used to control the fan speed to adjust the temperature of the first PCB board.

[0083] Here, the fan controller may control the fan speed according to the control waveform to adjust the temperature of the first PCB board.

[0084] For example, the control waveform includes a PWM (Pulse Width Modulation) signal, which controls the fan speed by varying the width of the pulses. A longer pulse width means a higher fan speed, and vice versa.

[0085] In this way, by adjusting the control waveform to regulate the fan speed, the temperature of the PCB board can be controlled or maintained within an appropriate range for testing at different temperatures.

[0086] After the above tests, we can obtain the relationship between different fan speeds, temperatures, and link loss per unit length. In subsequent actual tests, we can directly query this relationship to perform temperature control, query link loss per unit length, etc.

[0087] As an example, the relationship for a certain PCB board may include: 1. Fan speed: 100%, temperature: 25 degrees, link loss per unit length: 12db; 2. Fan speed: 80%, temperature: 40 degrees, link loss per unit length: 12.7db; 3. Fan speed: 50%, temperature: 55 degrees, link loss per unit length: 13.5db; 4. Fan speed: 10%, temperature: 90 degrees, link loss per unit length: 15db.

[0088] Of course, other rotation speeds, temperatures, and link losses per unit length may also be included, which are not listed here one by one.

[0089] Figure 5A schematic diagram of the structure of a test device provided in an embodiment of the present application; Figure 5 As shown, the device includes: An acquisition module, configured to acquire a test parameter set, wherein the test parameter set includes a test parameter of at least one temperature condition; A testing module, configured to perform a test using the test parameter set and the first test board to obtain a signal test result; The first test board includes: a first PCB board, and a transmitting end chip and a receiving end chip arranged on the first PCB board; The performing a loss test using the test parameter set and the first test board includes: Adjusting the temperature of the first PCB board and determining the adjusted target temperature of the first PCB board; Determine test parameters that match the target temperature, and perform signal testing using the matched test parameters.

[0090] In some embodiments, the acquisition module is configured to set a plurality of first parameters of the first test chip and a plurality of second parameters of the second test chip for a second test board; the second test board comprises: a second PCB board, a first test chip and a second test chip disposed on the second PCB board; Performing a pre-test based on the plurality of first parameters and the plurality of second parameters to obtain a test parameter set; The pre-test is performed based on the plurality of first parameters and the plurality of second parameters to obtain a test parameter set, including: At a first temperature, performing signal quality detection on a plurality of parameter combinations according to the plurality of first parameters and the plurality of second parameters, and determining the first parameter and the second parameter corresponding to the optimal signal quality result according to the plurality of signal quality results; adjusting the temperature, performing signal quality detection on a plurality of parameter combinations according to the plurality of first parameters and the plurality of second parameters at the adjusted second temperature, and determining the first parameter and the second parameter corresponding to the optimal signal quality result according to the plurality of signal quality results; By analogy, the first parameter and the second parameter corresponding to the optimal signal quality results under multiple temperatures are obtained as the test parameter set; The test parameter set is saved to the transmitting end chip and the receiving end chip.

[0091] In some embodiments, the test parameters include: a first parameter and a second parameter; The first parameter is used by the transmitting end chip to adjust the preset value of the signal; The second parameter is used by the receiving end chip to perform signal equalization to increase the clarity of the received signal.

[0092] In some embodiments, the acquisition module is further used to perform temperature zoning on the second test plate to obtain at least one temperature zone; Using a temperature sensor to collect the temperature of each temperature sensor; The temperature of the second PCB is determined according to the temperature of each temperature sensor and the coefficient of the temperature zone where the temperature sensor is located.

[0093] In some embodiments, determining the test parameters that match the adjusted temperature of the PCB board, and performing a signal test using the matched test parameters, includes: determining the temperature of the first PCB board according to a temperature sensor provided on the first PCB board; Triggering the transmitting chip to select a first parameter according to the temperature of the first PCB board and to send a test signal according to the first parameter; triggering the receiving chip to select a second parameter according to the temperature of the first PCB board and to adjust the received test signal according to the second parameter; determining a number of bit errors based on the sent test signal and the received test signal; If the number of bit errors exceeds the threshold, the limit value of the link loss is determined; If the number of bit errors does not exceed the threshold, the temperature of the first PCB board is readjusted to determine the adjusted temperature of the first PCB board; a test parameter matching the adjusted temperature is determined, and a signal test is performed using the matching test parameter.

[0094] Here, the first PCB board and the transmitter chip and receiver chip provided on the first PCB board included in the first test board can be understood as part of the hardware of the test module, and corresponding test operations are implemented using these hardware.

[0095] In some embodiments, the test module is used to determine the loss per unit length corresponding to the temperature when the number of bit errors exceeds a threshold; A limit value of the link loss is determined based on the link length and unit length loss of the first PCB board.

[0096] In some embodiments, there are multiple temperature sensors; each temperature sensor is used to test the temperature in a different temperature zone; The transmitting chip and the receiving chip are used to determine the weight coefficient corresponding to the temperature zone to which each temperature sensor belongs; and determine the target temperature of the first PCB board according to each temperature sensor and the weight coefficient.

[0097] In some embodiments, the test module is further configured to assign a weight coefficient to each temperature zone based on the length of the link line in each temperature zone; the longer the link line, the greater the weight coefficient; or, A weight coefficient is assigned to each temperature zone based on the link loss corresponding to the link routing length and temperature in each temperature zone.

[0098] In some embodiments, if the first PCB is divided into multiple temperature zones, the testing module is used to determine the link length within each temperature zone; Determine the loss per unit length in each temperature region; Determine the link loss in each temperature zone based on the link length in each temperature zone and the unit length loss corresponding to each temperature zone; Based on the link loss in each temperature zone, the limit value of the link loss is determined.

[0099] In some embodiments, if the transmission paths of the link are distributed on different layers of the PCB board, the testing module is used to determine the trace lengths of the layers involved in each temperature zone; Determine the loss per unit length for each layer within each temperature region; Determine the link loss of each layer based on the trace length of the layers involved in each temperature zone and the unit length loss corresponding to each layer; The link loss of each temperature zone is determined based on the link losses of the layers involved in each temperature zone.

[0100] In some embodiments, the acquisition module is further used to detect the loss per unit length value of at least one PCB board at different temperatures using a loss test connector; the at least one PCB board includes: a first PCB board.

[0101] In some embodiments, the testing module is configured to control a fan speed using a fan controller to adjust the temperature of the first PCB board.

[0102] Here, the fan, fan controller, first test board, etc. described above can be understood as components included in the test module. The test module may also include other equipment, such as specialized test equipment configured for the test program described above. The acquisition module may also include machines that implement the aforementioned operations to complete the aforementioned operations and functions.

[0103] The second test board and other components described above can be understood as components included in the acquisition module. The acquisition module may also include other devices, such as a loss test connector and a constant temperature chamber. The acquisition module may also include a machine that connects to and controls the loss test connector, constant temperature chamber, and other components and acquires the result data to complete the above operations and functions.

[0104] It is understood that when implementing the corresponding test methods, the test devices provided in the above embodiments can, as needed, distribute the above-described processing to different modules to complete all or part of the above-described processing. Furthermore, the devices provided in the above embodiments and the corresponding method embodiments are based on the same concept. The specific implementation process is detailed in the method embodiments and will not be further described here.

[0105] An embodiment of the present application provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a test method.

[0106] An embodiment of the present application provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored. When the executable instructions are executed by a processor, the processor will execute the test method provided by the embodiment of the present application.

[0107] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface storage, optical disk, or CD-ROM; or various devices including one or any combination of the above memories.

[0108] In some embodiments, executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0109] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinating files (e.g., files storing one or more modules, subroutines, or code portions).

[0110] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0111] Figure 6A schematic diagram of the structure of an electronic device provided in an embodiment of the present application; Figure 6 As shown, the electronic device 60 includes: a processor 601, and a memory 602 in communication with the processor 601; the memory 602 stores instructions that can be executed by the processor 601. The instructions are executed by the processor 601, so that the processor 601 can perform: Acquire a test parameter set, wherein the test parameter set includes a test parameter of at least one temperature condition; Performing a loss test using the test parameter set and the first test board to obtain a limit value of link loss, wherein the limit value of link loss is used to at least reflect a driving capability of a transmitting end chip; The first test board includes: a first PCB board, and a transmitting end chip and a receiving end chip arranged on the first PCB board; The performing a loss test using the test parameter set and the first test board includes: Adjusting the temperature of the first PCB board and determining the adjusted target temperature of the first PCB board; Determine test parameters that match the target temperature, and perform a loss test using the matched test parameters.

[0112] In actual application, the electronic device 60 may further include: at least one network interface 603. The various components in the electronic device 60 are coupled together via a bus system 604. It is understood that the bus system 604 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 604 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 6 In the figure, various buses are labeled as bus system 604. There may be at least one processor 601 and at least one memory 602. The network interface 603 is used for wired or wireless communication between the electronic device 60 and other devices.

[0113] The memory 602 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device 60.

[0114] The methods disclosed in the above embodiments of the present application can be applied to or implemented by processor 601. Processor 601 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in processor 601 or by software instructions. Processor 601 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc. Processor 601 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium located in memory 602. Processor 601 reads information from memory 602 and, in conjunction with its hardware, completes the steps of the above test method.

[0115] In some embodiments, the electronic device 60 can be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to execute the aforementioned method.

[0116] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this application can be achieved. This is not a limitation herein.

[0117] In the above description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0118] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used in this application are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0119] It should be understood that in the various embodiments of the present application, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0120] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0121] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A testing method, characterized in that: The method comprises: Acquire a test parameter set, wherein the test parameter set includes a test parameter of at least one temperature condition; Performing a loss test using the test parameter set and the first test board to obtain a limit value of link loss, wherein the limit value of link loss is used to at least reflect a driving capability of a transmitting end chip; The first test board includes: a first PCB board, and a transmitting end chip and a receiving end chip arranged on the first PCB board; The performing a loss test using the test parameter set and the first test board includes: Adjusting the temperature of the first PCB board and determining the adjusted target temperature of the first PCB board; Determine test parameters that match the target temperature, and perform a loss test using the matched test parameters.

2. The method according to claim 1, characterized in that The obtaining of the test parameter set includes: For a second test board, a plurality of first parameters of the first test chip and a plurality of second parameters of the second test chip are set; the second test board comprises: a second PCB board, a first test chip and a second test chip arranged on the second PCB board; Performing a pre-test based on the plurality of first parameters and the plurality of second parameters to obtain a test parameter set; The pre-test is performed based on the plurality of first parameters and the plurality of second parameters to obtain a test parameter set, including: At a first temperature, performing signal quality detection on a plurality of parameter combinations according to the plurality of first parameters and the plurality of second parameters, and determining the first parameter and the second parameter corresponding to the optimal signal quality result according to the plurality of signal quality results; adjusting the temperature, performing signal quality detection on a plurality of parameter combinations according to the plurality of first parameters and the plurality of second parameters at the adjusted second temperature, and determining the first parameter and the second parameter corresponding to the optimal signal quality result according to the plurality of signal quality results; By analogy, the first parameter and the second parameter corresponding to the optimal signal quality results under multiple temperatures are obtained as the test parameter set; The test parameter set is saved to the transmitting end chip and the receiving end chip.

3. The method according to claim 2, characterized in that The test parameters include: a first parameter and a second parameter; The first parameter is used by the transmitting end chip to adjust the preset value of the signal; The second parameter is used by the receiving end chip to perform signal equalization to increase the clarity of the received signal.

4. The method according to claim 2, characterized in that Performing a pre-test based on the plurality of first parameters and the plurality of second parameters to obtain a test parameter set further includes: Performing temperature zoning on the second test plate to obtain at least one temperature zone; Using a temperature sensor to collect the temperature of each temperature sensor; The temperature of the second PCB is determined according to the temperature of each temperature sensor and the coefficient of the temperature zone where the temperature sensor is located.

5. The method according to claim 1, wherein Determining test parameters that match the adjusted temperature of the first PCB board, and performing a signal test using the matched test parameters, including: determining the temperature of the first PCB board according to a temperature sensor provided on the first PCB board; Triggering the transmitting chip to select a first parameter according to the temperature of the first PCB board and to send a test signal according to the first parameter; triggering the receiving chip to select a second parameter according to the temperature of the first PCB board and to adjust the received test signal according to the second parameter; determining a number of bit errors based on the sent test signal and the received test signal; If the number of bit errors exceeds the threshold, the limit value of the link loss is determined; If the number of bit errors does not exceed the threshold, the temperature of the first PCB board is readjusted to determine the adjusted temperature of the first PCB board; a test parameter matching the adjusted temperature is determined, and a signal test is performed using the matching test parameter.

6. The method according to claim 5, characterized in that Determining the limit value of the link loss includes: Determining a link length of the first PCB board and a unit length loss corresponding to a temperature when the number of bit errors exceeds a threshold; A limit value of the link loss is determined based on the link length and unit length loss of the first PCB board.

7. The method according to claim 5, characterized in that There are multiple temperature sensors; each temperature sensor is used to test the temperature in a different temperature zone; The step of determining the adjusted target temperature of the first PCB board includes: Determine the weight coefficient corresponding to the temperature zone to which each temperature sensor belongs; A target temperature of the first PCB board is determined according to each temperature sensor and the weight coefficient.

8. The method according to claim 7, characterized in that Determine the weight coefficient corresponding to the temperature zone to which each temperature sensor belongs, including: Assign a weight coefficient to each temperature zone based on the link length within each temperature zone. The longer the link, the greater the weight coefficient. or, A weight coefficient is assigned to each temperature zone based on the link loss corresponding to the link routing length and temperature in each temperature zone.

9. The method according to claim 6, characterized in that If the first PCB board is divided into a plurality of temperature zones, determining the link length of the first PCB board includes: determining the link length in each temperature zone; Determining the unit length loss corresponding to the temperature when the number of bit errors exceeds the threshold, including: determining the unit length loss in each temperature region; Accordingly, determining a limit value of the link loss based on the link length and the loss per unit length of the first PCB board includes: Determine the link loss in each temperature zone based on the link length in each temperature zone and the unit length loss corresponding to each temperature zone; Based on the link loss in each temperature zone, the limit value of the link loss is determined.

10. The method according to claim 9, characterized in that If the transmission paths of the link are distributed on different layers of the PCB board, determining the link length in each temperature zone includes: determining the routing length of the layers involved in each temperature zone; Determining the unit length loss in each temperature region includes: determining the unit length loss corresponding to each layer in each temperature region; Determining the link loss in each temperature zone according to the link length in each temperature zone and the unit length loss corresponding to each temperature zone includes: Determine the link loss of each layer based on the trace length of the layers involved in each temperature zone and the corresponding unit length loss of each layer; The link loss of each temperature zone is determined based on the link losses of the layers involved in each temperature zone.

11. The method according to claim 6, characterized in that The method further comprises: A loss test connector is used to detect the loss per unit length value of at least one PCB board at different temperatures; the at least one PCB board includes: a first PCB board.

12. The method according to claim 1, characterized in that The step of adjusting the temperature of the first PCB board includes: The fan controller is used to control the fan speed to adjust the temperature of the first PCB board.

13. A testing device, characterized in that: The device comprises: An acquisition module, configured to acquire a test parameter set, wherein the test parameter set includes a test parameter of at least one temperature condition; a testing module, configured to perform a loss test using the test parameter set and the first test board to obtain a limit value of link loss, wherein the limit value of link loss is used to at least reflect a driving capability of a transmitting end chip; The first test board includes: a first PCB board, and a transmitting end chip and a receiving end chip arranged on the first PCB board; The performing a loss test using the test parameter set and the first test board includes: Adjusting the temperature of the first PCB board and determining the adjusted target temperature of the first PCB board; Determine test parameters that match the target temperature, and perform a loss test using the matched test parameters.

14. An electronic device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the test method according to any one of claims 1 to 12.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the testing method according to any one of claims 1 to 12.

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