High-frequency power control system and method based on MOS (Metal Oxide Semiconductor) transistor

Abstract

The invention discloses a high-frequency power control system and a high-frequency power control method based on an MOS (Metal Oxide Semiconductor) transistor, which relate to the technical field of MOS transistor control, and are characterized in that the system has quick response and self-adaptive regulation and control capabilities on abnormal power consumption behaviors by performing targeted feedback regulation on gate driving parameters of a target MOS transistor and combining synchronous updating of a driving control logic strategy; and finally, a dynamic correction mechanism taking the periodic dynamic loss integral evaluation value TDE as a feedback basis is formed, the optimization effect of a driving control strategy can be verified by comparing the periodic dynamic loss integral evaluation values TDE before and after adjustment, repeated triggering of a parameter adjustment process is realized, a power control path capable of realizing closed-loop operation is constructed, and the power control efficiency is improved. According to the invention, loss sensing precision, strategy adjustment targeting and driving control closed loop of the MOS tube in a high-frequency working scene are realized, and multiple defects in time precision, energy identification and response path in the existing power control technology are effectively overcome.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS tube control, and in particular to a high-frequency power control system and method based on MOS tubes. Background Art

[0002] Currently, with the continuous advancement of electronic technology and manufacturing processes, semiconductor device manufacturing, as a key link in the field of microelectronics, undertakes the core task of converting design logic into physical circuits. Among them, integrated circuit transistors are the basic units for building core functional modules such as CMOS logic, power management, and signal driving. Their processing methods directly affect the performance, stability, and energy consumption of the chip. As transistor manufacturing processes continue to evolve towards high integration, high frequency, and small size, typical structures such as MOS transistors are widely used in high-frequency, high-speed control circuits.

[0003] However, transistor structures with integrated gas purification functions usually need to maintain a stable power control state in a high-frequency dynamic switching environment during operation. The power control strategies commonly used in the industry currently rely on fixed gate drive voltage, static threshold control or periodic average power regulation. These methods cannot accurately track and process the instantaneous switching loss behavior in each cycle when transistors such as MOS tubes are switched at high frequency. In particular, in transistors involving gas purification mechanisms, sensitive material modules such as surface adsorption layers and ionization capture regions may be embedded in their structures. These modules have high responsiveness and sensitivity to power fluctuations, current glitches, and short-term electric field disturbances. If the above-mentioned traditional control strategies ignore the distribution of switching losses within the microscopic time scale, it will lead to a reduction in the overall energy efficiency of the system and even induce problems such as local heat accumulation and structural degradation. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the present invention provides a high-frequency power control system and method based on MOS tubes, which solves the problems mentioned in the background technology.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: A high-frequency power control method based on MOS tubes, comprising the following steps:

[0006] S1. Synchronously sample the drain voltage and drain current of the target MOS tube in each switching cycle, and establish an instantaneous switching power data set IPD within the switching cycle according to time segments.

[0007] S2. Based on the instantaneous switching power data set IPD, integrate the power data in the current switching cycle to obtain the cycle dynamic loss integral evaluation value TDE in the current cycle, and bind it with the cycle number to form a time series data sequence;

[0008] S3. Using the time series data sequence composed of the periodic dynamic loss integral evaluation value TDE, a power fluctuation analysis model PFA is established to analyze the fluctuation trend of the periodic dynamic loss integral evaluation value TDE, identify abnormal peaks, oscillation drift and trend deviation behavior characteristics, and mark abnormal power consumption periods;

[0009] S4. Based on the abnormal cycle marking results output by the power fluctuation analysis model PFA, feedback is provided to adjust the gate drive parameters of the target MOS tube, including the drive voltage, turn-on delay time, and turn-off dead time parameters, and the drive control logic strategy is adjusted synchronously;

[0010] S5. Apply the adjusted drive control logic strategy to subsequent cycles, re-execute steps S1 and S2, obtain the new cycle dynamic loss integral evaluation value TDE_New, compare it with the dynamic loss integral evaluation value TDE data of the previous cycle, and judge the effectiveness of the current drive adjustment strategy.

[0011] Preferably, said S1 includes S11 and S12;

[0012] S11. After the MOS transistor enters the switching working state, a high-bandwidth data acquisition module is used to synchronously sample the drain voltage signal and the drain current signal of the target MOS transistor. During the sampling process, a unified clock is triggered to achieve time-synchronous acquisition of the voltage and current values ​​within the same cycle, thereby forming a voltage sampling sequence and a current sampling sequence.

[0013] S12. Based on the obtained voltage sampling sequence and current sampling sequence, the voltage value and current value in each time segment are paired and calculated point by point according to the preset time segment division method to construct the instantaneous power data of the corresponding time segment; the instantaneous power results of multiple time segments are arranged in chronological order to form the instantaneous switching power data set IPD corresponding to the current switching cycle.

[0014] Preferably, said S2 includes S21 and S22;

[0015] S21, receiving the instantaneous switching power data set IPD output in step S1, performing segment-by-segment cumulative calculation on the power data corresponding to all time segments within the current switching cycle, obtaining the total dynamic energy loss value within a single switching cycle of the current MOS tube, and defining the total dynamic energy loss value as the cycle dynamic loss integral evaluation value TDE;

[0016] S22. Bind the cycle dynamic loss integral evaluation value TDE to the cycle number corresponding to the current switching cycle, and record the two in one-to-one correspondence to form a time series data sequence of the cycle dynamic loss integral evaluation value TDE containing continuous cycles, providing a historical loss record basis for subsequent power fluctuation trend analysis.

[0017] Preferably, said S3 includes S31 and S32;

[0018] S31. Based on the time series data sequence formed by the periodic dynamic loss integral evaluation value TDE, and through the historical evolution relationship of the data sequence under continuous switching cycles, a power fluctuation analysis model PFA for characterizing the power consumption trend change characteristics is constructed. The power fluctuation analysis model PFA is used to fit the overall trend line, average value trajectory and fluctuation distribution state of the periodic dynamic loss integral evaluation value TDE;

[0019] The power fluctuation analysis model PFA is established through steps S311, S312 and S313;

[0020] S311, performing a weighted sliding average smoothing process on the continuous periodic dynamic loss integral evaluation values ​​TDE within a specified sliding time window to obtain a periodic dynamic loss mean trajectory line;

[0021] S312, using a regression curve to fit the periodic dynamic loss integral evaluation value TDE point value from the current period to several previous periods, to generate a periodic dynamic loss trend line for indicating the overall evolution direction of power consumption;

[0022] S313. Normalize the standard deviation of the deviation between the periodic dynamic loss integral evaluation value TDE and the mean trajectory line of each period, and count the fluctuation range and frequency to form a power fluctuation distribution state map, which is then combined with the periodic dynamic loss mean trajectory line and the periodic dynamic loss trend line to form the three structural elements of the power fluctuation analysis model PFA.

[0023] Preferably, S32, based on the established power fluctuation analysis model PFA, compare and analyze the periodic dynamic loss integral evaluation value TDE corresponding to the current switching cycle with three structural elements of the power fluctuation analysis model PFA, specifically including the following three judgment conditions:

[0024] Condition 1: Compare the periodic dynamic loss integral evaluation value TDE of the current period with the periodic dynamic loss mean trajectory line. If the deviation exceeds the set threshold range, it is identified as a peak abnormal fluctuation.

[0025] Condition 2: Compare the current cycle's cycle dynamic loss integral evaluation value TDE with the slope and trend direction of the cycle dynamic loss trend line. If consecutive cycles show an upward deviation trend, it is identified as a continuous increase in power consumption.

[0026] Condition 3: Check the historical fluctuation frequency boundary between the current period dynamic loss integral evaluation value TDE and the power fluctuation distribution state map. If alternating up and down oscillations are present, it is identified as periodic oscillation drift.

[0027] When the periodic dynamic loss integral evaluation value TDE meets the abnormal characteristic standard in any one of the three judgment conditions, it is marked as a power consumption abnormality cycle.

[0028] Preferably, said S4 includes S41 and S42;

[0029] S41. Based on the marking result of the abnormal power consumption cycle, identifying whether the current cycle belongs to the abnormal power consumption cycle; if it is determined to be the abnormal power consumption cycle, generating a drive control strategy adjustment trigger signal, wherein the drive control strategy adjustment trigger signal is used to activate the feedback adjustment channel in the gate control system and start the corresponding gate drive parameter correction process;

[0030] The gate drive parameter correction process includes steps S411, S412 and S413;

[0031] S411, identifying the gate drive parameter configuration set used in the current cycle;

[0032] S412: Calling a preset driving parameter adjustment strategy template, and determining target parameters to be adjusted for driving dimensions corresponding to the abnormal power consumption characteristics, including a driving voltage setting value, a turn-on delay time setting value, and a turn-off dead time setting value;

[0033] S413: Generate adjusted gate drive parameter setting values ​​as valid input for the next cycle execution.

[0034] Preferably, S42, performing feedback adjustment of the gate drive parameters of the target MOS tube and synchronously updating the drive control logic, adjusting the trigger signal based on the drive control strategy and completing the generation of the target parameter setting value, calling the gate drive parameter setting value corresponding to the cycle and applying it to the gate drive module of the target MOS tube in the current control cycle;

[0035] The gate drive parameters include: a drive voltage setting value, which is used to adjust the gate signal amplitude to match the dynamic power consumption state; a turn-on delay time setting value, which is used to correct the turn-on edge trigger timing to avoid cross conduction; and a turn-off dead time setting value, which is used to adjust the turn-off process time window to achieve soft switching or suppress overshoot.

[0036] At the same time, according to the application results of the gate drive parameter setting values, the gate drive parameter control configuration table is synchronously updated, and the gate signal output scheduling rules and cycle parameter execution paths associated therewith are synchronously adjusted.

[0037] Preferably, said S5 includes S51 and S52;

[0038] S51. After the gate drive parameter feedback adjustment is completed and the actual application is completed, the drain voltage signal and the drain current signal of the target MOS tube are re-collected in the next switching cycle, the voltage sampling sequence and the current sampling sequence in the cycle are obtained, and a new instantaneous switching power data set IPD_New is constructed.

[0039] Preferably, S52, inputting the new instantaneous switching power data set IPD_New into the periodic energy evaluation process, recalculating the new periodic dynamic loss integral evaluation value TDE_New corresponding to the current period, and comparing and analyzing the new periodic dynamic loss integral evaluation value TDE_New with the periodic dynamic loss integral evaluation value TDE of the period before adjustment, and judging the effectiveness of the drive adjustment strategy based on the comparative analysis results, specifically including:

[0040] When the new period dynamic loss integral evaluation value TDE_New is less than the period dynamic loss integral evaluation value TDE, it is determined that the driving adjustment effect has reached the expected result;

[0041] When the new cycle dynamic loss integral evaluation value TDE_New ≥ the cycle dynamic loss integral evaluation value TDE, it is determined that the drive adjustment effect does not meet expectations, and the gate drive parameter correction process is called again.

[0042] A high-frequency power control system based on MOS tubes, including a MOS tube data acquisition module, a dynamic loss evaluation module, a loss trend identification module, a gate drive module and a drive adjustment decision module;

[0043] The MOS transistor data acquisition module synchronously samples the drain voltage and drain current of the target MOS transistor in each switching cycle, and establishes an instantaneous switching power data set IPD in the switching cycle according to time segments;

[0044] The dynamic loss evaluation module integrates the power data in the current switching cycle based on the instantaneous switching power data set IPD, evaluates and obtains the cycle dynamic loss integral evaluation value TDE in the current cycle, and binds it with the cycle number to form a time series data sequence;

[0045] The loss trend identification module uses the time series data sequence composed of the periodic dynamic loss integral evaluation value TDE to establish a power fluctuation analysis model PFA, analyze the fluctuation trend of the periodic dynamic loss integral evaluation value TDE, identify abnormal peaks, oscillation drift and trend deviation behavior characteristics, and mark abnormal power consumption periods;

[0046] The gate drive module adjusts the gate drive parameters of the target MOS tube, including the drive voltage, turn-on delay time and turn-off dead time parameters, based on the abnormal cycle marking results output by the power fluctuation analysis model PFA, and simultaneously adjusts the drive control logic strategy;

[0047] The drive adjustment decision module applies the adjusted drive control logic strategy to the subsequent cycle, re-executes steps S1 and S2, obtains the new cycle dynamic loss integral evaluation value TDE_New, compares it with the dynamic loss integral evaluation value TDE data of the previous cycle, and determines the effectiveness of the current drive adjustment strategy.

[0048] The present invention provides a high-frequency power control system and method based on MOS tubes, which has the following beneficial effects:

[0049] (1) By making targeted feedback adjustments to the gate drive parameters of the target MOS tube and combining them with the synchronous update of the drive control logic strategy, the system is able to quickly respond to abnormal power consumption behavior and perform adaptive control. Finally, a dynamic correction mechanism is formed based on the periodic dynamic loss integral evaluation value TDE as the feedback basis. By comparing the periodic dynamic loss integral evaluation value TDE before and after adjustment, the optimization effect of the drive control strategy can be verified, and the parameter adjustment process can be repeatedly triggered. A power control path with closed-loop operation is constructed, which realizes the precise loss perception, targeted strategy adjustment, and closed-loop drive control of the MOS tube in high-frequency working scenarios, effectively overcoming the multiple deficiencies of existing power control technologies in time accuracy, energy recognition, and response path.

[0050] (2) Taking the periodic dynamic loss integral evaluation value TDE of the current switching cycle as the judgment object, it is compared with the periodic dynamic loss mean trajectory line, the periodic dynamic loss trend line and the power fluctuation distribution state map respectively, and judged in turn whether there is peak abnormal fluctuation, continuous rising power consumption behavior and periodic oscillation drift; once any judgment condition is met, the current cycle can be marked as a power consumption abnormality cycle, and the corresponding drive control strategy adjustment judgment signal is output. Based on the above mechanism, not only the joint modeling and intelligent judgment of the periodic dynamic loss integral evaluation value TDE in multiple dimensions such as evolution trend, center offset and statistical distribution are realized, but also through the combined reference of the model structure elements, an identification and judgment path that can dynamically identify power consumption risks and qualitatively distinguish fluctuation types is constructed, which has the characteristics of strong trend analysis capability, high abnormal response granularity and clear behavior recognition logic.

[0051] (3) By generating the trigger signal for adjusting the drive control strategy and starting the gate drive parameter correction process, the system can quickly respond and enter the three sub-processes of gate drive parameter configuration set identification, drive parameter adjustment strategy template call and target parameter generation based on the recognition result of the power consumption abnormality cycle, forming a new configuration result of the core drive parameters such as the drive voltage setting value, the conduction delay time setting value and the turn-off dead time setting value; then the above gate drive parameter setting values ​​are executed and applied in the actual control cycle, and the gate drive parameter control configuration table, the gate signal output scheduling rules and the cycle parameter execution path are updated synchronously to ensure that the drive parameters are not only set, but also can be dynamically distributed and adapted according to the cycle logic execution node, forming a closed-loop control chain integrating "setting-management-call-feedback", realizing an efficient control closed-loop path with the cycle dynamic loss integral evaluation value TDE as the performance feedback core, the gate drive parameter setting value as the execution entry, and the gate drive parameter control configuration table and the cycle parameter execution path as the strategy carrying structure, thereby improving the adjustment response rate, drive behavior consistency and fault self-repair capability of the system in actual operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is a schematic diagram of the steps of a high-frequency power control system based on MOS tubes of the present invention;

[0053] Figure 2 This is a schematic block diagram of a high-frequency power control method based on MOS tubes according to the present invention. DETAILED DESCRIPTION

[0054] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0055] Example 1

[0056] The present invention provides a high frequency power control system based on MOS tube, please refer to Figure 1 , including the following steps:

[0057] S1. Synchronously sample the drain voltage and drain current of the target MOS tube in each switching cycle, and establish an instantaneous switching power data set IPD within the switching cycle according to time segments.

[0058] S2. Based on the instantaneous switching power data set IPD, integrate the power data in the current switching cycle to obtain the cycle dynamic loss integral evaluation value TDE in the current cycle, and bind it with the cycle number to form a time series data sequence;

[0059] S3. Using the time series data sequence composed of the periodic dynamic loss integral evaluation value TDE, a power fluctuation analysis model PFA is established to analyze the fluctuation trend of the periodic dynamic loss integral evaluation value TDE, identify abnormal peaks, oscillation drift and trend deviation behavior characteristics, and mark abnormal power consumption periods;

[0060] S4. Based on the abnormal cycle marking results output by the power fluctuation analysis model PFA, feedback is provided to adjust the gate drive parameters of the target MOS tube, including the drive voltage, turn-on delay time, and turn-off dead time parameters, and the drive control logic strategy is adjusted synchronously;

[0061] S5. Apply the adjusted drive control logic strategy to subsequent cycles, re-execute steps S1 and S2, obtain the new cycle dynamic loss integral evaluation value TDE_New, compare it with the dynamic loss integral evaluation value TDE data of the previous cycle, and judge the effectiveness of the current drive adjustment strategy.

[0062] In this embodiment, a granular and time-continuous instantaneous switch power data set IPD and a periodic dynamic loss integral evaluation value TDE are constructed, thereby establishing a quantitative evaluation basis for the energy loss behavior of the MOS tube in each cycle at the power control layer; further, combined with the constructed power fluctuation analysis model PFA, not only a comprehensive modeling of the change trend of the periodic dynamic loss integral evaluation value TDE is achieved, but also the unstable power consumption behavior including abnormal peaks, periodic oscillations and trend deviations can be accurately identified based on the model output results; on this basis, targeted feedback adjustment of the gate drive parameters of the target MOS tube is carried out, combined with the synchronous update of the drive control logic strategy, so that the system The system has the ability to quickly respond to abnormal power consumption behavior and adaptively control it. Finally, a dynamic correction mechanism based on the periodic dynamic loss integral evaluation value TDE is formed. By comparing the periodic dynamic loss integral evaluation value TDE before and after adjustment, the optimization effect of the drive control strategy can be verified, and the parameter adjustment process can be repeatedly triggered, thus constructing a power control path with closed-loop operation. It realizes the precise loss perception, targeted strategy adjustment, and closed-loop drive control of MOS tubes in high-frequency working scenarios, effectively overcoming the multiple deficiencies of existing power control technologies in time accuracy, energy identification, and response path, and improving the operating efficiency, response accuracy, and overall stability of high-frequency power control systems.

[0063] Example 2

[0064] Specifically: S1 includes S11 and S12;

[0065] S11. After the MOS transistor enters the switching working state, a high-bandwidth data acquisition module is used to synchronously sample the drain voltage signal and the drain current signal of the target MOS transistor. During the sampling process, a unified clock is triggered to achieve time-synchronous acquisition of the voltage and current values ​​within the same cycle, thereby forming a voltage sampling sequence and a current sampling sequence.

[0066] S12. Based on the obtained voltage sampling sequence and current sampling sequence, the voltage value and current value in each time segment are paired and calculated point by point according to the preset time segment division method to construct the instantaneous power data of the corresponding time segment; the instantaneous power results of multiple time segments are arranged in chronological order to form the instantaneous switching power data set IPD corresponding to the current switching cycle.

[0067] Said S2 includes S21 and S22;

[0068] S21, receiving the instantaneous switching power data set IPD output in step S1, performing segment-by-segment cumulative calculation on the power data corresponding to all time segments within the current switching cycle, obtaining the total dynamic energy loss value within a single switching cycle of the current MOS tube, and defining the total dynamic energy loss value as the cycle dynamic loss integral evaluation value TDE;

[0069] S22. Bind the cycle dynamic loss integral evaluation value TDE to the cycle number corresponding to the current switching cycle, and record the two in one-to-one correspondence to form a time series data sequence of the cycle dynamic loss integral evaluation value TDE containing continuous cycles, providing a historical loss record basis for subsequent power fluctuation trend analysis.

[0070] In this embodiment, a unified clock trigger mechanism is used to synchronously sample the drain voltage and drain current signals of the target MOS transistor, forming a voltage sampling sequence and a current sampling sequence, ensuring precise temporal alignment of the sampled data. Based on this sampling sequence, a pairing calculation is performed at a preset time segment granularity to generate a complete and sequential instantaneous switching power dataset (IPD), achieving high-resolution expression of the MOS transistor's single-cycle power fluctuations. Subsequently, the instantaneous switching power dataset (IPD) is accumulated segment by segment to obtain the total dynamic energy loss value covering the entire switching cycle, which is defined as the cycle dynamic loss integral evaluation value (TDE). The cycle dynamic loss integral evaluation value (TDE) is then bound to its corresponding cycle number to form a TDE time series data sequence, enabling the system to record loss history and track trends.

[0071] Based on the above mechanism, this system realizes a full-dimensional acquisition and analysis path for voltage-current synchronization, segment-level power construction, and cycle-level energy calibration under millisecond-level cycles in the high-frequency operation scenario of MOS tubes. This provides a data foundation with strong temporal consistency, clear calculation structure, and high historical traceability for subsequent energy consumption modeling and control strategy adjustment, breaking through the long-standing underlying data bottleneck problems in existing power control systems, such as "unclear transient data coupling", "discontinuous cycle statistics", and "fuzzy data structure granularity".

[0072] Example 3

[0073] Specifically: S3 includes S31 and S32;

[0074] S31. Based on the time series data sequence formed by the periodic dynamic loss integral evaluation value TDE, and through the historical evolution relationship of the data sequence under continuous switching cycles, a power fluctuation analysis model PFA for characterizing the power consumption trend change characteristics is constructed. The power fluctuation analysis model PFA is used to fit the overall trend line, average value trajectory and fluctuation distribution state of the periodic dynamic loss integral evaluation value TDE;

[0075] The power fluctuation analysis model PFA is established through steps S311, S312 and S313;

[0076] S311, performing a weighted sliding average smoothing process on the continuous periodic dynamic loss integral evaluation values ​​TDE within a specified sliding time window to obtain a periodic dynamic loss mean trajectory line;

[0077] S312, using a regression curve to fit the periodic dynamic loss integral evaluation value TDE point value from the current period to several previous periods, to generate a periodic dynamic loss trend line for indicating the overall evolution direction of power consumption;

[0078] S313. Normalize the standard deviation of the deviation between the periodic dynamic loss integral evaluation value TDE and the mean trajectory line of each period, and count the fluctuation range and frequency to form a power fluctuation distribution state map, which is then combined with the periodic dynamic loss mean trajectory line and the periodic dynamic loss trend line to form the three structural elements of the power fluctuation analysis model PFA.

[0079] S32: Based on the established power fluctuation analysis model PFA, compare and analyze the periodic dynamic loss integral evaluation value TDE corresponding to the current switching cycle with the three structural elements of the power fluctuation analysis model PFA, specifically including the following three judgment conditions:

[0080] Condition 1: Compare the periodic dynamic loss integral evaluation value TDE of the current period with the periodic dynamic loss mean trajectory line. If the deviation exceeds the set threshold range, it is identified as a peak abnormal fluctuation.

[0081] Condition 2: Compare the current cycle's cycle dynamic loss integral evaluation value TDE with the slope and trend direction of the cycle dynamic loss trend line. If consecutive cycles show an upward deviation trend, it is identified as a continuous increase in power consumption.

[0082] Condition 3: Check the historical fluctuation frequency boundary between the current period dynamic loss integral evaluation value TDE and the power fluctuation distribution state map. If alternating up and down oscillations are present, it is identified as periodic oscillation drift.

[0083] When the periodic dynamic loss integral evaluation value TDE meets the abnormal characteristic standard in any one of the three judgment conditions, it is marked as a power consumption abnormality cycle, and a judgment signal for adjusting the drive control strategy is output.

[0084] In this embodiment, based on the change trajectory of the periodic dynamic loss integral evaluation value TDE in the historical period, a power fluctuation analysis model PFA is constructed, which completes the extraction of the periodic dynamic loss mean trajectory line, the construction of the periodic dynamic loss trend line, and the induction of the power fluctuation distribution state spectrum. The three together constitute the complete structural elements of the power fluctuation analysis model PFA. Furthermore, the periodic dynamic loss integral evaluation value TDE of the current switching cycle is used as the judgment object, and is compared with the periodic dynamic loss mean trajectory line, the periodic dynamic loss trend line and the power fluctuation distribution state map respectively, to judge whether there are peak abnormal fluctuations, continuous upward power consumption behavior and periodic oscillation drift; once any judgment condition is met, the current cycle can be marked as a power consumption abnormality cycle, and the corresponding drive control strategy adjustment judgment signal is output. Based on the above mechanism, not only is the joint modeling and intelligent judgment of the periodic dynamic loss integral evaluation value TDE in multiple dimensions such as evolution trend, center offset and statistical distribution realized, but also through the combined reference of the model structure elements, an identification and judgment path is constructed that can dynamically identify power consumption risks and qualitatively distinguish fluctuation types. It has the characteristics of strong trend analysis capability, high abnormal response granularity and clear behavior recognition logic, breaking through the technical limitations of existing power consumption monitoring technology that only relies on static thresholds or fixed intervals for judgment and is difficult to cope with the dynamic evolution process of power consumption.

[0085] Example 4

[0086] Specifically: S4 includes S41 and S42;

[0087] S41. Based on the marking result of the abnormal power consumption cycle, identifying whether the current cycle belongs to the abnormal power consumption cycle; if it is determined to be the abnormal power consumption cycle, generating a drive control strategy adjustment trigger signal, wherein the drive control strategy adjustment trigger signal is used to activate the feedback adjustment channel in the gate control system and start the corresponding gate drive parameter correction process;

[0088] The gate drive parameter correction process includes steps S411, S412 and S413;

[0089] S411, identifying the gate drive parameter configuration set used in the current cycle;

[0090] S412: Calling a preset driving parameter adjustment strategy template, and determining target parameters to be adjusted for driving dimensions corresponding to the abnormal power consumption characteristics, including a driving voltage setting value, a turn-on delay time setting value, and a turn-off dead time setting value;

[0091] S413: Generate adjusted gate drive parameter setting values ​​as valid input for the next cycle execution.

[0092] S42: Execute feedback adjustment of the target MOS transistor gate drive parameter and synchronous update of the drive control logic. After adjusting the trigger signal based on the drive control strategy and generating the target parameter setting value, call the gate drive parameter setting value corresponding to the cycle and apply it to the gate drive module of the target MOS transistor in the current control cycle.

[0093] The gate drive parameters include: a drive voltage setting value, which is used to adjust the gate signal amplitude to match the dynamic power consumption state; a turn-on delay time setting value, which is used to correct the turn-on edge trigger timing to avoid cross conduction; and a turn-off dead time setting value, which is used to adjust the turn-off process time window to achieve soft switching or suppress overshoot.

[0094] At the same time, based on the application results of the gate drive parameter setting values, the gate drive parameter control configuration table is updated synchronously, and the associated gate signal output scheduling rules and cycle parameter execution paths are adjusted synchronously to ensure that the subsequent cycle control process is consistent with the adjusted feedback strategy in terms of driving behavior, realizing the closed-loop response of the drive parameters and the dynamic adaptation of the control logic;

[0095] The gate drive parameter control configuration table is a structured data set used to manage and record the drive setting values ​​of the MOS tube in each control cycle. The configuration table contains multiple drive parameter fields, including: a drive voltage setting field, a turn-on delay time field, and a turn-off dead time field;

[0096] The gate signal output scheduling rules are used to define how to sequence the output of the gate drive signal generation logic of the MOS tube according to the set values ​​in the "gate drive parameter control configuration table" in a specific cycle, including the drive signal start time scheduling, drive signal duration setting, multi-level drive control waveform (such as soft drive / strong drive) scheduling call logic and interlock delay configuration with adjacent switching devices;

[0097] After entering a new cycle, the cycle parameter execution path system forms a full process path chain from cycle status judgment → reading the configuration table → scheduling the drive signal → feedback update record, which is used to ensure that the drive parameter setting value is not only recorded, but also can be referenced, transferred and executed in the actual control execution process, forming a cycle-level closed loop.

[0098] The path includes the following core nodes: periodic state initialization node, parameter reading and loading node, signal scheduling execution node and feedback correction input interface.

[0099] Said S5 includes S51 and S52;

[0100] S51. After the gate drive parameter feedback adjustment is completed and the actual application is completed, the drain voltage signal and the drain current signal of the target MOS tube are re-collected in the next switching cycle, the voltage sampling sequence and the current sampling sequence in the cycle are obtained, and a new instantaneous switching power data set IPD_New is constructed.

[0101] S52: Input the new instantaneous switch power data set IPD_New into the cycle energy evaluation process, recalculate the new cycle dynamic loss integral evaluation value TDE_New corresponding to the current cycle, and compare and analyze the new cycle dynamic loss integral evaluation value TDE_New with the cycle dynamic loss integral evaluation value TDE of the cycle before adjustment. The effectiveness of the drive adjustment strategy is judged based on the comparative analysis results, specifically including:

[0102] When the new period dynamic loss integral evaluation value TDE_New is less than the period dynamic loss integral evaluation value TDE, it is determined that the driving adjustment effect has reached the expected result;

[0103] When the new cycle dynamic loss integral evaluation value TDE_New ≥ the cycle dynamic loss integral evaluation value TDE, it is determined that the drive adjustment effect does not meet expectations, and the gate drive parameter correction process is called again.

[0104] In this embodiment, by initiating the drive control strategy adjustment trigger signal generation and gate drive parameter correction process, the system can quickly respond and enter the three sub-processes of gate drive parameter configuration set identification, drive parameter adjustment strategy template call and target parameter generation based on the identification result of the power consumption abnormality cycle, forming a new configuration result of core drive parameters such as the drive voltage setting value, turn-on delay time setting value and turn-off dead time setting value; then the above-mentioned gate drive parameter setting values ​​are executed and applied in the actual control cycle, and the gate drive parameter control configuration table, gate signal output scheduling rules and cycle parameter execution path are synchronously updated to ensure that the drive parameters are not only set, but also can be dynamically distributed and adapted according to the cycle logic execution node, forming a closed-loop control chain integrating "setting-management-call-feedback". Furthermore, by re-collecting the drain voltage signal and drain current signal after the drive parameter adjustment, a new instantaneous switching power data set IPD_New is constructed, and the new cycle dynamic loss integral evaluation value TDE_New is calculated. It is compared and analyzed with the cycle dynamic loss integral evaluation value TDE before the adjustment. If the drive adjustment does not achieve the expected effect, the gate drive parameter correction process can be automatically re-called to form a closed-loop reuse mechanism. This realizes an efficient control closed-loop path with the cycle dynamic loss integral evaluation value TDE as the performance feedback core, the gate drive parameter setting value as the execution entry, and the gate drive parameter control configuration table and the cycle parameter execution path as the strategy carrying structure. This enables the MOS tube to have the control advantages of drive behavior adaptation, parameter dynamic deduction, and execution process structured in complex, high-frequency, and changeable working environments, overcoming the structural limitations of existing power control systems such as "static drive response, fragmented parameter adjustment, and non-closed-loop strategy execution", and improving the system's adjustment response rate, drive behavior consistency, and fault self-repair capability in actual operation.

[0105] Example 5

[0106] A high-frequency power control method based on MOS tube, please refer to Figure 2 Specifically, it includes MOS tube data acquisition module, dynamic loss assessment module, loss trend identification module, gate drive module and drive adjustment decision module;

[0107] The MOS transistor data acquisition module synchronously samples the drain voltage and drain current of the target MOS transistor in each switching cycle, and establishes an instantaneous switching power data set IPD in the switching cycle according to time segments;

[0108] The dynamic loss evaluation module integrates the power data in the current switching cycle based on the instantaneous switching power data set IPD, evaluates and obtains the cycle dynamic loss integral evaluation value TDE in the current cycle, and binds it with the cycle number to form a time series data sequence;

[0109] The loss trend identification module uses the time series data sequence composed of the periodic dynamic loss integral evaluation value TDE to establish a power fluctuation analysis model PFA, analyze the fluctuation trend of the periodic dynamic loss integral evaluation value TDE, identify abnormal peaks, oscillation drift and trend deviation behavior characteristics, and mark abnormal power consumption periods;

[0110] The gate drive module adjusts the gate drive parameters of the target MOS tube, including the drive voltage, turn-on delay time and turn-off dead time parameters, based on the abnormal cycle marking results output by the power fluctuation analysis model PFA, and simultaneously adjusts the drive control logic strategy;

[0111] The drive adjustment decision module applies the adjusted drive control logic strategy to the subsequent cycle, re-executes steps S1 and S2, obtains the new cycle dynamic loss integral evaluation value TDE_New, compares it with the dynamic loss integral evaluation value TDE data of the previous cycle, and determines the effectiveness of the current drive adjustment strategy.

[0112] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A high-frequency power control method based on MOS tube, characterized by: The following steps are involved: S1. Synchronously sample the drain voltage and drain current of the target MOS tube in each switching cycle, and establish an instantaneous switching power data set IPD within the switching cycle according to time segments. S2. Based on the instantaneous switching power data set IPD, integrate the power data in the current switching cycle to obtain the cycle dynamic loss integral evaluation value TDE in the current cycle, and bind it with the cycle number to form a time series data sequence; S3. Using the time series data sequence composed of the periodic dynamic loss integral evaluation value TDE, a power fluctuation analysis model PFA is established to analyze the fluctuation trend of the periodic dynamic loss integral evaluation value TDE, identify abnormal peaks, oscillation drift and trend deviation behavior characteristics, and mark abnormal power consumption periods; S4. Based on the abnormal cycle marking results output by the power fluctuation analysis model PFA, feedback is provided to adjust the gate drive parameters of the target MOS tube, including the drive voltage, turn-on delay time, and turn-off dead time parameters, and the drive control logic strategy is adjusted synchronously; S5. Apply the adjusted drive control logic strategy to subsequent cycles, re-execute steps S1 and S2, obtain the new cycle dynamic loss integral evaluation value TDE_New, compare it with the dynamic loss integral evaluation value TDE data of the previous cycle, and judge the effectiveness of the current drive adjustment strategy.

2. The high-frequency power control method based on MOS tube according to claim 1, characterized in that: Said S1 includes S11 and S12; S11. After the MOS transistor enters the switching working state, a high-bandwidth data acquisition module is used to synchronously sample the drain voltage signal and the drain current signal of the target MOS transistor. During the sampling process, a unified clock is triggered to achieve time-synchronous acquisition of the voltage and current values ​​within the same cycle, thereby forming a voltage sampling sequence and a current sampling sequence. S12. Based on the obtained voltage sampling sequence and current sampling sequence, the voltage value and current value in each time segment are paired and calculated point by point according to the preset time segment division method to construct the instantaneous power data of the corresponding time segment; the instantaneous power results of multiple time segments are arranged in chronological order to form the instantaneous switching power data set IPD corresponding to the current switching cycle.

3. The high-frequency power control method based on MOS tube according to claim 2, characterized in that: Said S2 includes S21 and S22; S21, receiving the instantaneous switching power data set IPD output in step S1, performing segment-by-segment cumulative calculation on the power data corresponding to all time segments within the current switching cycle, obtaining the total dynamic energy loss value within a single switching cycle of the current MOS tube, and defining the total dynamic energy loss value as the cycle dynamic loss integral evaluation value TDE; S22. Bind the cycle dynamic loss integral evaluation value TDE to the cycle number corresponding to the current switching cycle, and record the two in one-to-one correspondence to form a time series data sequence of the cycle dynamic loss integral evaluation value TDE containing continuous cycles, providing a historical loss record basis for subsequent power fluctuation trend analysis.

4. The high-frequency power control method based on MOS tube according to claim 3, characterized in that: Said S3 includes S31 and S32; S31. Based on the time series data sequence formed by the periodic dynamic loss integral evaluation value TDE, and through the historical evolution relationship of the data sequence under continuous switching cycles, a power fluctuation analysis model PFA for characterizing the power consumption trend change characteristics is constructed. The power fluctuation analysis model PFA is used to fit the overall trend line, average value trajectory and fluctuation distribution state of the periodic dynamic loss integral evaluation value TDE; The power fluctuation analysis model PFA is established through steps S311, S312 and S313; S311, performing a weighted sliding average smoothing process on the continuous periodic dynamic loss integral evaluation values ​​TDE within a specified sliding time window to obtain a periodic dynamic loss mean trajectory line; S312, using a regression curve to fit the periodic dynamic loss integral evaluation value TDE point value from the current period to several previous periods, to generate a periodic dynamic loss trend line for indicating the overall evolution direction of power consumption; S313. Normalize the standard deviation of the deviation between the periodic dynamic loss integral evaluation value TDE and the mean trajectory line of each period, and count the fluctuation range and frequency to form a power fluctuation distribution state map, which is then combined with the periodic dynamic loss mean trajectory line and the periodic dynamic loss trend line to form the three structural elements of the power fluctuation analysis model PFA.

5. The high-frequency power control method based on MOS transistor according to claim 4, characterized in that: S32: Based on the established power fluctuation analysis model PFA, compare and analyze the periodic dynamic loss integral evaluation value TDE corresponding to the current switching cycle with the three structural elements of the power fluctuation analysis model PFA, specifically including the following three judgment conditions: Condition 1: Compare the periodic dynamic loss integral evaluation value TDE of the current period with the periodic dynamic loss mean trajectory line. If the deviation exceeds the set threshold range, it is identified as a peak abnormal fluctuation. Condition 2: Compare the current cycle's cycle dynamic loss integral evaluation value TDE with the slope and trend direction of the cycle dynamic loss trend line. If consecutive cycles show an upward deviation trend, it is identified as a continuous increase in power consumption. Condition 3: Check the historical fluctuation frequency boundary between the current period dynamic loss integral evaluation value TDE and the power fluctuation distribution state map. If alternating up and down oscillations are present, it is identified as periodic oscillation drift. When the periodic dynamic loss integral evaluation value TDE meets the abnormal characteristic standard in any one of the three judgment conditions, it is marked as a power consumption abnormality cycle.

6. The high-frequency power control method based on MOS transistor according to claim 5, characterized in that: Said S4 includes S41 and S42; S41, based on the marking result of the abnormal power consumption period, identifying whether the current period is an abnormal power consumption period; If it is determined to be an abnormal power consumption period, a drive control strategy adjustment trigger signal is generated, and the drive control strategy adjustment trigger signal is used to activate the feedback adjustment channel in the gate control system and start the corresponding gate drive parameter correction process; The gate drive parameter correction process includes steps S411, S412 and S413; S411, identifying the gate drive parameter configuration set used in the current cycle; S412: Calling a preset driving parameter adjustment strategy template, and determining target parameters to be adjusted for driving dimensions corresponding to the abnormal power consumption characteristics, including a driving voltage setting value, a turn-on delay time setting value, and a turn-off dead time setting value; S413: Generate adjusted gate drive parameter setting values ​​as valid input for the next cycle execution.

7. The high-frequency power control method based on MOS transistor according to claim 6, characterized in that: S42: Execute feedback adjustment of the target MOS transistor gate drive parameter and synchronous update of the drive control logic. After adjusting the trigger signal based on the drive control strategy and generating the target parameter setting value, call the gate drive parameter setting value corresponding to the cycle and apply it to the gate drive module of the target MOS transistor in the current control cycle. The gate drive parameters include: a drive voltage setting value for adjusting the gate signal amplitude to match the dynamic power consumption state; The turn-on delay time setting value is used to correct the turn-on edge trigger timing to avoid cross conduction; the turn-off dead time setting value is used to adjust the turn-off process time window to achieve soft switching or suppress overshoot; At the same time, according to the application results of the gate drive parameter setting values, the gate drive parameter control configuration table is synchronously updated, and the gate signal output scheduling rules and cycle parameter execution paths associated therewith are synchronously adjusted.

8. The high-frequency power control method based on MOS transistor according to claim 1, characterized in that: Said S5 includes S51 and S52; S51. After the gate drive parameter feedback adjustment is completed and the actual application is completed, the drain voltage signal and the drain current signal of the target MOS tube are re-collected in the next switching cycle, the voltage sampling sequence and the current sampling sequence in the cycle are obtained, and a new instantaneous switching power data set IPD_New is constructed.

9. The high-frequency power control method based on MOS transistor according to claim 8, characterized in that: S52: Input the new instantaneous switch power data set IPD_New into the cycle energy evaluation process, recalculate the new cycle dynamic loss integral evaluation value TDE_New corresponding to the current cycle, and compare and analyze the new cycle dynamic loss integral evaluation value TDE_New with the cycle dynamic loss integral evaluation value TDE of the cycle before adjustment. The effectiveness of the drive adjustment strategy is judged based on the comparative analysis results, specifically including: When the new period dynamic loss integral evaluation value TDE_New is less than the period dynamic loss integral evaluation value TDE, it is determined that the driving adjustment effect has reached the expected result; When the new cycle dynamic loss integral evaluation value TDE_New ≥ the cycle dynamic loss integral evaluation value TDE, it is determined that the drive adjustment effect does not meet expectations, and the gate drive parameter correction process is called again.

10. A high-frequency power control system based on a MOS transistor, applied to a high-frequency power control method based on a MOS transistor according to any one of claims 1 to 9, characterized in that: It includes MOS tube data acquisition module, dynamic loss evaluation module, loss trend identification module, gate drive module and drive adjustment decision module; The MOS transistor data acquisition module synchronously samples the drain voltage and drain current of the target MOS transistor in each switching cycle, and establishes an instantaneous switching power data set IPD in the switching cycle according to time segments; The dynamic loss evaluation module integrates the power data in the current switching cycle based on the instantaneous switching power data set IPD, evaluates and obtains the cycle dynamic loss integral evaluation value TDE in the current cycle, and binds it with the cycle number to form a time series data sequence; The loss trend identification module uses the time series data sequence composed of the periodic dynamic loss integral evaluation value TDE to establish a power fluctuation analysis model PFA, analyze the fluctuation trend of the periodic dynamic loss integral evaluation value TDE, identify abnormal peaks, oscillation drift and trend deviation behavior characteristics, and mark abnormal power consumption periods; The gate drive module adjusts the gate drive parameters of the target MOS tube, including the drive voltage, turn-on delay time and turn-off dead time parameters, based on the abnormal cycle marking results output by the power fluctuation analysis model PFA, and simultaneously adjusts the drive control logic strategy; The drive adjustment decision module applies the adjusted drive control logic strategy to the subsequent cycle, re-executes steps S1 and S2, obtains the new cycle dynamic loss integral evaluation value TDE_New, compares it with the dynamic loss integral evaluation value TDE data of the previous cycle, and determines the effectiveness of the current drive adjustment strategy.

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