Contact structure and manufacturing method thereof

Abstract

A contact structure according to the present disclosure includes a device layer over a substrate, a dielectric structure over the device layer, a first etch stop layer (ESL) over the dielectric structure, a through-via extending through the dielectric structure and the device layer and including a top of a through-via over the first ESL, a semiconductor device includes a first ESL disposed over a through hole, a guard ring structure disposed over the first ESL and around a top of the through hole, a protective layer disposed over the guard ring structure, a second ESL disposed conformally over a top surface of the first ESL, sidewalls of the guard ring structure, sidewalls of the protective layer, and a top surface of the protective layer, and a dielectric layer of the second ESL. The embodiment of the invention further discloses a method for manufacturing the contact structure.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and more particularly, to a contact structure and a manufacturing method thereof. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each smaller and more complex than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This downsizing process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] Through-substrate vias (TSVs) are commonly used in 3DICs because they route electrical signals from one side of the IC's silicon substrate to the other. The formation of TSVs can cause stress on surrounding structures, leading to delamination and failure. Protection structures have been developed to reduce, absorb, or isolate the stress generated by TSVs. Summary of the Invention

[0004] According to one aspect of an embodiment of the present application, a method for manufacturing a contact structure is provided, comprising: receiving a work-in-process (WIP) structure. The work-in-process structure comprises: a substrate, a device layer located above the substrate, and a plurality of interconnect layers located above the device layer and including a via formation region. The method further comprises: depositing a first etch stop layer (ESL) above the plurality of interconnect layers; depositing a first dielectric layer above the first ESL; depositing a second ESL above the first dielectric layer; depositing a second dielectric layer above the second ESL; forming a via opening through the second dielectric layer, the second ESL, the first dielectric layer, the first ESL, the via formation region, the device layer, and the depth of the substrate; depositing a metal fill layer above the second dielectric layer and the via opening; planarizing the metal fill layer to form a via structure and exposing the first dielectric layer; depositing a protective layer above the via structure and the exposed first dielectric layer; patterning the protective layer and the first dielectric layer to form a guard ring structure surrounding a portion of the via structure that is higher than the first ESL; and depositing a third dielectric layer above the guard ring structure and the first ESL.

[0005] According to another aspect of an embodiment of the present application, a contact structure is provided, including: a device layer located above a substrate; a dielectric structure located above the device layer; a first etch stop layer (ESL) located above the dielectric structure; a through hole passing through the dielectric structure and the device layer, wherein the top of the through hole is higher than the first ESL; a guard ring structure located above the first ESL and surrounding the top of the through hole; a protective layer disposed above the guard ring structure; a second ESL conformally disposed above the top surface of the first ESL, the sidewalls of the guard ring structure, the sidewalls of the protective layer, and the top surface of the protective layer; and a dielectric layer of the second ESL.

[0006] According to another aspect of an embodiment of the present application, a contact structure is provided, comprising: a device layer located above a substrate; a dielectric structure located above the device layer; a first etch stop layer (ESL) on the dielectric structure; a through hole extending through the dielectric structure and the device layer, wherein a top of the through hole extends through the first ESL; a guard ring structure located above the first ESL and surrounding a top of the through hole; a protective layer disposed above the guard ring structure; a second ESL conformally disposed above a top surface of the first ESL, sidewalls of the guard ring structure, sidewalls of the protective layer, and a top surface of the protective layer; and a dielectric layer of the second ESL, wherein the top comprises a height measured from the top surface of the dielectric structure, wherein the height is about peace treaty The through-hole is a ring-shaped line in a top view and has a diameter between about 2 μm and about 12 μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a flow chart illustrating an embodiment of a method of forming a through substrate via through an integrated circuit (IC) device structure according to various aspects of the present disclosure.

[0009] Figure 2-Figure 20 According to various aspects of the present disclosure, Figure 1 A partial cross-sectional view of a work-in-progress (WIP) structure in which the method operates.

[0010] Figure 21 is a partial perspective top view of a through-hole and guard ring structure according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0011] The present disclosure relates generally to integrated circuit devices and, more particularly, to interconnect structures for integrated circuit devices.

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spacing terms such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spacing terms are intended to encompass different orientations of the device in use or during operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and spacing descriptors used herein should be interpreted accordingly.

[0014] In addition, when "about," "approximately," etc. are used to describe a number or a range of numbers, the term is intended to include numbers within a reasonable range that takes into account variations inherent during manufacturing as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing the feature associated with the number, the number or range of numbers encompasses a reasonable range that includes the described number, such as within + / - 10% of the described number. For example, a layer of material having a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, where manufacturing tolerances associated with deposited material layers are known to those of ordinary skill in the art to be + / - 15%. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for purposes of simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0015] The interconnect structure electrically couples various components (e.g., transistors, resistors, capacitors, and / or inductors) fabricated on a substrate so that the various components can operate as designed. The interconnect structure includes a combination of dielectric layers and conductive layers configured to provide electrical signal routing. The conductive layers include vias and contact features that provide vertical connections and conductors that provide horizontal connections. In some embodiments, the interconnect structure may have five (5) to twenty (20) metal layers (or metallization layers) vertically interconnected by vias or contact features. During operation of the IC device, the interconnect structure routes signals between components of the IC device and / or distributes signals (e.g., clock signals, voltage signals, and / or ground signals) to the components. The interconnect structure is formed in a back-end-of-line (BEOL) process, typically after a front-end-of-line (FEOL) process forms active devices (such as transistors) on a substrate and a middle-of-line (MEOL) process forms source / drain contacts and gate contacts.

[0016] In some embodiments, it is desirable to provide a vertical interconnect extending through an interconnect structure and / or substrate to facilitate various device structures, such as CMOS image sensors (CIS), three-dimensional integrated circuits (3DIC), integrated chip systems (SoIC), systems on chips (SoC), chiplets, neuromorphic computing circuit designs, artificial intelligence (AI) systems, MEMS (microelectromechanical systems) devices, radio frequency (RF) devices, wafer-on-wafer (WoW) devices, and the like. Such a vertical interconnect may be referred to as a through silicon via or through substrate via (TSV) because it extends in whole or in part through the semiconductor substrate. The term TSV in this disclosure broadly includes through-hole structures that provide direct signal routing from the front side of the substrate to the back side of the substrate, and vice versa. During the manufacture and operation of structures including TSVs, the TSVs are subject to mechanical stresses caused by temperature changes. If the mechanical stress is not absorbed or distributed, it may affect the electrical characteristics of the TSV and the life of the semiconductor device.

[0017] The present disclosure provides a method for forming a guard ring structure surrounding a portion of a TSV. The guard ring structure includes one or more films having different thermal expansion coefficients, and the one or more films can absorb and distribute the stress applied to the TSV. By controlling the thickness and composition of each film in the guard ring structure, the guard ring structure can be customized according to the specific TSV design and application. The guard ring structure of the present disclosure shows promising results in reducing the mechanical stress on the TSV and improving its electrical characteristics, which can lead to more efficient and durable semiconductor devices.

[0018] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 FIG. 1 is a diagram illustrating a process for producing a work in process (WIP) structure 200 (eg, Figure 2-21100 and a flow chart of a method 100 for forming a device structure with a through-hole structure passing through the device structure. The method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved for other embodiments of the method. For simplicity, not all steps are described in detail herein. Figure 2-21 Describing method 100, Figure 2-21 is a partial cross-sectional view of a WIP structure 200 at different manufacturing stages according to various embodiments of the method 100. Because the WIP structure 200 will be manufactured into a device structure, the WIP structure 200 may be referred to herein as a device structure 200 depending on the context. For the avoidance of doubt, Figure 2-21 The X, Y and Z directions are perpendicular to each other. In this disclosure, unless otherwise explicitly stated, the same reference numerals denote the same features.

[0019] The present disclosure Figure 2-21 The device structure 200 shown in FIG. 2 is simplified, and not all features of the device structure 200 are shown or described in detail. Figure 2-21 The device structure 200 shown in the figure can be part of an IC chip, a system on a chip (SoC), or a portion thereof, which can include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof.

[0020] refer to Figure 1 and Figure 2-Figure 4 , the method 100 includes block 102, where a first etch stop layer (ESL) 204, a first dielectric layer 206, a second ESL 208, and a second dielectric layer 210 are deposited on a substrate 201. Figure 2Substrate 201 is part of WIP structure 200, which also includes a device layer 202 above substrate 201 and a lower interconnect structure 203 above device layer 202. In one embodiment, substrate 201 comprises silicon (Si). Alternatively or additionally, substrate 201 may comprise: another elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Alternatively, substrate 201 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate may be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements of the device structure 200, the substrate 201 may include various doped regions (not shown). In some embodiments, the substrate 201 may include a p-type doped region (e.g., a p-type well) and an n-type doped region (e.g., an n-type well). The p-type doped region may be doped with a p-type dopant, such as boron (e.g., BF2), indium, other p-type dopants, or a combination thereof. The n-type doped region may be doped with an n-type dopant, such as phosphorus (P), arsenic (As), other n-type dopants, or a combination thereof. In some embodiments, the substrate 201 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. Various doped regions may be formed directly on and / or in the substrate 201, for example, to provide a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes may be performed to form the various doped regions.

[0021] The device layer 202 includes transistors 2020 and middle of line (MEOL) contact structures. Each transistor 2020 can be a planar transistor or a multi-gate transistor, such as a fin FET (FinFET) or a gate-all-around (GAA) transistor. The FinFET includes a fin-shaped active region and a gate structure wrapped over the fin-shaped active region. The GAA transistor has a channel region formed by nanostructures of various shapes, such as nanowires, nanorods, or nanosheets. The GAA transistor includes a gate structure surrounding each of a plurality of nanostructures extending between two epitaxial source / drain components. The plurality of nanostructures can be formed by a substrate 201, which can be a silicon (Si) substrate, or by an epitaxial layer formed on the substrate 201. In the latter case, the epitaxial layer can include germanium (Ge) or silicon germanium (SiGe). Although the transistor 2020 is Figure 3 and follow-up Figures 4 to 21Although shown as a GAA transistor, it should be understood that transistor 2020 can also be a planar device or a FinFET.

[0022] Although not explicitly shown, the gate structure of transistor 2020 includes an interface layer connected to the nanostructure, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. The interface layer may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0023] The gate electrode layer of the gate structure may include a single layer or a multilayer structure, such as a metal layer having a selected work function to improve device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials, or combinations thereof.

[0024] The epitaxial source / drain components of transistor 2020 can be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. When the epitaxial source / drain components are n-type, they can include silicon (Si) doped with an n-type dopant, such as phosphorus (P) or arsenic (As). When the epitaxial source / drain components are p-type, they can include silicon germanium (SiGe) doped with a p-type dopant, such as boron (B) or boron difluoride (BF2). In some alternative embodiments not explicitly shown, the epitaxial source / drain components can include multiple layers. In one example, the epitaxial source / drain components can include a lightly doped first epitaxial layer adjacent to the nanostructures, a heavily doped second epitaxial layer above the lightly doped first epitaxial layer, and a cap epitaxial layer disposed above the heavily doped second epitaxial layer. The first epitaxial layer has a lower dopant concentration or a lower germanium content (when germanium is present) than the second epitaxial layer to reduce lattice mismatch defects. The second epitaxial layer has the highest dopant concentration or the highest germanium content (when germanium is present) to reduce resistance and increase strain on the channel. The cap epitaxial layer can have a lower dopant concentration and germanium content (when germanium is present) than the second epitaxial layer to increase etch resistance.

[0025] The MEOL structure in device layer 202 may include an interlayer dielectric (ILD) layer and source / drain contacts. The source / drain contacts extend through the ILD layer to physically and electrically couple to the epitaxial source / drain components. In some embodiments, the ILD layer may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphate silicate glass (PSG), boron-doped silicate glass (BSG) and / or other suitable dielectric materials. The ILD layer may be deposited using PECVD, FCVD, spin coating or a suitable deposition technique. In some embodiments, after the ILD layer is deposited, it may be annealed to improve its integrity. The source / drain contacts may include ruthenium (Ru), cobalt (Co), nickel (Ni) or copper (Cu). In one embodiment, the source / drain contacts include cobalt (Co). The source / drain contacts may be deposited using CVD, PVD or a suitable method. Although not shown, a contact etch stop layer (CESL) may be deposited prior to depositing the ILD layer such that the CESL is disposed between the ILD layer and the epitaxial source / drain components. The CESL may comprise silicon nitride, silicon carbonitride, or silicon oxynitride and may be deposited using CVD, ALD, or a suitable method. In some embodiments not explicitly shown, the source / drain contacts may comprise a barrier layer for contacting the ILD layer. Such a barrier layer may comprise a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, cobalt nitride, or nickel nitride. In addition, to reduce contact resistance, a silicide component may be disposed between the source / drain contacts and the epitaxial source / drain components. The silicide component may comprise titanium silicide.

[0026] like Figure 2 As shown, device layer 202 includes a via formation region 2022 that does not include transistor 2020 and an MEOL structure. That is, since via formation region 2022 in device layer 202 is formed along transistor 2020 and the MEOL structure, via formation region 2032 includes an interlayer dielectric (ILD) layer and at least one etch stop layer (ESL). Because via formation region 2030 does not include transistor 2020 and a metal gate structure, forming a via opening through via formation region 2022 does not involve etching through metal features and does not generate undesirable metal debris.

[0027] The lower interconnect structure 203 may be a lower portion of an interconnect structure that includes more metallization layers. In some embodiments, the lower interconnect structure 203 may include the first three (3) to the first six (6) metallization layers closest to the device layer 202. The number of levels in the lower interconnect structure 203 defines the penetration of the resulting through-hole through the interconnect structure. After the through-hole is formed, additional levels of metallization layers will be formed above the lower interconnect structure 203. These additional levels of metallization layers may be collectively referred to as the upper interconnect structure. In some embodiments, the number of metallization layers in the lower interconnect structure 203 is selected so that the metallization layer immediately above the lower interconnect structure is much larger and thicker than the topmost metallization layer in the lower interconnect structure 203. This ensures that the through-hole lands on a metallization layer that is more mechanically strong.

[0028] Each metallization layer in the lower interconnect structure 203 includes an etch stop layer (ESL), an intermetallic dielectric (IMD) layer disposed on the ESL, and a plurality of vertically extending vias and horizontal metal lines disposed in the IMD layer and the ESL. It can be said that the ESL is interleaved with the IMD layer, or the IMD layer is interleaved with the ESL. The ESL can share the same composition and can include silicon nitride or silicon oxynitride. The IMD layer can share the same composition and can include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphate silicate glass (PSG), boro-doped silicate glass (BSG), low-k dielectric material, other suitable dielectric materials, or combinations thereof. Example low-k dielectric materials include carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, benzocyclobutene (BCB), or polyimide. The vias and metal lines in the lower interconnect structure 203 may include titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al) and / or other suitable materials. In one embodiment, the vias and metal lines may include copper (Cu). In some embodiments, to prevent electromigration from the metal material or oxygen from the dielectric component from diffusing into the metal material, the vias and metal lines may each include a barrier layer to connect the ESL and IMD layers. The barrier layer may include titanium nitride (TiN), tantalum nitride (TaN) or cobalt nitride (CoN). Figure 2 As shown, the lower interconnect structure 203 includes a via-forming region 2030 that does not contain vias and metal lines. That is, since the via-forming region 2030 is formed along with the vias and metal lines, the via-forming region 2030 includes all IMD layers and ESL of the metallization layer. Because the via-forming region 2030 does not contain metal features, forming a via opening through the via-forming region 2030 does not involve etching through the metal features and does not generate undesirable metal debris.

[0029] In order to clearly illustrate the formation of the guard ring structure, Figure 2 The area of ​​the through hole forming region 2032 is magnified and shown in FIG. Figure 3 and for example the subsequent Figure 4-Figure 17 middle.

[0030] like Figure 3 and Figure 4 As shown, at block 102, a first ESL 204 is deposited on the top surface of the lower interconnect structure 203, including on the via formation region 2030. The first ESL 204 may include a dielectric material having silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), or a combination thereof. In some embodiments, the first ESL 204 may include silicon carbonitride, aluminum oxide, or aluminum nitride. The first ESL 204 may be deposited using plasma enhanced chemical vapor deposition (PECVD) or CVD. In some cases, the thickness of the first ESL 204 may be about 1000 Å. peace treaty A first dielectric layer 206 is deposited over the first ESL 204. The composition of the first dielectric layer 206 is different from the composition of the first ESL 204. In some embodiments, the first dielectric layer 206 may include silicon oxide and may be deposited using CVD, spin coating, or flowable CVD (FCVD). In one embodiment, the first dielectric layer 206 is deposited using CVD to ensure its structural integrity. The thickness of the first dielectric layer 206 may vary greatly depending on the design of the guard ring structure and the thickness of the metallization layer that accommodates the guard ring structure. In some cases, the thickness of the first dielectric layer 206 may be about peace treaty between.

[0031] At block 102, as Figure 4As shown, a second ESL 208 is deposited over first dielectric layer 206. Second ESL 208 serves as a chemical mechanical polishing (CMP) stop layer. During the subsequent CMP planarization step, second ESL 208 slows the polishing rate to provide a signal to the CMP tool to stop the CMP process. In some embodiments, second ESL 208 may include a dielectric material comprising silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), or a combination thereof. In some embodiments, second ESL 208 may include silicon carbonitride, silicon nitride, silicon carbide, or silicon carbon oxynitride. Second ESL 208 may be deposited using PECVD or CVD. At block 102, a second dielectric layer 210 is deposited over second ESL 208. Second dielectric layer 210 serves as a sacrificial layer to provide a depth of material to be polished away during the subsequent CMP planarization step. To provide a uniform planarization rate, second dielectric layer 210 is formed using PECVD or CVD rather than spin coating or FCVD. In some embodiments, the second dielectric layer 210 may include silicon oxide. The second dielectric layer 210 is thicker than the first dielectric layer 206. In some embodiments, the thickness of the second dielectric layer 210 may be between 200 nm and 500 nm.

[0032] refer to Figure 1 and Figure 5, method 100 includes block 104, in which a via opening 211 is formed through second dielectric layer 210, second ESL 208, first dielectric layer 206, and first ESL 204. To form via opening 211, a mask layer is formed over second dielectric layer 210. The mask layer may include photoresist, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or titanium nitride. In one embodiment, the mask layer may be a photoresist layer having a thickness between approximately 5 μm and approximately 15 μm. The photoresist layer has a composition different from that of the ESL, ILD, and IMD layers, and its composition allows for selective etching of the ESL, ILD, IMD, and substrate 201. In this embodiment, the mask layer may be deposited using spin coating or FCVD. The deposited mask layer then undergoes a pre-exposure bake process, exposure to radiation reflected from or transmitted through the photomask, a post-exposure bake process, and a development process to form a patterned mask layer. A patterned mask layer is then applied as an etching mask to etch the ESL, ILD layer, IMD layer, and substrate 201. The etching process here can be a dry etching process (e.g., a reactive ion etching (RIE) process). In some cases, the exemplary dry etching process can be implemented with an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), a chlorine-containing gas (e.g., Cl2 and / or BCl3), a bromine-containing gas (e.g., HBr), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. The etching at block 104 is terminated when the depth of the via opening 211 into the substrate 201 is between 2 μm and approximately 150 μm (e.g., between 10 μm and approximately 60 μm). In some embodiments, the via opening 211 is substantially circular in a top view (i.e., viewed along the Z direction) and has a diameter D between approximately 2 μm and approximately 12 μm. The diameter D defines the shape and size of the through-hole formed in the via opening 211.

[0033] refer to Figure 1 and Figure 6Method 100 includes block 106, in which a metal fill layer 212 is formed over the via opening 211. At block 106, a barrier layer 213 and the metal fill layer 212 are deposited over the via opening 211. In some embodiments, the barrier layer 213 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), or a combination thereof, and the metal fill layer 212 may include copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), ruthenium (Ru), or a combination thereof. In one embodiment, the barrier layer 213 includes titanium nitride (TiN), and the metal fill layer 212 includes copper (Cu). At block 106, the barrier layer 213 is first deposited over the via opening 211 using PVD, CVD, MOCVD, ALD, or a combination thereof. The metal fill layer 212 is then deposited using electroplating, PVD, CVD, electroless plating, or a suitable method. In one embodiment, the metal fill layer 212 is deposited using electroplating. In this embodiment, a seed layer may be deposited over the barrier layer 213 using PVD or a suitable process. Then, a metal fill layer 212 may be deposited over the seed layer using electroplating. In embodiments using electroplating, the seed layer may include copper (Cu), titanium (Ti), or a combination thereof, and the metal fill may include copper. Figure 6 As shown, at block 106, a barrier layer 213 is deposited over the via opening 211, contacting the sidewalls ( Figure 6 Not shown, but Figures 18-21 ), sidewalls of the device layer 202, sidewalls of the via-hole formation region 2030 of the lower interconnect structure 203, sidewalls of the first ESL 204 and the first dielectric layer 206, and sidewalls of the second ESL 208 and the second dielectric layer 210. The barrier layer 213 separates the metal filling layer 212 from the substrate 201, the sidewalls of the device layer 202, the sidewalls of the via-hole formation region 2030 of the lower interconnect structure 203, the sidewalls of the first ESL 204 and the first dielectric layer 206, and the sidewalls of the second ESL 208 and the second dielectric layer 210.

[0034] refer to Figure 1 and Figure 7-Figure 9 , the method 100 includes block 108, in which the metal fill layer 212 and the second dielectric layer 210 are planarized to form the through hole 2120. After the barrier layer 213 and the metal fill layer 212 are deposited over the second dielectric layer 210 and into the through hole opening 211, a planarization process, such as a CMP process, may be performed to remove excess metal fill layer 213, the second dielectric layer 210, and the second ESL 208. The additional thickness of the metal fill layer 212 helps ensure surface planarity of the WIP structure 200. Figure 7In some embodiments shown, after planarization at block 108, a through-hole 2120 is formed comprising the barrier layer 213 and the metal fill layer 212. In some embodiments, the CMP process removes the dielectric layer and the metal fill layer 212 at a uniform rate, and the top surfaces of the through-hole 2120 and the first dielectric layer 206 are substantially coplanar, as shown in FIG. Figure 7 In some alternative embodiments, the metal fill layer 212 may be removed at a faster or slower rate than the surrounding dielectric layer. Figure 8 , which shows an alternative embodiment in which the CMP process removes the metal fill layer 212 at a faster rate. Figure 8 The recessed through hole 2120R is shown. As the name implies, the recessed through hole 2120R includes a top recess or concave top surface that is lower than the first dielectric layer 206. As described below, the top recess may affect the cross-sectional profile of the guard ring structure. Then refer to Figure 9 , which shows another alternative embodiment, wherein the CMP process removes the metal fill layer 212 at a slower rate. Figure 9 A raised through-hole via 2120P is shown. As the name implies, the raised through-hole via 2120P includes a top protrusion or convex top surface that is higher than the first dielectric layer 206. As described below, the top protrusion may affect the cross-sectional profile of the guard ring structure.

[0035] refer to Figure 1 and Figure 10 , the method 100 includes block 110, where a protective layer 214 is deposited over the first dielectric layer 206 and the through-hole 2120. Figure 10 As shown, at block 110, a protective layer 214 is deposited on the through hole 2120 (or Figure 8 The recessed through hole 2120R or Figure 9 2120P) and on the top surface of the first dielectric layer 206. The protective layer 214 may include a dielectric material comprising silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), or a combination thereof. In some embodiments, the protective layer 214 may include silicon carbonitride, aluminum oxide, or aluminum nitride. The protective layer 214 may be deposited using PECVD or CVD. Because the protective layer 214 will withstand etching in a subsequent etching process, the thickness of the protective layer 214 is greater than the thickness of the first ESL 204. The ratio of the thickness of the protective layer 214 to the thickness of the first ESL 204 may be between about 1.1 and about 10. This ratio is not insignificant. When the ratio is less than 1.1, the mechanical strength of the protective layer 214 after the patterning process may not be sufficient to cover the through-hole 2120. When the ratio is greater than 10, the protective layer 214 may be too thick to interfere with the formation of metal contact features in the metallization layer above the through-hole 2120. In some cases, the thickness of protective layer 214 can be about peace treaty between.

[0036] refer to Figure 1 and Figure 11 , method 100 includes block 112, where a patterned mask 215 is formed over the protective layer 214. To form the patterned mask 215, a photoresist layer is deposited over the protective layer 214 using spin coating. The deposited photoresist layer may undergo a pre-exposure bake process, exposure to radiation reflected from or transmitted through the photomask, a post-exposure bake process, and a development process to form the patterned mask 215. Figure 11 As shown, patterned mask 215 is used as an etching mask to pattern first dielectric layer 206 and protective layer 214. The shape and size of patterned mask 215 determine the outline shape and size of guard ring structure 2140 to be formed. As described below, patterned mask 215 can have a circular, elliptical, racetrack, rectangular, square, or even triangular shape in a top view. In all embodiments, the vertical projection area of ​​patterned mask 215 completely surrounds the vertical projection area of ​​through-hole 2120.

[0037] refer to Figure 1 and Figure 12 , the method 100 includes block 114, in which the protective layer 214 and the first dielectric layer 206 are etched. A patterned mask 215 is then applied as an etch mask to etch the protective layer 214 and the first dielectric layer 206. The etching of the protective layer 214 and the first dielectric layer 206 may include a dry etching process, a wet etching process, or a combination thereof. In some cases, different etching processes or different etching chemistries may be used to etch the protective layer 214 and the first dielectric layer 206. After patterning the protective layer 214 and the first dielectric layer 206, the remaining patterned mask 215 may be removed by ashing, stripping, or selective etching. Figure 12 As shown, the through hole 2120 includes a top portion that is higher than the top surface of the lower interconnect structure 203 by a first height H1. The patterned first dielectric layer 206 surrounds the sidewalls of the top portion of the through hole 2120. The patterned protective layer 214 covers the first dielectric layer 206 and the top surface of the through hole 2120. In some embodiments, the patterned protective layer 214 and the patterned first dielectric layer 206 include tapered sidewalls that gradually narrow upward. In some cases, the first height H1 is about peace treaty between.

[0038] refer to Figure 1 and Figure 13 , the method 100 includes block 116, where a third ESL 216 is deposited over the patterned first dielectric layer 206, the patterned protective layer 214, and the first ESL 204. Figure 13As shown, at block 116, a third ESL 216 is conformally deposited on the top surfaces of the protective layer 214 and the first ESL 204 and on the sidewalls of the first dielectric layer 206 and the protective layer 214. The third ESL 216 may include a dielectric material having silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), or a combination thereof. In some embodiments, the third ESL 216 may include silicon carbonitride, aluminum oxide, or aluminum nitride. The third ESL 216 may be deposited using PECVD or CVD. In some cases, the thickness of the third ESL 216 may be about 1000 Å. peace treaty At the conclusion of the operations at block 116 , the guard ring structure 2140 is substantially formed. The guard ring structure 2140 includes the first ESL 204 , the first dielectric layer 206 , the capping layer 214 , and the third ESL 216 .

[0039] refer to Figure 1 and Figure 14-16 , method 100 includes block 118, where a third dielectric layer 218 is deposited over the third ESL 216. The third dielectric layer 218 may share the same composition as the IMD layer in the lower interconnect structure 203. In some embodiments, the third dielectric layer 218 may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boro-doped silicate glass (BSG), a low-k dielectric material, other suitable dielectric materials, or combinations thereof. Example low-k dielectric materials include carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, benzocyclobutene (BCB), or polyimide.

[0040] Figure 14 An embodiment is shown in which the planarization at box 108 removes the metal fill layer 212 and the surrounding dielectric material at substantially the same rate. As a result, the top surfaces of the through-hole 2120 in the guard ring structure 2140 and the first dielectric layer 206 are substantially coplanar. The protective layer 214 in the guard ring structure 2140 acts as a cap over the top surface of the through-hole 2120. In this embodiment, the top of the through-hole 2120 is higher than the first ESL 204 by a first height H1, which is approximately peace treaty The guard ring structure 2140 including the first ESL 204, the first dielectric layer 206, the protective layer 214 and the third ESL 216 rises above the top surface of the lower interconnect structure 203 by a second height H2, which is about peace treaty When viewed in the vertical direction (i.e., the Z direction), the through-hole 2120 is substantially circular and has a diameter D between approximately 2 μm and approximately 12 μm. Although the sidewalls of the guard ring structure 2140 may be tapered, the width of the widest portion or bottom of the guard ring structure 2140 has a width W between approximately 2.2 μm and approximately 13 μm. Measured from the sidewalls of the through-hole 2120, the guard ring structure 2140 has a sidewall thickness S, which may be between approximately 10 nm and approximately 1000 nm. The ratio of the sidewall thickness S to the diameter D may be between approximately 0.01 and approximately 0.5. This ratio is not insignificant. When the ratio is less than 0.01, the guard ring structure 2140 may not be thick enough to reduce stress applied to or by the through-hole 2120. When the ratio is greater than 0.5, the guard ring structure 2140 may occupy excessive area, with limited marginal benefits.

[0041] Figure 15 An embodiment is shown in which the planarization at frame 108 removes the metal fill layer 212 at a faster rate. As a result, in the guard ring structure 2140, the top surface of the recessed through-hole 2120R is lower than the first dielectric layer 206. The protective layer 214 in the guard ring structure 2140 above the top surface of the recessed through-hole 2120R also includes a recessed profile. In this embodiment, the top of the recessed through-hole 2120R is higher than the top surface of the lower interconnect structure 203 by a third height H3, and the third height H3 is less than the thickness of the first dielectric layer 206. The guard ring structure 2140, including the first ESL 204, the first dielectric layer 206, the protective layer 214, and the third ESL 216, rises from the top surface of the lower interconnect structure 203 to a fourth height H4, and the fourth height H4 is approximately peace treaty When viewed in the vertical direction (i.e., the Z direction), the recessed through-hole 2120R is substantially circular and has a diameter D between about 2 μm and about 12 μm. Although the sidewalls of the guard ring structure 2140 may be tapered, the width of the widest portion or bottom of the guard ring structure 214 has a width W, which is between about 2.2 μm and about 13 μm. Measured from the sidewalls of the through-hole 2120, the guard ring structure 2140 has a sidewall thickness S, which may be between about 10 nm and about 1000 nm. The ratio of the sidewall thickness S to the diameter D may be between about 0.01 and about 0.5. This ratio is not insignificant. When the ratio is less than 0.01, the guard ring structure 2140 may not be thick enough to reduce the stress applied to or by the recessed through-hole 2120R. When the ratio is greater than 0.5, the guard ring structure 2140 may occupy too much area with limited marginal benefits.

[0042] Figure 16An embodiment is shown in which the planarization at frame 108 removes dielectric material around the metal fill layer 212 at a faster rate. As a result, the convex top surface of the raised through-hole via 2120P is higher than the first dielectric layer 206 in the guard ring structure 2140. The protective layer 214 in the guard ring structure 2140 above the top surface of the raised through-hole via 2120P also includes a raised profile. In this embodiment, the top of the raised through-hole via 2120P is higher than the top surface of the lower interconnect structure 203 by a fifth height H5, which is greater than the thickness of the first dielectric layer 206. The guard ring structure 2140, including the first ESL 204, the first dielectric layer 206, the protective layer 214, and the third ESL 216, rises from the first ESL 204 to a sixth height H6, which is greater than the second height H2 or the fourth height H4. When viewed in the vertical direction (i.e., the Z direction), the raised through-hole 2120P is substantially circular and has a diameter D between approximately 2 μm and approximately 12 μm. Although the sidewalls of the guard ring structure 2140 may be tapered, the width of the widest portion or bottom of the guard ring structure 2140 has a width W that is between approximately 2.2 μm and approximately 13 μm. Measured from the sidewalls of the through-hole 2120, the guard ring structure 2140 has a sidewall thickness S that may be between approximately 10 nm and approximately 1000 nm. The ratio of the sidewall thickness S to the diameter D may be between approximately 0.01 and approximately 0.5. This ratio is not insignificant. When the ratio is less than 0.01, the guard ring structure 2140 may not be thick enough to reduce the stress applied to or by the raised through-hole 2120P. When the ratio is greater than 0.5, the guard ring structure 2140 may occupy too much area with limited marginal benefits.

[0043] Brief Reference Figure 21 , which shows different top-view profiles of the guard ring structure 2140 vertically overlapping the through-hole 2120. Figure 21 The outline (A) in FIG. 1 includes an elliptical guard ring structure 2140 (as shown by the outline of the first dielectric layer 206 because it represents the maximum outline of the guard ring structure) that surrounds and overlaps the through hole 2120, which is circular and has a diameter D. The elliptical guard ring structure 2140 includes a major axis A1 and a minor axis A2. To ensure that the guard ring structure 2140 completely surrounds the through hole 2120, the minor axis A2 is larger than the diameter D by a margin between 2% and 100%. Figure 21The outline (B) in FIG. 2 includes a circular guard ring structure 2140 (shown as the outline of the first dielectric layer 206 because it represents the maximum outline of the guard ring structure) that surrounds and overlaps the through hole 2120, which is circular and has a diameter D. The circular guard ring structure 2140 includes a guard ring diameter GD. To ensure that the guard ring structure 2140 completely surrounds the through hole 2120, the guard ring diameter GD is larger than the diameter D by a margin between 2% and 100%. Figure 21 The outline (C) in FIG. 1 includes a triangular guard ring structure 2140 (shown as the outline of the first dielectric layer 206 because it represents the maximum outline of the guard ring structure) that surrounds and overlaps the through-hole 2120, which is circular and has a diameter D. To ensure that the guard ring structure 2140 completely surrounds the through-hole 2120, the shortest distance between the sides of the triangular guard ring is between approximately 10 nm and 1000 nm. Figure 21 The outline (D) in FIG. 2 includes a rectangular guard ring structure 2140 (as shown by the outline of the first dielectric layer 206 because it represents the maximum outline of the guard ring structure) that surrounds and overlaps the through hole 2120, which is circular and has a diameter D. The rectangular guard ring structure 2140 includes a first edge dimension E1 and a second edge dimension E2. To ensure that the guard ring structure 2140 completely surrounds the through hole 2120, the shorter of E1 and E2 is larger than the diameter D by a margin between 2% and 100%. When E1 and E2 are the same, the guard ring structure 2140 has a square top-view outline. Figure 21 The outline (E) in FIG. 2 includes a racetrack-shaped guard ring structure 2140 (as shown by the outline of the first dielectric layer 206 because it represents the maximum outline of the guard ring structure) that surrounds and overlaps the through-hole 2120, which is circular and has a diameter D. The racetrack-shaped guard ring structure 2140 includes a central rectangle sandwiched between two semicircles. The central rectangle has a non-zero width E3 and a height equal to twice the radius R of the two semicircles. To ensure that the guard ring structure 2140 completely surrounds the through-hole 2120, the width E3 is non-zero, and twice the radius R is greater than the diameter D by a margin between 2% and 100%.

[0044] When the stress applied by or on the through-hole 2120 is uniform in all directions, profile (B) or square profile (D) can be used because they distribute the stress substantially uniformly in all directions. When the stress applied by or on the through-hole 2120 is stronger in one direction than in the other directions, profile (A), rectangular profile (D), or profile (E) can be used so that the major axis or direction of the larger dimension aligns with the stress direction to better withstand or distribute the stress. Profile (C) is used when the design or geometry of the surrounding structure only allows for a triangular guard ring structure 2140.

[0045] refer to Figure 1 and Figures 17-20 , the method 100 includes block 120, where a conductive feature is formed to couple to a top surface of the through hole 2120. The conductive feature may have different configurations, some of which are Figures 17-20 First, refer to Figure 17 . The metallization layer and through-via 2120 in the lower interconnect structure 203 are coupled upward to the upper interconnect structure 240. The upper interconnect structure 240 may include two (2) to seventeen (17) levels of metallization layers. After depositing the third ESL 216 and the third dielectric layer 218, a first through-via 220 is formed to extend through the third dielectric layer 218, the third ESL 216 and the protective layer 214 to connect with and couple to the through-via. A metal line 222 (or metal island 222) is formed above the first through-via 220. The metal line 222 and the first through-via 220 may include a barrier layer and a metal fill layer, the barrier layer separating the metal layer from the surrounding dielectric layer. The barrier layer may include titanium nitride (TiN) and the metal fill layer may include copper (Cu). Typically, outside the through-via formation area, the height of the first through-via 220 is less than the height of the second through-via 219 because the top of the through-via 2120 is higher than the first ESL 204. After a planarization step to remove excess material, fourth ESL 224 is deposited over metal line 222. After another dielectric layer is formed over fourth ESL 224, third via 228 is formed. Third via 228 extends through fourth ESL 224 to couple to metal line 222. Because first and third vias 220 and 228 have dimensions measured in nanometers, while through-via 2120 has a diameter measured in micrometers, they are arranged in an array to connect with through-via 2120. The array of first vias 220 may include more vias than the array of third vias 228 to provide mechanical strength and reduce resistance. In some embodiments, the array of first vias 220 may include 10 to 90 vias, while the array of third vias 228 may include 2 to 50 vias.

[0046] exist Figure 18In the configuration shown, the metal line 222 is omitted, and a fourth through hole 2200 having a height greater than the first through hole 220 can be formed to connect with the through hole 2120. The fourth through hole 2200 also forms an array. Figure 17 Unlike the illustrated configuration, the number of fourth through-holes 2200 and the number of third through-holes 228 are the same because each third through-hole 228 is formed over one of the fourth through-holes 2200 .

[0047] exist Figure 19 In the illustrated configuration, after the third dielectric layer 218 is deposited, the third ESL 216 on the top surface of the protective layer 214 is removed during a planarization process. A fourth ESL 224 is deposited directly on the protective layer 214. It should be noted that the third ESL 216 still exists along the sidewalls of the first dielectric layer 206. A third via 228 extends through the fourth ESL 224 and the protective layer 214 to electrically and physically couple to the through-hole 2120. Because the bottom surface of the fourth ESL 224 directly contacts the protective layer 214, it can be said that the third dielectric layer 218 is not present between the fourth ESL 224 and the protective layer 214 along the Z-direction.

[0048] exist Figure 20 In the illustrated configuration, first via 220 is omitted, and a metal pad 2220 is formed to extend through third dielectric layer 218, third ESL 216, and protective layer 214 to connect to the top surface of through-via 2120. Metal pad 2220 may substantially overlap the vertically projected area of ​​through-via 2120. In some embodiments, metal pad 2220 may be circular in a top view and have a pad diameter PD. The ratio of pad diameter PD to diameter D of through-via 2120 may be between 0.9 and approximately 1.1. In other words, the difference between pad diameter PD and diameter D of through-via 2120 is equal to or less than 10% of diameter D. Third via 228 extends through fourth ESL 224 to couple to metal pad 2220.

[0049] In subsequent processing, the substrate 201 may be subjected to a grinding process, a CMP process, or a combination thereof until the through-via 2120 is exposed. The exposed through-via 2120 may be used to electrically couple to other structures, such as an integrated circuit (IC) die, an interposer, or a package substrate.

[0050] In one exemplary aspect, the present disclosure relates to a method for manufacturing a contact structure. The method includes: receiving a work-in-process (WIP) structure including a substrate, a device layer located above the substrate, and a plurality of interconnect layers located above the device layer and including a via formation region; depositing a first etch stop layer above the plurality of interconnect layers; depositing a first dielectric layer above the first etch stop layer; depositing a second etch stop layer above the first dielectric layer; depositing a second dielectric layer above the second etch stop layer; forming a via opening through the depth of the second dielectric layer, the second etch stop layer, the first dielectric layer, the first etch stop layer, the via formation region, the device layer, and the substrate; depositing a metal fill layer above the second dielectric layer and the via opening; planarizing the metal fill layer to form a via structure and exposing the first dielectric layer; depositing a protective layer above the via structure and the exposed first dielectric layer; patterning the protective layer and the first dielectric layer to form a guard ring structure surrounding a portion of the via structure that is higher than the first etch stop layer; and depositing a third dielectric layer above the guard ring structure and the first etch stop layer.

[0051] In some embodiments, the method further includes depositing a third etch stop layer over the guard ring structure and the first etch stop layer before depositing the third dielectric layer. In some embodiments, depositing the third etch stop layer includes conformally depositing the third etch stop layer over a top surface of the first etch stop layer, sidewalls of the first dielectric layer, sidewalls of the protective layer, and a top surface of the protective layer. In some embodiments, the first etch stop layer comprises silicon carbonitride, aluminum nitride, or aluminum oxide. In some embodiments, the first dielectric layer comprises silicon oxide. In some embodiments, the protective layer comprises silicon carbonitride, aluminum nitride, or aluminum oxide. In some embodiments, the first thickness of the first etch stop layer is less than the second thickness of the protective layer. In some embodiments, the ratio of the second thickness to the first thickness is between 1.1 and 10. In some embodiments, the thickness of the first dielectric layer is between and In some embodiments, the via formation region includes a plurality of intermetal dielectric layers and is free of conductive features.

[0052] In another exemplary aspect, the present disclosure relates to a contact structure. The contact structure includes: a device layer located above a substrate; a dielectric structure located above the device layer; a first etch stop layer located above the dielectric structure; a through hole extending through the dielectric structure and the device layer, wherein a top of the through hole is higher than the first etch stop layer; a guard ring structure located above the first etch stop layer and surrounding the top of the through hole; a protective layer disposed above the guard ring structure; a second etch stop layer conformally disposed above a top surface of the first etch stop layer, sidewalls of the guard ring structure, sidewalls of the protective layer, and a top surface of the protective layer; and a dielectric layer of the second etch stop layer.

[0053] In some embodiments, the through-hole is an annular circuit in a top-down view and includes a diameter, wherein the guard ring structure includes a thickness measured from a sidewall of the through-hole, wherein a ratio of the thickness to the diameter is between 0.01 and 0.5. In some embodiments, the guard ring structure includes a circular, rectangular, elliptical, or racetrack shape in a top-down view. In some embodiments, the first thickness of the first etch stop layer is less than the second thickness of the protective layer. In some embodiments, the ratio of the second thickness to the first thickness is between 1.1 and 10.

[0054] In another exemplary aspect, the present disclosure relates to a contact structure. The contact structure includes: a device layer located above a substrate; a dielectric structure located above the device layer; a first etch stop layer on the dielectric structure; a through hole extending through the dielectric structure and the device layer, wherein a top of the through hole extends through the first etch stop layer; a guard ring structure located above the first etch stop layer and surrounding a top of the through hole; a protective layer disposed above the guard ring structure; a second etch stop layer conformally disposed above a top surface of the first etch stop layer, sidewalls of the guard ring structure, sidewalls of the protective layer, and a top surface of the protective layer; and a dielectric layer of the second etch stop layer, wherein the top comprises a height measured from the top surface of the dielectric structure, wherein the height is and The through-hole is a ring-shaped line in a top view and has a diameter between 2 μm and 12 μm.

[0055] In some embodiments, the first etch stop layer, the protective layer, and the second etch stop layer comprise silicon carbonitride, aluminum nitride, or aluminum oxide. In some embodiments, the guard ring structure comprises silicon oxide. In some embodiments, the contact structure further comprises a metal line extending through the dielectric layer, the second etch stop layer, and the protective layer to contact the top surface of the through hole. In some embodiments, the metal line comprises a width, and the ratio of the diameter of the through hole to the width of the metal line is between 0.9 and 1.1.

[0056] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a contact structure, comprising: A work-in-process structure is received, the work-in-process structure comprising: substrate, a device layer located above the substrate, and a plurality of interconnect layers located above the device layer and including via formation regions; depositing a first etch stop layer over the plurality of interconnect layers; depositing a first dielectric layer over the first etch stop layer; depositing a second etch stop layer over the first dielectric layer; depositing a second dielectric layer over the second etch stop layer; forming a via opening to a depth through the second dielectric layer, the second etch stop layer, the first dielectric layer, the first etch stop layer, the via formation region, the device layer, and the substrate; depositing a metal fill layer over the second dielectric layer and the via opening; planarizing the metal filling layer to form a through-hole structure and expose the first dielectric layer; depositing a protective layer over the through-hole structure and the exposed first dielectric layer; patterning the protection layer and the first dielectric layer to form a protection structure surrounding a portion of the through-hole structure that is higher than the first etch stop layer; and A third dielectric layer is deposited over the protection structure and the first etch stop layer.

2. The method according to claim 1, further comprising: Before depositing the third dielectric layer, a third etch stop layer is deposited over the protection structure and the first etch stop layer. 3 . The method of claim 2 , depositing the third etch stop layer comprises conformally depositing the third etch stop layer over a top surface of the first etch stop layer, sidewalls of the first dielectric layer, sidewalls of the protection layer, and a top surface of the protection layer.

4. The method according to claim 1, wherein The via forming region includes a plurality of intermetal dielectric layers and has no conductive features.

5. A contact structure comprising: a device layer, located above the substrate; a dielectric structure located above the device layer; a first etch stop layer located above the dielectric structure; a through hole, passing through the dielectric structure and the device layer, wherein a top of the through hole is higher than the first etch stop layer; a guard ring structure located above the first etch stop layer and surrounding the top of the through hole; a protective layer, disposed above the guard ring structure; a second etch stop layer conformally disposed over a top surface of the first etch stop layer, sidewalls of the guard ring structure, sidewalls of the protection layer, and a top surface of the protection layer; and The second etch stop layer is a dielectric layer.

6. The contact structure according to claim 5, in, The through hole is circular in a top view and includes a diameter, Wherein, the guard ring structure includes a thickness measured from the sidewall of the through hole, Wherein, the ratio of the thickness to the diameter is between 0.01 and 0.

5.

7. The contact structure according to claim 5, wherein: A first thickness of the first etch stop layer is smaller than a second thickness of the protection layer.

8. A contact structure comprising: a device layer, located above the substrate; a dielectric structure located above the device layer; a first etch stop layer located above the dielectric structure; a through hole extending through the dielectric structure and the device layer, wherein a top of the through hole extends through the first etch stop layer; a guard ring structure located above the first etch stop layer and surrounding the top of the through hole; a protective layer, disposed above the guard ring structure; a second etch stop layer conformally disposed over a top surface of the first etch stop layer, sidewalls of the guard ring structure, sidewalls of the protection layer, and a top surface of the protection layer; and the dielectric layer of the second etch stop layer, wherein the top portion comprises a height measured from the top surface of the dielectric structure, Wherein, the height is and between, The through hole is circular in a top view and has a diameter between 2 μm and 12 μm.

9. The contact structure according to claim 8, further comprising: A metal line extends through the dielectric layer, the second etch stop layer and the protection layer to connect with a top surface of the through hole.

10. The contact structure according to claim 9, in, The metal line comprises a width, Wherein, a ratio of the diameter of the through hole to the width of the metal wire is between 0.9 and 1.1.

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