Method for acquiring protocol result and computing equipment

Abstract

The invention discloses a protocol result obtaining method and computing device.In the method, for any thread block, all threads in the thread block are operated, elements stored in multiple registers corresponding to the threads are stipulated, protocol results corresponding to the threads are obtained, and according to the protocol results corresponding to the threads, the elements stored in multiple registers corresponding to the threads are stipulated. Updating a protocol result in a shared memory corresponding to the thread block; the element belongs to an input tensor; running a target thread in each thread block, and updating a first protocol result in the global memory according to a protocol result in the shared memory corresponding to each thread block; running a target thread in the target thread block, and determining a first protocol result in the global memory as a protocol result corresponding to the input tensor; the target thread block belongs to a plurality of thread blocks. Through the register-shared memory-global memory protocol mode, the problem of low acquisition efficiency of the protocol result in related technologies is solved.

Description

Technical Field

[0001] The present application relates to the technical field of computing devices, and in particular to a method for obtaining protocol results and a computing device. Background Art

[0002] The reduction operation is to combine multiple numbers into one result, such as finding the maximum value, calculating the sum, etc.

[0003] In related technologies, threads within a thread block typically write the reduction results computed by that thread directly to global memory. Communication within and across thread blocks then relies on global memory to determine the reduction results corresponding to the input tensor based on the reduction results computed by multiple threads.

[0004] However, in the method of the related art, each thread in each thread block needs to access the global memory. Since it takes a long time for the thread to access the global memory, the method of the related art has the problem of low efficiency. Summary of the Invention

[0005] The present application provides a method for obtaining reduction results and a computing device to at least solve the problem of low efficiency in obtaining reduction results in related technologies.

[0006] This application provides a method for obtaining a specification result, including:

[0007] For any thread block, run each thread in the thread block, perform reduction processing on the elements stored in the multiple registers corresponding to the thread, obtain the reduction result corresponding to the thread, and update the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread; the elements belong to the input tensor;

[0008] Run the target thread in each thread block and update the first reduction result in the global memory according to the reduction result in the shared memory corresponding to each thread block;

[0009] Run the target thread in the target thread block and determine the first reduction result in the global memory as the reduction result corresponding to the input tensor; the target thread block belongs to multiple thread blocks.

[0010] The present application provides a computing device, comprising:

[0011] A graphics processor is configured to, for any thread block, run each thread in the thread block, perform reduction processing on elements stored in a plurality of registers corresponding to the thread, obtain a reduction result corresponding to the thread, and update the reduction result in a shared memory corresponding to the thread block based on the reduction result corresponding to the thread; the elements belong to an input tensor;

[0012] The graphics processor is further configured to run the target thread in each thread block and update the first reduction result in the global memory according to the reduction result in the shared memory corresponding to each thread block;

[0013] The graphics processor is further configured to run a target thread in a target thread block and determine the first reduction result in the global memory as the reduction result corresponding to the input tensor; the target thread block belongs to multiple thread blocks.

[0014] The present application provides a computing device, comprising:

[0015] a processor, and a memory communicatively coupled to the processor;

[0016] Memory is used to store computer-executable instructions;

[0017] The processor is used to execute the computer-executable instructions stored in the memory to implement the steps of the method for obtaining the reduction result as described above.

[0018] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the method for obtaining the reduction result as described above are implemented.

[0019] The present application also provides a computer program product, including a computer program, which implements the steps of the aforementioned method for obtaining the reduction result when the computer program is executed by a processor.

[0020] This application executes each thread in any thread block, performs reduction processing on the elements (input tensors) stored in multiple registers corresponding to the thread, obtains the thread-specific reduction result, and updates the reduction result in the shared memory corresponding to the thread block based on the thread-specific reduction result. A computing device executes the target thread in each thread block and updates the first reduction result in global memory based on the reduction result in the shared memory corresponding to each thread block. The computing device executes the target thread in the target thread block and determines the first reduction result in global memory as the reduction result corresponding to the input tensor; the target thread block belongs to multiple thread blocks. Because this method utilizes a register-shared memory-global memory reduction scheme, it eliminates the need to access global memory during reduction within a thread block, reducing the number of global memory accesses. Because the thread access rate for global memory is lower than the thread access rate for shared memory, the efficiency of obtaining the reduction result corresponding to the input tensor is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0023] Figure 2 A flowchart of a first embodiment of a method for obtaining a reduction result provided in an embodiment of the present application;

[0024] Figure 3a A flowchart of a second embodiment of a method for obtaining a reduction result provided in an embodiment of the present application;

[0025] Figure 3b A schematic diagram of a scenario for creating a thread block provided in an embodiment of the present application;

[0026] Figure 4 A flowchart of a third embodiment of a method for obtaining a reduction result provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of the structure of the computing device provided in this application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, other embodiments obtained by ordinary technicians in this field without making any creative work are all within the scope of protection of this application.

[0029] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0030] The reduction operation is to combine multiple numbers into one result, such as finding the maximum value, calculating the sum, etc.

[0031] In related technologies, threads within a thread block typically write the reduction results computed by that thread directly to global memory. Communication within and across thread blocks then relies on global memory to determine the reduction results corresponding to the input tensor based on the reduction results computed by multiple threads.

[0032] However, in the method of the related art, each thread in each thread block needs to access the global memory. Since it takes a long time for the thread to access the global memory, the method of the related art has the problem of low efficiency.

[0033] Therefore, in response to the above-mentioned technical problems in the related art, it was discovered during the research process that if a register-shared memory-global memory reduction method is adopted, the number of global memory accesses can be reduced, thereby improving the efficiency of obtaining the reduction results corresponding to the input tensor. Therefore, the present application proposes a method for obtaining reduction results and a computing device. Specifically, the computing device runs each thread in any thread block, performs reduction processing on the elements stored in multiple registers corresponding to the thread (belonging to the input tensor), obtains the reduction result corresponding to the thread, and updates the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread. The computing device runs the target thread in each thread block and updates the first reduction result in the global memory based on the reduction result in the shared memory corresponding to each thread block. The computing device runs the target thread in the target thread block (belonging to multiple thread blocks) and determines the first reduction result in the global memory as the reduction result corresponding to the input tensor.

[0034] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0035] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the method of this application depends, the specific application environment architecture or specific hardware architecture is described here. Figure 1 , Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application.

[0036] like Figure 1 As shown, the computing device 10 includes a central processing unit 101 and a graphics processing unit 102. The graphics processing unit 102 includes a global memory 1021, a total shared memory 1022, and a plurality of registers. Figure 1 Four registers are shown, namely register 1, register 2, register 3, and register 4. It should be noted that the total shared memory 1022 may include the shared memory corresponding to each thread block. It should also be noted that the duration of a thread accessing global memory is greater than the duration of a thread accessing shared memory.

[0037] The central processing unit 101 is electrically connected to the graphics processing unit 102 .

[0038] exist Figure 1 In the embodiment, the CPU 101 can determine the reduction mode according to the input tensor.

[0039] The graphics processor 102 can run each thread in any thread block, perform reduction processing on the elements stored in multiple registers corresponding to the thread, obtain the reduction result corresponding to the thread, and update the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread; the elements belong to the input tensor.

[0040] The graphics processor 102 may run the target thread in each thread block and update the first reduction result in the global memory according to the reduction result in the shared memory corresponding to each thread block.

[0041] The graphics processor 102 may run a target thread in a target thread block and determine the first reduction result in the global memory as the reduction result corresponding to the input tensor; the target thread block belongs to multiple thread blocks.

[0042] It should be noted that Figure 1 This is a schematic diagram of a computing device provided in an embodiment of the present application. This embodiment of the present application is not Figure 1 The actual form of the various components included in the Figure 1 The interaction mode between the components is limited, and in the application of the solution, it can be set according to actual needs.

[0043] The technical solution of the present application is described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0044] Figure 2 This is a flow chart of a method for obtaining a reduction result according to an embodiment of the present application. Figure 2 , the method specifically comprises the following steps:

[0045] S201: For any thread block, run each thread in the thread block, perform reduction processing on the elements stored in multiple registers corresponding to the thread, obtain the reduction result corresponding to the thread, and update the reduction result in the shared memory corresponding to the thread block according to the reduction result corresponding to the thread.

[0046] In this embodiment, the graphics processor in the computing device may include at least one thread block. Each thread block may include multiple threads. It should be noted that, in one implementation, when the protocol mode is the three-level protocol mode, the graphics processor in the computing device may include multiple thread blocks; when the protocol mode is the register mode, the graphics processor in the computing device may include one thread block; and when the protocol mode is the shared memory mode, the graphics processor in the computing device may include one thread block.

[0047] Each thread can correspond to multiple registers. Each register can store an element. It should be noted that the element belongs to the input tensor. In one implementation, a register can store one element.

[0048] The graphics processor in the computing device runs each thread in any thread block, performs reduction processing on elements stored in multiple registers corresponding to the thread, and obtains a reduction result corresponding to the thread.

[0049] The graphics processing unit (GPU) in the computing device can run each thread in the thread block and update the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread. In one implementation, the GPU in the computing device can run each thread in the thread block and call BlockReduce (a code module) to cause BlockReduce to update the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread. It should be noted that BlockReduce can be used to reduce the reduction results corresponding to multiple threads in a thread block.

[0050] In one implementation:

[0051] The central processing unit in the computing device can determine the number of elements in the input tensor.

[0052] The central processing unit in the computing device can determine the corresponding reduction mode of the input tensor based on the number of elements. The reduction mode includes register mode, shared memory mode, or three-level reduction mode.

[0053] The graphics processor in the computing device may create at least one thread block according to a protocol mode.

[0054] It should be noted that, in one implementation, when the reduction mode is a three-level reduction mode, the number of thread blocks can be greater than 1; in one implementation, when the reduction mode is a register mode, the number of thread blocks can be 1; in one implementation, when the reduction mode is a shared memory mode, the number of thread blocks can be 1.

[0055] It should also be noted that, in one implementation, the graphics processor in the computing device can determine the kernel corresponding to the protocol mode based on the protocol mode, and start the kernel corresponding to the protocol mode to create at least one thread block. In one implementation, the graphics processor in the computing device can determine the kernel corresponding to the three-level protocol mode based on the protocol mode being the three-level protocol mode, and start the kernel corresponding to the three-level protocol mode to create multiple thread blocks. In one implementation, the graphics processor in the computing device can determine the kernel corresponding to the register mode based on the protocol mode being the register mode, and start the kernel corresponding to the register mode to create one thread block. In one implementation, the graphics processor in the computing device can determine the kernel corresponding to the shared memory mode based on the protocol mode being the shared memory mode, and start the kernel corresponding to the shared memory mode to create one thread block.

[0056] The graphics processor in the computing device can, when the reduction mode is the three-level reduction mode, run each thread in any thread block, perform reduction processing on the elements stored in multiple registers corresponding to the thread, obtain the reduction result corresponding to the thread, and update the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread.

[0057] S202: Run the target thread in each thread block, and update the first reduction result in the global memory according to the reduction result in the shared memory corresponding to each thread block.

[0058] In this embodiment, the graphics processor in the computing device can execute the target thread in each thread block and update the first reduction result in global memory based on the reduction result in the shared memory corresponding to each thread block. In one implementation, for any thread block, the graphics processor in the computing device can execute the target thread in that thread block and, using an atomic write, update the first reduction result in global memory based on the reduction result in the shared memory corresponding to that thread block.

[0059] Through atomic writes, when multiple threads update the first reduction result in the global memory at the same time, it can be ensured that one thread is executed first and then another thread to avoid data confusion.

[0060] It should be noted that, for any thread block, the target thread in the thread block updates the first reduction result in the global memory according to the reduction result in the shared memory corresponding to the thread block after each thread in the thread block updates the reduction result in the shared memory corresponding to the thread block according to the reduction result corresponding to the thread.

[0061] It should also be noted that, for any thread block, the target thread in the thread block updates the first reduction result in the global memory according to the reduction result in the shared memory corresponding to the thread block after each thread in the thread block updates the reduction result in the shared memory corresponding to the thread block according to the reduction results of each batch corresponding to the thread.

[0062] In one implementation, the target thread in each thread block is the first thread in each thread block.

[0063] S203: Run the target thread in the target thread block, and determine the first reduction result in the global memory as the reduction result corresponding to the input tensor.

[0064] In this embodiment, the multiple thread blocks may include a target thread block. In one implementation, the target thread block may be a first thread block among the multiple thread blocks.

[0065] It should be noted that the target thread in the target thread block is the target thread in each thread block. After updating the first reduction result in the global memory based on the reduction result in the shared memory corresponding to the thread block, the first reduction result in the global memory is determined as the reduction result corresponding to the input tensor.

[0066] In one implementation, the target thread block may be the thread block with the smallest thread block sequence number. In one implementation, the target thread block may be the thread block with the thread block sequence number 0.

[0067] The graphics processor in the computing device can run the target thread in the target thread block and determine the first reduction result in the global memory as the reduction result corresponding to the input tensor.

[0068] Beneficial effects of this embodiment: In this embodiment, a computing device executes each thread in any thread block, performs reduction processing on elements stored in multiple registers corresponding to the thread, obtains a reduction result corresponding to the thread, and updates the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread; the element belongs to an input tensor. The computing device can execute a target thread in each thread block, update a first reduction result in global memory based on the reduction result in the shared memory corresponding to each thread block, execute a target thread in a target thread block, and determine the first reduction result in global memory as the reduction result corresponding to the input tensor; the target thread block belongs to multiple thread blocks. Through the above method, registers are first used to perform reduction within a thread, shared memory is then used to perform reduction within a thread block, and finally global memory is used to perform reduction between thread blocks. This reduces the number of global memory accesses and avoids directly performing global synchronization of reduction results. Because the speed at which threads access shared memory is greater than the speed at which threads access global memory, the above method improves the efficiency of obtaining reduction results.

[0069] Figure 3a This is a flow chart of a second embodiment of a method for obtaining a reduction result provided in an embodiment of the present application. Figure 3a , the method specifically comprises the following steps:

[0070] S301: Determine the number of elements in the input tensor.

[0071] In this embodiment, the input tensor may include multiple elements.

[0072] The central processing unit in the computing device can determine the number of elements in the input tensor.

[0073] S302: Determine the reduction mode corresponding to the input tensor based on the number of elements.

[0074] In this embodiment, the central processing unit in the computing device can determine the reduction mode corresponding to the input tensor according to the number of elements.

[0075] The following describes the process by which a central processing unit in a computing device determines the reduction mode corresponding to an input tensor based on the number of elements.

[0076] In one implementation:

[0077] The central processing unit (CPU) in a computing device can obtain the element range corresponding to each reduction mode (also called a reduction path). For example, the element range corresponding to register mode is (0, 512]; the element range corresponding to shared memory mode is (512, 8064]; and the element range corresponding to three-level reduction mode is (8064, +∞].

[0078] The CPU in the computing device can determine the reduction mode for the input tensor based on the number of elements (data_size) and the range of element numbers corresponding to each reduction mode. For example, the CPU in the computing device can determine that the reduction mode for the input tensor is level 3 based on the number of elements being 9000.

[0079] In addition, it should be noted that, in one implementation:

[0080] The central processing unit in the computing device can also obtain the model of the graphics processing unit when the protocol mode is the shared memory mode or the three-level protocol mode.

[0081] The central processing unit (CPU) in a computing device can determine the size of the shared memory based on the GPU model. In one implementation, the shared memory is part of the total shared memory. It should be noted that the shared memory corresponding to each thread block is accessible to threads in that thread block and is not accessible to threads in other thread blocks.

[0082] The CPU in the computing device can send the size of the shared memory to the GPU.

[0083] The graphics processor in the computing device can determine the shared memory corresponding to each thread block based on the size of the shared memory. For example, the size of the shared memory can be 164KB.

[0084] S303: Create at least one thread block according to the specification mode.

[0085] In this embodiment, the computing device may create at least one thread block according to the specification mode.

[0086] For example, Figure 3b A schematic diagram of a scenario for creating a thread block provided in an embodiment of the present application is shown in FIG. Figure 3b As shown, when the protocol mode is register mode, the computing device can create a thread block, which can be a 32x64 thread block; when the protocol mode is shared memory mode, the computing device can create a thread block, which can be a 128x256 thread block; when the protocol mode is shared memory mode, the computing device can create 4xSM (the number of streaming multiprocessors) thread blocks, which include 1024 threads.

[0087] In one implementation:

[0088] The central processing unit in the computing device may determine the first quantity according to the protocol mode.

[0089] The first number is the number of thread blocks.

[0090] The following describes a process in which a central processing unit in a computing device determines the first quantity according to a protocol mode.

[0091] In one implementation, the central processing unit (CPU) in the computing device may, when the protocol mode is the three-level protocol mode, determine the first number as the product of the number of streaming multiprocessors in the computing device and a preset multiplier. In one implementation, the preset multiplier may be 4. In other words, the first number may be 4 x SM (the number of streaming multiprocessors).

[0092] In one implementation, a central processing unit in the computing device may determine a sequence length value (num_tokens) corresponding to the input tensor as the first number when the reduction mode is the three-level reduction mode.

[0093] In one implementation, a central processing unit (CPU) in a computing device may, when the reduction mode is not the three-level reduction mode, determine a preset first quantity as the first quantity. In one implementation, the preset first quantity may be 1. In one implementation, when the reduction mode is the register mode, the CPU in the computing device may determine a sequence length value (num_tokens) corresponding to an input tensor as the initial first quantity. Based on the fact that the reduction mode is the register mode, the CPU in the computing device may reduce the initial first quantity to obtain a reduced initial first quantity, and determine the reduced initial first quantity as the first quantity.

[0094] The central processing unit in the computing device may determine the second number according to the protocol mode, wherein the second number is the number of threads included in the thread block.

[0095] Next, a process of determining the second quantity according to the protocol mode by the central processing unit in the computing device is described.

[0096] In one implementation:

[0097] The central processing unit in the computing device can obtain the feature dimension value (hidden_size) corresponding to the input tensor.

[0098] The central processing unit in the computing device can determine whether the feature dimension value is greater than a preset threshold. In one implementation, the preset threshold can be 1024.

[0099] The central processing unit in the computing device may determine the preset threshold as the second number when the feature dimension value is greater than the preset threshold.

[0100] or,

[0101] The central processing unit in the computing device may determine the preset threshold as the second number when the feature dimension value is less than or equal to the preset threshold.

[0102] In one implementation:

[0103] The central processing unit in the computing device may determine the preset threshold value as the second number when the protocol mode is the three-level protocol mode.

[0104] The central processing unit in the computing device may obtain a feature dimension value corresponding to the input tensor when the reduction mode is not the three-level reduction mode. The central processing unit in the computing device may determine whether the feature dimension value is greater than a preset threshold. If the feature dimension value is greater than the preset threshold, the central processing unit in the computing device may determine the preset threshold as a second number. Alternatively, if the feature dimension value is less than or equal to the preset threshold, the central processing unit in the computing device may determine the preset threshold as the second number.

[0105] In addition, after determining the first number and the second number, the central processing unit in the computing device may send a processing message to the graphics processing unit; wherein the processing message may include the first number and the second number. In one implementation, the processing message may also include a protocol mode.

[0106] After obtaining the first number and the second number, the graphics processor in the computing device may create at least one thread block according to the first number and the second number, wherein the number of threads included in each thread block is consistent with the second number.

[0107] S304: When the reduction mode is the three-level reduction mode, for any thread block, run each thread in the thread block, perform reduction processing on the elements stored in multiple registers corresponding to the thread, obtain the reduction result corresponding to the thread, and update the reduction result in the shared memory corresponding to the thread block according to the reduction result corresponding to the thread.

[0108] In this embodiment, the graphics processor in the computing device can obtain the protocol mode corresponding to the input tensor sent by the central processing unit in the computing device.

[0109] The graphics processor in the computing device can, when the reduction mode is the three-level reduction mode, run each thread in any thread block, perform reduction processing on the elements stored in multiple registers corresponding to the thread, obtain the reduction result corresponding to the thread, and update the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread.

[0110] In addition, it should be noted that, in one implementation:

[0111] The graphics processing unit in the computing device may, when the reduction mode is register mode, run each thread in the thread block, perform reduction processing on elements stored in multiple registers corresponding to the thread, obtain a reduction result corresponding to the thread, and update a second reduction result stored in global memory based on the reduction result corresponding to the thread. The graphics processing unit in the computing device may run the target thread in the thread block and determine the second reduction result in global memory as the reduction result corresponding to the input tensor.

[0112] It can be understood that when the specification mode is the register mode, each thread in the thread block is a thread created by the kernel corresponding to the register mode.

[0113] In addition, it should be noted that, in one implementation:

[0114] The graphics processor in the computing device can, when the reduction mode is shared memory mode, run each thread in the thread block, perform reduction processing on elements stored in multiple registers corresponding to the thread, obtain the reduction result corresponding to the thread, and update the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread. The graphics processor in the computing device can run the target thread in the thread block, determine the reduction result in the shared memory corresponding to the thread block as the reduction result corresponding to the input tensor, and store the reduction result corresponding to the input tensor in global memory.

[0115] It can be understood that when the specification mode is the shared memory mode, each thread in the thread block is a thread created by the kernel corresponding to the shared memory mode.

[0116] S305: Run the target thread in each thread block, and update the first reduction result in the global memory according to the reduction result in the shared memory corresponding to each thread block.

[0117] In this embodiment, the graphics processor in the computing device can run the target thread in each thread block and update the first reduction result in the global memory according to the reduction result in the shared memory corresponding to each thread block.

[0118] The specific implementation process is the same as S202 and will not be repeated here.

[0119] S306: Run the target thread in the target thread block, and determine the first reduction result in the global memory as the reduction result corresponding to the input tensor.

[0120] In this embodiment, the target thread block belongs to multiple thread blocks.

[0121] The graphics processor in the computing device can run the target thread in the target thread block and determine the first reduction result in the global memory as the reduction result corresponding to the input tensor.

[0122] The specific implementation process is the same as S203 and will not be repeated here.

[0123] Beneficial effects of this embodiment: In this embodiment, the computing device can determine the reduction mode corresponding to the input tensor based on the number of elements in the input tensor (the reduction mode includes a three-level reduction mode, a register mode, or a shared memory mode). The computing device can create at least one thread block based on the reduction mode. When the reduction mode is the three-level reduction mode, the computing device can, for any thread block, run each thread in the thread block, perform reduction processing on the elements stored in multiple registers corresponding to the thread, obtain the reduction result corresponding to the thread, and update the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread. The computing device can run the target thread in each thread block, update the first reduction result in the global memory based on the reduction result in the shared memory corresponding to each thread block; run the target thread in the target thread block, and determine the first reduction result in the global memory as the reduction result corresponding to the input tensor; the target thread block belongs to multiple thread blocks. Through the above method, on the one hand, the corresponding reduction mode can be accurately determined based on the number of elements in the input tensor, and then based on the reduction mode, the number of thread blocks to be created and the number of threads included in each thread block can be determined, thereby improving resource utilization; on the other hand, based on the three-level reduction mode, the register-shared memory-global memory method is adopted to perform step-by-step reduction, which reduces the number of global memory accesses, avoids direct global synchronization of reduction results, and improves the efficiency of obtaining reduction results.

[0124] Below, through method embodiment three, the process of "for any thread block, running each thread in the thread block, reducing the elements stored in multiple registers corresponding to the thread, obtaining the reduction result corresponding to the thread, and updating the reduction result in the shared memory corresponding to the thread block according to the reduction result corresponding to the thread" in S201 of the embodiment is explained.

[0125] Figure 4 This is a flow chart of a third embodiment of a method for obtaining a reduction result provided in an embodiment of the present application. Figure 4 , the method specifically comprises the following steps:

[0126] S401: For the i-th thread in any thread block, run the i-th thread, and obtain multiple j-th batches of elements corresponding to the i-th thread from the input tensor stored in the global memory according to the vectorization width.

[0127] In this embodiment, the graphics processor in the computing device runs the i-th thread in any thread block and retrieves multiple j-th batches of elements corresponding to the i-th thread from the input tensor stored in global memory based on the vectorization width (VEC_SIZ). For example, the vectorization width (VEC_SIZ) can be 1. For another example, the vectorization width (VEC_SIZ) can be 4. For another example, the vectorization width (VEC_SIZ) can be 8.

[0128] It should be noted that i is 1, 2, ..., up to N in sequence; N is the number of threads included in the thread block;

[0129] j is 1, 2, ..., up to M in sequence; M is the total number of element batches corresponding to each thread.

[0130] Below, first, a process of obtaining the vectorization width of a graphics processor in a computing device is described.

[0131] In one implementation:

[0132] The central processing unit in the computing device can obtain the preset vectorization width corresponding to each protocol mode. For example, the preset vectorization width (VEC_SIZ) corresponding to the register mode can be 8, the preset vectorization width (VEC_SIZ) corresponding to the shared memory mode can be 4, and the preset vectorization width (VEC_SIZ) corresponding to the three-level protocol mode can be 1.

[0133] After determining the reduction mode corresponding to the input tensor, the central processing unit in the computing device can determine the vectorization width according to the reduction mode corresponding to the input tensor and the preset vectorization width corresponding to each reduction mode.

[0134] The central processing unit in the computing device may send a vectorization width to a graphics processing unit in the computing device.

[0135] In one implementation:

[0136] The central processing unit in the computing device can obtain the number of elements corresponding to the input tensor.

[0137] The central processing unit in the computing device can obtain the storage address corresponding to the input tensor.

[0138] The central processing unit in the computing device may obtain multiple candidate vectorization widths, for example, 1, 4, and 8.

[0139] For any candidate vectorization width, the central processing unit in the computing device can determine whether the number of elements and the storage address are integer multiples of the candidate vectorization width.

[0140] The central processing unit in the computing device may determine the candidate vectorization width as the vectorization width when the number of elements and the storage address are integer multiples of the candidate vectorization width.

[0141] The central processing unit in the computing device may send a vectorization width to a graphics processing unit in the computing device.

[0142] The following describes a process in which a graphics processor in a computing device runs the i-th thread and obtains multiple j-th batches of elements corresponding to the i-th thread from an input tensor stored in a global memory according to a vectorization width.

[0143] In one implementation:

[0144] A graphics processor in the computing device, running the i-th thread, can determine the storage addresses of multiple j-th batches of elements based on the thread program number of the i-th thread, the thread block number of the thread block to which the i-th thread belongs, the storage address of the input tensor, and the vectorization width.

[0145] The graphics processor in the computing device, running the i-th thread, can obtain multiple j-th batches of elements corresponding to the i-th thread from the input tensor stored in the global memory according to the storage addresses of the multiple j-th batches of elements.

[0146] S402: Run the i-th thread, and store multiple j-th batches of elements corresponding to the i-th thread into multiple registers corresponding to the i-th thread.

[0147] In this embodiment, the graphics processor in the computing device runs the i-th thread and can, after obtaining multiple j-th batches of elements corresponding to the i-th thread, store the multiple j-th batches of elements corresponding to the i-th thread in multiple registers corresponding to the i-th thread.

[0148] S403: Run the i-th thread, perform reduction processing on the j-th batch of elements stored in multiple registers corresponding to the i-th thread, and obtain the reduction result of the j-th batch corresponding to the i-th thread.

[0149] In this embodiment, the graphics processor in the computing device can run the i-th thread, perform reduction processing on the j-th batch of elements stored in multiple registers corresponding to the i-th thread, and obtain the j-th batch reduction result corresponding to the i-th thread.

[0150] In one implementation, a graphics processor in a computing device may run the i-th thread, compare the j-th batch of elements stored in multiple registers corresponding to the i-th thread, determine a maximum element, and determine the maximum element as the reduction result of the j-th batch corresponding to the i-th thread.

[0151] In one implementation, a graphics processor in a computing device may run the i-th thread and, based on a loop unrolling function, perform parallel reduction processing on the j-th batch of elements stored in multiple registers corresponding to the i-th thread to obtain the j-th batch of reduction results corresponding to the i-th thread.

[0152] It should also be noted that the graphics processor in the computing device runs each thread in parallel. For the i-th thread, the graphics processor in the computing device can run the i-th thread and perform reduction processing on the j-th batch of elements stored in the multiple registers corresponding to the i-th thread, thereby obtaining the j-th batch of reduction results corresponding to the i-th thread.

[0153] S404: Run the i-th thread, and update the reduction results in the shared memory corresponding to the thread block according to the j-th batch reduction results corresponding to the i-th thread.

[0154] In this embodiment, the graphics processor in the computing device may run the i-th thread and update the reduction results in the shared memory corresponding to the thread block according to the j-th batch reduction results corresponding to the i-th thread.

[0155] It should be noted that, in one implementation, the graphics processor in the computing device can run the i-th thread and call BlockReduce, so that BlockReduce updates the reduction results in the shared memory corresponding to the thread block according to the reduction results of the j-th batch corresponding to the i-th thread.

[0156] In one implementation:

[0157] The graphics processor in the computing device can run the i-th thread, perform reduction processing on the j-th batch of reduction results corresponding to the i-th thread and the reduction results in the shared memory, obtain a new reduction result, and determine the new reduction result as the reduction result in the shared memory corresponding to the thread block.

[0158] For example, when the reduction processing is to find the maximum value, the graphics processor in the computing device can run the i-th thread, determine the larger of the reduction result of the j-th batch corresponding to the i-th thread and the reduction result in the shared memory as the new reduction result, and determine the new reduction result as the reduction result in the shared memory corresponding to the thread block.

[0159] Beneficial effects of this embodiment: In this embodiment, for the i-th thread in any thread block, the computing device (the graphics processor in the computing device) can execute the i-th thread and, based on the vectorization width, retrieve multiple j-th batches of elements corresponding to the i-th thread from the input tensor stored in global memory. The computing device (the graphics processor in the computing device) can execute the i-th thread and store the multiple j-th batches of elements corresponding to the i-th thread in multiple registers corresponding to the i-th thread. The computing device (the graphics processor in the computing device) can execute the i-th thread and perform reduction processing on the j-th batch of elements stored in the multiple registers corresponding to the i-th thread to obtain the reduction result for the j-th batch corresponding to the i-th thread. The computing device (the graphics processor in the computing device) can execute the i-th thread and, based on the reduction result for the j-th batch corresponding to the i-th thread, update the reduction result in the shared memory corresponding to the thread block. Here, i is 1, 2, ..., up to N; N is the number of threads in the thread block. j is 1, 2, ..., up to M; M is the total number of element batches corresponding to each thread. Through the above method, elements can be obtained in an orderly manner based on the vectorization width, and then the elements can be reduced, thereby improving the acquisition efficiency and accuracy of the reduction results corresponding to the thread.

[0160] The following are device embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0161] An embodiment of the present application provides a computing device including a graphics processor and a central processing unit.

[0162] A graphics processor is configured to, for any thread block, run each thread in the thread block, perform reduction processing on elements stored in a plurality of registers corresponding to the thread, obtain a reduction result corresponding to the thread, and update the reduction result in a shared memory corresponding to the thread block based on the reduction result corresponding to the thread; the elements belong to an input tensor;

[0163] The graphics processor is further configured to run the target thread in each thread block and update the first reduction result in the global memory according to the reduction result in the shared memory corresponding to each thread block;

[0164] The graphics processor is further configured to run a target thread in a target thread block and determine the first reduction result in the global memory as the reduction result corresponding to the input tensor; the target thread block belongs to at least one thread block.

[0165] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0166] In one implementation,

[0167] CPU, which determines the number of elements in the input tensor;

[0168] The central processing unit is further used to determine the reduction mode corresponding to the input tensor based on the number of elements; the reduction mode includes a three-level reduction mode, a register mode, or a shared memory mode;

[0169] The graphics processor is further configured to create at least one thread block according to the specification mode;

[0170] The graphics processor is further configured to, when the reduction mode is the three-level reduction mode, run each thread in any thread block, perform reduction processing on elements stored in multiple registers corresponding to the thread, obtain a reduction result corresponding to the thread, and update the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread.

[0171] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0172] In one implementation, the central processing unit is specifically configured to:

[0173] Get the range of element numbers corresponding to each specification mode;

[0174] Determine the reduction mode corresponding to the input tensor based on the number of elements and the range of element numbers corresponding to each reduction mode.

[0175] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0176] In one implementation,

[0177] The central processing unit is configured to determine a first number according to a protocol mode; the first number is the number of thread blocks;

[0178] The central processing unit is configured to determine a second number according to the protocol mode; the second number is the number of threads included in the thread block;

[0179] The graphics processor is configured to create at least one thread block according to the first quantity and the second quantity.

[0180] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0181] In one implementation, the central processing unit is configured to:

[0182] In the case where the protocol mode is the three-level protocol mode, the product of the number of streaming multiprocessors in the computing device and a preset multiple is determined as the first number; or

[0183] When the reduction mode is the three-level reduction mode, the sequence length value corresponding to the input tensor is determined as the first quantity.

[0184] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0185] In one implementation, the central processing unit is configured to:

[0186] Get the feature dimension value corresponding to the input tensor;

[0187] Determine whether the feature dimension value is greater than a preset threshold;

[0188] When the feature dimension value is greater than a preset threshold, the preset threshold is determined as a second number; or,

[0189] When the feature dimension value is less than or equal to the preset threshold, the preset threshold is determined as the second number.

[0190] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0191] In one implementation, the central processing unit is configured to:

[0192] In the case where the protocol mode is the three-level protocol mode, the preset threshold is determined to be the second number; or,

[0193] When the reduction mode is not the three-level reduction mode, obtain the feature dimension value corresponding to the input tensor.

[0194] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0195] In one implementation, a graphics processor is configured to:

[0196] For the i-th thread in any thread block, run the i-th thread and obtain multiple j-th batches of elements corresponding to the i-th thread from the input tensor stored in global memory according to the vectorization width;

[0197] Run the i-th thread and store the j-th batch of elements corresponding to the i-th thread into the registers corresponding to the i-th thread.

[0198] Run the i-th thread, perform reduction processing on the j-th batch of elements stored in multiple registers corresponding to the i-th thread, and obtain the reduction result of the j-th batch corresponding to the i-th thread;

[0199] Run the i-th thread and update the reduction result in the shared memory corresponding to the thread block according to the reduction result of the j-th batch corresponding to the i-th thread;

[0200] Where i is 1, 2, ..., up to N; N is the number of threads included in the thread block;

[0201] j is 1, 2, ..., up to M in sequence; M is the total number of element batches corresponding to each thread.

[0202] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0203] In one implementation, the central processing unit is further configured to:

[0204] Get the preset vectorization width corresponding to each protocol mode;

[0205] Determine the vectorization width based on the reduction mode corresponding to the input tensor and the preset vectorization width corresponding to each reduction mode.

[0206] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0207] In one implementation, the central processing unit is further configured to:

[0208] Get the number of elements corresponding to the input tensor;

[0209] Get the storage address corresponding to the input tensor;

[0210] Get multiple vectorization widths to be selected;

[0211] For any candidate vectorization width, determine whether the number of elements and storage address are integer multiples of the candidate vectorization width;

[0212] When the number of elements and the storage address are integer multiples of the vectorization width to be selected, the vectorization width to be selected is determined as the vectorization width.

[0213] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0214] In one implementation, the graphics processor is further configured to:

[0215] When the reduction mode is register mode, each thread in the thread block is run, and elements stored in multiple registers corresponding to the thread are reduced to obtain a reduction result corresponding to the thread, and a second reduction result stored in the global memory is updated according to the reduction result corresponding to the thread;

[0216] Run the target thread in the thread block and determine the second reduction result in the global memory as the reduction result corresponding to the input tensor.

[0217] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0218] In one implementation, the graphics processor is further configured to:

[0219] When the reduction mode is the shared memory mode, each thread in the thread block is run, and the elements stored in the multiple registers corresponding to the thread are reduced to obtain the reduction result corresponding to the thread, and the reduction result in the shared memory corresponding to the thread block is updated according to the reduction result corresponding to the thread;

[0220] Run the target thread in the thread block, determine the reduction result in the shared memory corresponding to the thread block as the reduction result corresponding to the input tensor, and store the reduction result corresponding to the input tensor to the global memory.

[0221] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0222] In one implementation,

[0223] The central processing unit is further used to obtain the model of the graphics processing unit when the protocol mode is the shared memory mode or the three-level protocol mode;

[0224] The CPU is also used to determine the size of the shared memory based on the model of the graphics processor;

[0225] The graphics processor is further configured to determine the shared memory corresponding to each thread block according to the size of the shared memory.

[0226] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0227] In one implementation, the target thread block is the first thread block among the multiple thread blocks; and the target thread in each thread block is the first thread in each thread block.

[0228] The computing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0229] Figure 5 This is a schematic diagram of the structure of the computing device provided in this application. Figure 5 As shown, the computing device 50 provided in this embodiment includes: a processor 51 and a memory 52 communicatively connected to the processor 51 .

[0230] The memory 52 is used to store computer-executable instructions.

[0231] The processor 51 is configured to execute computer-executable instructions stored in the memory 52 to implement the solution of the aforementioned method embodiment.

[0232] In one implementation, the memory 52 may be independent or integrated with the processor 51. Optionally, when the memory 52 is a device independent of the processor 51, the computing device 50 may further include a bus 53 for connecting the above devices.

[0233] The specific implementation process of the processor 51 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0234] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when run.

[0235] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0236] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0237] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0238] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0239] The above is a method for obtaining the result of a regulation and a computing device provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for obtaining a reduction result, characterized in that: include: For any thread block, run each thread in the thread block, perform reduction processing on elements stored in multiple registers corresponding to the thread, obtain a reduction result corresponding to the thread, and update the reduction result in the shared memory corresponding to the thread block based on the reduction result corresponding to the thread; the element belongs to the input tensor; Run the target thread in each thread block and update the first reduction result in the global memory according to the reduction result in the shared memory corresponding to each thread block; Running a target thread in a target thread block, and determining the first reduction result in the global memory as the reduction result corresponding to the input tensor; The target thread block belongs to multiple thread blocks.

2. The method according to claim 1, characterized in that The method includes running each thread in any thread block, performing reduction processing on elements stored in multiple registers corresponding to the thread, obtaining a reduction result corresponding to the thread, and updating the reduction result in the shared memory corresponding to the thread block according to the reduction result corresponding to the thread, including: Determine the number of elements in the input tensor; Determining a reduction mode corresponding to the input tensor according to the number of elements; the reduction mode includes a three-level reduction mode, a register mode, or a shared memory mode; Creating at least one thread block according to the specification mode; When the reduction mode is the three-level reduction mode, for any thread block, each thread in the thread block is run, and the elements stored in the multiple registers corresponding to the thread are reduced to obtain the reduction result corresponding to the thread, and the reduction result in the shared memory corresponding to the thread block is updated according to the reduction result corresponding to the thread.

3. The method according to claim 2, characterized in that Determining the reduction mode corresponding to the input tensor according to the number of elements includes: Get the range of element numbers corresponding to each specification mode; The reduction mode corresponding to the input tensor is determined according to the number of elements and the range of the number of elements corresponding to each reduction mode.

4. The method according to claim 3, characterized in that The step of creating at least one thread block according to the specification mode includes: Determining a first number according to the protocol mode; the first number is the number of thread blocks; Determining a second number according to the protocol mode; the second number is the number of threads included in the thread block; The at least one thread block is created according to the first number and the second number.

5. The method according to claim 4, characterized in that The determining the first quantity according to the protocol model includes: In the case where the protocol mode is the three-level protocol mode, the product of the number of streaming multiprocessors in the computing device and a preset multiple is determined as the first number; or When the reduction mode is the three-level reduction mode, the sequence length value corresponding to the input tensor is determined as the first quantity.

6. The method according to claim 4, characterized in that The determining the second quantity according to the protocol model includes: Obtain the feature dimension value corresponding to the input tensor; Determining whether the feature dimension value is greater than a preset threshold; In the case where the feature dimension value is greater than the preset threshold, the preset threshold is determined as the second number; or, When the feature dimension value is less than or equal to the preset threshold, the preset threshold is determined as the second number.

7. The method according to claim 6, characterized in that The obtaining of the feature dimension value corresponding to the input tensor includes: In the case where the protocol mode is the three-level protocol mode, the preset threshold is determined to be the second number; or, When the reduction mode is not the three-level reduction mode, obtain the feature dimension value corresponding to the input tensor.

8. The method according to claim 1 or 2, characterized in that The method includes running each thread in any thread block, performing reduction processing on elements stored in multiple registers corresponding to the thread, obtaining a reduction result corresponding to the thread, and updating the reduction result in the shared memory corresponding to the thread block according to the reduction result corresponding to the thread, including: For an i-th thread in any thread block, run the i-th thread and, based on the vectorization width, obtain a plurality of j-th batches of elements corresponding to the i-th thread from the input tensor stored in the global memory; Run the i-th thread and store multiple j-th batches of elements corresponding to the i-th thread into multiple registers corresponding to the i-th thread; Running the i-th thread, performing reduction processing on the j-th batch of elements stored in the multiple registers corresponding to the i-th thread, and obtaining a reduction result of the j-th batch corresponding to the i-th thread; Run the i-th thread, and update the reduction results in the shared memory corresponding to the thread block according to the j-th batch reduction results corresponding to the i-th thread; Where i is 1, 2, ..., up to N; N is the number of threads included in the thread block; j is 1, 2, ..., up to M in sequence; M is the total number of element batches corresponding to each thread.

9. The method according to claim 8, characterized in that The method further comprises: Get the preset vectorization width corresponding to each protocol mode; The vectorization width is determined according to the reduction mode corresponding to the input tensor and the preset vectorization width corresponding to each reduction mode.

10. The method according to claim 8, characterized in that The method further comprises: Get the number of elements corresponding to the input tensor; Obtain the storage address corresponding to the input tensor; Get multiple vectorization widths to be selected; For any candidate vectorization width, determining whether the number of elements and the storage address are integer multiples of the candidate vectorization width; When the number of elements and the storage address are integer multiples of the candidate vectorization width, the candidate vectorization width is determined as the vectorization width.

11. The method according to claim 2, characterized in that The method further comprises: When the reduction mode is the register mode, running each thread in the thread block, performing reduction processing on elements stored in a plurality of registers corresponding to the thread, obtaining a reduction result corresponding to the thread, and updating a second reduction result stored in the global memory according to the reduction result corresponding to the thread; Run the target thread in the thread block, and determine the second reduction result in the global memory as the reduction result corresponding to the input tensor.

12. The method according to claim 2, characterized in that The method further comprises: When the reduction mode is the shared memory mode, running each thread in the thread block, performing reduction processing on elements stored in a plurality of registers corresponding to the thread, obtaining a reduction result corresponding to the thread, and updating the reduction result in the shared memory corresponding to the thread block according to the reduction result corresponding to the thread; Run the target thread in the thread block, determine the reduction result in the shared memory corresponding to the thread block as the reduction result corresponding to the input tensor, and store the reduction result corresponding to the input tensor in the global memory.

13. The method according to claim 2, characterized in that The method further comprises: When the protocol mode is the shared memory mode or the three-level protocol mode, obtaining a model of a graphics processor; Determining the size of the shared memory according to the model of the graphics processor; The shared memory corresponding to each thread block is determined according to the size of the shared memory.

14. The method according to claim 1, wherein The target thread block is the first thread block among the multiple thread blocks; the target thread in each thread block is the first thread in each thread block.

15. A computing device, characterized in that include: a processor, and a memory communicatively connected to the processor; The memory is used to store computer-executable instructions; The processor is configured to execute the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 14.

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