Floating-point number multiplication method and floating-point number multiplication circuit

Abstract

The invention provides a floating-point number multiplication method and a floating-point number multiplication circuit, and relates to the technical field of processors, and the method comprises the steps: obtaining a first index of a first floating-point number and a second index of a second floating-point number; according to the first index and the second index, obtaining a to-be-shifted parameter for performing to-be-shifted operation on a decimal part of a product of the first floating-point number and the second floating-point number; the to-be-shifted parameter comprises a shifting direction and a shifting digit; in the process of obtaining the shift result of the product according to the to-be-shifted parameter, obtaining overflow information of a fractional part of the shift result according to the to-be-shifted parameter; the overflow information comprises overflow or no overflow; and adjusting the index of the shift result according to the overflow information to obtain a multiplication result of the first floating-point number and the floating-point number. The method provided by the invention has the advantage of short floating-point number multiplication operation period.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processors, and particularly relates to a floating-point multiplication method and a floating-point multiplication circuit. BACKGROUND

[0002] When performing multiplication on floating-point numbers, in order to ensure that the decimal part does not overflow, the decimal part of the product needs to be shifted, and when the decimal part is shifted, the exponent will also change. After the decimal part of the product is shifted, the exponent may overflow the exponent range of the floating-point number, in which case the exponent needs to be handled by carrying.

[0003] In the related art, after obtaining the product of floating-point numbers, a shift operation is performed on the product, and then the value of the highest bit of the shift result is analyzed, and it is determined whether the exponent needs to be carried according to the analysis result.

[0004] However, this method needs to first obtain the shift result of the product, then determine the shift strategy according to the shift result, and then perform exponent shifting according to the shift strategy. This method has low processing efficiency and results in a long operation period of multiplication. SUMMARY

[0005] Embodiments of the present application provide a floating-point multiplication method and a floating-point multiplication circuit to solve the problems of low multiplication efficiency and long period in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a floating-point multiplication method, including: obtaining a first exponent of a first floating-point number and a second exponent of a second floating-point number; obtaining a to-be-shifted parameter for performing a to-be-shifted operation on the decimal part of the product of the first floating-point number and the second floating-point number according to the first exponent and the second exponent; the to-be-shifted parameter includes a shift direction and a shift bit number; in the process of obtaining a shift result of the product according to the to-be-shifted parameter, obtaining overflow information of the decimal part of the shift result according to the to-be-shifted parameter; the overflow information includes overflow or no overflow; adjusting the exponent of the shift result according to the overflow information to obtain a multiplication result of the first floating-point number and the floating-point number.

[0007] In a second aspect, the embodiments of the present application provide a floating-point multiplication circuit, comprising an overflow information obtaining unit, and a to-be-shifted parameter obtaining unit and an exponent adjusting unit connected with the overflow information obtaining unit; the to-be-shifted parameter obtaining unit is configured to obtain a first exponent of a first floating-point number and a second exponent of a second floating-point number; and according to the first exponent and the second exponent, a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating-point number and the second floating-point number is obtained; the to-be-shifted parameter comprises a shift direction and a shift bit number; the overflow information obtaining unit is configured to, in a process of obtaining a shift result of the product according to the to-be-shifted parameter, obtain overflow information of a decimal part of the shift result according to the to-be-shifted parameter; the overflow information comprises overflow or no overflow; and the exponent adjusting unit is configured to adjust an exponent of the shift result according to the overflow information, to obtain a multiplication result of the first floating-point number and the floating-point number.

[0008] In a third aspect, the embodiments of the present application further provide a floating-point multiplication device, comprising: a first obtaining module configured to obtain a first exponent of a first floating-point number and a second exponent of a second floating-point number; a second obtaining module configured to obtain, according to the first exponent and the second exponent, a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating-point number and the second floating-point number; the to-be-shifted parameter comprises a shift direction and a shift bit number; a third obtaining module configured to, in a process of obtaining a shift result of the product according to the to-be-shifted parameter, obtain overflow information of a decimal part of the shift result according to the to-be-shifted parameter; the overflow information comprises overflow or no overflow; and an exponent adjusting module configured to adjust an exponent of the shift result according to the overflow information, to obtain a multiplication result of the first floating-point number and the floating-point number.

[0009] In a fourth aspect, the embodiments of the present application further provide an electronic device, comprising a processor; a memory for storing instructions executable by the processor; and the processor is configured to execute the instructions to implement the method of the first aspect.

[0010] In a fifth aspect, the embodiments of the present application further provide a computer readable storage medium, when instructions in the computer readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method of the first aspect.

[0011] In the embodiment of the present application, the first exponent of the first floating-point number and the second exponent of the second floating-point number are obtained; in the process of obtaining the product of the first floating-point number and the second floating-point number, the shift parameter for the decimal part of the product to be subjected to a shift operation is obtained according to the first exponent and the second exponent; the shift parameter includes a shift direction and a shift bit number; in the process of obtaining the shift result of the decimal part of the product subjected to the shift operation according to the shift operation parameter, the overflow information of the shift result decimal part is obtained, the exponent of the shift result is adjusted according to the overflow information, and the multiplication result of the first floating-point number and the floating-point number is obtained. Compared with the method in the related art that the shift result is obtained, and then it is judged whether the exponent carry is needed according to the detection result of the highest value of the shift result, the embodiment reduces the processing time of the exponent carry and reduces the operation period of the floating-point number multiplication operation.

[0012] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creating labor intensity.

[0014] Figure 1 is a floating-point number multiplication method application scenario provided by the embodiment of the present application; Figure 2 is a floating-point number multiplication method step flowchart provided by the embodiment of the present application; Figure 3 is a floating-point number multiplication method step flowchart provided by the embodiment of the present application; Figure 4 is a floating-point number multiplication method step flowchart provided by the embodiment of the present application; Figure 5 is a floating-point number multiplication method step flowchart provided by the embodiment of the present application; Figure 6 is a floating-point number multiplication method step flowchart provided by the embodiment of the present application; Figure 7 is a floating-point number multiplication method step flowchart provided by the embodiment of the present application; Figure 8 is a floating-point number multiplication method step flowchart provided by the embodiment of the present application; Figure 9 is a flow chart of a floating-point multiplication method provided by an embodiment of the present application. Figure 10 is a schematic diagram of a floating-point multiplication circuit provided by an embodiment of the present application. Figure 11 is a schematic diagram of a shift information acquisition circuit provided by an embodiment of the present application. Figure 12 is a schematic diagram of an exponent carry information acquisition circuit provided by an embodiment of the present application. Figure 13 is a block diagram of a floating-point multiplication device provided by an embodiment of the present application. Figure 14 is a block diagram of an electronic device provided by an embodiment of the present application. Figure 15 is a block diagram of another electronic device provided by another embodiment of the present application. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0016] The terms “first”, “second”, and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by “first”, “second”, and the like are generally of a kind and do not limit the number of objects, for example, the first object can be one or more. In addition, the term “and / or” in the application file is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character “ / ” generally represents an “or” relationship between the associated objects. The term “multiple” in the embodiments of the present application means two or more, and other quantifiers are similar.

[0017] Figure 1 is a schematic diagram of an application scenario of a floating-point multiplication method provided by an embodiment of the present application, referring to Figure 1 , the floating-point multiplication instruction is a commonly used instruction in a processor, which can be used to instruct the first floating-point number and the second floating-point number to perform multiplication operation, and then obtain the product between the first floating-point number and the second floating-point number.

[0018] During the multiplication operation, the clock frequency is high, and the time of each operation period is short. The operation process of the floating-point multiplication operation is relatively complex, which leads to that the floating-point multiplication operation usually needs multiple periods to be completed. For example, in the related art, in some processor architectures, the multiplication operation between half-precision floating-point numbers, the multiplication operation between single-precision floating-point numbers, and the multiplication operation between double-precision floating-point numbers all need three periods.

[0019] Further, the floating-point number usually includes a sign part, an exponent part and a mantissa part, and the floating-point multiplication operation can be expressed by the following formula:

[0020] wherein, is a first floating-point number, is a second floating-point number, is a product between the first floating-point number and the second floating-point number. According to the above formula, the floating-point multiplication operation is to multiply the values of the first floating-point number and the second floating-point number.

[0021] Specifically, the sign values of the first floating-point number and the second floating-point number are multiplied, the exponent values of the first floating-point number and the second floating-point number are multiplied, and the decimal values of the first floating-point number and the second floating-point number are multiplied, so as to obtain the product between the first floating-point number and the second floating-point number, and then the product is converted into a binary floating-point number representation. Further, the sign value multiplication is an exclusive or operation on the binary sign parts of the first floating-point number and the second floating-point number; the exponent value multiplication is an addition operation on the binary exponent parts of the first floating-point number and the second floating-point number; and the decimal value multiplication is a multiplication operation on the binary mantissa parts of the first floating-point number and the second floating-point number.

[0022] Based on the above processing process of the multiplication operation, the value range of the result obtained by multiplying the decimal parts of the two floating-point numbers should be [0, 4). If the two floating-point numbers are both normalized numbers, the value range of the result of the decimal part multiplication operation should be [1, 4), and if the actual result obtained by multiplying the binary mantissa parts of the two floating-point numbers is between [2, 4), the mantissa part of the product of the two floating-point numbers needs to be shifted to the right, and the exponent part of the product of the two floating-point numbers needs to be incremented by 1.

[0023] If the two floating-point numbers are both non-normalized numbers, the actual result obtained by multiplying the binary mantissa parts of the two floating-point numbers is between [0, 1).

[0024] Based on the above processing process of the multiplication operation, the value range of the multiplication operation result exponent part should be If the exponent part is greater than the upper limit value of the floating-point exponent , it needs to be overflowed to infinity; if the exponent part is less than the lower limit value of the floating-point exponent , then the product decimal part needs to be left shifted and the product exponent part needs to be reduced. That is, after obtaining the product of the two floating-point numbers, the decimal part in the product needs to be shifted according to the shift bit number and the shift direction.

[0025] If the value of the exponent part of the result obtained by performing the multiplication operation on the exponent parts of the two floating-point numbers is in , and the result of the multiplication of the decimal parts is in , the decimal part of the multiplication result needs to be left shifted, and the exponent value is reduced after the left shift.

[0026] In the related art, the product of the two floating-point numbers is usually calculated first, then the product is analyzed for shifting to determine whether left shift or right shift is needed, and the product is left shifted or right shifted according to the determination result to obtain a shift result, and then it is analyzed whether the highest bit of the shift result is 1, and if it is 1, it is determined that the shift result overflows, and the exponent is incremented by 1. However, this method has a long processing period.

[0027] To solve the problems in the related art, an embodiment of the present application provides a floating-point multiplication method, which comprises: obtaining a first exponent of a first floating-point number and a second exponent of a second floating-point number; obtaining a to-be-shifted parameter for performing a to-be-shifted operation on the decimal part of the product of the first floating-point number and the second floating-point number according to the first exponent and the second exponent; the to-be-shifted parameter comprises a shift direction and a shift bit number; in the process of obtaining a shift result of the product according to the to-be-shifted parameter, obtaining overflow information of the decimal part of the shift result according to the to-be-shifted parameter; the overflow information comprises overflow or no overflow; adjusting the exponent of the shift result according to the overflow information to obtain a multiplication result of the first floating-point number and the second floating-point number. This embodiment reduces the exponent carry processing time and reduces the operation period of the floating-point multiplication operation.

[0028] The floating-point multiplication method provided by the embodiment of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] Figure 2 is a step flowchart of the floating-point multiplication method provided by an embodiment of the present application, as shown in Figure 2 , the method can comprise: Step 101, obtaining a first exponent of a first floating-point number and a second exponent of a second floating-point number.

[0030] The first floating-point number and the second floating-point number are floating-point numbers to be multiplied. The binary representation of the floating-point number comprises three parts, namely the sign part (sign), the exponent part (exp) and the mantissa part (frac). The calculation method and value range of each part of the floating-point number will be described by way of example as follows: The exponent part exp of the floating-point number can be normalized according to the following formula to obtain a normalized result of the exponent part exp of the floating-point number :

[0031] According to the expression, if the exponent exp of the floating-point number is 0, the normalized result of the exponent of the floating-point number is exp = 1; if the exponent exp of the floating-point number is not 0, the normalized result of the exponent of the floating-point number is exp .

[0032] In this step, the first exponent of the first floating-point number is obtained, including: obtaining the normalized result of the exponent exp of the first floating-point number , and determining the normalized result of the exponent of the first floating-point number as the first exponent of the first floating-point number. The second exponent of the second floating-point number is obtained, including: obtaining the normalized result of the exponent exp of the second floating-point number , and determining the normalized result of the exponent of the second floating-point number as the second exponent of the second floating-point number.

[0033] Step 102, according to the first exponent and the second exponent, obtaining a shift parameter for a decimal part of a product of the first floating-point number and the second floating-point number to be shifted.

[0034] The shift parameter includes a shift direction and a shift bit number.

[0035] For example, the shift bit number can include a left shift number and / or a right shift number, and the shift direction includes left shift or right shift.

[0036] For example, the shift parameter for the decimal part of the product of the first floating-point number and the second floating-point number to be shifted can be obtained according to the first exponent and the second exponent in the process of obtaining the product of the first floating-point number and the second floating-point number.

[0037] For example, the first number of leading zeros of the first floating-point number and the second number of leading zeros of the second floating-point number can be obtained, and the left shift number can be obtained according to the first exponent, the second exponent, the first number of leading zeros and the second number of leading zeros; and the right shift number can be obtained according to the first exponent and the second exponent.

[0038] Step 103, in the process of obtaining a shift result of the product according to the shift parameter, obtaining overflow information of the decimal part of the shift result according to the shift parameter.

[0039] The overflow information includes overflow or no overflow.

[0040] ​The product is shifted according to the to-be-shifted parameter, and a shift result is obtained.

[0041] In an example, the to-be-shifted operation includes a left shift operation, the shift direction in the to-be-shifted operation parameter is left shift, and the shift bit number is the left shift number. An initial shift mask with the highest bit being 1 can be obtained, and the initial shift mask is shifted according to the to-be-shifted operation parameter during the process of obtaining the product, to obtain a shift mask. The shift mask and the shift result of the product are subjected to an AND operation, to obtain overflow information corresponding to the left shift operation.

[0042] In an example, the to-be-shifted operation includes a right shift operation, the shift direction in the to-be-shifted operation parameter is right shift, and the shift bit number is the right shift number. The right shift number is used to obtain overflow information corresponding to the right shift operation.

[0043] In step 104, the exponent of the shift result is adjusted according to the overflow information, to obtain the multiplication result of the first floating-point number and the floating-point number.

[0044] In an example, if the overflow information is that the decimal part of the shift result overflows, or the third exponent of the product is not all 1, the third exponent of the product is subjected to a plus one operation to perform an exponent carry; if the overflow information is no overflow, or the third exponent is all 1, the third exponent is maintained unchanged.

[0045] The decimal part of the floating-point number generates a carry when performing multiplication, and the carry needs to be detected during the left shift operation and the right shift operation. In the related art, the product of the floating-point numbers is first obtained, and then the product is subjected to a left shift operation or a right shift operation to obtain a shift result, and then it is determined whether the highest bit of the shift result is 1. If the highest bit is 1, it is determined that the shift result overflows, and then the exponent of the shift result is subjected to a carry operation. However, this method needs to first obtain the product, then shift the product, and then analyze the value of the highest bit of the shift result. This processing method is slow, and the floating-point multiplication period is long.

[0046] In the embodiment of the present application, the first exponent of the first floating-point number and the second exponent of the second floating-point number are obtained. During the process of obtaining the product of the first floating-point number and the second floating-point number, the to-be-shifted parameter for performing a to-be-shifted operation on the decimal part of the product is obtained according to the first exponent and the second exponent. The to-be-shifted parameter includes a shift direction and a shift bit number. During the process of obtaining the shift result of the to-be-shifted operation on the decimal part of the product according to the to-be-shifted operation parameter, overflow information of the decimal part of the shift result is obtained. The exponent of the shift result is adjusted according to the overflow information, to obtain the multiplication result of the first floating-point number and the floating-point number. Compared with the method in the related art that obtains the shift result and then determines whether the exponent needs to be carried according to the detection result of the highest bit value of the shift result, the embodiment reduces the processing time of the exponent carry and reduces the operation period of the floating-point multiplication.

[0047] Referring to Figure 3 , the floating-point multiplication method of the embodiment can further include the following steps: Step 201, obtaining a first exponent of a first floating-point number and a second exponent of a second floating-point number.

[0048] The method of this step has been described in the foregoing step 101, and will not be repeated here.

[0049] Step 202, obtaining a to-be-shifted parameter for shifting the fractional part of the product according to the first exponent and the second exponent.

[0050] The to-be-shifted parameter includes a shift direction and a shift bit number.

[0051] The method of this step has been described in the foregoing step 102, and will not be repeated here.

[0052] Step 203, in the process of obtaining the shift result of the product according to the to-be-shifted parameter, obtaining an initial mask in the case where the shift direction is left shift and the shift bit number includes a left shift number.

[0053] The value of the highest bit of the initial mask is 1, and the values of the other bits are 0.

[0054] For example, obtaining a first bit number of the fractional part of the first floating-point number and a second bit number of the fractional part of the second floating-point number, obtaining a third bit number of the fractional part of the product of the first floating-point number and the second floating-point number according to the first bit number and the second bit number, and constructing the initial mask with the bit number equal to the third bit number and the value of the highest bit being 1.

[0055] For example, in the case where the shift direction is left shift, the initial mask is obtained according to the following method :

[0056] wherein, is a hot bit constant, and is obtained, and then is operated with the fractional part of the product, and then is reduced to determine whether the exponent needs to be incremented.

[0057] The bit width of the fractional part of the floating-point number is , and the bit width of the product is equal to the bit width of the fractional part of the product. The bit width of the fractional part of the floating-point number is related to the type of the floating-point number, and the correspondence between the type of the floating-point number and the bit width of the fractional part is shown in Table 1:

[0058] wherein, f64, f32 and f16 respectively represent a double-precision floating-point number, a single-precision floating-point number and a half-precision floating-point number.

[0059] According to the expression of the initial mask, the initial mask bit number is equal to , and the value of the highest bit is 1.

[0060] Step 204, according to the left shift number, the value of the highest bit of the initial mask is right shifted to obtain the shift mask.

[0061] For example, the initial mask is 10000000000000000000, and the left shift number is 2, then the shift mask obtained after shifting is 00100000000000000000.

[0062] For example, the first leading zero quantity of the decimal part of the first floating-point number and the second leading zero quantity of the decimal part of the second floating-point number are obtained, and the third leading zero quantity is obtained by performing an or operation on the first leading zero quantity and the second leading zero quantity; the left shift number corresponding to the decimal part of the product is obtained according to the third exponent and the third leading zero quantity.

[0063] For example, step 204 can include the following sub-steps: Sub-step A1, according to the first exponent and the second exponent, the third exponent of the product is obtained.

[0064] For example, the floating-point number types of the first floating-point number and the second floating-point number are the same, the exponent sum of the first exponent and the second exponent is obtained, and a preset exponent bias value corresponding to the floating-point number type of the first floating-point number and the second floating-point number is obtained; the exponent difference value between the exponent sum and the preset exponent bias value is determined as the third exponent.

[0065] For example, the third exponent can be obtained by the following method :

[0066] Wherein, is the first exponent, is the second exponent, is a preset exponent bias value corresponding to the floating-point number type of the first floating-point number and the second floating-point number.

[0067] Sub-step A2, if the third exponent is equal to zero, then according to the first shift value, the value of the highest bit of the initial mask is right shifted to obtain the shift mask.

[0068] Wherein, the first shift value is equal to the sum of the left shift number and 1.

[0069] For example, if the third exponent is equal to zero, the initial mask can be shifted to the left by the left shift number, and then shifted to the right by one bit, to obtain the shift mask; or the initial mask can be shifted to the right by one bit first, and then shifted to the left by the left shift number, to obtain the shift mask; or the initial mask can be directly shifted to the right by the first shift value, to obtain the shift mask.

[0070] For example, the shift mask can be obtained according to the following method :

[0071] According to the expression, if the third exponent of the product is equal to 0, the initial mask is shifted to the right by , and then shifted to the right by one bit.

[0072] In sub-step A3, if the third exponent is not equal to zero, the initial mask is shifted to the right by the left shift number, to obtain the shift mask.

[0073] In this embodiment, if the third exponent is equal to zero, the initial mask is shifted to the left by the left shift number, and then shifted to the right by one bit, to obtain the shift mask; otherwise, the initial mask is directly shifted to the left by the left shift number, to obtain the shift mask. Based on the shift mask, the subsequent overflow analysis can ensure the accuracy of the obtained overflow information.

[0074] In step 205, the shift mask and the product are subjected to AND operation, to obtain an AND operation result.

[0075] For example, the AND operation result can be obtained according to the following method .

[0076] For example, the number of bits of the shift mask is equal to the number of bits of the decimal part of the product; and step 205 can include the following sub-steps: In sub-step B1, the shift mask and the product are subjected to AND operation, to obtain an initial AND operation result.

[0077] The shift mask and the product are both in binary format, and the shift mask and the product are subjected to bit-by-bit AND operation, to obtain the initial AND operation result.

[0078] For example, if the shift mask is 00100000000000000000 and the product is 11100000001010000000, the initial AND operation result obtained by the AND operation is 1.

[0079] In sub-step B2, the data from the highest bit to the first bit of the initial AND operation result is intercepted, to obtain the AND operation result. ​​

[0080] The total number of bits from the highest bit of the initial and operation results to the first position is equal to the mantissa bit width of the preset floating-point number type.

[0081] When the product is left-shifted, the maximum number of left-shifted bits is equal to the mantissa width. In this embodiment, it is not necessary to analyze all the bits of the initial AND operation result, but to intercept part of the data and determine the intercepted part of the data as the AND operation result.

[0082] In this step, the AND operation result is obtained by intercepting the high bit to the low bit from the initial AND operation result. For example, the AND operation result can be obtained according to the following method: :

[0083] in,( ) The corresponding bit is the high bit, The corresponding bit is the low bit.

[0084] In this embodiment, an AND operation is performed on the initial mask and the product to obtain an initial AND result. The maximum number of left shift bits is equal to the mantissa width, so the data from the most significant bit to the first position of the initial AND result is truncated to obtain the AND result. This method not only retains the valid portion of the initial AND result that can reflect overflow information, but also truncates data that is not useful for overflow determination, thereby reducing the amount of data to be processed and improving processing efficiency.

[0085] Step 206: Obtain overflow information of the decimal part of the left shift result according to the AND operation result.

[0086] For example, an OR reduction operation is performed on the AND operation result to obtain an OR reduction operation result, and overflow information is obtained based on the OR reduction operation result.

[0087] For example, the product is 00.1100, the constructed initial mask is 100000, the shift direction for the product is left, and the number of left shifts is 2. Then the initial mask is shifted right by two bits, and the resulting shift mask is 001000. The shift mask and the product are ANDed, and the result of the AND operation is 001000.

[0088] Performing an OR operation on the AND result 001000 yields a result of 1, indicating that the overflow information corresponding to the left shift operation is overflow. Shifting the product 00.1100 left by two bits yields 11.0000, indicating an overflow. This embodiment demonstrates that the method of this embodiment accurately obtains overflow information for the shift result of the product.

[0089] In the embodiment, an initial mask is obtained, the highest bit of the initial mask is 1, and the other bits are 0. In the process of obtaining the product, the highest bit of the initial mask is shifted left according to the left shift number to obtain a shifted mask, and then the shifted mask and the product are subjected to an AND operation to obtain an AND operation result. According to the AND operation result, the overflow information of the shift result corresponding to the left shift operation can be accurately obtained.

[0090] In addition, in the process of obtaining the product, the overflow information is obtained in the embodiment, and it is not necessary to perform a shift operation on the product after the product is obtained, and then analyze the judgment result of whether the highest bit of the shift result is 1 to obtain the overflow information. In other words, the method for obtaining the overflow information in the embodiment can be executed in parallel with the method for obtaining the product, the time for obtaining the overflow information is shortened, and then the time for performing the exponential carry based on the overflow information is shortened, and the operation period of the floating point multiplication operation is shortened.

[0091] Step 206 includes sub-step C1 to sub-step C2: Sub-step C1, performing an OR reduction operation on the AND operation result to obtain an OR reduction operation result.

[0092] For example, the OR reduction operation result is obtained according to the following method :

[0093] Wherein,.orR represents the OR reduction operation.

[0094] Sub-step C2, obtaining the overflow information of the decimal part of the shift result according to the OR reduction operation result.

[0095] The overflow information obtained in the sub-step is the overflow information corresponding to the decimal part of the left shift result.

[0096] In the embodiment, the OR reduction operation is performed on the AND operation result to obtain the OR reduction operation result; the AND operation result can include multiple bits of data, and only in the case that the overflow information is overflow, the AND operation result includes a bit with a value of 1, and the bit number is the same as the bit number equal to 1 in the shift code; otherwise, in the case that the overflow information is not overflow, the data of each bit of the AND operation result is 0. The OR reduction operation can determine whether the AND operation result includes a value of 1, and therefore, in the embodiment, according to the OR reduction operation result of the OR reduction operation performed on the AND operation result, the overflow information of the product can be quickly and accurately obtained.

[0097] For example, sub-step C2 can include the following sub-step: Sub-step C21, obtaining a third exponent of the product according to the first exponent and the second exponent.

[0098] Sub-step C22, according to the third exponent, obtaining the first overflow information of the shift result; For example, sub-step C22 can include sub-step C221 to sub-step C223: Sub-step C221, obtaining the first number of leading zeros of the first floating-point number, and the second number of leading zeros of the second floating-point number.

[0099] For example, if the first exponent of the first floating-point number is equal to zero, obtaining the first splicing result obtained by splicing 0 and the mantissa of the first floating-point number, and determining the number of leading zeros of the first splicing result as the first number of leading zeros of the first floating-point number; if the first exponent of the first floating-point number is not equal to zero, determining the first number of leading zeros of the first floating-point number as zero. Wherein, the splicing operation of 0 and the mantissa of the first floating-point number is , and the obtained splicing result is . .

[0100] If the second exponent of the second floating-point number is equal to zero, obtaining the second splicing result obtained by splicing 0 and the mantissa of the second floating-point number, and determining the number of leading zeros of the second splicing result as the second number of leading zeros of the second floating-point number; if the second exponent of the second floating-point number is not equal to zero, determining the second number of leading zeros of the second floating-point number as zero. Wherein, the splicing operation of 0 and the mantissa of the second floating-point number is , and the obtained splicing result is . .

[0101] Sub-step C222, according to the first number of leading zeros and the second number of leading zeros, obtaining the third number of leading zeros of the product; For example, performing an or operation on the first number of leading zeros and the second number of leading zeros to obtain the third number of leading zeros; or performing an addition operation on the first number of leading zeros and the second number of leading zeros to obtain the third number of leading zeros.

[0102] Sub-step C223, according to the comparison result of the third exponent and the third number of leading zeros, obtaining the first overflow information of the shift operation on the decimal part of the product.

[0103] For example, if the third exponent is less than the third number of leading zeros, determining that the first overflow information is no overflow; otherwise, determining that the first overflow information is overflow.

[0104] For example, the first overflow information is obtained according to the following method :

[0105] According to the expression, if the third exponent is less than the third number of leading zeros , then the first overflow information is determined as not overflow; otherwise, the first overflow information is determined as overflow. In the expression, is a condition that will not overflow when calculating the left shift value. In the process, 1 bit is needed to record the case that the multiplication of the decimal part will not overflow when the left shift operation is performed.

[0106] In the embodiment, the first number of leading zeros of the first floating point number and the second number of leading zeros of the second floating point number are obtained, and the third number of leading zeros of the product is obtained according to the first number of leading zeros and the second number of leading zeros. The embodiment does not need to obtain the product between the first floating point number and the second floating point number first, and the leading zero detection is performed on the product to obtain the third number of leading zeros, thereby shortening the period of obtaining the third number of leading zeros. The third exponent is reduced by 1 for each left shift, and if the product is shifted according to the number of left shifts when the third exponent is less than the third number of leading zeros, overflow will occur, otherwise, overflow will not occur. According to the third exponent and the third number of leading zeros, the first overflow information obtained according to the analysis of the exponent can be quickly and accurately obtained.

[0107] In sub-step C23, if the result of the or reduction operation is 1 and the first overflow information is overflow, it is determined that the overflow information of the decimal part of the shift result of the left shift is overflow.

[0108] The first overflow information is the overflow information obtained according to the exponent of the product.

[0109] In sub-step C24, if the result of the or reduction operation is 0 or the first overflow information is not overflow, it is determined that the overflow information of the decimal part of the shift result is not overflow.

[0110] The overflow information is the overflow information of the decimal part of the shift result of the left shift.

[0111] For example, the overflow information of the product can be obtained according to the following method :

[0112] In the embodiment, the first overflow information of the shift result of the shift operation on the decimal part of the product is obtained according to the third exponent. If the result of the or reduction operation is 1, it is determined that the overflow information determined according to the shift mask is overflow. If the result of the or reduction operation is 1 and the first overflow information is overflow, it can be accurately determined that the overflow information of the shift result of the product is overflow. If the result of the or reduction operation is 0 or the first overflow information is not overflow, it can be accurately determined that the overflow information of the shift result of the product is not overflow. Otherwise, through the double judgment of the result of the or reduction operation analysis and the first overflow information, it can be accurately determined that the overflow information of the shift result of the product is overflow.

[0113] Step 207, in the process of obtaining the shift result of the product according to the parameter to be shifted, when the shift direction includes right shifting and the number of shift bits includes the right shift value, if the value of the highest bit of the decimal part of the product is equal to 1 and the number of right shift bits is equal to 1, it is determined that the decimal part of the shift result of the right shift overflows.

[0114] Obtain a comparison result of the right shift number and 1, perform an AND operation on the comparison result and the value of the most significant bit of the decimal part of the product, and obtain overflow information of the decimal part of the right shift result. The comparison result includes: whether the right shift number is equal to 1 or not equal to 1.

[0115] Step 208: If the value of the most significant bit of the decimal part of the product is equal to 0, or the number of right shifts is not equal to 1, then determine that the decimal part of the shifted result does not overflow.

[0116] If the right shift number is equal to 1, that is , if the value of the highest bit of the decimal part of the product is 1, the result of the AND operation of the two is 1, otherwise the result of the AND operation of the two is 0. In this embodiment, based on the comparison result of whether the right shift number is 1 and the AND operation of the highest bit of the decimal part of the product, overflow information of the decimal part of the shift result can be quickly and accurately obtained.

[0117] Carry detection during right shift, only by shifting right 1 bit can the index be carried. is equal to 0, It is possible to carry to the exponent only when it is greater than 1 after shifting right by one bit, and it is possible to carry to the exponent only when it is greater than or equal to two bits after shifting right by one bit. After the shift, the value is less than 1, and it is impossible to carry to the exponent. For example, the overflow information can be obtained according to the following method :

[0118] in, Indicates the value of the most significant decimal place of the product. If Equal to 1, indicating Greater than 2; otherwise, Not greater than 2.

[0119] According to this expression, the product of bitwise AND the number of right shifts ( ) performs a logical AND operation. If the result is 1, it means that dMul is greater than 2 and the number of right shifts is equal to 1. In this case, it means that the product overflowed. If the value of the highest bit of the decimal part of the product is not equal to 1, it means Not greater than 2, then No overflow.

[0120] In the case of right shift, only right shift 1 bit can cause the exponent to carry. Because the condition of right shift operation is that the third exponent of the product Therefore, in the case of right shift, the third exponent of the product equals 0, and the right shift number equals 1, the exponent can carry. In the case of right shift number greater than or equal to 2, after the product is right shifted by 2 bits, the shift result is less than 1, so the exponent cannot carry any more. Therefore, if the shift number is not equal to 1, the overflow information is not overflow.

[0121] In other words, if the value of the highest bit of the decimal part of the product is not equal to 1, or the shift number is not equal to 1, it is determined that the overflow information is not overflow.

[0122] Every time the product is right shifted by 1 bit, the third exponent of the product increases by 1, and the third exponent of the product increases from a negative number to 0. In this embodiment, the right shift value and the value of the highest bit of the decimal part of the product are ANDed. If the right shift value is 1, the value of the highest bit of the decimal part is 1, and the third exponent of the product is 0, if the product is right shifted by 1 bit, the shift result will overflow, that is, the overflow information is overflow; otherwise, it can be determined that the shift result is not overflow. Based on this embodiment, the overflow information can be accurately obtained when the shift direction is right shift and the shift number is the right shift value.

[0123] In step 209, if the overflow information is not overflow, or the value of each bit of the third exponent of the product is 1, the exponent is kept unchanged.

[0124] For example, the method for obtaining the overflow information may include:

[0125] According to the expression, it is determined whether the product satisfies the left shift condition. If the left shift condition is satisfied, and the overflow information corresponding to the left shift operation is overflow, it is determined that the overflow information of the product is overflow. If the left shift condition is not satisfied, and the overflow information corresponding to the right shift operation is overflow, it is determined that the overflow information of the product is overflow. Except for these two cases, it is determined that the overflow information of the product is not overflow.

[0126] In step 210, if the overflow information is overflow, and the value of at least one bit of the third exponent of the product is equal to 0, the exponent is incremented by 1.

[0127] For example, according to the value of , the value of or is selected, and special cases are considered, such as is all 1, the exponent carry result is obtained, for example, according to the following method:

[0128] In the embodiment, if the overflow information is not overflow, or the value of each digit in the third exponent of the product is 1, it indicates that the third exponent will overflow to infinity if a carry occurs, and thus the exponent is kept unchanged. If the overflow information is overflow, and the value of at least one digit in the third exponent of the product is equal to 0, it indicates that the decimal part of the result of the shifting of the product overflows, and the third exponent has room for a carry, and thus the exponent is incremented. Based on the embodiment, the carry of the exponent of the product can be accurately processed, and the entire processing process does not need to be based on the result of the shifting of the product, and the carry analysis of the exponent can be processed in parallel with the process of obtaining the product, which shortens the processing time and reduces the operation period of the floating-point multiplication operation.

[0129] The method further includes the following steps: In step 210, a first mantissa of the first floating-point number and a second mantissa of the second floating-point number are obtained.

[0130] In step 211, a first partial product of the first mantissa and the second mantissa is obtained.

[0131] For example, the first partial product of the first mantissa and the second mantissa can be obtained by using the Booth encoding method. For example, the first partial product of the first mantissa and the second mantissa can be obtained by using the Radix-4 method.

[0132] In step 212, the first partial product is compressed to obtain a first compression result, and a second partial product of the first implicit bit of the first floating-point number and the second implicit bit of the second floating-point number is obtained in the process of compressing the first partial product.

[0133] For example, the partial product is compressed by using a carry-save adder compression (CSA).

[0134] In step 213, a product of the first floating-point number and the second floating-point number is obtained according to the first compression result and the second partial product.

[0135] After the partial product is generated by using the Booth encoding, the CSA can be used to compress all the partial products into two partial products, and then the two compressed partial products are added to obtain the product of the first floating-point number and the second floating-point number.

[0136] In the related art, the method for obtaining the product of the floating-point numbers is as shown in Figure 4 In the timing optimization in the slow Booth encoding, the calculation of the implicit bit needs the or reduction of the exponent bit to be calculated, and the result of each partial product is affected by the implicit bit, and thus the time for generating the partial product is slow, which causes the slow start of the CSA compression.

[0137] In this embodiment, referring to Figure 4 First, the implicit bit is removed to generate the partial product and CSA compression begins directly. CSA compression requires multiple stages. During CSA compression, the implicit bit is calculated and the partial product of two implicit bits is added. This is combined with the partial product after several stages of CSA compression before further compression. This allows for timing optimization during Booth encoding.

[0138] For example, refer to Figure 5 Taking f64 as an example, the decimal part is 53 bits and the mantissa part is 52 bits. If the decimal part is directly fast-Booth-encoded, 27 partial products will be generated. If the mantissa part is Booth-encoded first, 27 partial products will also be generated. The subsequent implicit bits will add 2 partial products, for a total of 29 partial products.

[0139] In this embodiment, a first mantissa of a first floating-point number and a second mantissa of a second floating-point number are obtained, a first partial product is obtained based on the first mantissa and the second mantissa, the first partial product is compressed to obtain a first compression result, and in the process of compressing the first partial product, a second partial product of a first implicit bit of the first floating-point number and a second implicit bit of the second floating-point number is obtained, the product of the first floating-point number and the second floating-point number is obtained based on the first compression result and the second partial product, the implicit bit is calculated while compressing and the partial product of two implicit bits is added, and the partial product is combined with the compressed partial product and then further compressed. Thus, the time for obtaining the product can be shortened, and the operation cycle of the floating-point multiplication operation can be shortened.

[0140] Figure 5 and Figure 6 In the compression process shown, CSA uses the CSA3_2 compressor to compress three operands into two operands. In this embodiment, during the processing of the last four partial products, the first-level CSA4_2 compressor is used to replace the CSA3_2 compressor for compression processing to achieve timing optimization.

[0141] according to Figure 6 In the illustrated embodiment, in the process of calculating the product of double-precision floating-point numbers, the optimized fast Booth encoding time will exceed the time of the first-level CSA3_2. The method of this embodiment has a positive benefit in timing and realizes the timing optimization of obtaining the product of floating-point numbers.

[0142] For example, the decimal parts of the first floating point number and the second floating point number may be directly multiplied using the multiplication sign “*”, and then the product is output to the synthesizer for optimization.

[0143] Figure 7 This is a flowchart of the specific steps of a floating-point multiplication method provided in an embodiment of the present application.Figure 7 The method can include: Step S1, performing sign processing on a first sign of the first floating-point number and a second sign of the second floating-point number to obtain a sign result.

[0144] The sign of the product is obtained according to the following formula .

[0145] Step S2, performing sign processing on a first exponent of the first floating-point number and a second exponent of the second floating-point number to obtain an exponent of the product of the first floating-point number and the second floating-point number before the product is processed by shifting.

[0146] Step S3, calculating a to-be-shifted value of a decimal part of the product of the first floating-point number and the second floating-point number.

[0147] The to-be-shifted value of the product of the first floating-point number and the second floating-point number is obtained according to the following formula:

[0148]

[0149]

[0150] wherein, and are a left shift number and a right shift number respectively, the data from the bit number to the lowest bit of the to-be-shifted value of the product of the first floating-point number and the second floating-point number is taken as , and the data from the bit number to the lowest bit of the to-be-shifted value of the product of the first floating-point number and the second floating-point number is taken as . If the determined shift direction is left shift, the final shift number , otherwise, . Step S4, obtaining a decimal multiplication result of the product of the first floating-point number and the second floating-point number.

[0151] Step S5, obtaining a special result of the multiplication operation on the special number when the first floating-point number and / or the second floating-point number is a special number.

[0152] The steps S1 to S5 can be processed in parallel, so that the processing implementation can be saved and the processing period of the floating-point number multiplication operation can be reduced.

[0153] The steps S1 to S5 can be processed in parallel, so that the processing implementation can be saved and the processing period of the floating-point number multiplication operation can be reduced.

[0154] ​Optionally, the first exponent of the first floating point number and the second exponent of the second floating point number are obtained; in the process of calculating the product of the first floating point number and the second floating point number, the to-be-shifted parameter for shifting the decimal part of the product is obtained according to the first exponent and the second exponent; the to-be-shifted parameter comprises a shift bit number and a shift direction; the decimal part of the product is shifted according to the shift bit number and the shift direction, to obtain the multiplication result of the first floating point number and the second floating point number.

[0155] Optionally, the to-be-shifted parameter for shifting the decimal part of the product is obtained according to the first exponent and the second exponent, comprising: the third exponent of the product is obtained according to the first exponent of the first floating point number and the second exponent of the second floating point number; the shift bit number corresponding to the decimal part of the product is obtained according to the third exponent.

[0156] Optionally, in the case that the shift bit number comprises a left shift bit number, the shift bit number corresponding to the decimal part of the product is obtained according to the third exponent, comprising: the first leading zero quantity of the decimal part of the first floating point number and the second leading zero quantity of the decimal part of the second floating point number are obtained; the third leading zero quantity is obtained by performing an OR operation on the first leading zero quantity and the second leading zero quantity; the left shift bit number corresponding to the decimal part of the product is obtained according to the third exponent and the third leading zero quantity.

[0157] Optionally, the left shift bit number corresponding to the decimal part of the product is obtained according to the third exponent and the third leading zero quantity, comprising: if the third leading zero quantity is less than the third exponent, the third leading zero quantity is determined as the left shift bit number; if the third leading zero quantity is greater than or equal to the third exponent, the difference between the third exponent and the first preset exponent is determined as the left shift bit number.

[0158] Optionally, the first leading zero quantity of the decimal part of the first floating point number and the second leading zero quantity of the decimal part of the second floating point number are obtained, comprising: if the first exponent of the first floating point number is equal to zero, the first splicing result obtained by splicing zero and the mantissa of the first floating point number is obtained, and the leading zero quantity of the first splicing result is determined as the first leading zero quantity of the decimal part of the first floating point number; if the first exponent of the first floating point number is not equal to zero, the first leading zero quantity of the decimal part of the first floating point number is determined as zero; if the second exponent of the second floating point number is equal to zero, the second splicing result obtained by splicing zero and the mantissa of the second floating point number is obtained, and the leading zero quantity of the second splicing result is determined as the second leading zero quantity of the decimal part of the second floating point number; if the second exponent of the second floating point number is not equal to zero, the second leading zero quantity of the decimal part of the second floating point number is determined as zero.

[0159] Optionally, in the case that the shift number includes a right shift number, the shift number corresponding to the decimal part of the product is obtained according to the third index, including: determining the difference between the second preset index and the third index as the right shift number corresponding to the decimal part of the product.

[0160] Optionally, the to-be-shifted parameter for the shift operation on the decimal part of the product is obtained according to the first index and the second index, including: obtaining the third index of the product according to the first index of the first floating-point number and the second index of the second floating-point number; if the third index is greater than zero, determining that the shift direction is left shift; if the third index is less than or equal to zero, determining that the shift direction is right shift.

[0161] Optionally, the first index of the first floating-point number and the second index of the second floating-point number are obtained, including: if the first floating-point number and the second floating-point number both belong to the first digital type, obtaining the first index of the first floating-point number and the second index of the second floating-point number; wherein the first digital type includes other digital types except the second digital type, and the second digital type includes: zero, non-number, and infinite number.

[0162] Optionally, the method further includes: if the first floating-point number and / or the second floating-point number belongs to the second digital type, obtaining the multiplication result of the first floating-point number and the second floating-point number according to the multiplication operation strategy corresponding to the second digital type; the second digital type includes: zero, non-number, and infinite number; wherein the multiplication operation strategy includes: if the first floating-point number and / or the second floating-point number is non-number, determining that the multiplication result of the first floating-point number and the second floating-point number is equal to a preset value; if the first floating-point number and the second floating-point number are both zero, or one of the first floating-point number and the second floating-point number is zero and the other is a digital type other than non-number and infinite, determining that the multiplication result of the first floating-point number and the second floating-point number is equal to zero; if the first floating-point number and the second floating-point number are both infinite numbers, or one of the first floating-point number and the second floating-point number is infinite and the other is a digital type other than non-number and zero, determining that the multiplication result of the first floating-point number and the second floating-point number is equal to infinite.

[0163] Optionally, the first index of the first floating-point number is obtained, including: obtaining a first initial index of the first floating-point number; if the first initial index is equal to zero, determining that the first index of the first floating-point number is equal to 1; if the first initial index is not equal to zero, determining that the first index of the first floating-point number is equal to the first initial index; the second index of the second floating-point number is obtained, including: obtaining a second initial index of the second floating-point number; if the second initial index is equal to zero, determining that the second index of the second floating-point number is equal to 1; if the second initial index is not equal to zero, determining that the second index of the second floating-point number is equal to the first initial index.

[0164] Step S6, according to the value to be shifted and the decimal multiplication result, carry detection is performed.

[0165] According to the method of any one of the preceding embodiments, according to the value to be shifted and the decimal multiplication result, carry detection is performed.

[0166] Step S7, according to the carry detection result and the exponent before the product is subjected to the shift processing, first exponent carry processing is performed.

[0167] Step S8, according to the value to be shifted and the decimal multiplication result, decimal shift is performed.

[0168] Steps S6 to S8 can be processed in parallel, thereby processing implementation can be saved and the processing period of the floating-point multiplication operation can be reduced.

[0169] The method of carry detection is as described in any one of the preceding embodiments, which will not be repeated here.

[0170] Step S9, after the decimal shift, mantissa rounding is performed to obtain the mantissa of the product.

[0171] Step S10, according to the first exponent carry processing and the decimal rounding result, second exponent carry processing is performed on the result after the mantissa rounding to obtain the exponent of the product after the shift operation.

[0172] Step S11, according to the sign, the exponent and the mantissa of the product, the mantissa, the product of the first floating-point number and the second floating-point number is obtained, which is the normal result.

[0173] Step S12, according to the mantissa of the product, the mantissa rounding result and the special result, the identification bit is obtained.

[0174] Step S13, according to the normal result and the special result, the final multiplication result of the first floating-point number and the second floating-point number is obtained.

[0175] Optionally, the shift result of the product of the first floating-point number and the second floating-point number is obtained; the shift result is the result of the shift operation on the decimal part of the product; the mantissa rounding operation is performed on the shift result to obtain the mantissa rounding result of the shift result; in the process of the mantissa rounding operation, the first judgment result of whether the mantissa of the shift result satisfies the first preset rounding condition is obtained; if the first judgment result is that the mantissa satisfies the first preset rounding condition, the target mantissa of the multiplication result of the first floating-point number and the second floating-point number is obtained according to the mantissa rounding result.

[0176] Optionally, the first judgment result of whether the mantissa satisfies the first preset rounding condition is obtained, including: obtaining a first parameter of the shift result; the first parameter includes at least one of the following: a value of the first reserved bit of the shift result, a value of the first rounding bit, and a value of the first sticky bit; and the first judgment result of whether the mantissa satisfies the first preset rounding condition is obtained according to the first parameter.

[0177] Optionally, in the case where the shift operation includes a right shift operation, the value of the first sticky bit is obtained, including: obtaining a shift mask; data of the shift mask from a second position to a lowest bit of the shift mask is 1, and data of other bits of the shift mask is 0; a total number of bits from the second position to the lowest bit of the shift mask is equal to a right shift number of the decimal part of the product subjected to the right shift operation; obtaining first data from a third position of the decimal part of the product to a lowest bit of the product; and a total number of bits from the third position to the lowest bit of the product is equal to a difference between the total width corresponding to the preset floating-point number type and 1. The shift mask and the first data are subjected to an AND operation to obtain an AND operation result; and the AND operation result is subjected to an OR reduction operation to obtain the value of the first sticky bit corresponding to the right shift operation.

[0178] Optionally, the shift result is subjected to a mantissa rounding operation to obtain a mantissa rounding result of the shift result, including: the preset mantissa is subjected to the mantissa rounding operation to obtain the mantissa rounding result of the shift result; wherein, if the shift result satisfies a first condition, the preset mantissa includes: data of the shift result from a fourth position to a lowest bit; and a total number of bits from the fourth position to the lowest bit of the shift result is equal to a sum of a mantissa bit width corresponding to the preset floating-point number type and 1; and the first condition includes: the shift operation is a left shift operation, the decimal part of the product overflows, and the exponent of the product is not equal to 0; if the shift result does not satisfy the first condition, the preset mantissa includes: a zero padding result of data of the shift result from a fifth position to a lowest bit subjected to a low-bit zero padding operation; and a total number of bits from the fifth position to the lowest bit of the shift result is equal to the mantissa bit width corresponding to the preset floating-point number type.

[0179] Optionally, the shift result is subjected to a mantissa rounding operation to obtain a mantissa rounding result of the shift result, including: data of the preset mantissa from a highest bit to a sixth position is subjected to a plus 1 operation to obtain the mantissa rounding result of the shift result; wherein, a total number of bits from the highest bit of the preset mantissa to the sixth position is equal to a mantissa width of the preset floating-point number type.

[0180] Optionally, the method further includes: if the first judgment result is that the mantissa does not satisfy the first preset rounding condition, obtaining a target mantissa of a multiplication result of the first floating-point number and the second floating-point number according to the preset mantissa.

[0181] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information is not overflow, and the first determination result is that the mantissa does not satisfy the first preset rounding condition, the method further comprises: determining the data from the highest bit to the sixth bit of the preset mantissa as the target mantissa of the multiplication result of the first floating-point number and the second floating-point number; and the total number of bits between the highest bit and the sixth bit of the preset mantissa is equal to the mantissa width of the preset floating-point number type.

[0182] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information is not overflow, and the first determination result is that the mantissa satisfies the first preset rounding condition, the method further comprises: obtaining the target mantissa of the multiplication result of the first floating-point number and the second floating-point number according to the mantissa rounding result, comprising: determining the mantissa rounding result as the target mantissa of the multiplication result.

[0183] Optionally, the method further comprises: obtaining the overflow information of the exponent of the shift result; if the overflow information is overflow, the preset target mantissa is determined as the target mantissa of the multiplication result; wherein if the preset rounding mode is a rounding mode other than the rounding mode to zero, the rounding mode for positive numbers to down and the rounding mode for negative numbers to up, the total number of bits of the preset target mantissa is equal to the mantissa bit width corresponding to the preset floating-point number type, and each bit value is 0; if the preset rounding mode is the rounding mode to zero, the rounding mode for positive numbers to down or the rounding mode for negative numbers to up, the total number of bits of the preset target mantissa is equal to the mantissa bit width corresponding to the preset floating-point number type, and each bit value is 1.

[0184] Optionally, the method further comprises: obtaining the exponent of the shift result, and performing an exponent carry operation on the exponent of the shift result to obtain an exponent carry result; in the process of performing the exponent carry operation, obtaining a second determination result of whether the exponent of the shift result satisfies a first preset carry condition; if the second determination result is that the exponent satisfies the first preset carry condition, obtaining the target exponent of the multiplication result of the first floating-point number and the second floating-point number according to the exponent carry result; if the second determination result is that the exponent does not satisfy the first preset carry condition, obtaining the target exponent of the multiplication result of the first floating-point number and the second floating-point number according to the exponent.

[0185] Optionally, the second determination result of whether the exponent of the shift result satisfies the first preset carry condition comprises: if the mantissa of the shift result satisfies the first preset rounding condition, and the value of each bit of the preset mantissa of the shift result from the highest bit to the sixth bit is 1, it is determined that the second determination result is that the exponent of the shift result satisfies the first preset carry condition; the total number of bits between the highest bit and the sixth bit of the preset mantissa is equal to the mantissa width of the preset floating-point number type; if the mantissa of the shift result does not satisfy the first preset rounding condition, or the value of any bit of the preset mantissa of the shift result from the highest bit to the sixth bit is 0, it is determined that the second determination result is that the exponent of the shift result does not satisfy the first preset carry condition.

[0186] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information is an overflow, determining the preset target exponent as the target exponent of the multiplication result; wherein if the preset rounding mode is a rounding mode other than the rounding to zero mode, rounding down for positive numbers and rounding up for negative numbers, the preset target exponent is an exponent with a total bit number equal to the exponent bit width of the preset floating-point number and each bit value being equal to 1; if the preset rounding mode is the rounding to zero mode, rounding down for positive numbers or rounding up for negative numbers, the preset target exponent is an exponent with a total bit number equal to the exponent bit width of the preset floating-point number, the value of the lowest bit being 0 and the values of the other bits being 1.

[0187] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information is not an overflow and the second determination result is that the exponent satisfies the first preset carry condition, obtaining the multiplication result of the first floating-point number and the second floating-point number according to the exponent carry result, including: determining the exponent carry result as the target exponent of the multiplication result; if the overflow information is not an overflow and the second determination result is that the exponent does not satisfy the first preset carry condition, obtaining the multiplication result of the first floating-point number and the second floating-point number according to the exponent, including: determining the exponent of the shift result as the target exponent of the multiplication result.

[0188] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information of the exponent is an overflow, determining the sign bit of the multiplication result as an overflow; if the shift result satisfies any one of the second conditions, determining the sign bit of the multiplication result as an inaccuracy; the second conditions include: the overflow information is an overflow, the shift result first rounding bit, and the value of the first sticky bit is 1; if the exponent of the product is equal to 0 and the exponent of the shift result does not satisfy the preset second carry condition and the shift result satisfies any one of the second conditions, determining the sign bit of the multiplication result as an underflow.

[0189] Optionally, the method further comprises: if the values of the exponent from the highest bit to the first bit are all 1 and the exponent satisfies the third condition, determining the overflow information as an overflow; the third condition includes: the value of the lowest bit of the exponent is 1 or the exponent satisfies the first preset carry condition; if the shift result does not satisfy the third condition, determining that the exponent of the shift result does not satisfy the preset second carry condition, and the third condition includes: the data of the preset tail number of the shift result from the highest bit to the sixth bit are all 1, the value of the second reserved bit of the shift result is 1, and the tail number of the shift result satisfies the second preset rounding condition.

[0190] Optionally, the method further comprises: obtaining a second parameter of the shift result; the second parameter comprises at least one of: a value of a second reserved bit of the shift result, a value of a second rounding bit, and a value of a second sticky bit; obtaining a third judgment result of whether the mantissa satisfies a second preset rounding condition according to the second parameter; the value of the second reserved bit is a value of the preset mantissa at a seventh position; a position interval between the seventh position and a lowest bit of the mantissa is equal to a sum of a mantissa bit width of the preset floating-point number type and 1; the value of the second rounding bit is a value of the preset mantissa at an eighth position; a total bit number from the eighth position to the lowest bit of the preset mantissa is equal to the mantissa bit width of the preset floating-point number type; in a case where the shift operation is left shift, the value of the second sticky bit is an or reduction operation result of data of the preset mantissa from a ninth position to the lowest bit; a total bit number from the ninth position to the lowest bit of the preset mantissa is equal to a difference between the mantissa bit width of the preset floating-point number type and 1; in a case where the shift operation is right shift, the value of the second sticky bit is equal to a value of a first sticky bit corresponding to the right shift operation.

[0191] By the embodiment, the problem of long processing period caused by serial processing of each part of the floating-point number is avoided, and the method of obtaining the shift value in step S6 can be implemented by referring to any method of the foregoing embodiments. In the related art, three periods are required to calculate the product of the half-precision floating-point number, the product of the single-precision floating-point number, and the product of the double-precision floating-point number. Based on the embodiment, the processing time can be shortened, and the operation period of the half-precision floating-point number product and the single-precision floating-point number product can be shortened to two. For the multiplication operation of the double-precision floating-point number, the operation can be completed in a half period of the third period, that is, based on the embodiment, the number of periods of the floating-point multiplication operation can be shortened.

[0192] In one embodiment, referring to Figure 8 For the multiplication operation of the double-precision floating-point number (f64), the operation can be processed in three periods. The first period is used to perform steps S1 to S5 in parallel and store the processing results in the corresponding register 1. The second period is used to obtain the data of steps S6 to S8 and store the data in the corresponding register 2. Steps S9 to S13 are performed in the third period. Based on the method of the embodiment, the result is calculated in a half period of the third period, and the data can be bypassed to other functional units for fast wake-up.

[0193] Continuing to refer to Figure 8 The decimal multiplication is implemented by using the fast Booth and set compression method, the partial product is stored in the register 1, the partial product is added to obtain the product, and then the decimal shift operation of step S8 is performed on the product. The set compression method is the carry-saved adder (CSA) method.

[0194] In one embodiment, referring to Figure 9 For multiplication of half-precision floating-point numbers (f16) and single-precision floating-point numbers (f32), the operation period can be shortened to two periods. The first period is used to perform steps S1-S5 in parallel and store the processing results in the respective corresponding registers Reg; and the second period is used to perform steps S6-S13. Based on the method of the embodiment, the second period is completed in half a period, and the data can be bypassed to other functional units for fast wake-up.

[0195] In combination with Figure 8 and Figure 9 , the difference between the two processing methods is that, Figure 9 The embodiment can calculate the product of floating-point numbers by multiplication, Figure 8 The embodiment shown in the figure obtains the product of floating-point numbers by the fast Booth and CSA compression method.

[0196] It should be noted that f64 can also be implemented by the two-period processing method shown in Figure 9 f32 and f16 can also be implemented by the three-period processing method shown in Figure 8 .

[0197] The embodiment optimizes the timing of the floating-point multiplication calculation method, designs a pipeline, and shortens the floating-point multiplication calculation period of f32 and f16 in the processor to two periods, and f64 to three periods, and all can support fast wake-up. The embodiment can shorten the calculation period of floating-point multiplication, improve the performance of the processor in executing floating-point multiplication instructions, and is not limited to the processor, but also can improve the calculation performance in other calculation fields that require floating-point multiplication.

[0198] For example, based on the method of the embodiment, in the application scenario of half-precision floating-point multiplication and single-precision floating-point multiplication based on a CPU processor, the number of floating-point multiplication periods in the related art is reduced from 3 to 2, and the total period is reduced by 33.3%.

[0199] Referring to Figure 10The embodiment provides a floating point multiplication circuit, which comprises an overflow information acquisition unit 302, and a to-be-shifted parameter acquisition unit 301 and an index adjustment unit 303 connected with the overflow information acquisition unit 302; the to-be-shifted parameter acquisition unit 301 is used for acquiring a first index of a first floating point number and a second index of a second floating point number; and the to-be-shifted parameter acquisition unit 301 is further used for acquiring a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating point number and the second floating point number according to the first index and the second index; the to-be-shifted parameter comprises a shift direction and a shift bit number; the overflow information acquisition unit 302 is used for acquiring overflow information of a shift result of the shift operation on the decimal part of the product according to the to-be-shifted operation parameter; the overflow information comprises overflow or no overflow; and the index adjustment unit 303 is used for adjusting an index of the shift result according to the overflow information, so as to obtain a multiplication result of the first floating point number and the second floating point number.

[0200] With reference to Figure 11 In the case that the shift direction is left shift and the shift bit number comprises a left shift bit number, the overflow information acquisition unit comprises a shift mask acquisition unit, the shift mask acquisition unit is used for acquiring an initial mask, and the initial mask is shifted right by a value of a highest bit of the initial mask according to the left shift bit number, so as to obtain a shift mask; the value of the highest bit of the initial mask is 1, and the values of other bits are 0; a first AND operation subunit is used for performing AND operation on the shift mask and the product, so as to obtain an AND operation result; and a left shift operation overflow information acquisition subunit is used for acquiring overflow information of the decimal part of the left shift result according to the AND operation result.

[0201] Optionally, the left shift operation overflow information acquisition subunit comprises a first overflow information acquisition subunit, and a second AND operation subunit connected with the first overflow information acquisition subunit.

[0202] The first overflow information acquisition subunit is used for acquiring a first number of leading zeros of the first floating point number and a second number of leading zeros of the second floating point number, and acquiring a third number of leading zeros of the product according to the first number of leading zeros and the second number of leading zeros; the first overflow information acquisition subunit is further used for acquiring a third index of the product according to the first index and the second index, and acquiring first overflow information of the shift result according to a comparison result of the third index and the third number of leading zeros; and the second AND operation subunit is used for determining that the overflow information of the decimal part of the left shift result is overflow if the or reduction operation result is 1 and the first overflow information is overflow; and determining that the overflow information of the decimal part of the left shift result is no overflow if the or reduction operation result is 0 or the first overflow information is no overflow.

[0203] With reference to Figure 11The second AND operation subunit obtains the first overflow information leftShiftNoOverFlow and the result of the OR and reduction operation dMulShiftMask, and performs an AND operation to obtain the overflow information corresponding to the left shift operation leftShiftOverFlow.

[0204] In the case of right shift, the shift bit number includes the right shift number, and the overflow information obtaining unit includes a third AND operation subunit. If the value of the highest bit of the product decimal part is equal to 1 and the right shift number is equal to 1, the third AND operation subunit determines that the decimal part of the right shift result overflows. If the value of the highest bit of the product decimal part is equal to 0 or the right shift number is not equal to 1, the third AND operation subunit determines that the decimal part of the right shift result does not overflow.

[0205] Referring to Figure 11 The third AND operation subunit obtains the right shift value (shiftBits==1) and the value of the highest bit of the product decimal part (dMul(2*decimlWidth-1)), and performs an AND operation to obtain the overflow information corresponding to the right shift operation rightShiftOverFlow.

[0206] Referring to Figure 12 The exponent adjusting unit includes a first OR operation subunit and a first multiplexer (MUX) connected to the first OR operation subunit. If the overflow information is no overflow or the values of all bits in the third exponent of the product are equal to 1, the first OR operation subunit determines that the product overflows. If the overflow information is overflow and the value of at least one bit in the third exponent of the product is equal to 0, the first OR operation subunit determines that the product does not overflow. If the overflow information is no overflow or the values of all bits in the third exponent of the product are equal to 1, the first multiplexer keeps the exponent unchanged. If the overflow information is overflow and the value of at least one bit in the third exponent of the product is equal to 0, the first multiplexer performs a carry operation on the exponent.

[0207] Referring to Figure 13The embodiment of the application provides a floating point multiplication device, and the device 40 comprises: a first obtaining module 401, which is used for obtaining a first exponent of a first floating point and a second exponent of a second floating point; a second obtaining module 402, which is used for obtaining a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating point and the second floating point according to the first exponent and the second exponent; the to-be-shifted parameter comprises a shift direction and a shift bit number; a third obtaining module 403, which is used for obtaining overflow information of a decimal part of a shift result according to the to-be-shifted parameter in a process of obtaining the shift result of the product according to the to-be-shifted parameter; the overflow information comprises overflow or no overflow; and an exponent adjusting module 404, which is used for adjusting the exponent of the shift result according to the overflow information, so as to obtain a multiplication result of the first floating point and the second floating point.

[0208] Optionally, in the case that the shift direction is left shift, the shift bit number comprises a left shift number; the third obtaining module 403 is further used for: obtaining an initial mask; the highest bit of the initial mask is 1, and the other bits are 0; shifting the value of the highest bit of the initial mask to the right according to the left shift number, so as to obtain a shift mask; performing an AND operation on the shift mask and the product, so as to obtain an AND operation result; and obtaining the overflow information of the decimal part of the shift result according to the AND operation result.

[0209] Optionally, the third obtaining module 403 is further used for: performing an OR reduction operation on the AND operation result, so as to obtain an OR reduction operation result; and obtaining the overflow information of the decimal part of the shift result according to the OR reduction operation result.

[0210] Optionally, the third obtaining module 403 is further used for: obtaining a third exponent of the product according to the first exponent and the second exponent; obtaining first overflow information of the shift result according to the third exponent; if the OR reduction operation result is 1 and the first overflow information is overflow, determining that the overflow information of the decimal part of the shift result is overflow; and if the OR reduction operation result is 0 or the first overflow information is no overflow, determining that the overflow information of the decimal part of the shift result is no overflow.

[0211] Optionally, the third obtaining module 403 is further used for: obtaining a first number of leading zeros of the first floating point and a second number of leading zeros of the second floating point; obtaining a third number of leading zeros of the product according to the first number of leading zeros and the second number of leading zeros; and obtaining the first overflow information of the shift result according to a comparison result of the third exponent and the third number of leading zeros.

[0212] Optionally, the mantissa of the initial mask is equal to the number of bits of the decimal part of the product; optionally, the third obtaining module 403 is further configured to: perform an AND operation on the shifted mask and the product to obtain an initial AND operation result; and obtain an AND operation result by intercepting data from the highest bit to the first bit of the initial AND operation result, wherein the total number of bits from the highest bit to the first bit of the initial AND operation result is equal to the width of the mantissa of the preset floating-point number type.

[0213] Optionally, the third obtaining module 403 is further configured to: obtain a third exponent of the product according to the first exponent and the second exponent; if the third exponent is equal to zero, obtain the shifted mask by right-shifting the value of the highest bit of the initial mask according to a first shift value; the first shift value is equal to the sum of the left shift number and 1; if the third exponent is not equal to zero, obtain the shifted mask by right-shifting the value of the highest bit of the initial mask according to the left shift number.

[0214] Optionally, in the case that the shift direction includes right shifting and the shift number includes the right shift number, the third obtaining module 403 is further configured to: if the value of the highest bit of the decimal part of the product is equal to 1 and the right shift number is equal to 1, determine that the decimal part of the shift result overflows; if the value of the highest bit of the decimal part of the product is equal to 0 or the right shift number is not equal to 1, determine that the decimal part of the shift result does not overflow.

[0215] Optionally, the exponent adjusting module is further configured to: if the overflow information is no overflow or the value of each bit of the third exponent of the product is equal to 1, keep the exponent unchanged; if the overflow information is overflow and the value of at least one bit of the third exponent of the product is equal to 0, perform a carry operation on the exponent.

[0216] Optionally, the apparatus 40 further includes: a fourth obtaining module configured to obtain a first mantissa of the first floating-point number and a second mantissa of the second floating-point number; a fifth obtaining module configured to obtain a first partial product according to the first mantissa and the second mantissa; a sixth obtaining module configured to obtain a first compressed result by compressing the first partial product, and obtain a second partial product of a first implicit bit of the first floating-point number and a second implicit bit of the second floating-point number in the process of compressing the first partial product; and a compression module configured to obtain the product of the first floating-point number and the second floating-point number according to the first compressed result and the second partial product.

[0217] In summary, in the embodiment of the present application, it is not necessary to determine whether the exponent needs to be incremented according to the detection result of the value of the highest bit of the shift result after obtaining the product of the first floating-point number and the second floating-point number and performing the shift operation on the product, compared with the method in the related art that first obtains the product, then performs the shift operation on the product, determines whether the value of the highest bit of the shift result is 1, and determines whether the exponent needs to be incremented according to the determination result. The embodiment reduces the processing time of the exponent increment and the operation period of the floating-point multiplication operation.

[0218] Figure 14 FIG. 5 is a block diagram of an electronic device 500 according to an example embodiment. The electronic device 500 can be, for example, a mobile phone, a computer, a digital broadcasting terminal, a message transmitting / receiving device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0219] Referring to Figure 14 The electronic device 500 can include one or more of the following components: a processing component 502, a memory 504, a power supply component 506, a multimedia component 508, an audio component 510, an input / output (I / O) interface 512, a sensor component 514, and a communication component 516.

[0220] The processing component 502 usually controls overall operations of the electronic device 500, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 502 can include one or more processors 520 to execute instructions to complete all or part of steps of the above-described methods. The memory 504 is used to store various types of data to support operations of the electronic device 500. The memory 504 can be implemented by any type of volatile or nonvolatile storage devices or a combination thereof. The power supply component 506 supplies power for various components of the electronic device 500. The power supply component 506 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 500.

[0221] The multimedia component 508 includes a screen to provide an output interface between the electronic device 500 and a user. The audio component 510 is used to output and / or input audio signals. The received audio signals can be further stored in the memory 504 or transmitted via the communication component 516. The I / O interface 512 provides an interface between the processing component 502 and peripheral interface modules.

[0222] The sensor component 514 includes one or more sensors to provide state evaluation of various aspects for the electronic device 500. The sensor component 514 can include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The communication component 516 is used to facilitate wired or wireless communication between the electronic device 500 and other devices. The electronic device 500 can access a wireless network based on a communication standard. In an example embodiment, the communication component 516 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the electronic device 500 is used to implement a floating-point multiplication method provided by the embodiments.

[0223] In an example embodiment, a non-transitory computer readable storage medium including instructions, such as the memory 504 including instructions, is also provided, which can be executed by the processor 520 of the electronic device 500 to complete the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0224] Figure 15 is a block diagram of an electronic device 600 according to an example embodiment. For example, the electronic device 600 can be provided as a server. Referring to Figure 15 , the electronic device 600 includes a processing component 622, which further includes one or more processors, and a memory resource represented by a memory 632, for storing instructions executable by the processing component 622, such as an application program. The application program stored in the memory 632 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 622 is configured to execute the instructions to perform a floating point multiplication method provided by the embodiments of the present application.

[0225] The electronic device 600 can also include a power supply component 626 configured to perform power management of the electronic device 600, a wired or wireless network interface 650 configured to connect the electronic device 600 to a network, and an input / output (I / O) interface 658. The electronic device 600 can operate based on an operating system stored in the memory 632, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™ or the like.

[0226] The embodiments of the present application also provide a computer program product including a computer program, which when executed by a processor implements a floating point multiplication method.

[0227] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims.

Claims

1. A floating point multiplication method, characterized in that: include: Get the first exponent of the first floating point number and the second exponent of the second floating point number; Obtaining, according to the first exponent and the second exponent, a parameter to be shifted for performing a shift operation on a decimal part of a product of the first floating-point number and the second floating-point number; the parameter to be shifted includes a shift direction and a shift number; In the process of obtaining the shift result of the product according to the parameter to be shifted, overflow information of the decimal part of the shift result is obtained according to the parameter to be shifted; the overflow information includes overflow or no overflow; The exponent of the shift result is adjusted according to the overflow information to obtain a multiplication result of the first floating-point number and the second floating-point number.

2. The method according to claim 1, characterized in that In a case where the shift direction is left shift and the shift number includes the left shift number, obtaining overflow information of the decimal part of the shift result according to the parameter to be shifted includes: Get an initial mask; the value of the highest bit of the initial mask is 1, and the values ​​of other bits are 0; Shifting the highest bit of the initial mask rightward according to the number of left shifts to obtain a shift mask; Performing an AND operation on the shift mask and the product to obtain an AND operation result; According to the AND operation result, overflow information of the decimal part of the shift result is obtained.

3. The method according to claim 2, characterized in that The step of obtaining overflow information of a decimal part of a shift result according to the AND operation result includes: Performing an OR operation on the AND operation result to obtain an OR operation result; According to the result of the OR reduction operation, overflow information of the decimal part of the shift result is obtained.

4. The method according to claim 3, characterized in that The step of obtaining overflow information of a decimal part of a shift result according to the result of the OR reduction operation comprises: Obtaining a third exponent of the product according to the first exponent and the second exponent; Obtaining first overflow information of the shift result according to the third index; If the result of the OR reduction operation is 1 and the first overflow information is overflow, determining the overflow information of the fractional part of the shift result as overflow; If the result of the OR reduction operation is 0, or the first overflow information is no overflow, then the overflow information of the fractional part of the shift result is determined to be no overflow.

5. The method according to claim 4, characterized in that The obtaining, according to the third index, first overflow information of the shift result includes: Obtaining a first number of leading zeros of the first floating-point number and a second number of leading zeros of the second floating-point number; Obtaining a third number of leading zeros of the product according to the first number of leading zeros and the second number of leading zeros; First overflow information of the shift result is obtained according to a comparison result of the third exponent and the third number of leading zeros.

6. The method according to claim 2, characterized in that Performing an AND operation on the shift mask and the product to obtain an AND operation result, including: Performing an AND operation on the shift mask and the product to obtain an initial AND operation result; intercepting data from the highest bit to the first bit in the initial AND operation result to obtain the AND operation result; The total number of bits from the highest bit of the initial AND operation result to the first position is equal to the mantissa width of the preset floating-point number type.

7. The method according to claim 2, characterized in that The step of right-shifting the highest bit of the initial mask according to the number of left shifts to obtain a shift mask comprises: Obtaining a third exponent of the product according to the first exponent and the second exponent; If the third index is zero, the value of the highest bit of the initial mask is shifted rightward according to a first shift value to obtain the shift mask; the first shift value is equal to the sum of the left shift number and 1; If the third index is not equal to zero, the value of the highest bit of the initial mask is shifted right according to the number of left shifts to obtain the shift mask.

8. The method according to claim 1, characterized in that In a case where the shift direction includes right shifting and the shift number includes the right shift number, obtaining overflow information of the decimal part of the shift result according to the parameter to be shifted includes: If the value of the most significant bit of the decimal part of the product is equal to 1, and the number of right shift bits is equal to 1, then it is determined that the decimal part of the shift result overflows; If the value of the most significant bit of the decimal part of the product is equal to 0, or the right shift number is not equal to 1, it is determined that the decimal part of the shift result does not overflow.

9. The method according to claim 1, characterized in that The step of adjusting the exponent of the shift result according to the overflow information to obtain a multiplication result of the first floating-point number and the second floating-point number includes: If the overflow information indicates no overflow, or the values ​​of all digits in the third exponent of the product are 1, keeping the exponent unchanged; If the overflow information indicates overflow, and the value of at least one bit in the third exponent of the product is equal to 0, a carry operation is performed on the exponent.

10. The method according to claim 1, characterized in that The method further comprises: Obtaining a first mantissa of the first floating-point number and a second mantissa of the second floating-point number; Obtain a first partial product according to the first mantissa and the second mantissa; compressing the first partial product to obtain a first compression result, and in the process of compressing the first partial product, obtaining a second partial product of a first implicit bit of the first floating-point number and a second implicit bit of the second floating-point number; The product of the first floating-point number and the second floating-point number is obtained according to the first compression result and the second partial product.

11. A floating-point multiplication circuit, characterized in that: It includes an overflow information acquisition unit, a parameter to be shifted acquisition unit, and an exponent adjustment unit; the overflow information acquisition unit is connected to the parameter to be shifted acquisition unit and the exponent adjustment unit; a to-be-shifted parameter obtaining unit, configured to obtain a first exponent of the first floating-point number and a second exponent of the second floating-point number; The to-be-shifted parameter acquisition unit is further configured to acquire, based on the first exponent and the second exponent, a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating-point number and the second floating-point number; the to-be-shifted parameter includes a shift direction and a shift number. The overflow information obtaining unit is configured to obtain overflow information of a decimal part of the shift result according to the to-be-shifted parameter in a process of obtaining the shift result of the product according to the to-be-shifted parameter; the overflow information includes overflow or no overflow; An exponent adjustment unit is used to adjust the exponent of the shift result according to the overflow information to obtain a multiplication result of the first floating-point number and the second floating-point number.

12. The circuit according to claim 11, characterized in that In the case where the shift direction is left shift and the shift number includes the left shift number, the overflow information acquiring unit includes a shift mask acquiring subunit, a first AND operation subunit connected to the shift mask acquiring subunit, and a left shift operation overflow information acquiring subunit connected to the first AND operation subunit: The shift mask acquisition subunit is used to obtain an initial mask and right-shift the value of the highest bit of the initial mask according to the number of left shifts to obtain a shift mask; the value of the highest bit of the initial mask is 1, and the values ​​of other bits are 0; The first AND operation subunit is configured to perform an AND operation on the shift mask and the product to obtain an AND operation result; The left shift operation overflow information obtaining subunit is used to obtain overflow information of the decimal part of the shift result according to the AND operation result.

13. The circuit according to claim 11, characterized in that In a case where the shift direction includes right shifting and the shift number includes a right shift number, the overflow information acquiring unit includes: a third AND operation subunit, configured to determine that the decimal part of the shift result overflows if the value of the most significant bit of the decimal part of the product is equal to 1 and the number of right shift bits is equal to 1; The third AND operation subunit is further configured to determine that the shift result decimal part does not overflow if the value of the most significant bit of the decimal part of the product is equal to 0, or the right shift number is not equal to 1.

14. The circuit according to claim 11, wherein: The index adjustment unit includes a first OR operation subunit and a first multiplexer connected to the first OR operation subunit; The first OR operation subunit is configured to determine that the product overflows if the overflow information indicates no overflow or the values ​​of each digit in the third exponent of the product are all 1; The first OR operation subunit is further configured to determine that the product does not overflow if the overflow information indicates overflow and the value of at least one bit in the third exponent of the product is equal to 0; The first multiplexer is configured to keep the exponent unchanged if the overflow information indicates no overflow or if the values ​​of all digits in the third exponent of the product are 1; The first multiplexer is further configured to perform a carry operation on the exponent if the overflow information indicates overflow and the value of at least one bit in the third exponent of the product is equal to 0.

15. A floating-point multiplication device, characterized in that: The device comprises: A first acquisition module, configured to acquire a first exponent of a first floating-point number and a second exponent of a second floating-point number; a second acquiring module, configured to acquire, according to the first exponent and the second exponent, a parameter to be shifted for performing a shift operation on a decimal part of a product of the first floating-point number and the second floating-point number; the parameter to be shifted includes a shift direction and a shift number; A third obtaining module is configured to obtain overflow information of a decimal part of the shift result according to the to-be-shifted parameter in a process of obtaining the shift result of the product according to the to-be-shifted parameter; the overflow information includes overflow or no overflow; An exponent adjustment module is configured to adjust the exponent of the shift result according to the overflow information to obtain a multiplication result of the first floating-point number and the second floating-point number.

16. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method according to any one of claims 1 to 10.

17. A computer-readable storage medium, characterized in that When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method according to any one of claims 1 to 10.

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