Caching method and system for access unit of superscalar processor

Abstract

The invention belongs to the field of integrated circuits and computer system structures, and provides a caching method and system for a memory access unit of a superscalar processor, and the method comprises the steps: receiving a plurality of memory access instructions in the same period, and determining a corresponding Bank in a to-be-accessed cache through the memory access instructions; after the memory access instruction obtains a cache access permission, if cache line missing occurs, generating a missing request, merging all the missing requests, and performing parallel prefetching training on the merged missing requests by utilizing a mode of fusing a constant step length prefetching mode and a complex step length prefetching mode to obtain a prefetching request and a prefetching cache address corresponding to the prefetching request; requesting a missing cache line from the first-level cache to the second-level cache based on the missing queue, and writing the missing cache line back to the cache line of the corresponding data cache in the first-level cache; and storing the bus consistency request by using the sniffing queue, judging whether the data in the multi-core cache are consistent or not by using the consistency request, and performing consistency modification according to a judgment result. The cache hit rate and the bandwidth utilization rate are improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits and computer architecture, and particularly relates to a cache method and system for a memory access unit of a superscalar processor. BACKGROUND

[0002] The statements in this section merely provide background information related to the present application and do not necessarily constitute the prior art.

[0003] With the rise of high-load applications such as big data, cloud computing, and artificial intelligence, the performance bottleneck of processors is increasingly concentrated in the storage subsystem. Modern high-performance processors often use multi-level cache structures to alleviate the speed gap between main memory and CPU. Superscalar processors improve instruction throughput through techniques such as out-of-order execution and multi-issue, but the design and management of their cache subsystems directly affect the overall system performance.

[0004] The cache of a traditional memory access unit is usually a single-port or limited multi-port structure, which is difficult to support superscalar multi-channel concurrent memory access, resulting in a bottleneck in cache access bandwidth and insufficient cache concurrency. When multiple channels access the cache concurrently, the conflict processing and arbitration mechanism of the cache bank is imperfect, which easily causes resource waste and conflict delay, resulting in complex bank management and arbitration. Existing hardware prefetching is mostly fixed-step or simple flow detection, and the cache replacement strategy is single, the prefetching and replacement mechanism is simple, which is difficult to adapt to diversified program behaviors, resulting in low cache hit rate and bandwidth utilization. In a multi-core / multi-thread environment, the cache consistency maintenance overhead is large, the write-back and cache backfill management is not flexible, the data consistency and write-back efficiency are low, which affects the system performance. SUMMARY

[0005] To solve the above problems, the present application provides a cache method and system for a memory access unit of a superscalar processor, which mainly includes multi-channel concurrent cache access, prefetching and replacement, hierarchical write-back and consistency queue coordination, etc., realizes multi-channel concurrent cache access, efficient bank arbitration, prefetching and dynamic replacement, cache write-back and consistency coordination optimization, and improves the overall memory access unit throughput and energy efficiency.

[0006] According to some embodiments, the first aspect of the present application provides a cache method for a memory access unit of a superscalar processor, which adopts the following technical solution: A cache method for a memory access unit of a superscalar processor, comprising: receiving multiple memory access instructions in the same cycle, determining the corresponding bank to be accessed in the cache using the memory access instructions, and if the multiple memory access instructions access the same bank, determining the access authority of the memory access instructions based on the cache line where the instruction address is located; When the cache access permission of the access instruction is obtained, if a cache line miss occurs, a miss request is generated and saved in a miss queue, the miss queue supports request merging in a cache line unit, and a constant step prefetch mode and a complex step prefetch mode are fused to perform parallel prefetch training on the merged miss request, to obtain a prefetch request and a corresponding prefetch cache address; Based on the miss queue, it is first determined whether there is a replaced cache line corresponding to the miss request in the write-back queue, if there is, the replaced cache line is written back to the second-level cache after the miss queue requests the missed cache line from the first-level cache to the second-level cache, and the corresponding data cache line in the first-level cache is written back; The bus consistency request is stored in the sniffing queue, the consistency of data in the multi-core cache is judged by the consistency request, and the consistency is modified according to the judgment result.

[0007] Further, the access instruction is used to determine the Bank to be accessed in the cache, and specifically, The target index is used to determine the cache to be accessed, the cache index is used to determine the cache line address in the address cache and the corresponding cache line in the data cache, and the Bank index is used to determine the Bank in the cache line; The access instruction includes a target index, a cache index, a Bank index and other basic fields; The cache includes an address cache and a data cache, and the address cache and the data cache are 8-way set associative, each way has 256 rows, and each row is divided into 16 Banks; Each cache address row in the address cache stores a corresponding cache line address, which is used to determine whether the access address of the access instruction hits, and the data of the corresponding Bank in the corresponding cache data is valid in the hit case; Each cache line in the data cache stores the data to be accessed.

[0008] Further, when multiple access instructions access the same Bank, the access permission of the access instruction is determined based on the cache line where the Bank is located, and specifically, If multiple access instructions access the same Bank, the cache lines accessed by the multiple access instructions are different, only the access instruction with the highest sequential priority is allowed to access, and the remaining access instructions have no access permission and wait for the next cycle to determine; If multiple access instructions access the same Bank, the cache lines accessed by the multiple access instructions are the same, and parallel access is allowed.

[0009] Further, the merged missing requests are trained in parallel using the fusion of the constant step prefetch mode and the complex step prefetch mode, wherein the training process of each missing request comprises: determining the corresponding constant entry in the constant prefetch queue according to the address index in the missing request; determining the complex entry in the complex prefetch entry queue according to the complex entry index in the corresponding constant entry; if the step in the complex entry is equal to the step of the last missing request, the confidence is increased by 1; if the step in the complex entry is not equal to the step of the last missing request, the confidence is decreased by 1; if the final confidence is 0, the step in the constant entry is updated to the step in the complex entry, otherwise the constant entry is not updated; the complex entry index is left shifted by one bit and then is XORed with the step in the complex entry to obtain a modified complex entry index and is returned to the constant entry for updating, completing the prefetch training of one missing request; after the training of all missing requests is completed, the pending arbitration prefetch requests are generated based on all entries with a confidence greater than 1 in the updated constant prefetch queue and the complex prefetch entry queue; the priority of the pending arbitration prefetch request is determined based on the constant prefetch queue, the complex prefetch entry queue, and the serial numbers of the entries in the two queues, and 4 pending arbitration prefetch requests are selected as the prefetch requests in descending order of priority to generate the prefetch queue.

[0010] Further, the priority of the constant prefetch queue is lower than that of the complex prefetch entry queue, and both the constant prefetch queue and the complex prefetch entry queue have 128 entries, and the internal priority is that the smaller the entry serial number is, the higher the priority is.

[0011] When all cache lines are not the data to be accessed by the access instruction, the replaced cache line is written into the write-back queue.

[0012] Further, the data in the multi-core cache is judged based on the consistency request, and the consistency is modified according to the judgment result, specifically: based on the consistency request, if the data in the cache line accessed by the requester and the data in the cache line of the requested party are inconsistent, it is determined whether the inconsistent cache line of the requested party is the replaced cache line in the write-back queue or the cache line state is dirty, if so, the replaced cache line of the request is written back to the L2 cache based on the write-back queue, otherwise, the cache of the requested party is not operated.

[0013] based on the consistency request, if the data in the cache line accessed by the requester and the data in the cache line of the requested party are consistent, the cache of the requested party is not operated.

[0014] According to some embodiments, a second aspect of the present application provides a cache system for a memory access unit of a superscalar processor, which adopts the following technical solution: A cache system for a memory access unit of a superscalar processor, comprising: A memory processing module configured to receive a plurality of memory access instructions in the same cycle, determine the corresponding Bank in the cache to be accessed by the memory access instructions, and determine the access authority of the memory access instructions based on the cache line where the Bank is located if the plurality of memory access instructions access the same Bank; A prefetch training module configured to generate a missing request and save it in a missing queue if a cache line is missing when the memory access instruction obtains the cache access authority, merge all missing requests, and perform parallel prefetch training on the merged missing requests in a constant step prefetch mode and a complex step prefetch mode fusion manner to obtain a prefetch request and a corresponding prefetch cache address; A missing write-back module configured to confirm whether there is a replaced cache line corresponding to the missing request in the write-back queue based on the missing queue, wait for the missing replaced cache line to be written back to the secondary cache by the write-back queue if there is, and then request the missing cache line from the primary cache to the secondary cache based on the missing queue and write back the corresponding cache line in the data cache in the primary cache; A consistency detection module configured to store bus consistency requests in a sniffing queue, determine whether the data in the multi-core cache is consistent by using the consistency request, and modify the consistency according to the determination result.

[0015] According to some embodiments, a third aspect of the present application provides a computer readable storage medium.

[0016] A computer readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the cache method for a memory access unit of a superscalar processor according to the first aspect.

[0017] According to some embodiments, a fourth aspect of the present application provides a computer device.

[0018] A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the cache method for a memory access unit of a superscalar processor according to the first aspect when executing the program.

[0019] According to some embodiments, a fifth aspect of the present application provides a computer program product or computer program.

[0020] The application provides a computer program product or computer program, which comprises computer instructions stored in a computer readable storage medium.

[0021] Compared with the prior art, the application has the following beneficial effects: The application utilizes multi-channel concurrent Cache access, prefetching and replacement, hierarchical write-back and consistency queue cooperation, Cache energy efficiency dynamic management and the like, is suitable for various chip designs and implementations of high-performance general-purpose processors, embedded processors, AI accelerators and the like, realizes multi-channel concurrent Cache access, efficient arbitration of Banks, prefetching and dynamic replacement, Cache write-back and consistency cooperation optimization, and improves the overall memory unit throughput and energy efficiency.

[0022] The application improves Cache concurrent access bandwidth and data throughput by 20%, improves Cache hit rate and prefetch hit rate by 15%.

[0023] The application improves Cache hit rate and bandwidth utilization through prefetching and dynamic replacement mechanism, optimizes write-back and backfill processes through write-back and missing management queue cooperation, reduces main memory access delay, and supports Cache consistency to meet the scalability of multi-core systems. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings, which form a part of the specification, are included to provide a further understanding of the application, and are incorporated herein for explanation by illustrating a preferred embodiment of the present application.

[0025] Figure 1 is a general structure block diagram of a Cache facing a memory unit of a superscalar processor in an embodiment of the application; Figure 2 is a Cache implementation architecture in an embodiment of the application; Figure 3 is an SPT / CSPT prefetch training process in an embodiment of the application; Figure 4 is a pipeline implementation of SPT and CSPT in an embodiment of the application. DETAILED DESCRIPTION

[0026] The application will be further described below in combination with the accompanying drawings and embodiments.

[0027] It should be noted that the following detailed description is exemplary in nature and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0028] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0029] The embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0030] Term explanation: Snoop Queue (SNQ), stores bus coherence requests, to ensure cache data consistency in multi-core, Interconnect sends requests for other core access or modify the same Cache line, SNQ receives the request to create Entry and request L1 DCache access permission, check or modify the corresponding Cache line CSA state bit, if the state of the Cache line is dirty, the cache line needs to be written back to memory, and the other core is notified of the data modification of the address.

[0031] Write Back Queue (WBQ), manages the cache lines written back due to Dirty / Slience Evict, completes a write operation, i.e., writes back from the first level cache to the second level cache for at least 4 clock cycles, to improve the efficiency of write back, and completes the write back operation in units of cache lines.

[0032] Miss Queue (MQ), used to handle Cache Miss. When a cache line miss occurs, a read request is initiated to the second level cache, and the instructions in the sleep state in the queue are awakened after the data is backfilled into the cache. Special entries are set for instructions accessing None Cacheable address space, and the queue supports processing of bus exception conditions such as Bus Error.

[0033] Embodiment one As shown in Figure 1 The present embodiment provides a cache method for a superscalar processor memory access unit. The method in the present embodiment includes the following steps: The plurality of memory access instructions are received in the same cycle, and the memory access instructions are used to determine the corresponding Bank to be accessed in the cache, and if the plurality of memory access instructions access the same Bank, the access authority of the memory access instruction is determined based on the cache line where the Bank is located; When the memory access instruction obtains the cache access authority, if a cache line miss occurs, a miss request is generated and saved in a miss queue, and all miss requests are merged, and the merged miss requests are trained in parallel using a constant step prefetch mode and a complex step prefetch mode fusion manner to obtain a prefetch request and a corresponding prefetch cache address; Based on the miss queue, it is first determined whether there is a replaced cache line corresponding to the miss request in the write-back queue, if there is, the replaced cache line is written back to the secondary cache after the write-back queue writes back the replaced cache line to the secondary cache, and then the miss cache line is requested from the primary cache to the secondary cache based on the miss queue, and the corresponding data cache cache line in the primary cache is written back; The bus consistency request is stored in the sniffing queue, the consistency of the data in the multi-core cache is judged by using the consistency request, and the consistency is modified according to the judgment result.

[0034] When all cache lines are not data to be accessed by the access instruction, the replaced cache line is written into the write-back queue.

[0035] The memory access instruction is used to determine the corresponding Bank to be accessed in the cache, specifically: The target index is used to determine the cache to be accessed, the cache index is used to determine the cache line address in the address cache and the corresponding cache line in the data cache, and the Bank index is used to determine the Bank in the cache line; The memory access instruction includes a target index, a cache index, a Bank index and other basic fields; The cache includes an address cache and a data cache, and the address cache and the data cache are 8-way set associative, each way has 256 rows, and each row is divided into 16 Banks; Each cache address row in the address cache stores the corresponding cache line address, which is used to determine whether the access address of the memory access instruction hits, and the data of the corresponding Bank in the corresponding cache data is valid in the hit case; each cache line in the data cache stores the data to be accessed.

[0036] As Figure 2A multi-channel Banked Cache access structure is shown: the Cache adopts a set-associative, Banked structure, supports multiple memory access instructions entering the access stage in parallel per cycle. The Cache arbiter detects instruction address conflicts, allocates Cache address space, and improves multi-channel concurrent capability. When the Cache is accessed, if multiple instructions in the same cycle access the same Bank, the arbiter gives access permission according to the instruction address overlap and age vector, avoiding Bank conflicts resulting in errors.

[0037] Each Cache line (512bit) of the Data Cache is composed of 16 Banks (32bit), each Bank has an independent read port and write port. The Bank is composed of RAM and cannot perform read and write operations simultaneously. In the read operation, 8 Ways share a read enable signal (Ren) and a read address signal (Raddr), at this time each Way outputs 32bit data, a total of 256bit (32x8bit) is read out. In the write operation, only the write enable signal (Wen) of one Way is selected to be pulled high, and 32bit data is written to the corresponding Bank.

[0038] In the read operation, the Tag Cache reads 8 Ways simultaneously and outputs 8 Tag values. In the write operation, only one Tag value is written to one Way. The Tag Cache is used to determine whether the address is hit, and the Data Cache data is valid in the hit case.

[0039] The state management of the Cache is realized by 8x256 state registers, each Cache line has a corresponding state register, and the register width is 2bit, which is used to record the state information in the MESI protocol. Since the current design supports Invalid, Exclusive and Modified three states, each state register needs to encode these three states.

[0040] When multiple memory access instructions access the same Bank, the access permission of the memory access instruction is determined based on the cache line where the Bank is located, specifically: If multiple memory access instructions access the same Bank, and the cache lines accessed by the multiple memory access instructions are different, only the memory access instruction with the highest sequential priority is allowed to access, and the remaining memory access instructions have no access permission and wait for the next cycle to be judged; If multiple memory access instructions access the same Bank, and the cache lines accessed by the multiple memory access instructions are the same, parallel access is allowed.

[0041] Specifically, the cache arbiter assigns instructions to the corresponding bank based on the bank index of the target address. If multiple instructions access the same bank in the same cycle, the bank arbiter's arbitration is as shown in Table 1. Bank conflict detection logic ensures that different banks can be accessed in parallel and that conflicts within the same bank are efficiently arbitrated, improving overall cache access bandwidth.

[0042] Table 1 Bank arbitrator arbitration status

[0043] like Figure 3 As shown, the method of fusion of the constant step size prefetch mode and the complex step size prefetch mode is used to perform parallel prefetch training on the merged missing requests, wherein the training process of each missing request includes: Determine the corresponding constant entry in the constant prefetch queue according to the address index in the missing request; Determine a complex entry in the complex prefetch entry queue according to the complex entry index in the corresponding constant entry; If the step size in the complex entry is equal to the step size of the previous missing request, the confidence is increased by 1; if the step size in the complex entry is not equal to the step size of the previous missing request, the confidence is decreased by 1; if the final confidence is 0, the step size in the constant entry is updated to the step size in the complex entry, otherwise the constant entry is not updated; Shift the complex table entry index left by one bit and perform an XOR operation with the step size in the complex table entry to obtain the corrected complex table entry index and return it to the constant table entry for updating, completing the prefetch training of a missing request; After all missing request prefetch training is completed, prefetch requests to be decided are generated based on all entries with confidence greater than 1 in the updated constant prefetch queue and complex prefetch entry queue; Based on the constant prefetch queue, the complex prefetch entry queue and the sequence numbers of the entries in the two, the priority of the prefetch request to be decided is obtained, and four prefetch requests to be decided are selected from high to low priority as prefetch requests to generate a prefetch queue.

[0044] The priority of the constant prefetch queue is lower than that of the complex prefetch entry queue. Both the constant prefetch queue and the complex prefetch entry queue have 128 entries. The internal priority is that the smaller the entry number, the higher the priority.

[0045] When a miss occurs in the process of instruction accessing Cache, the miss queue (Miss Queue, MQ) records the missing Cache line, and the miss request is sent to the prefetch module for training to predict the future addresses that may be accessed. The prefetch module uses the IPCP (Instruction PC Prediction) algorithm for the following two common address access patterns: Sequential access mode: When traversing an array or a loop, the memory address shows a continuous and increasing regularity.

[0046] Stride access mode: In matrix operations or block calculations, the memory address increases or decreases by a certain fixed step size.

[0047] Two prefetch modes, SPT and CSPT, are proposed. Stride Prediction Table (SPT): For memory access patterns with fixed step size, record and learn the step size information of instructions to predict the next memory address that may be accessed. Complex Stride Prediction Table (CSPT): For memory access behavior with complex stride mode, use more complex prediction logic and data structure to record multi-step or nonlinear rules to improve the accuracy of prediction.

[0048] In the constant stride prefetch mode, the number of SPT entries is 128, which is indexed by PC[14:6], and records PC corresponding Addr[13:6] for calculating stride. Stride represents the step size, which is used to determine whether the step size is constant. Confidence represents the confidence of the current stride (2 bits). When Confidence is greater than 1, prefetch is triggered, and 3 Cache lines are prefetched.

[0049] The complex stride prefetch mode is based on the SPT entry, and an additional set of CSPT Entry training is added. CSPT saves Stride (stride) and Confidence information. SPT's Signature (signature) is used as an index to find CSPT. When the stride is equal, confidence is increased by one; when the stride is not equal, confidence is reduced by one; if Confidence is 0, update to new stride. XOR the signature<<1 with the stride to get the new Signature and update SPT.

[0050] Figure 2The prefetch training process of the middle instruction address is as follows: first, the instruction PC [14:6] indexes the SPT table item, calculates the stride, and judges whether the prefetch needs to be triggered according to the confidence, and updates the information of the corresponding table item. The signature is used as an index to update the information of the CSPT table item, and if the miss occurs, the table item information of the CSPT is updated.

[0051] Figure 4 The pipeline implementation of SPT and CSPT is shown. The prefetch training adopts a three-stage pipeline structure.

[0052] 1. Prefetch 0 stage: receiving and merging the missing cache requests.

[0053] When the access request obtains the cache access right, if the cache line miss occurs, the PF module (prefetch module) collects the missing requests (up to 4) and merges them to avoid repeated triggering of the same instruction PC, which causes the confidence training to be wrong.

[0054] 2. Prefetch 1 stage: training the table item based on the request.

[0055] The merged request is used to train the table item in the prediction queue. The table items of SPT and CSPT are updated at the same time during the training. After the training is completed, the table item with a confidence greater than 1 is selected to trigger the prefetch request. Therefore, the constant stride prediction table and the complex stride prediction table may trigger the prefetch request at the same time, and these requests are sent to the next stage of the arbitration module. The design of the confidence can effectively reduce the interference of invalid instructions and the tolerance of the prefetch of the address corresponding to the instruction PC.

[0056] 3. Prefetch 2 stage: arbitrating the prefetch request and generating the prefetch address.

[0057] Since the CSPT and SPT will generate the prefetch request, the design hardware stipulates that the priority of the CSPT request is higher than that of the SPT. The requests with smaller serial numbers (Entry 0-127, the serial number decreases from high to low priority) are preferentially satisfied according to the priority of the table item serial number. The winning arbitration prefetch request is sent to the prefetch queue. The prefetch queue has a depth of 16 entries, which saves the cache address information of the prefetch. The prefetch queue is set to have 16 table items, and the SPT and CSPT may trigger the prefetch request. Four requests are received per cycle, and four are selected after arbitration. The priority judgment is as follows: the SPT / CSPT has 128 table items, and the internal priority 0-127 is from high to low, that is, 0 priority is the highest, and 127 priority is the lowest. The priority of the CSPT request is higher than that of the SPT request.

[0058] The prefetch address request enters the Cache Arbiter through the Load channel, and its priority is the lowest when entering the Cache Arbiter, so as to reduce the influence on normal instruction execution. When the cache line is missing, the MQ initiates a prefetch request to the L2 Cache. The prefetched cache line is marked with an additional tag. If the MQ full backpressure decision occurs, the generation of the prefetch request is stopped, and the prefetch training result of this time is abandoned.

[0059] The prefetch and cache replacement mechanism: the cache prefetch algorithm based on instruction pointer classification (IPCP) is adopted, combined with constant stride (Stride Predicate Table, SPT) and complex stride prediction table (CSPT) two address prefetch modes, the prefetch length, stride and confidence are adjusted according to the address access situation, so as to improve the prefetch hit rate and bandwidth utilization.

[0060] The Cache write-back cooperates with the MQ, and the WBQ (write-back queue) stores the dirty data under the replacement of the L1 Cache. The FIFO queue is adopted, and the L2 Cache is written back to the bus bandwidth in cooperation with the MQ arbitration. The MQ (cache miss queue) stores the cache miss request, supports cooperation with the WBQ and SNQ, and the backfill data priority can be dynamically adjusted. The Cache write-back and backfill are both in the unit of Cache line, the multiple write-in of the same Cache line is combined, and the bus pressure is reduced. The Cache adopts the least recently used (LRU, Least Recently Used) replacement algorithm. The time sequence of data access is recorded through the linked list, and the data that has not been accessed for the longest time is eliminated.

[0061] When the Cache line is replaced in the group-connected Cache, the physical address is first indexed to the Cache Set, and then the replacement path is selected from the multiple paths in the Cache Set according to the replacement algorithm. The hardware records the access priority of each Way through an 8x8 priority matrix. When a Way is accessed, the row corresponding to the Way is set to 1 (indicating that the priority of the Way is the highest), and the column corresponding to the Way is set to 0 (indicating that the priority of the other Ways is lower than that of the Way). When replacing, the Way corresponding to the row with all values of 0 in the matrix (i.e., the priority of the Way is the lowest) is selected for replacement.

[0062] When all cache lines are not the data to be accessed by the access instruction, the cache line to be replaced is written into the write-back queue.

[0063] Hierarchical write back and fill queue, support Cache Line granularity write back and fill, combine multiple write operations to reduce Cache decision pressure. In the process of fill, Cache replacement occurs in 8 way full case, Cache replacement strategy uses LRU priority matrix, support address priority adjustment.

[0064] The data in the multi-core cache is judged to be consistent by using a consistency request, and a consistency modification is made according to the judgment result, specifically: Based on the consistency request, if the data in the cache line of the requestor cache and the cache line of the requested cache are inconsistent, it is determined whether the inconsistent cache line in the requested cache is a replaced cache line in the write back queue, if yes, the requested replaced cache line is written back to the requested cache based on the write back queue, otherwise, the requested cache has no operation.

[0065] Based on the consistency request, if the data in the cache line of the requestor cache and the cache line of the requested cache are consistent, the requested cache has no operation.

[0066] Embodiment 4: Cache consistency management, design SNQ queue to store consistency requests, receive interface supports ACE protocol, monitor bus consistency requests, periodically update Cache line state, trigger invalidation and data write back when necessary. According to the protocol, the following state Cache line state switching.

[0067] ReadClean: read clean data, ensure that the requestor cache line is consistent with the main memory, if the target cache line is dirty, it needs to be written back to the main memory or directly provide data, the target cache line may become Shared. Cache line state change Modified→ Shared or keep; ReadNotSharedDirty: read data, ensure that the target cache line is not shared dirty data. If the target cache line is dirty, provide data and update to Shared. Cache line state change Modified→ Shared; ReadShared: read shared data, allow multiple caches to share. Read data from main memory or other cache, update the target cache line state to Shared. Cache line state change Exclusive→ Shared or keep; ReadUnique: read data, ensure that the requestor cache line is unique. If the target cache line is dirty, it needs to be written back to the main memory or directly provide data, the target cache line is invalidated. Cache line state change Modified / Shared→ Invalid.

[0068] Cache coherency cooperation mechanism. The Cache design coherency queue (Snoop Queue, SNQ) is responsible for storing multi-core / multi-thread coherency requests, supporting ACE protocol and Cache line state management. The Cache line state is changed according to different coherency requests in the multi-core / multi-thread environment.

[0069] Embodiment two The embodiment provides a cache system for a superscalar processor memory access unit, which comprises: The memory processing module is configured to receive a plurality of memory access instructions in the same cycle, determine the corresponding Bank to be accessed in the cache by using the memory access instructions, and determine the access authority of the memory access instruction based on the cache line where the Bank is located when the plurality of memory access instructions access the same Bank. The prefetch training module is configured to generate a missing request and save it in the missing queue when the memory access instruction obtains the cache access authority if a cache line is missing, merge all missing requests, perform parallel prefetch training on the merged missing requests in a constant step prefetch mode and a complex step prefetch mode fusion manner, and obtain a prefetch request and a corresponding prefetch cache address. The missing write-back module is configured to confirm whether there is a replaced cache line corresponding to the missing request in the write-back queue based on the missing queue, wait for the write-back queue to write the missing replaced cache line back to the secondary cache if there is, and request the missing cache line from the primary cache to the secondary cache based on the missing queue and write the cache line corresponding to the data cache in the primary cache back. The coherency detection module is configured to store bus coherency requests by using the snoop queue, judge whether the data in the multi-core cache is consistent by using the coherency request, and modify the coherency according to the judgment result.

[0070] The above modules and the corresponding steps realize the same examples and application scenarios, but are not limited to the content disclosed in the above embodiment one. It should be noted that the above modules as part of the system can be executed in a computer system such as a group of computer executable instructions.

[0071] The description of each embodiment in the above embodiments has its own emphasis, and the parts not described in detail in a certain embodiment can refer to the related description of other embodiments.

[0072] The proposed system can be implemented in other ways. For example, the system embodiments described above are only illustrative, for example, the division of the above modules is only a logical function division, and in actual implementation, there can be another division way, for example, a plurality of modules can be combined or integrated into another system, or some features can be ignored or not executed.

[0073] Embodiment three The embodiment provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement steps in the cache method for a superscalar processor memory access unit as described in the embodiment one.

[0074] Embodiment four The embodiment provides a computer device, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements steps in the cache method for a superscalar processor memory access unit as described in the embodiment one when executing the program.

[0075] Embodiment five The embodiment provides a computer program product or computer program, which comprises computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes steps in the cache method for a superscalar processor memory access unit as described in the embodiment one.

[0076] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can be in the form of a hardware embodiment, a software embodiment or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer usable program code.

[0077] The present application is described with reference to flowcharts and / or block diagrams of the method, device (system) and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the computer or other programmable data processing device produce a device implemented in the flowcharts and / or block diagrams. Figure 1 The device for implementing the function specified in one flow or multiple flows and / or blocks Figure 1 The device for implementing the function specified in one flow or multiple flows and / or blocks

[0078] These computer program instructions can also be stored in a computer readable storage medium, which can guide the computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer readable storage medium produce a product comprising instruction devices, which implement the flowcharts and / or block diagrams. Figure 1one or more processes and / or blocks Figure 1 the function specified in the one or more blocks.

[0079] These computer program instructions can also be loaded into a computer or other programmable data processing devices, so that a series of operational steps are performed on the computer or other programmable data processing devices to generate a computer implemented process, so that the instructions executed on the computer or other programmable data processing devices provide a process for implementing the flow Figure 1 one or more processes and / or blocks Figure 1 the function specified in the one or more blocks.

[0080] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by computer programs instructing related hardware, and the programs can be stored in a computer readable storage medium. When the programs are executed, they can include the processes of the above-mentioned embodiment methods. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), or the like.

[0081] Although the specific embodiments of the present application are described above with reference to the drawings, the description is not a limitation on the scope of protection of the present application. Those of ordinary skill in the art should understand that various modifications or changes made on the basis of the technical solutions of the present application without creative labor are still within the scope of protection of the present application.

Claims

1. A cache method for a memory access unit of a superscalar processor, characterized in that: include: Receive multiple memory access instructions in the same cycle, use the memory access instructions to determine the corresponding bank in the cache to be accessed, and if multiple memory access instructions access the same bank, determine the access rights of the memory access instructions based on the cache line where the bank is located; When a memory access instruction obtains cache access rights, if a cache line miss occurs, a miss request is generated and stored in a miss queue. At the same time, all miss requests are merged, and parallel prefetch training is performed on the merged miss requests using a fusion of a constant-step prefetch mode and a complex-step prefetch mode to obtain prefetch requests and their corresponding prefetch cache addresses. Based on the miss queue, first confirm with the write-back queue whether there is a cache line to be replaced corresponding to the miss request. If so, wait for the write-back queue to write the missing cache line back to the second-level cache, then request the missing cache line from the first-level cache to the second-level cache based on the miss queue, and write it back to the cache line of the corresponding data cache in the first-level cache; The sniffing queue is used to store bus consistency requests, and the consistency requests are used to determine whether the data in the multi-core cache is consistent, and consistency modifications are performed based on the determination results.

2. A cache method for a superscalar processor memory access unit according to claim 1, characterized in that: The method of using the memory access instruction to determine the corresponding bank in the cache to be accessed is as follows: Determine the cache to be accessed based on the target index, use the cache index to determine the cache line address in the address cache and its corresponding cache line in the data cache; and use the bank index to determine the bank in the cache line. The memory access instruction includes a target index, a cache index, a bank index and other basic fields; The cache includes two parts: address cache and data cache. Both the address cache and data cache are 8-way set associative, each way has 256 rows, and each row is divided into 16 banks. Among them, each cache address line in the address cache stores the corresponding cache line address, which is used to determine whether the access address of the memory access instruction hits. In the case of a hit, the data of the corresponding Bank in the corresponding cache data is valid; Each cache line in the data cache stores the data to be accessed.

3. The cache method for a superscalar processor memory access unit according to claim 1, wherein: If multiple memory access instructions access the same bank, the access rights of the memory access instructions are determined based on the cache line where the bank is located, specifically: If multiple memory access instructions access the same bank, but the cache lines accessed by the multiple memory access instructions are different, only the memory access instruction with the highest execution priority is allowed to access the bank. The remaining memory access instructions have no access rights and will be judged in the next cycle. If multiple memory access instructions access the same bank, and the cache lines accessed by the multiple memory access instructions are the same, parallel access is allowed.

4. The cache method for a superscalar processor memory access unit according to claim 1, wherein: The method of using a fusion of a constant step size prefetch mode and a complex step size prefetch mode to perform parallel prefetch training on the merged missing requests, wherein the training process of each missing request includes: Determine the corresponding constant entry in the constant prefetch queue according to the address index in the missing request; Determine a complex entry in the complex prefetch entry queue according to the complex entry index in the corresponding constant entry; If the step size in the complex entry is equal to the step size of the previous missing request, the confidence is increased by 1; if the step size in the complex entry is not equal to the step size of the previous missing request, the confidence is decreased by 1; if the final confidence is 0, the step size in the constant entry is updated to the step size in the complex entry, otherwise the constant entry is not updated; Shift the complex table entry index left by one bit and perform an XOR operation with the step size in the complex table entry to obtain the corrected complex table entry index and return it to the constant table entry for updating, completing the prefetch training of a missing request; After all missing request prefetch training is completed, prefetch requests to be decided are generated based on all entries with confidence greater than 1 in the updated constant prefetch queue and complex prefetch entry queue; Based on the constant prefetch queue, the complex prefetch entry queue and the sequence numbers of the entries in the two, the priority of the prefetch request to be decided is obtained, and four prefetch requests to be decided are selected from high to low priority as prefetch requests to generate a prefetch queue.

5. The cache method for a superscalar processor memory access unit according to claim 4, wherein: The priority of the constant prefetch queue is lower than that of the complex prefetch entry queue. Both the constant prefetch queue and the complex prefetch entry queue have 128 entries. The internal priority is that the smaller the entry number, the higher the priority.

6. The cache method for a superscalar processor memory access unit according to claim 1, wherein: The consistency request is used to determine whether the data in the multi-core cache is consistent, and consistency modification is performed according to the determination result, specifically: Based on the consistency request, if the data in the cache line of the requesting party cache is inconsistent with the data in the cache line of the requested party cache, it is determined whether the inconsistent cache line in the requested party cache is the replaced cache line in the write-back queue. If so, the requested replaced cache line is written back to the requested party cache based on the write-back queue. Otherwise, the requested party cache does not perform any operation. Based on the consistency request, if the data in the cache line of the requesting party cache is consistent with the data in the cache line of the requested party cache, the requested party cache does not perform any operation.

7. A cache system for a superscalar processor memory access unit, characterized in that: include: A memory access processing module is configured to receive multiple memory access instructions in the same cycle, use the memory access instructions to determine the corresponding bank in the cache to be accessed, and if multiple memory access instructions access the same bank, determine the access rights of the memory access instructions based on the cache line where the bank is located; The prefetch training module is configured to generate a miss request and store it in a miss queue when a cache line miss occurs after a memory access instruction obtains cache access rights. The module also merges all the miss requests and performs parallel prefetch training on the merged miss requests by combining a constant step size prefetch mode and a complex step size prefetch mode to obtain prefetch requests and their corresponding prefetch cache addresses. The miss write-back module is configured to first confirm with the write-back queue whether there is a cache line to be replaced corresponding to the miss request based on the miss queue. If so, the module waits for the write-back queue to write the missing cache line back to the secondary cache, and then requests the missing cache line from the primary cache to the secondary cache based on the miss queue, and writes it back to the cache line corresponding to the data cache in the primary cache. The consistency detection module is configured to use the sniffing queue to store bus consistency requests, use the consistency requests to determine whether the data in the multi-core cache is consistent, and perform consistency modification based on the determination result.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the cache method for a memory access unit of a superscalar processor as claimed in any one of claims 1 to 6 are implemented.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the cache method for a superscalar processor memory access unit are implemented as described in any one of claims 1 to 6.

10. A computer program product, characterized in that The computer program product includes a computer program, and when the computer program is executed by a processor, the computer program implements the steps of the cache method for a memory access unit of a superscalar processor according to any one of claims 1 to 6.

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