Integrated Circuit Design Optimization Method and System Based on Data Mining

Abstract

This application relates to the field of data processing technology and discloses a data mining-based integrated circuit design optimization method and system. The method includes: extracting multi-process node transistor parameter vector sets using EDA tools; performing data augmentation using a two-layer process-aware generative adversarial network to obtain a cross-node circuit sample library; inputting the sample library into an R-PTT prediction model to obtain a performance prediction matrix; using this matrix, optimizing the optimal device size combination through a multi-objective genetic algorithm; and finally, performing SPICE simulation to obtain verified integrated circuit design parameters. This application solves the problems of data scarcity and poor model generalization ability in existing data mining-based integrated circuit design optimization methods when applied across process nodes, improving the accuracy and efficiency of design optimization under new process nodes.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to an integrated circuit design optimization method and system based on data mining. Background Technology

[0002] Existing integrated circuit design optimization methods mainly rely on traditional circuit simulation and manual tuning based on experience. Design engineers use SPICE simulators to analyze circuit performance and manually adjust device parameters based on simulation results, iterating repeatedly until design specifications are met. With the rapid development of semiconductor process technology, some research has begun to explore the application of machine learning techniques to circuit design optimization. By establishing mathematical models between device parameters and circuit performance, these methods can guide the selection of design parameters, reducing the number of design iterations and improving design efficiency to some extent.

[0003] However, existing data mining-based integrated circuit design optimization methods have significant shortcomings. These primarily manifest in the inability to effectively transfer and reuse models trained on other process nodes when faced with new process nodes. This necessitates the collection of substantial new process data and retraining of the models, resulting in significant time and cost waste. More critically, in the early stages of a new process node, available design data is extremely scarce. Traditional data mining methods, lacking sufficient training samples, cannot establish reliable optimization models, leading to poor design optimization results and low first-time tape-out success rates.

[0004] The fundamental problem with existing technologies lies in the lack of an effective cross-process node knowledge transfer mechanism, which fails to fully leverage design experience from existing process nodes to guide design optimization for new process nodes. Due to significant differences in physical characteristics between different process nodes, simple parameter scaling cannot accurately reflect the complex impact of process variations on circuit performance, and existing methods lack intelligent algorithms capable of adaptively handling these process differences. Furthermore, existing data augmentation techniques are primarily designed for fields such as image processing and cannot effectively handle the complex nonlinear relationships between process parameters and circuit performance in integrated circuit design. This results in low-quality synthesized data, further limiting the accuracy and reliability of optimization models. Summary of the Invention

[0005] This application provides a data mining-based integrated circuit design optimization method and system to address the problems of data scarcity and poor model generalization ability in the application of existing data mining-based integrated circuit design optimization methods across process nodes, thereby improving the accuracy and efficiency of design optimization under new process nodes.

[0006] In a first aspect, this application provides a data mining-based integrated circuit design optimization method, which includes:

[0007] EDA tools are used to extract process features from multi-process node circuit design data to obtain transistor parameter vector sets.

[0008] Based on the transistor parameter vector set, a cross-node circuit sample library is obtained by performing data augmentation processing through a two-layer process-aware generative adversarial network.

[0009] The cross-node circuit sample library is input into the R-PTT prediction model to predict power consumption and delay, and the performance prediction matrix is ​​obtained.

[0010] Based on the performance prediction matrix, a multi-objective genetic algorithm is used to optimize circuit parameters and obtain the optimal combination of device sizes.

[0011] SPICE simulation was performed on the optimal device size combination to obtain the verified integrated circuit design parameters.

[0012] Optionally, the step of extracting process features from multi-process node circuit design data using EDA tools to obtain a transistor parameter vector set includes:

[0013] Numerical extraction of transistor channel length, oxide layer thickness, and doping concentration at multiple process nodes yields a set of fundamental process parameters.

[0014] Based on the aforementioned process fundamental parameter set, feature encoding processing is performed on the circuit topology and device dimensions to obtain the design parameter encoding matrix;

[0015] Based on the design parameter encoding matrix, data annotation processing is performed on power consumption, delay, and area performance indicators to obtain performance label vectors;

[0016] The process basic parameter set and the performance label vector are concatenated to obtain a high-dimensional feature vector.

[0017] The high-dimensional feature vector is processed by assigning process node identifier codes to obtain the transistor parameter vector set.

[0018] Optionally, the step of performing data augmentation processing on the transistor parameter vector set through a two-layer process-aware generative adversarial network to obtain a cross-node circuit sample library includes:

[0019] The transistor parameter vector set is input into the first-layer process encoder and the second-layer parameter encoder respectively for two-layer feature extraction processing to obtain the process embedding vector and the parameter embedding vector.

[0020] A two-layer conditional input vector is obtained by performing a three-layer splicing and fusion process based on the random noise vector, the process embedding vector, and the parameter embedding vector.

[0021] The dual-layer conditional input vector is input into the dual-path parameter generator for parallel adversarial generation processing to obtain the synthetic design parameter vector.

[0022] Based on the synthetic design parameter vector, a two-layer process discriminator is used to perform true / false discrimination and process classification. When the first-layer discrimination probability is greater than 0.7 and the second-layer process classification accuracy is greater than 0.8, a discrimination probability matrix is ​​generated; otherwise, the parameter generation process is re-executed.

[0023] The synthetic design parameter vector, which has been subjected to two-layer discrimination, is subjected to process consistency verification to obtain the cross-node circuit sample library.

[0024] Optionally, the step of inputting the cross-node circuit sample library into the R-PTT prediction model to perform power delay prediction and obtain a performance prediction matrix includes:

[0025] The process features and design parameters in the cross-node circuit sample library are respectively input into the process feature attention head and the design parameter attention head for multi-head attention weight calculation to obtain the process weight matrix and the parameter weight matrix.

[0026] Based on the process weight matrix and the parameter weight matrix, cross-domain feature fusion processing is performed using a cross-attention head to obtain a fused feature vector;

[0027] The fused feature vector is input into the process migration adaptation layer for residual connection transformation. When the process node difference is greater than 0.5, the adaptation transformation matrix is ​​activated to obtain the adapted feature vector.

[0028] Based on the adapted feature vector, power consumption, latency and area are predicted in parallel through a multi-task regression layer to obtain a multi-dimensional performance output vector.

[0029] The multidimensional performance output vector is subjected to matrix reconstruction processing to obtain the performance prediction matrix.

[0030] Optionally, the step of inputting the fused feature vector into the process migration adaptation layer for residual connection transformation processing, and activating the adaptation transformation matrix when the process node difference is greater than 0.5, to obtain the adapted feature vector, includes:

[0031] The fused feature vector is subjected to process node difference quantification calculation, and the process difference coefficient is obtained based on the feature distance between the source process node and the target process node;

[0032] Based on the process difference coefficient, a threshold judgment process is performed. When the process difference coefficient is greater than 0.5, the adaptation transformation module is activated; otherwise, the pass-through connection process is performed to obtain the path selection signal.

[0033] The fused feature vector is input into the adaptation transformation matrix according to the path selection signal and linearly transformed to obtain the transformed feature vector.

[0034] The fused feature vector and the transformed feature vector are subjected to residual weighted summation, with the weight coefficients being the normalized values ​​of the process difference coefficients, to obtain the residual fused vector.

[0035] The residual fusion vector is subjected to batch normalization and activation function processing to obtain the adapted feature vector.

[0036] Optionally, the step of optimizing circuit parameters using a multi-objective genetic algorithm based on the performance prediction matrix to obtain the optimal combination of device sizes includes:

[0037] Based on the power consumption, delay, and area prediction values ​​in the performance prediction matrix, a multi-objective fitness function is constructed to obtain a fitness evaluation vector.

[0038] Based on the fitness evaluation vector, the initial device size population is subjected to non-dominated sorting and crowding distance calculation to obtain a hierarchical population structure.

[0039] Individuals in the hierarchical population structure are subjected to process-constrained simulated binary crossover and polynomial mutation operations. The crossover probability is set to 0.9 when the fitness of an individual ranks in the top 50%, and 0.7 otherwise, to obtain the offspring population.

[0040] The offspring population is re-predicted using the performance prediction matrix. Individuals are retained when the predicted power consumption is less than a set threshold and the delay meets the timing constraints, resulting in a filtered population.

[0041] Based on the screened population, Pareto front extraction and diversity preservation processing are performed to obtain the optimal device size combination.

[0042] Optionally, the step of performing SPICE simulation verification on the optimal device size combination to obtain verified integrated circuit design parameters includes:

[0043] The device width-to-length ratio and bias voltage parameters in the optimal device size combination are input into the SPICE netlist generator to perform circuit netlist construction processing, and a simulation netlist file is obtained.

[0044] Monte Carlo process deviation analysis was performed based on the simulation netlist file, with 1000 random simulations to obtain a performance statistics data set.

[0045] The power consumption, delay, and area simulation results in the performance statistics set are compared with the performance prediction matrix to calculate the deviation and obtain the prediction error vector.

[0046] Based on the prediction error vector, an error threshold judgment process is performed. When the power consumption deviation is less than 5% and the delay deviation is less than 3%, parameter confirmation is performed. Otherwise, R-PTT prediction model parameter fine-tuning is triggered to obtain a verification status indicator.

[0047] Based on the verification status identifier, the device size parameters that have passed verification are subjected to DRC and LVS rule checks to obtain the verified integrated circuit design parameters.

[0048] Secondly, this application provides an integrated circuit design optimization system based on data mining, the integrated circuit design optimization system based on data mining comprising:

[0049] The extraction module is used to extract process features from multi-process node circuit design data using EDA tools to obtain transistor parameter vector sets.

[0050] The enhancement module is used to perform data enhancement processing based on the transistor parameter vector set through a two-layer process-aware generative adversarial network to obtain a cross-node circuit sample library.

[0051] The prediction module is used to input the cross-node circuit sample library into the R-PTT prediction model to predict power consumption delay and obtain a performance prediction matrix;

[0052] The screening module is used to optimize circuit parameters based on the performance prediction matrix using a multi-objective genetic algorithm to obtain the optimal combination of device sizes.

[0053] The verification module is used to perform SPICE simulation verification on the optimal device size combination to obtain verified integrated circuit design parameters.

[0054] Thirdly, a data mining-based integrated circuit design optimization device is provided, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor invokes the instructions in the memory to cause the data mining-based integrated circuit design optimization device to execute the aforementioned data mining-based integrated circuit design optimization method.

[0055] Fourthly, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a computer, cause the computer to perform the aforementioned data mining-based integrated circuit design optimization method.

[0056] The technical solution provided in this application utilizes EDA tools to extract process features from multi-process node circuit design data to obtain transistor parameter vector sets. This effectively solves the problem that traditional methods cannot uniformly process data from different process nodes, ensuring the comparability and consistency of design data across process nodes. A two-layer process-aware generative adversarial network (GAN) performs data augmentation to obtain a cross-node circuit sample library, innovatively addressing the key bottleneck of scarce design data for new process nodes. Through an intelligent data generation mechanism, it can synthesize high-quality design samples for data-scarce process nodes, significantly improving the training effect of data mining models. An R-PTT prediction model performs power consumption and delay prediction to obtain a performance prediction matrix, overcoming the limitation of traditional prediction models in handling process differences. Through process-aware attention mechanisms and adaptive transfer techniques, it achieves accurate performance prediction across process nodes, providing a reliable objective function for design optimization. A multi-objective genetic algorithm optimizes circuit parameters to obtain the optimal combination of device dimensions, effectively balancing multiple conflicting design objectives such as power consumption, delay, and area, avoiding design bias problems that may occur with traditional single-objective optimization. SPICE simulation verification process yields verified integrated circuit design parameters, establishing a complete closed-loop verification mechanism to ensure the practical feasibility and performance reliability of the optimization results, and avoiding deviations between theoretical optimization and practical applications.

[0057] In specific integrated circuit design optimization applications, the two-layer process-aware generative adversarial network algorithm of this application, through hierarchical feature extraction and cross-domain generation mechanisms, can accurately capture the essential differences and common patterns between different process nodes. The generated synthetic samples not only maintain consistency with real data in statistical characteristics, but more importantly, preserve the correctness of process physical characteristics. The process migration adaptation layer algorithm in the R-PTT prediction model can intelligently adjust the prediction strategy according to the degree of process difference through residual connection and adaptive transformation mechanisms. When the process difference is small, the original features are maintained to avoid overfitting; when the process difference is large, adaptation transformation is activated to compensate for process offset. This adaptive mechanism significantly improves the prediction accuracy of the model under different process scenarios. The multi-objective genetic algorithm combined with the crossover and mutation operation of process constraints ensures that the generated design scheme satisfies both performance optimization objectives and actual manufacturing constraints, avoiding unmanufacturable design schemes that may be generated by traditional optimization algorithms, and providing directly usable optimization results for engineering practice. Attached Figure Description

[0058] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a schematic diagram of one embodiment of the integrated circuit design optimization method based on data mining in this application.

[0060] Figure 2 This is a schematic diagram of one embodiment of the integrated circuit design optimization system based on data mining in this application.

[0061] Figure 3 This is a schematic block diagram of the integrated circuit design optimization device based on data mining in an embodiment of the present invention. Detailed Implementation

[0062] This application provides a data mining-based integrated circuit design optimization method and system. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" or "having" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0063] For ease of understanding, the specific process of the embodiments of this application is described below. Please refer to [link / reference]. Figure 1 One embodiment of the integrated circuit design optimization method based on data mining in this application includes:

[0064] Step S101: Use EDA tools to extract process features from multi-process node circuit design data to obtain transistor parameter vector sets;

[0065] Step S102: Based on the transistor parameter vector set, perform data augmentation processing through a two-layer process-aware generative adversarial network to obtain a cross-node circuit sample library;

[0066] Step S103: Input the cross-node circuit sample library into the R-PTT prediction model to predict power consumption and delay, and obtain the performance prediction matrix;

[0067] Step S104: Based on the performance prediction matrix, optimize the circuit parameters using a multi-objective genetic algorithm to obtain the optimal combination of device sizes;

[0068] Step S105: Perform SPICE simulation verification on the optimal device size combination to obtain the verified integrated circuit design parameters.

[0069] It is understood that the executing entity of this application can be an integrated circuit design optimization system based on data mining, or it can be a terminal or a server; no specific limitation is made here. This application's embodiments use a server as an example for illustration.

[0070] Specifically, EDA tools are used to extract process features from multi-process node circuit design data. First, key process parameters such as transistor channel length, oxide thickness, and doping concentration for different process nodes are extracted from the SPICE model library. Channel length reflects the device's dimensional characteristics, oxide thickness affects gate capacitance and leakage current, and doping concentration determines threshold voltage and carrier mobility. Next, the circuit topology is feature-encoded, converting basic topologies such as common-source amplifiers, differential pairs, and current mirrors in analog circuits into numerical coding matrices, while recording the aspect ratio and bias conditions of each transistor. Then, data annotation is performed on three key performance indicators: power consumption, delay, and area. Simulations are used to obtain the performance label vector corresponding to each design sample. Finally, the process parameter set and performance label vectors are concatenated to form a high-dimensional feature vector containing both process and performance information. A unique identifier containing process node information is assigned to each vector, completing the construction of the transistor parameter vector set.

[0071] A two-layer process-aware generative adversarial network (GAN) inputs transistor parameter vector sets into a first-layer process encoder and a second-layer parameter encoder. The first-layer encoder specifically handles process node-related physical parameters, such as process angles and temperature ranges, mapping these parameters into 128-dimensional process embedding vectors via a multilayer perceptron. The second-layer encoder processes circuit design parameters, including device dimensions and bias voltages, generating corresponding parameter embedding vectors. Random noise vectors, serving as the source of randomness in the generation process, are concatenated and fused with the process embedding vectors and parameter embedding vectors in a three-layer process to form a two-layer conditional input vector. A dual-path parameter generator receives this input vector and generates process-related parameters and design-related parameters through two parallel generation paths, then merges them into a synthetic design parameter vector. The two-layer process discriminator includes a true / false discrimination branch and a process classification branch. When the first-layer discrimination probability is greater than 0.7 and the second-layer process classification accuracy is greater than 0.8, it indicates that the generated parameter vector is both realistic and conforms to the characteristics of the target process node. In this case, a discrimination probability matrix is ​​generated and the sample is retained; otherwise, the parameter generation process is re-executed until the quality requirements are met.

[0072] The R-PTT prediction model inputs data from a cross-node circuit sample library into a process feature attention head and a design parameter attention head, respectively. The process feature attention head uses a self-attention mechanism to calculate the correlation weights between different process parameters, while the design parameter attention head calculates the dependencies between design variables such as device size and bias voltage. Attention weights are obtained through the dot product of the query matrix, key matrix, and value matrix, reflecting the importance distribution of the input features. The cross-attention head performs cross-domain feature fusion of the process weight matrix and parameter weight matrix, establishing a mapping relationship between process features and design parameters, and generating a fused feature vector. The process migration adaptation layer first calculates the feature distance between the source and target process nodes, obtaining the process difference coefficient through Euclidean distance metric. When the process difference coefficient is greater than 0.5, the adaptation transformation module is activated, linearly transforming the fused feature vector through a learnable adaptation transformation matrix to compensate for systematic differences between different process nodes. The multi-task regression layer contains three parallel output branches, predicting power consumption, delay, and area metrics respectively. Each branch uses a fully connected layer structure, mapping the adapted feature vector to the corresponding performance prediction value.

[0073] The multi-objective genetic algorithm first constructs a multi-objective fitness function based on the predicted values ​​of power consumption, delay, and area in the performance prediction matrix, transforming the three performance indicators into minimization objectives. The quality of individuals is evaluated using the weight vector method or Pareto dominance relation. The initial device size population contains multiple candidate design schemes, with each individual representing a specific combination of device aspect ratios. The non-dominated sorting algorithm divides the individuals in the population into different levels according to Pareto dominance relations: the first level represents non-dominated solutions, the second level represents solutions dominated by the first level, and so on. Crowding distance calculation is used to maintain the diversity of solutions within the same level, assessing the rarity of each individual by calculating its distance from neighboring individuals in the objective space. A process constraint-simulated binary crossover operation generates offspring individuals considering manufacturing constraints. The crossover probability is set to 0.9 when the individual's fitness ranks in the top 50%, and 0.7 when it ranks lower, controlling the algorithm's convergence speed and exploration capability through adaptive crossover probability. The multinomial mutation operation randomly perturbs the device size parameters of individuals, with the mutation amplitude controlled by the distribution exponent, ensuring that the generated offspring individuals retain both parental characteristics and a certain degree of innovation.

[0074] SPICE simulation verification converts the optimal device size combination into a standard SPICE netlist format. The netlist file contains the model parameters, connections, and simulation commands for each transistor. Monte Carlo process deviation analysis simulates process variations in actual manufacturing through random sampling. 1000 simulation runs are set up, with device parameters varying randomly within a specified range in each simulation to simulate the impact of process corners, voltage variations, temperature fluctuations, and other factors on circuit performance. The performance statistics dataset includes power consumption, delay, and area values ​​obtained from each simulation. Statistical analysis yields the mean, standard deviation, and distribution characteristics of the performance indicators. The prediction error vector is generated by calculating the absolute and relative errors between the simulation results and the predicted values. When the power consumption deviation is less than 5% and the delay deviation is less than 3%, the accuracy of the prediction model meets the requirements, and the parameter verification process is executed. If the error exceeds the threshold, the R-PTT prediction model parameter fine-tuning process is triggered, updating the model weights using new simulation data. DRC rule checks verify whether the device dimensions meet manufacturing constraints such as minimum linewidth and minimum spacing, while LVS checks ensure the consistency between the layout and the schematic.

[0075] In one specific embodiment, the process of performing step S101 may specifically include the following steps:

[0076] Numerical extraction of transistor channel length, oxide layer thickness, and doping concentration at multiple process nodes yields a set of fundamental process parameters.

[0077] Based on the set of basic process parameters, feature encoding is performed on the circuit topology and device dimensions to obtain the design parameter encoding matrix;

[0078] Based on the design parameter encoding matrix, data annotation processing is performed on power consumption, delay, and area performance indicators to obtain performance label vectors;

[0079] The process basic parameter set and performance label vector are concatenated to obtain a high-dimensional feature vector.

[0080] The high-dimensional feature vectors are processed by assigning process node identifier codes to obtain the transistor parameter vector set.

[0081] Specifically, key physical process parameters are extracted from the PDK device model library for each process node using EDA tools. Transistor channel length represents the minimum feature size of the device; for example, the nominal channel length is 28nm in the 28nm process, 14nm in the 14nm process, and 7nm in the 7nm process. These values ​​are directly read from the SPICE model parameters provided by the process manufacturers. Oxide thickness reflects the physical thickness of the gate dielectric, affecting the device's gate capacitance and leakage current characteristics. It is obtained by analyzing the TOX parameters in the device model; the oxide thickness is typically 1.5nm in the 28nm process, approximately 1.2nm in the 14nm process, and approximately 0.9nm in the 7nm process. Doping concentration describes the density distribution of impurity atoms in the silicon substrate, affecting the device's threshold voltage and carrier mobility. It is extracted from the NSUB parameters in the model parameters, and the values ​​typically range from 10^17 to 10^19 cm^-3. These values ​​are organized into a set of basic process parameters, with each process node corresponding to a parameter vector, which includes channel length, oxide thickness, doping concentration, and other key process parameters such as mobility and junction depth.

[0082] Feature encoding converts the circuit topology into a numerical representation. First, it identifies the basic building blocks in the circuit, such as common-source amplifiers, differential pairs, current mirrors, and common-gate cascades. Each topology is assigned a unique code identifier; for example, a common-source amplifier is encoded as 1, a differential pair as 2, a current mirror as 3, and composite topologies are represented by combined codes. Device size information includes the width W and length L of each transistor. These values ​​are directly read from the circuit netlist. For example, the NMOS transistor in the input stage differential pair has a width of 5μm and a length of 0.5μm, recorded as W / L=5 / 0.5. Simultaneously, layout-related parameters such as the multi-index M and single-index width, as well as operating point information such as bias voltage and current, are recorded. This information is encoded into a matrix, with rows representing different devices in the circuit and columns representing various design parameters, forming a design parameter encoding matrix. The matrix dimension is the number of devices × the number of parameter types.

[0083] Data annotation processing obtains circuit performance metrics through SPICE simulation. Power consumption annotation includes static power consumption and dynamic power consumption. Static power consumption is calculated by multiplying the static current of each device by the supply voltage using DC analysis. Dynamic power consumption is obtained by integrating the current change during the switching process using transient analysis. Delay annotation measures the propagation delay and settling time of the circuit using AC analysis or transient analysis. For analog circuits, the delay characteristic corresponding to a -3dB bandwidth is typically measured, while for digital circuits, the propagation delay time from input to output is measured. Area annotation is calculated based on the layout dimensions of the devices, including the area of ​​active devices and wiring. The actual occupied area of ​​each transistor is extracted using layout tools, plus the area overhead of interconnects and vias. These three performance metrics constitute a performance tag vector, with each circuit design sample corresponding to a three-dimensional vector. For example, the performance tag vector for a certain operational amplifier is [power consumption 2.5mW, delay 100ps, area 0.01mm²].

[0084] Dimensional concatenation merges the set of fundamental process parameters and the performance label vector into a unified feature representation. The set of fundamental process parameters is typically 10-15 dimensional, containing the main physical parameters of the process. The performance label vector is 3 dimensional, containing power consumption, latency, and area. The concatenation operation is implemented through array concatenation, joining the two vectors end-to-end to form a higher-dimensional feature vector. The resulting high-dimensional feature vector has dimensions equal to the sum of the process parameter dimension and the performance label dimension, typically 13-18 dimensions. This concatenation method preserves the correspondence between process information and performance information, enabling subsequent machine learning algorithms to utilize both process features and performance targets for training and prediction simultaneously.

[0085] A process node identifier is assigned to each high-dimensional feature vector, adding process node identity information. The identifier uses a hierarchical coding structure. The first layer represents the process technology node, such as 001 for 28nm, 002 for 14nm, and 003 for 7nm. The second layer represents the design type, such as 01 for operational amplifiers, 02 for comparators, and 03 for reference circuits. The third layer represents the sample number, using an incremental numeric encoding. The identifier format is "process node-design type-sample number", such as "001-01-0523" representing the 523rd design sample of an operational amplifier using the 28nm process. The identifier is encoded as a numerical value and appended to the end of the high-dimensional feature vector, forming a transistor parameter vector set. Each vector contains process parameters, design parameters, performance labels, and process node identification information.

[0086] In one specific embodiment, the process of performing step S102 may specifically include the following steps:

[0087] The transistor parameter vector set is input into the first-layer process encoder and the second-layer parameter encoder respectively for two-layer feature extraction processing to obtain the process embedding vector and the parameter embedding vector.

[0088] A two-layer conditional input vector is obtained by performing a three-layer splicing and fusion process based on the random noise vector, the process embedding vector, and the parameter embedding vector.

[0089] The dual-layer conditional input vector is input into the dual-path parameter generator for parallel adversarial generation processing to obtain the synthetic design parameter vector.

[0090] Based on the synthetic design parameter vector, a two-layer process discriminator is used to perform true / false discrimination and process classification. When the first-layer discrimination probability is greater than 0.7 and the second-layer process classification accuracy is greater than 0.8, a discrimination probability matrix is ​​generated; otherwise, the parameter generation process is re-executed.

[0091] The synthetic design parameter vectors that pass the two-layer discrimination are subjected to process consistency verification to obtain a cross-node circuit sample library.

[0092] Specifically, the feature extraction process of the two-layer process-aware generative adversarial network separates the transistor parameter vector set according to data type. The first-layer process encoder specifically handles process-related parameters, including physical process features such as channel length, oxide thickness, doping concentration, and carrier mobility. The process encoder adopts a three-layer fully connected neural network structure. The input layer receives the original process parameters, the first hidden layer contains 256 neurons, the second hidden layer contains 128 neurons, and the output layer generates a 128-dimensional process embedding vector. The encoding process maps the original process parameters to a high-dimensional semantic space through nonlinear transformation. Each dimension represents a specific combination of process features, such as the first 32 dimensions encoding device size-related characteristics, the middle 32 dimensions encoding electrical characteristics, and the last 64 dimensions encoding process change sensitivity. The second-layer parameter encoder handles circuit design-related parameters, including design variables such as device aspect ratio, bias voltage, and topology encoding. The parameter encoder also adopts a three-layer network structure, but it is specifically optimized for the distribution characteristics of design parameters, outputting a 128-dimensional parameter embedding vector, where the first 64 dimensions represent device size features, and the last 64 dimensions represent circuit topology and bias features. The three-layer concatenation and fusion process combines vectors from three different sources into a unified conditional input. The random noise vector is a 100-dimensional Gaussian-distributed random number, used to introduce randomness and diversity into the generation process, ensuring that the generated design parameters have a sufficient range of variation. The process embedding vector and parameter embedding vector are each 128-dimensional, containing high-level semantic features extracted from the original data. The concatenation operation joins the three vectors end-to-end in a specific order, forming a 356-dimensional two-layer conditional input vector. The concatenation order is: random noise vector first, process embedding vector in the middle, and parameter embedding vector last. This arrangement allows the generator to first use randomness to determine the generation direction, then adjust the generation strategy according to process constraints, and finally combine the design parameter features to complete the specific parameter generation. Batch normalization is also performed during the concatenation process to ensure that the numerical ranges of the vectors from different sources are consistent, preventing certain features from dominating the generation process.

[0093] The dual-path parameter generator receives a 356-dimensional conditional input vector and processes process-sensitive parameters and design-independent parameters through two parallel generation paths. The first path specifically generates parameters strongly correlated with the process node, such as device threshold voltage and carrier mobility—physical parameters that change significantly with process variations. This path comprises a four-layer fully connected network, progressively expanding the input dimension from 356 to 256, 128, and 64, ultimately outputting a 32-dimensional process-sensitive parameter vector. The second path generates parameters related to the design strategy but relatively insensitive to process changes, such as circuit topology and device connectivity choices. It also employs a four-layer network structure, outputting a 48-dimensional design strategy parameter vector. The outputs of the two paths are merged through a weighted fusion mechanism, with weights adaptively adjusted based on the characteristics of the target process node, ultimately forming an 80-dimensional synthetic design parameter vector. This vector contains complete design information adapted to the characteristics of the target process node.

[0094] A two-layer process discriminator performs dual verification of the synthesized design parameter vector. The first layer discriminator is responsible for authenticity detection, determining whether the generated parameter vector possesses the statistical characteristics of a real design. This authenticity detection employs a binary classification network structure. An 80-dimensional synthesized parameter vector is input, and a single probability value is output through a three-layer fully connected network, representing the likelihood that the parameter vector represents a real design. The network uses a sigmoid activation function to ensure the output probability is between 0 and 1; a probability greater than 0.7 indicates sufficient authenticity of the generated parameters. The second layer discriminator performs process classification, determining whether the generated parameter vector conforms to the feature distribution of the target process node. Process classification uses a multi-classification network structure, with the output dimension equal to the number of process node types. For example, when supporting 28nm, 14nm, and 7nm processes, it outputs a 3-dimensional probability vector, normalized using a softmax function. The process classification accuracy is obtained by calculating the matching degree between the predicted and target process nodes; an accuracy greater than 0.8 indicates that the generated parameters meet the process requirements. Only when both the true / false discrimination probability is greater than 0.7 and the process classification accuracy is greater than 0.8 will a discrimination probability matrix containing two probability values ​​be generated and the sample be accepted. Otherwise, the parameter vector will be marked as unqualified and the parameter generation process will be re-executed.

[0095] Process conformance verification performs a final quality check on the synthesized design parameter vectors that have passed the two-layer discrimination. The verification process includes two aspects: physical constraint checking and performance rationality checking. Physical constraint checking verifies whether the generated device parameters meet process manufacturing limitations, such as device width not being less than the minimum design rule, length not exceeding the layout boundary, and bias voltage within the process-allowed power supply range. This process compares the generated parameters against the constraints of the corresponding process node by searching the process design rule library; parameter vectors that do not meet the constraints are automatically discarded. Performance rationality checking uses a fast performance estimation model to predict the basic performance indicators of the generated design, verifying whether indicators such as power consumption, delay, and area are within reasonable ranges, avoiding the generation of physically feasible but poorly performing design schemes. The verified synthesized design parameter vectors are stored according to process nodes, forming a cross-node circuit sample library. Each sample contains design parameter information and the corresponding process node identifier.

[0096] In one specific embodiment, the process of executing step S103 may specifically include the following steps:

[0097] The process features and design parameters in the cross-node circuit sample library are respectively input into the process feature attention head and the design parameter attention head to perform multi-head attention weight calculation processing to obtain the process weight matrix and the parameter weight matrix.

[0098] Based on the process weight matrix and parameter weight matrix, cross-domain feature fusion processing is performed using cross-attention heads to obtain the fused feature vector;

[0099] The fused feature vector is input into the process migration adaptation layer for residual connection transformation. When the process node difference is greater than 0.5, the adaptation transformation matrix is ​​activated to obtain the adapted feature vector.

[0100] Based on the adapted feature vector, power consumption, latency and area are predicted in parallel through a multi-task regression layer to obtain a multi-dimensional performance output vector.

[0101] The multidimensional performance output vector is reconstructed to obtain the performance prediction matrix.

[0102] Specifically, the multi-head attention mechanism of the R-PTT prediction model separates and processes data from the cross-node circuit sample library according to feature type. Process features include physical process parameters extracted from samples, such as channel length, oxide thickness, and doping concentration. Design parameters include circuit design information such as device aspect ratio, bias voltage, and topology encoding. The process feature attention head employs a self-attention mechanism, using the process feature vector as the input source for three matrices: query matrix Q, key matrix K, and value matrix V. These three matrices are generated through a linear transformation layer. The dimension of the query matrix Q is the number of samples multiplied by the feature dimension, while the key matrix K and value matrix V have the same dimension. The attention weights are obtained by calculating the matrix product of Q and the transpose of K, then scaling by dividing by the square root of the feature dimension, and finally normalizing using a softmax function to ensure that the sum of the weights in each row is 1. The process weight matrix reflects the correlation strength between different process features, such as the correlation between channel length and carrier mobility, and the dependence of oxide thickness on gate capacitance. The design parameter attention head uses the same calculation process, but specifically deals with circuit design-related features to generate a parameter weight matrix, which reveals the intrinsic relationship between device size, bias conditions, and topology.

[0103] Cross-attention heads are used for cross-domain feature fusion. The process weight matrix serves as the source of keys and values, while the parameter weight matrix serves as the source of queries. A mapping relationship between process features and design parameters is established through a cross-attention mechanism. The fusion process first calculates the dot product of the parameter query matrix and the process key matrix to obtain a cross-domain attention score. This score represents the degree of attention each design parameter pays to different process features. The attention score is then normalized using softmax and multiplied by the process value matrix to generate the fused feature representation. This cross-domain fusion mechanism enables the model to learn the impact of process changes on design parameters. For example, when migrating from a 28nm process to a 7nm process, the device aspect ratio needs to be adjusted accordingly to compensate for the performance changes caused by process scaling. The dimension of the fused feature vector is equal to the dimension of the original feature vector, but it contains the interaction information between the process and design parameters, providing rich semantic representations for subsequent process migration processing.

[0104] The process transfer adaptation layer first calculates the difference between the process node of the current input sample and the baseline process node during model training. This difference is obtained by calculating the Euclidean distance between the feature vectors of the two process nodes, with the distance value normalized to between 0 and 1. When the process node difference is greater than 0.5, it indicates a significant difference between the source and target processes, requiring compensation using the adaptation transformation matrix. The adaptation transformation matrix is ​​a learnable parameter matrix with dimensions of feature dimension × feature dimension, learning the parameter mapping relationship between different process nodes through training. The transformation process multiplies the fused feature vector with the adaptation matrix to obtain the transformed feature vector after process correction. The residual connection mechanism performs a weighted sum of the original fused feature vector and the transformed feature vector. The weight coefficients are determined by the process difference; the greater the difference, the higher the weight of the transformation result. When the process difference is less than or equal to 0.5, the system considers the process difference to be small and directly performs an identity transformation, keeping the original features unchanged. The adapted feature vector combines the original design information and process transfer compensation, accurately reflecting the feature representation of the design under the target process.

[0105] The multi-task regression layer comprises three parallel prediction branches, responsible for predicting power consumption, latency, and area, respectively. Each branch employs an independent fully connected network structure. The power consumption prediction branch contains two hidden layers: the first layer has 128 neurons, and the second layer has 64 neurons. The output layer outputs a single neuron, providing the predicted power consumption value. The latency and area prediction branches use the same network structure but have independent weight parameters, allowing each branch to specifically learn the prediction patterns for its corresponding performance metric. All three branches share the same adapted feature vector as input but generate targeted prediction results through different network weights. Power consumption prediction focuses on the static and dynamic power consumption characteristics of the device, latency prediction emphasizes signal propagation and setup time characteristics, and area prediction considers device layout and routing overhead. The output of each branch is processed using appropriate activation functions: ReLU is used for power consumption and area to ensure positive outputs, while the Softplus function is used for latency to ensure smooth output. The outputs of the three prediction branches are combined to form a 3D multidimensional performance output vector, containing complete performance prediction information for the corresponding design under the target process technology.

[0106] The matrix reconstruction process organizes the multidimensional performance output vectors of multiple samples into a unified matrix format. The reconstruction process treats each 3D output vector as a row in the matrix according to the sample order, forming a performance prediction matrix of sample number × 3. The first column of the matrix contains the predicted power consumption values ​​for all samples, the second column contains the predicted delay values, and the third column contains the predicted area values. The reconstruction process also includes post-processing steps, such as outlier detection and boundary constraints, to ensure that the prediction results are within a physically reasonable range. Outlier detection uses statistical methods to identify predicted values ​​that significantly deviate from the normal range, while boundary constraints limit the prediction results to the maximum and minimum values ​​allowed by the process technology. The performance prediction matrix provides the basis for calculating the objective function for subsequent multi-objective optimization algorithms. Each row represents the predicted performance of a candidate design scheme, and each column represents the distribution of an optimization objective.

[0107] In one specific embodiment, the process of performing residual connection transformation on the input process migration adaptation layer of the fused feature vector can specifically include the following steps:

[0108] The fused feature vector is subjected to process node difference quantification calculation, and the process difference coefficient is obtained based on the feature distance between the source process node and the target process node.

[0109] Threshold judgment is performed based on the process difference coefficient. When the process difference coefficient is greater than 0.5, the adaptation transformation module is activated; otherwise, the pass-through connection process is performed to obtain the path selection signal.

[0110] Based on the path selection signal, the fused feature vector is input into the adaptation transformation matrix for linear transformation processing to obtain the transformed feature vector;

[0111] The fused feature vector and the transformed feature vector are subjected to residual weighted summation, with the weight coefficients being the normalized values ​​of the process difference coefficients, to obtain the residual fused vector.

[0112] Batch normalization and activation function processing are applied to the residual fusion vector to obtain the adapted feature vector.

[0113] Specifically, the fused feature vector is separated according to feature type, and the portion containing process node identifiers and process physical parameters is extracted as the process feature sub-vector. The source process node feature vector contains the process parameters corresponding to the current input sample, such as the key physical parameters of the 28nm process: channel length 28nm, oxide thickness 1.5nm, and doping concentration 5×10^18 cm-3. The target process node feature vector represents the target process environment that the model expects to predict, such as the parameters of the 7nm process: channel length 7nm, oxide thickness 0.9nm, and doping concentration 8×10^18 cm-3. The feature distance is calculated using a weighted Euclidean distance formula. Different process parameters are assigned different weights according to their impact on circuit performance. The channel length has the highest weight of 0.4, the oxide thickness has a weight of 0.3, the doping concentration has a weight of 0.2, and other parameters have a weight of 0.1. The distance calculation result is mapped to the range of 0 to 1 using the sigmoid function to obtain the process difference coefficient. This coefficient reflects the similarity between the source and target processes; the larger the value, the more significant the process difference.

[0114] The threshold judgment process compares the process difference coefficient with a preset threshold of 0.5, generating a binary path selection signal to control subsequent processing. When the process difference coefficient is greater than 0.5, it indicates a significant difference between the source and target processes, requiring process compensation through the adaptation transformation module. In this case, the path selection signal is set to 1, activating the adaptation transformation path. When the process difference coefficient is less than or equal to 0.5, the two process nodes are considered relatively close, and accurate prediction can be obtained directly using the original features. The path selection signal is set to 0, enabling the direct connection path. The threshold of 0.5 is selected based on extensive experimental data statistics. This value effectively distinguishes between cases requiring process adaptation and those not requiring adaptation, avoiding unnecessary transformation processing for similar processes while ensuring that significantly different processes are adequately compensated. The path selection signal serves as the control condition for subsequent processing modules, implementing an adaptive process migration strategy.

[0115] The adaptation transformation matrix is ​​a learnable parameter matrix obtained through training. Its dimension is the fused feature vector dimension multiplied by the fused feature vector dimension, specifically used to model the parameter mapping relationship between different process nodes. When the path selection signal is 1, the fused feature vector and the adaptation transformation matrix undergo matrix multiplication to achieve linear transformation. Each row of the transformation matrix corresponds to one dimension of the output feature, and each column corresponds to one dimension of the input feature. The values ​​of the matrix elements reflect the contribution of the input feature to the output feature. The transformation process can learn the parameter adjustment rules brought about by process scaling, such as scaling the device width proportionally and adjusting the threshold voltage accordingly when migrating from 28nm to 7nm. When the path selection signal is 0, the system performs an identity transformation, meaning the transformed feature vector equals the original fused feature vector, avoiding unnecessary modifications to similar processes. The transformed feature vector contains a feature representation optimized for the target process node, more accurately reflecting the characteristics of the design under the target process.

[0116] The residual weighted summation process linearly combines the original fused feature vector and the transformed feature vector, with weight coefficients determined by the process difference coefficient, achieving adaptive feature fusion. The weight coefficient calculation employs normalization, mapping the process difference coefficient to a weight α in the transformed feature vector, while the weight of the original feature vector is 1-α, ensuring the sum of the two weights is 1. When the process difference coefficient is close to 1, the weight of the transformed feature vector is close to 1, and the weight of the original feature vector is close to 0, indicating that process adaptation is primarily based on the transformation result. When the process difference coefficient is close to 0, the weight of the original feature vector is close to 1, and the weight of the transformed feature vector is close to 0, indicating that the original features are largely preserved. The residual fused vector is calculated using a weighted summation formula. This vector combines the original design information and process adaptation information, preserving the essential characteristics of the design while making necessary adjustments for the target process. The residual connection mechanism also facilitates gradient propagation, avoiding the gradient vanishing problem in deep networks.

[0117] Batch normalization and activation function processing standardize and nonlinearly transform the residual fusion vector. Batch normalization calculates the mean and variance of all samples in the current batch for each corresponding dimension, adjusting the values ​​of each feature dimension to a standard normal distribution with a mean of 0 and a variance of 1. The normalization process includes learnable scaling parameters γ and offset parameters β, allowing the model to adjust the distribution characteristics of the features as needed. The activation function used is the GELU function, which has smoother gradient characteristics than the traditional ReLU function, providing a more stable training process. The GELU function is implemented using a Gaussian error function, providing small but non-zero gradients in the negative region, which helps the network learn richer feature representations. After activation function processing, the adapted feature vector is obtained. This vector undergoes process difference quantization, adaptive transformation, residual fusion, and normalization, containing complete feature information optimized for the target process node.

[0118] In one specific embodiment, the process of executing step S104 may specifically include the following steps:

[0119] Based on the power consumption, delay, and area prediction values ​​in the performance prediction matrix, a multi-objective fitness function is constructed to obtain the fitness evaluation vector.

[0120] Based on the fitness evaluation vector, the initial device size population is subjected to non-dominated sorting and crowding distance calculation to obtain a hierarchical population structure.

[0121] Individuals in the hierarchical population structure are subjected to process-constrained simulation of binary crossover and polynomial mutation operations. The crossover probability is set to 0.9 when the fitness of an individual ranks in the top 50%, and 0.7 otherwise, to obtain the offspring population.

[0122] The performance indicators of the offspring population are re-predicted using the performance prediction matrix. Individuals are retained when the predicted power consumption is less than the set threshold and the delay meets the timing constraints, resulting in the filtered population.

[0123] Pareto front extraction and diversity preservation processing were performed on the screened population to obtain the optimal combination of device sizes.

[0124] Specifically, the objective fitness function construction process converts the three performance indicators—power consumption, delay, and area—in the performance prediction matrix into fitness values ​​that the optimization algorithm can handle. Since all three indicators are minimization objectives, the fitness function employs a reciprocal transformation and normalization. The power consumption fitness is calculated as 1 / (predicted power consumption + ε), where ε is a very small positive number (1e-6) to prevent division by zero. The delay fitness and area fitness use the same reciprocal transformation. To avoid the influence of numerical differences between indicators of different dimensions on the optimization process, the system normalizes the three fitness components separately, unifying their numerical range to between 0 and 1. Normalization uses a maximum-minimum standardization method, subtracting the minimum value of that dimension from each fitness component and then dividing by the difference between the maximum and minimum values. The multi-objective fitness evaluation vector is a 3-dimensional vector, with each dimension corresponding to the normalized fitness value of a performance indicator. The vector's magnitude reflects the overall performance level of the individual, and the vector direction reflects performance bias characteristics. The fitness evaluation vector also includes a constraint violation penalty term; when the device size exceeds the manufacturing process limitations, the corresponding fitness value is multiplied by a penalty factor for weight reduction.

[0125] The non-dominated sorting process hierarchically sorts individuals in the initial device-size population according to Pareto dominance. Each individual represents a specific set of device-size parameters, such as the input transistor width, load transistor width, and bias current design variables in a differential amplifier. Dominance is determined by comparing the fitness evaluation vectors of two individuals; individual A dominates individual B if and only if A is not inferior to B in all objectives and is strictly superior to B in at least one objective. The non-dominated sorting algorithm first identifies non-dominated individuals in the population that form the first frontier F1, then removes individuals dominated by F1 from the remaining individuals, repeating this process to obtain the second frontier F2, third frontier F3, and so on, forming a hierarchical structure. Crowding distance calculation is used to maintain the diversity of individuals within the same frontier. For each individual within the frontier, the sum of its distances to neighboring individuals in each objective dimension is calculated. The crowding distance of boundary individuals is set to infinity to ensure their retention, while the crowding distance of intermediate individuals reflects their sparsity in the objective space. The hierarchical population structure sorts individuals according to frontier level and crowding distance, with individuals of lower frontier level having higher priority, and individuals with larger crowding distances within the same frontier having higher priority.

[0126] The simulated binary crossover operation, considering manufacturing constraints, generates offspring individuals. The crossover process selects two parent individuals, and the crossover probability is determined based on their fitness ranking. Fitness ranking is calculated by combining frontier level and crowding distance; the top 50% of individuals are considered high-quality and have a crossover probability of 0.9, while the remaining individuals have a crossover probability of 0.7. The simulated binary crossover uses a distribution index parameter to control the similarity between offspring and parent individuals. The distribution index is set to 20, ensuring that offspring are generated near their parents but possess some exploratory ability. The crossover process is performed independently for each design variable, and the generated offspring must meet manufacturing constraints such as minimum device width, maximum length, and bias voltage range. A multinomial mutation operation randomly perturbs the crossover individuals, with a mutation probability set to 1 / number of variables, ensuring that on average, each individual mutates one variable. The mutation amplitude is controlled by a multinomial distribution with a distribution index of 20, making small-amplitude mutations more likely than large-amplitude mutations, maintaining population stability while introducing necessary diversity. The offspring population is the same size as the parent population, providing a sufficient number of candidate individuals for subsequent performance evaluation and selection operations.

[0127] The performance metric re-prediction process inputs each individual in the offspring population into the R-PTT prediction model to obtain its predicted power consumption, delay, and area at the target process node. The prediction process first converts the individual's device size parameters into the model input format, including feature encodings such as aspect ratio, bias conditions, and topology. The model's output prediction values ​​are then denormalized to restore the original units, such as power consumption in milliwatts, delay in picoseconds, and area in square millimeters. The constraint checking process verifies whether the prediction results meet design specifications. Power consumption thresholds are set according to the application scenario; for example, low-power applications require power consumption less than 5mW. Delay constraints are determined according to timing requirements; for example, high-speed applications require delay less than 100ps. Individuals that meet the constraints are retained in the filtered population, while those that do not are directly eliminated to prevent infeasible solutions from participating in subsequent optimization processes. The filtering process also includes outlier detection, identifying and removing individuals with obviously unreasonable prediction results, such as negative power consumption or excessively large delays—physically impossible situations. The size of the selected population is usually smaller than that of the original offspring population, but all individuals meet the basic performance and constraint requirements.

[0128] Pareto front extraction and diversity preservation processes identify the optimal solution set from the screened population. First, all individuals are re-ranked using non-dominated sorting, and the first front is extracted as the Pareto optimal solution for the current generation. A diversity preservation mechanism ensures the uniform distribution of the solution set in the target space, preventing excessive concentration of solutions in any local area. Crowding distance is recalculated to determine the distribution density used for quantification; solutions with larger distances exhibit better diversity characteristics. When the number of solutions in the Pareto front exceeds a preset limit, solutions with larger crowding distances are retained, while solutions in overly dense regions are removed. The solution set also needs to meet practicality requirements, eliminating solutions with unreasonable parameter combinations, such as mismatched device size ratios or extreme bias conditions, based on engineering judgment. The optimal device size combination contains multiple Pareto optimal solutions, each representing a performance trade-off, providing design engineers with different design options. The solution set is categorized and labeled according to performance characteristics, such as power-priority solutions, delay-priority solutions, and area-priority solutions, facilitating selection based on specific application requirements.

[0129] In one specific embodiment, the process of executing step S105 may specifically include the following steps:

[0130] Input the aspect ratio and bias voltage parameters of the device in the optimal device size combination into the SPICE netlist generator to construct the circuit netlist and obtain the simulation netlist file.

[0131] Monte Carlo process deviation analysis was performed based on the simulation netlist file, with 1000 random simulations to obtain a performance statistics data set;

[0132] The deviation between the power consumption, delay, and area simulation results in the performance statistics set and the performance prediction matrix is ​​calculated to obtain the prediction error vector.

[0133] Error threshold judgment is performed based on the prediction error vector. When the power consumption deviation is less than 5% and the delay deviation is less than 3%, parameter confirmation is performed. Otherwise, R-PTT prediction model parameter fine-tuning is triggered to obtain the verification status indicator.

[0134] Based on the verification status identifier, the device size parameters that have passed verification are checked using DRC and LVS rules to obtain the verified integrated circuit design parameters.

[0135] Specifically, the SPICE netlist generator converts the optimal combination of device dimensions into a standard circuit simulation format. The netlist construction process first reads the device aspect ratio parameters, writing the width (W) and length (L) values ​​of each transistor into the corresponding device declaration line. The device declaration uses standard SPICE syntax, formatted as "M device name, drain node, gate node, source node, body node, model name, W=width value, L=length value", such as "M1 vout vin vss vss nmos W=10u L=0.5u" representing an NMOS transistor. Bias voltage parameters are implemented through independent voltage source declarations, including voltage settings for key nodes such as supply voltage VDD and bias voltage VBIAS. The netlist file also contains device model calling statements, specifying the process library file used and device model parameters, such as ".lib 'process.lib' tt" indicating calling a device model for a typical process corner. Circuit connections are automatically generated based on the topology, ensuring all device nodes are correctly connected to form a complete circuit network. The simulation command section defines the analysis type and simulation parameters, including different simulation settings such as DC operating point analysis, AC small-signal analysis, and transient analysis. The netlist file is ultimately saved in .sp or .cir format and can be directly loaded and executed by the SPICE simulator.

[0136] Monte Carlo process deviation analysis simulates random variations in the actual manufacturing process using statistical simulation methods. The simulation setup defines 1000 independent random simulation runs, with device parameters varying randomly within a statistically distributed range in each simulation. Process deviation parameters include random variations in key physical parameters such as device geometry deviation, threshold voltage deviation, and carrier mobility deviation. Geometry deviation is modeled using a Gaussian distribution, with the standard deviation of device width and length typically ranging from 3% to 5% of the nominal value, reflecting the precision limitations of photolithography and etching processes. Threshold voltage deviation considers random variations in doping concentration and oxide layer thickness, with a standard deviation of approximately 50mV to 100mV, significantly impacting the static and dynamic characteristics of the circuit. Temperature and power supply voltage are also treated as random variables, with temperature varying from -40°C to 125°C and power supply voltage fluctuating within ±5% of the nominal value. Each simulation run generates a complete set of performance index data, including circuit characteristic parameters such as power consumption, delay, gain, and bandwidth. The performance statistics dataset summarizes all simulation results, calculates the mean, standard deviation, maximum, minimum, and distribution characteristics of each index, and provides a data foundation for subsequent statistical analysis and model validation.

[0137] The bias calculation process quantitatively compares the statistical results of the Monte Carlo simulation with the output of the R-PTT prediction model. The calculation is performed on three key indicators: power consumption, delay, and area. Power consumption bias is calculated using a relative error formula: the bias value equals the absolute value of the difference between the simulation mean and the predicted value, divided by the simulation mean, and then multiplied by 100% to convert it to a percentage. Delay bias and area bias are calculated using the same method to ensure the comparability of errors across different dimensions. The bias calculation also considers the statistical uncertainty of the simulation results. When the simulation standard deviation is large, confidence intervals are used for comparison to determine whether the predicted value falls within the 95% confidence interval. The prediction error vector is a 3-dimensional vector, recording the percentage of prediction error for power consumption, delay, and area. The vector's magnitude reflects the overall prediction accuracy, and the numerical distribution of each component reveals the model's differences in predictive ability across different performance indicators. The error vector also includes an error type identifier, distinguishing between systematic and random errors. Systematic errors indicate that the model has biases that require correction, while random errors reflect the model's prediction uncertainty.

[0138] Error threshold judgment processing evaluates the prediction error based on preset accuracy requirements. The power consumption deviation threshold is set at 5%, and the delay deviation threshold at 3%. These thresholds are determined based on engineering experience and can meet the accuracy requirements of most integrated circuit designs. Threshold judgment uses a logical AND operation; the prediction accuracy is considered acceptable only when the power consumption deviation is less than 5% and the delay deviation is less than 3%, and the parameter confirmation process is executed. Although area deviation is not involved in threshold judgment, it is recorded as a reference indicator in the verification status identifier. When any key indicator exceeds the error threshold, the system triggers the parameter fine-tuning mechanism of the R-PTT prediction model, updating the model weights using newly acquired simulation data. Parameter fine-tuning uses an online learning algorithm, using simulation results as new training samples, and adjusting model parameters through gradient descent, focusing on optimizing performance indicators with insufficient prediction accuracy. The verification status identifier records the verification results for each device size combination, including error values, whether verification passed, and detailed information such as the model parts requiring fine-tuning. Parameter combinations that pass verification are marked as "verification passed," and combinations that fail verification are marked as "re-optimization required," providing clear processing guidance for subsequent design flows.

[0139] DRC and LVS rule checks verify whether device size parameters, determined by error thresholds, meet manufacturing and design constraints. DRC checks verify whether device geometry conforms to process design rules. DRC rules include geometric constraints such as minimum linewidth, minimum spacing, and minimum area rules. The check process compares the actual device dimensions with the limits in the process rule library one by one. The minimum linewidth check ensures that the device width and length are not less than the minimum allowed by the process; for example, the minimum gate length for a 7nm process is 7nm, and the device width is not less than 60nm. The minimum spacing check verifies that the distance between adjacent devices meets isolation requirements, avoiding parasitic effects and process interference between devices. The density rule check ensures uniform device density distribution in the layout, meeting the requirements of subsequent processes such as chemical mechanical polishing. The LVS check verifies the consistency between the layout and the schematic, ensuring that the device connections in the layout completely match the circuit netlist. The LVS process first extracts the device netlist from the layout, then compares it with the original circuit netlist to check for consistency in device quantity, connections, and device parameters. Device size parameters that pass DRC and LVS checks are marked as "Design rule verification passed", forming verified integrated circuit design parameters that meet both performance requirements and manufacturing constraints and can be directly used for subsequent layout design and tape-out manufacturing.

[0140] The above describes the integrated circuit design optimization method based on data mining in the embodiments of this application. The following describes the integrated circuit design optimization system based on data mining in the embodiments of this application. Please refer to [link / reference]. Figure 2 One embodiment of the integrated circuit design optimization system based on data mining in this application includes:

[0141] The extraction module is used to extract process features from multi-process node circuit design data using EDA tools to obtain transistor parameter vector sets.

[0142] The enhancement module is used to perform data enhancement processing based on the transistor parameter vector set through a two-layer process-aware generative adversarial network to obtain a cross-node circuit sample library.

[0143] The prediction module is used to input the cross-node circuit sample library into the R-PTT prediction model to predict power consumption delay and obtain a performance prediction matrix;

[0144] The screening module is used to optimize circuit parameters based on the performance prediction matrix using a multi-objective genetic algorithm to obtain the optimal combination of device sizes.

[0145] The verification module is used to perform SPICE simulation verification on the optimal device size combination to obtain verified integrated circuit design parameters.

[0146] above Figure 2 The integrated circuit design optimization system based on data mining in this embodiment of the invention will be described in detail from the perspective of modular functional entities. The integrated circuit design optimization device based on data mining in this embodiment of the invention will be described in detail from the perspective of hardware processing.

[0147] Reference Figure 3 This invention also provides a data mining-based integrated circuit design optimization device, which can be a server, and its internal structure can be as follows: Figure 3 As shown, the data mining-based integrated circuit design optimization device includes a processor, memory, display screen, input device, network interface, and database connected via a system bus. The processor, part of the computer design, provides computational and control capabilities. The memory of the data mining-based integrated circuit design optimization device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system, computer programs, and the database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the data mining-based integrated circuit design optimization device stores the data corresponding to this embodiment. The network interface of the data mining-based integrated circuit design optimization device is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements the above-described method.

[0148] Those skilled in the art will understand that Figure 3The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the data mining-based integrated circuit design optimization device to which the present invention is applied.

[0149] The present invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when the instructions are executed on a computer, cause the computer to perform the steps of the data mining-based integrated circuit design optimization method.

[0150] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0151] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a data mining-based integrated circuit design optimization device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0152] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data mining-based integrated circuit design optimization method, characterized in that, The method includes: EDA tools are used to extract process features from multi-process node circuit design data to obtain transistor parameter vector sets. Based on the transistor parameter vector set, a cross-node circuit sample library is obtained by performing data augmentation processing through a two-layer process-aware generative adversarial network. The cross-node circuit sample library is input into the R-PTT prediction model for power consumption delay prediction to obtain a performance prediction matrix. This includes: inputting the process features and design parameters in the cross-node circuit sample library into the process feature attention head and the design parameter attention head respectively for multi-head attention weight calculation to obtain a process weight matrix and a parameter weight matrix; and performing cross-domain feature fusion processing based on the process weight matrix and the parameter weight matrix through a cross-attention head to obtain a fused feature vector. The fused feature vector is input into the process migration adaptation layer for residual connection transformation. When the process node difference is greater than 0.5, the adaptation transformation matrix is ​​activated to obtain the adapted feature vector, including: performing process node difference quantification calculation on the fused feature vector, and obtaining the process difference coefficient based on the feature distance between the source process node and the target process node. Based on the process difference coefficient, a threshold judgment process is performed. When the process difference coefficient is greater than 0.5, the adaptation transformation module is activated; otherwise, a pass-through connection process is executed to obtain a path selection signal. The fused feature vector is input into the adaptation transformation matrix according to the path selection signal for linear transformation processing to obtain a transformed feature vector. The fused feature vector and the transformed feature vector are then subjected to residual weighted summation processing, with the weight coefficient being the normalized value of the process difference coefficient, to obtain a residual fused vector. The residual fused vector is then subjected to batch normalization and activation function processing to obtain the adapted feature vector. Based on the adapted feature vector, power consumption, latency, and area are predicted in parallel through a multi-task regression layer to obtain a multi-dimensional performance output vector; the multi-dimensional performance output vector is then subjected to matrix reconstruction to obtain the performance prediction matrix. Based on the performance prediction matrix, a multi-objective genetic algorithm is used to optimize circuit parameters and obtain the optimal combination of device sizes. SPICE simulation was performed on the optimal device size combination to obtain the verified integrated circuit design parameters.

2. The integrated circuit design optimization method based on data mining according to claim 1, characterized in that, The process of extracting process features from multi-process node circuit design data using EDA tools to obtain a transistor parameter vector set includes: Numerical extraction of transistor channel length, oxide layer thickness, and doping concentration at multiple process nodes yields a set of fundamental process parameters. Based on the aforementioned process fundamental parameter set, feature encoding processing is performed on the circuit topology and device dimensions to obtain the design parameter encoding matrix; Based on the design parameter encoding matrix, data annotation processing is performed on power consumption, delay, and area performance indicators to obtain performance label vectors; The process basic parameter set and the performance label vector are concatenated to obtain a high-dimensional feature vector. The high-dimensional feature vector is processed by assigning process node identifier codes to obtain the transistor parameter vector set.

3. The integrated circuit design optimization method based on data mining according to claim 1, characterized in that, The step of performing data augmentation processing based on the transistor parameter vector set through a two-layer process-aware generative adversarial network to obtain a cross-node circuit sample library includes: The transistor parameter vector set is input into the first-layer process encoder and the second-layer parameter encoder respectively for two-layer feature extraction processing to obtain the process embedding vector and the parameter embedding vector. A two-layer conditional input vector is obtained by performing a three-layer splicing and fusion process based on the random noise vector, the process embedding vector, and the parameter embedding vector. The dual-layer conditional input vector is input into the dual-path parameter generator for parallel adversarial generation processing to obtain the synthetic design parameter vector. Based on the synthetic design parameter vector, a two-layer process discriminator is used to perform true / false discrimination and process classification. When the first-layer discrimination probability is greater than 0.7 and the second-layer process classification accuracy is greater than 0.8, a discrimination probability matrix is ​​generated; otherwise, the parameter generation process is re-executed. The synthetic design parameter vector, which has been subjected to two-layer discrimination, is subjected to process consistency verification to obtain the cross-node circuit sample library.

4. The integrated circuit design optimization method based on data mining according to claim 1, characterized in that, The process of optimizing circuit parameters using a multi-objective genetic algorithm based on the performance prediction matrix to obtain the optimal combination of device sizes includes: Based on the power consumption, delay, and area prediction values ​​in the performance prediction matrix, a multi-objective fitness function is constructed to obtain a fitness evaluation vector. Based on the fitness evaluation vector, the initial device size population is subjected to non-dominated sorting and crowding distance calculation to obtain a hierarchical population structure. Individuals in the hierarchical population structure are subjected to process-constrained simulated binary crossover and polynomial mutation operations. The crossover probability is set to 0.9 when the fitness of an individual ranks in the top 50%, and 0.7 otherwise, to obtain the offspring population. The offspring population is re-predicted using the performance prediction matrix. Individuals are retained when the predicted power consumption is less than a set threshold and the delay meets the timing constraints, resulting in a filtered population. Based on the screened population, Pareto front extraction and diversity preservation processing are performed to obtain the optimal device size combination.

5. The integrated circuit design optimization method based on data mining according to claim 1, characterized in that, The SPICE simulation verification process for the optimal device size combination yields verified integrated circuit design parameters, including: The device width-to-length ratio and bias voltage parameters in the optimal device size combination are input into the SPICE netlist generator to perform circuit netlist construction processing, and a simulation netlist file is obtained. Monte Carlo process deviation analysis was performed based on the simulation netlist file, with 1000 random simulations to obtain a performance statistics data set. The power consumption, delay, and area simulation results in the performance statistics set are compared with the performance prediction matrix to calculate the deviation and obtain the prediction error vector. Based on the prediction error vector, an error threshold judgment process is performed. When the power consumption deviation is less than 5% and the delay deviation is less than 3%, parameter confirmation is performed. Otherwise, R-PTT prediction model parameter fine-tuning is triggered to obtain a verification status indicator. Based on the verification status identifier, the device size parameters that have passed verification are subjected to DRC and LVS rule checks to obtain the verified integrated circuit design parameters.

6. A data mining-based integrated circuit design optimization system, characterized in that, For implementing the data mining-based integrated circuit design optimization method as described in any one of claims 1 to 5, the data mining-based integrated circuit design optimization system comprises: The extraction module is used to extract process features from multi-process node circuit design data using EDA tools to obtain transistor parameter vector sets. The enhancement module is used to perform data enhancement processing based on the transistor parameter vector set through a two-layer process-aware generative adversarial network to obtain a cross-node circuit sample library. The prediction module is used to input the cross-node circuit sample library into the R-PTT prediction model to predict power consumption and delay, and obtain a performance prediction matrix. This includes: inputting the process features and design parameters from the cross-node circuit sample library into a process feature attention head and a design parameter attention head respectively for multi-head attention weight calculation to obtain a process weight matrix and a parameter weight matrix; and performing cross-domain feature fusion processing based on the process weight matrix and the parameter weight matrix through a cross-attention head to obtain a fused feature vector. The fused feature vector is input into the process migration adaptation layer for residual connection transformation. When the process node difference is greater than 0.5, the adaptation transformation matrix is ​​activated to obtain the adapted feature vector, including: performing process node difference quantification calculation on the fused feature vector, and obtaining the process difference coefficient based on the feature distance between the source process node and the target process node. Based on the process difference coefficient, a threshold judgment process is performed. When the process difference coefficient is greater than 0.5, the adaptation transformation module is activated; otherwise, a pass-through connection process is executed to obtain a path selection signal. The fused feature vector is input into the adaptation transformation matrix according to the path selection signal for linear transformation processing to obtain a transformed feature vector. The fused feature vector and the transformed feature vector are then subjected to residual weighted summation processing, with the weight coefficient being the normalized value of the process difference coefficient, to obtain a residual fused vector. The residual fused vector is then subjected to batch normalization and activation function processing to obtain the adapted feature vector. Based on the adapted feature vector, power consumption, latency, and area are predicted in parallel through a multi-task regression layer to obtain a multi-dimensional performance output vector; the multi-dimensional performance output vector is then subjected to matrix reconstruction to obtain the performance prediction matrix. The screening module is used to optimize circuit parameters based on the performance prediction matrix using a multi-objective genetic algorithm to obtain the optimal combination of device sizes. The verification module is used to perform SPICE simulation verification on the optimal device size combination to obtain verified integrated circuit design parameters.

7. An integrated circuit design optimization device based on data mining, characterized in that, It includes a memory and a processor, the memory storing a computer program that can run on the processor, and the processor executing the computer program to implement the data mining-based integrated circuit design optimization method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is run by the processor, it causes the processor to execute the data mining-based integrated circuit design optimization method as described in any one of claims 1 to 5.

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