Large dynamic range signal acquisition circuit

Abstract

The invention provides a novel large dynamic range signal acquisition circuit, which is used for solving the technical problem of high signal acquisition cost caused by the fact that more channels are needed to carry out measuring range lap joint if an existing large dynamic range acquisition circuit needs to finely acquire signals in a larger range. The large dynamic range signal acquisition circuit provided by the invention comprises a power divider, M comparators, an attenuation link, an ADC conversion module, a splicing circuit and an FPGA, large dynamic range signal acquisition can be realized by adopting a single signal channel through a design method of signal equal division, feature extraction and attenuation control, the range coverage range is from a millivolt level to a kilovolt level, and the measurement range is wide. The signal acquisition range is widened, the number of channels is reduced, the economic use efficiency of the channels is improved, the test cost is saved, and the analog-to-digital conversion method has important significance on analog-to-digital conversion of uncertain amplitude signals in a specific environment.

Description

Technical Field

[0001] The present invention relates to a signal acquisition circuit, in particular to a signal acquisition circuit with a large dynamic range. Background Art

[0002] In the field of high-energy physics signal measurement, the acquisition of fast pulse analog signals with large dynamic range and uncertain amplitude is a measurement problem. The acquisition of fast pulse analog signals is generally completed by the data acquisition circuit to convert the analog signal into a digital signal, and then output it to the back-end digital processing module for processing. In reality, due to the large dynamic range of the signals generated by high-energy physics, the large differences in the output signal characteristics of different detectors and the influence of factors such as signal attenuation during propagation, the signal intensity acting on the data acquisition input end often varies and fluctuates greatly. Traditional single-channel data acquisition systems can generally only process pulse signals with amplitudes that vary within a certain range. They are prone to the "clipping" phenomenon when acquiring large-amplitude signals or the phenomenon of too low resolution when acquiring small-amplitude signals, which brings difficulties to subsequent signal analysis.

[0003] Currently, the use of multi-channel range overlap is an effective method for measuring large dynamic signals, but it is subject to high measurement costs and unstable multi-channel consistency. At the same time, the use of data acquisition attenuation automatic switching technology can achieve the measurement of large dynamic range signals using only one channel, thus bringing very beneficial effects to the acquisition and analysis of such signals. Most existing large dynamic data measurement methods do not have a real-time and fast variable gain design. The measurement signal is only within a very small range. The typical data acquisition input range is within 10V, and the input range of high-speed and high-precision ADC chips is within 1.5V. This can only sacrifice small signal measurement accuracy by adding a separate attenuator to the peripheral circuit, or increase the cost of multi-channel range overlap to achieve signal acquisition. It is impossible to achieve a balance between large-amplitude signal acquisition, small signal accurate acquisition, and low-cost acquisition.

[0004] Xia Ye et al. published a paper titled "Automatic Shifting Laser Power Measurement Method Based on Relay Arrays," available in Electronic Measurement Technology, Vol. 6, No. 4, 2013, pp. 72-75. This measurement method designed an automatic shifting circuit suitable for laser power measurement. Using a feedback resistor to control the relay switches, this method suffers from significant time jitter, preventing rapid shifting and measuring fast pulse signals, and ineffectively detecting DC components in the signal. It is suitable for applications with low switch internal resistance and high current carrying capacity. Analog Devices' HMC series of programmable attenuators offer programmable attenuation, but the attenuation control signal is externally supplied, preventing real-time adjustment of the attenuation factor based on the input signal's characteristics.

[0005] like Figure 1As shown in the figure, it is an existing large dynamic range acquisition circuit, which divides the measured signal into two equal parts, adopts a design method of one channel with small attenuation and the other channel with large attenuation, and finally splices the two signals. Branch A adopts the idea of ​​attenuation first and then amplification. On the basis of maintaining the original characteristics of the signal, it effectively suppresses the reflection caused by the change of system impedance by the micro-variable resistance when the switching diode is turned on, thereby realizing the precise measurement of small signals; Branch B realizes the measurement of large signals with large attenuation (for example, 100 times). The measurement ranges of the two branches complement each other, realizing the conditioning of large dynamic signals, and expanding the dynamic range of the digital acquisition system from millivolt level to hundred-volt level. The design concept of this type of large dynamic signal acquisition circuit is simple and clear, but a channel is specially set up for range overlap. If you want to accurately obtain a larger range of signals, more channels are required for range overlap, resulting in a higher cost of signal acquisition. Summary of the Invention

[0006] The purpose of the present invention is to solve the technical problem that if the existing large dynamic range acquisition circuit wants to accurately acquire a larger range of signals, more channels are required for range overlap, resulting in high signal acquisition costs, and to provide a new large dynamic range signal acquisition circuit.

[0007] In order to achieve the above object, the technical solution provided by the present invention is as follows:

[0008] A large dynamic range signal acquisition circuit is characterized in that it includes a power divider, M comparators, an attenuation link, an ADC conversion module, a splicing circuit and an FPGA, where M is greater than or equal to 2.

[0009] The attenuation link includes a transmission line and M attenuation units arranged in sequence on the transmission line in input and output order, each attenuation unit includes an attenuator and a control switch; the control switch is used to pull up and connect the corresponding attenuator, and pull down and connect the transmission line of the attenuation link;

[0010] The input end of the power divider receives an external analog input signal and is used to divide the external analog input signal into (M+1) branch signals;

[0011] The (M+1) output terminals of the power divider are respectively connected to the first input terminals of the M comparators and the input terminal of the first attenuator, so as to respectively send the (M+1) branch signals to the M comparators and the first attenuator; the second input terminals of the M comparators are respectively connected to corresponding reference voltages;

[0012] The attenuation values ​​of the M attenuators increase sequentially from the first to the Mth attenuators, the reference voltages of the M comparators increase sequentially from the first to the Mth attenuators, and the output end of the i-th comparator is connected to the i-th control switch and the input end of the splicing circuit, i=1, 2, ...M;

[0013] The splicing circuit is used to perform data splicing according to the levels output by the M comparators to form a characteristic digital code;

[0014] The input end of the ADC conversion module is connected to the output end of the Mth attenuator, and is used to convert the branch signal attenuated by the attenuation link from an analog signal to a digital signal;

[0015] The two input ends of the FPGA are respectively connected to the output end of the splicing circuit and the output end of the ADC conversion module, and are used to combine and encode the digital signal output by the ADC conversion module and the characteristic digital code output by the splicing circuit (2) to perform signal differentiation and post-processing; the output end of the FPGA serves as the output end of the large dynamic range signal acquisition circuit, and is used to output the encoded digital signal.

[0016] Furthermore, the frequency range of the power divider is DC to 2 GHz, and the average power tolerance is greater than 5W.

[0017] Furthermore, the control switch is a high-speed GaN MOS switch.

[0018] Furthermore, the control switch is designed in the form of a transmission gate.

[0019] Furthermore, the comparator is a comparator in the form of a digital circuit, or a comparator in the form of an analog circuit.

[0020] Furthermore, M=4;

[0021] The power splitter is a one-to-five power splitter.

[0022] Furthermore, the attenuation values ​​of the four attenuators are 6dB, 9.5dB, 14dB, and 40dB respectively;

[0023] The analog input signal range is 10mV to 2000V;

[0024] The maximum input voltage of the ADC conversion module is 1V;

[0025] The reference voltages of the four comparators are 0.1V, 1V, 10V, and 100V respectively.

[0026] The beneficial effects of the present invention compared to the prior art are as follows:

[0027] 1. The present invention provides a large dynamic range signal acquisition circuit. Through the design method of signal equal division + feature extraction + attenuation control, a single signal channel can be used to achieve signal acquisition with a large dynamic range. The range covers from millivolts to kilovolts. This not only improves the signal acquisition range, but also saves the number of channels, improves the economic use efficiency of the channels, and saves testing costs. It is of great significance for the analog-to-digital conversion of uncertain amplitude signals under specific environments.

[0028] 2. The present invention divides the output of each comparator into two paths, one of which is used to form a characteristic digital code, that is, to form a signal characteristic mark. The digital signal output by the ADC conversion module is combined with the characteristic digital code and encoded, so that the signal characteristics can be quickly and directly identified at the back end of the data reception.

[0029] 3. The present invention provides a large dynamic range signal acquisition circuit, which adopts a stepped multi-stage attenuation link. It can automatically select different attenuation multiples according to the signal conditions. It has a good range overlap effect and can better adapt to the test environment. It can achieve high-quality acquisition of millivolt to kilovolt signals and improve the economic utilization efficiency of the channel.

[0030] 4. The present invention achieves high-quality acquisition of millivolt to hundred-volt signals, combined with high-speed GaN MOS switches, and realizes the splicing of nanosecond pulse signals, which has strong engineering prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a schematic diagram of the principle of the existing large dynamic range acquisition circuit;

[0032] Figure 2 This is a schematic diagram of the principle of an embodiment of a large dynamic range signal acquisition circuit of the present invention;

[0033] Figure 3 It is a schematic diagram of the principle of the control switch in the attenuation link in an embodiment of the present invention.

[0034] The specific reference numerals are as follows:

[0035] 1-power divider; 2-splicing circuit. DETAILED DESCRIPTION

[0036] In order to make the advantages and features of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] The present invention aims to solve the problem of acquiring large dynamic range signals with uncertain range and provides a large dynamic range signal acquisition circuit. Figure 2As shown, the large dynamic range signal acquisition circuit includes a power divider 1, four comparators, an attenuation chain, an ADC conversion module, a splicing circuit 2, and an FPGA. The attenuation chain includes four groups of attenuation units arranged in input and output order, each of which includes a control switch and an attenuator. The four comparators are sequentially denoted as comparator C1, comparator C2, comparator C3, and comparator C4; the four control switches are sequentially denoted as control switch S1, control switch S2, control switch S3, and control switch S4; and the four attenuators are sequentially denoted as attenuator ATT1, attenuator ATT2, attenuator ATT3, and attenuator ATT4.

[0038] The power divider 1 adopts a high-performance power divider with a wide frequency range coverage (preferably DC to 2GHz), a large average withstand power (preferably above 5W), and a small insertion loss. The purpose is to reliably obtain the external large dynamic range fast-front analog input signal and accurately divide it equally. In this embodiment, the power divider 1 is a one-to-five power divider. In other embodiments of the present invention, the type of power divider 1 needs to be selected according to the number of comparators. The analog input signal is divided into five paths by the one-to-five power divider to obtain five branch signals. The five output ends of the one-to-five power divider are respectively connected to the first input ends of comparator C1, comparator C2, comparator C3, and comparator C4 and the input end of attenuator ATT1, and are used to send the four branch signals into comparator C1, comparator C2, comparator C3, and comparator C4 respectively, and the other branch signal enters the attenuation link through attenuator ATT1. The second input ends of comparator C1, comparator C2, comparator C3, and comparator C4 are respectively used to connect to the corresponding reference voltage.

[0039] The attenuation values ​​of the four attenuators increase successively from attenuator ATT1 to attenuator ATT4. In this embodiment, the attenuation value of attenuator ATT1 is preferably 6dB, the attenuation value of attenuator ATT2 is preferably 9.5dB, the attenuation value of attenuator ATT3 is preferably 14dB, and the attenuation value of attenuator ATT4 is preferably 40Db, realizing a combination of 6dB+9.5dB+14dB+40dB, so that the total attenuation multiple is 69.5dB, and millivolt to kilovolt signals can be obtained.

[0040] The reference voltages of comparators C1, C2, C3, and C4 increase sequentially from comparator C1 to comparator C4. The voltages of the branch signals entering the four comparators are compared with their corresponding reference voltages. If the voltage of the branch signal is greater than the reference voltage of the corresponding comparator, the comparator outputs a high level. If the voltage of the branch signal is less than the reference voltage of the corresponding comparator, the comparator outputs a low level. The voltages of the branch signals entering the four comparators are denoted as signal voltage V1, signal voltage V2, signal voltage V3, and signal voltage V4, respectively. The reference voltages of the four comparators are denoted as reference voltage Vref1, reference voltage Vref2, reference voltage Vref3, and reference voltage Vref4, respectively. Signal voltage V1 is compared with reference voltage Vref1, signal voltage V2 is compared with reference voltage Vref2, signal voltage V3 is compared with reference voltage Vref3, and signal voltage V4 is compared with reference voltage Vref4.

[0041] The output results of the four comparators are divided into two paths. One path is transmitted to the FPGA through the splicing circuit 2 and re-encoded with the output of the ADC conversion module. The purpose is to mark the amplitude information with analog input and the total attenuation information of the attenuation link, providing key parameters for data post-processing; the other output results of the four comparators are transmitted to the corresponding attenuator of the attenuation link to control its switches S1~S4.

[0042] Specifically, the output terminals of comparators C1, C2, C3 and C4 are connected to the input terminal of the splicing circuit 2, which is used to perform data splicing on the levels output by the four comparators to form a characteristic digital code for signal feature marking.

[0043] The output of comparator C1 is connected to control switch S1, the output of comparator C2 is connected to control switch S2, the output of comparator C3 is connected to control switch S3, and the output of comparator C4 is connected to control switch S4, which are used to control the pull-up or pull-down of the corresponding control switch according to the output of the comparator. When the control switch is pulled up, it is used to connect to the corresponding attenuator, and when it is pulled down, it is used to connect to the transmission line of the attenuation link. That is, by pulling up or pulling down the control switch, the corresponding attenuator is controlled to be in a connected state or a short-circuit state, thereby controlling the attenuator participating in the attenuation in the attenuation link. Figure 3 As shown, taking the control switch S1 as an example, it includes two sub-switches S1-1 and S1-2. If the comparator C1 outputs a high level, the sub-switches S1-1 and S1-2 are pulled up to connect to the corresponding attenuator. At this time, the attenuator ATT1 is connected. If the comparator C1 outputs a low level, the sub-switches S1-1 and S1-2 are pulled down to connect to the transmission line. At this time, the attenuator ATT1 is short-circuited.

[0044] The control switch in the present invention is preferably a high-speed GaN MOS switch, such as the EPC2010C model. Combined with low parasitic devices, strong drive, and low-inductance design, it can achieve a turn-on time of less than 0.2ns, achieving picosecond-level switching and reducing dead time caused by range conversion, enabling effective measurement of high-dynamic, fast-leading pulse signals. Furthermore, the control switch is preferably designed using a transmission gate method to balance the on-time and off-time.

[0045] The input of the ADC conversion module is connected to the output of attenuator ATT4 and is used to convert the branch signal attenuated by the attenuation link from an analog signal to a digital signal. The two inputs of the FPGA are respectively connected to the output of splicing circuit 2 and the output of the ADC conversion module. Based on the codeword setting, the digital signal output by the ADC conversion module is combined and encoded with the characteristic digital code output by splicing circuit 2 for signal differentiation and post-processing. The output of the FPGA serves as the output of the large dynamic range signal acquisition circuit and is used to output the encoded digital signal. Because the encoded digital signal carries the characteristic digital code, the computer software in the back-end data processing unit can automatically detect and identify the characteristic digital code. Therefore, during data calibration, the analog signal and digital signal can be calibrated based on the characteristic digital code to achieve signal differentiation and post-processing. In other words, the back-end data processing unit interprets the data based on the characteristic digital code and the calibration results.

[0046] The four comparators in the present invention can be implemented by digital circuits or by analog circuits. The digital circuit form is implemented using FPGA hardware programming language, and the analog circuit form is implemented in the form of an open-loop amplifier, which can achieve a faster flipping speed.

[0047] Taking the total attenuation of the attenuation link as 69.5dB, assuming the analog input signal range is 10mV to 2000V (at this time the comparator input signal range is 2mV to 400V), and the maximum input voltage of the back-end ADC conversion module is 1V as an example, the reference voltage Vref1 of the comparator C1 is preferably 0.1V, the reference voltage Vref2 of the comparator C2 is preferably 1V, the reference voltage Vref3 of the comparator C3 is preferably 10V, and the reference voltage Vref4 of the comparator C4 is preferably 100V.

[0048] The range coverage principle of the large dynamic range signal acquisition circuit of the present invention is as follows: if the analog input voltage is less than 0.5V, the signal voltages V1 to V4 after voltage division are all less than 0.1V. At this time, the outputs of the four comparators are all low level 0, and the four switches are controlled to pull down, so that the four attenuators are in a short-circuit state. At this time, the signal is directly passed to the ADC conversion module. At this time, the signal does not pass through any attenuator, and the total attenuation factor is 0dB. If the voltage range of the analog input voltage is 0.5V to 5V, the voltage range of the signal voltages V1 to V4 after voltage division is 0.1V to 1V. At this time, the output of comparator C1 is high level 1, which is used to control switch S1 to pull up, so that attenuator ATT1 is turned on. The outputs of comparators C2 to C4 are low level 0, which is used to control switches S2 to S4 to pull down to connect the transmission line, so that attenuators ATT2 to ATT4 are in a short-circuit state. At this time, the total attenuation factor is 6dB. If the voltage range of the analog input voltage is 5V~50V, the voltage range of the signal voltage V1~V4 is 1V~10V. At this time, the output of comparator C1 and comparator C2 is high level 1, which is used to control the switches S1 and S2 to pull up, so that attenuators ATT1 and attenuators ATT2 are turned on. The output of comparator C3 and comparator C4 is low level 0, which is used to control the switches S3 and S4 to pull down to connect the transmission line, so that attenuators ATT2~ATT4 are in a short-circuit state. At this time, the total attenuation factor is 15.5dB. If the analog input voltage range is 50V to 500V, the voltage range of the divided signal voltage V1 to V4 is 10V to 100V. At this time, comparators C1, C2, and C3 output a high level 1, which is used to control switches S1, S2, and S3 to pull up, turning on attenuators ATT1, ATT2, and ATT3. Comparator C4 outputs a low level 0, which is used to control switch S4 to pull down the transmission line, short-circuiting attenuator ATT4. At this time, the total attenuation factor is 29.5dB. If the analog input voltage is greater than 500V, the divided signal voltages V1 to V4 are all greater than 100V. At this time, comparators C1 to C4 all output a high level 1, which is used to control switches S1 to S4 to pull up, turning on attenuators ATT1 to ATT4. At this time, the total attenuation factor reaches the maximum value of 69.5dB. The specific range coverage table is shown in Table 1:

[0049] Table 1

[0050]

[0051] The present invention uses a design method of signal equal division + feature extraction + attenuation control to achieve signal acquisition with a large dynamic range using a single signal channel, thereby increasing the signal acquisition range, saving the number of channels, and reducing the cost of use. This is of great significance for the analog-to-digital conversion of uncertain amplitude signals under specific environments. The step-by-step signal attenuation link can automatically select different attenuation multiples according to the signal conditions, and can achieve high-quality acquisition of millivolt to kilovolt signals, thereby improving the economic efficiency of the channel. In addition, the present invention divides the output of each comparator into two paths, one of which is used to form a signal feature mark, that is, adding a feature identification code to the digital signal output by the ADC conversion module, so that the signal feature can be quickly and directly identified at the back end of the data receiving unit.

[0052] The above description is only used to illustrate the technical solution of the present invention, rather than to limit it. For ordinary professional and technical personnel in this field, the specific technical solutions recorded in the above embodiments can be modified, or some of the technical features therein can be replaced by equivalents. These modifications or replacements do not cause the essence of the corresponding technical solution to deviate from the scope of the technical solution protected by the present invention.

Claims

1. A large dynamic range signal acquisition circuit, characterized in that: It includes a power divider (1), M comparators, an attenuation link, an ADC conversion module, a splicing circuit (2) and an FPGA, where M is greater than or equal to 2; The attenuation link includes a transmission line and M attenuation units sequentially arranged on the transmission line, each attenuation unit includes an attenuator and a control switch; the control switch is used to select a connection to a corresponding attenuator or a connection to the transmission line of the attenuation link; The input end of the power divider (1) receives an external analog input signal and is used to divide the signal into (M+1) branch signals; The (M+1) output ends of the power divider (1) are respectively connected to the first input ends of the M comparators and the input end of the first attenuator, for respectively sending the (M+1) branch signals to the M comparators and the first attenuator; the second input ends of the M comparators are respectively connected to corresponding reference voltages; The attenuation values ​​of the M attenuators increase in sequence from the first to the Mth attenuators, the reference voltages of the M comparators increase in sequence from the first to the Mth attenuators, and the output end of the i-th comparator is connected to the i-th control switch and the input end of the splicing circuit (2), i=1, 2, ...M; The splicing circuit (2) is used to perform data splicing according to the levels output by the M comparators to form a characteristic digital code; The input end of the ADC conversion module is connected to the output end of the Mth attenuator, and is used to convert the branch signal attenuated by the attenuation link from an analog signal to a digital signal; The two input ends of the FPGA are respectively connected to the output end of the splicing circuit (2) and the output end of the ADC conversion module, and are used to combine and encode the digital signal output by the ADC conversion module and the characteristic digital code output by the splicing circuit (2) to perform signal differentiation and post-processing; the output end of the FPGA serves as the output end of the large dynamic range signal acquisition circuit, and is used to output the encoded digital signal.

2. The large dynamic range signal acquisition circuit according to claim 1, characterized in that: The power divider (1) has a frequency range of DC to 2 GHz and an average withstand power greater than 5 W.

3. The large dynamic range signal acquisition circuit according to claim 2, characterized in that: The control switch is a high-speed GaN MOS switch.

4. The large dynamic range signal acquisition circuit according to claim 3, characterized in that: The control switch is designed in the form of a transmission gate.

5. The large dynamic range signal acquisition circuit according to claim 1, characterized in that: The comparator is a comparator in the form of a digital circuit or a comparator in the form of an analog circuit.

6. A large dynamic range signal acquisition circuit according to any one of claims 1 to 5, characterized in that: M=4; The power splitter (1) is a one-to-five power splitter.

7. The large dynamic range signal acquisition circuit according to claim 6, characterized in that: The attenuation values ​​of the four attenuators are 6dB, 9.5dB, 14dB, and 40dB respectively; The analog input signal range is 10mV to 2000V; The maximum input voltage of the ADC conversion module is 1V; The reference voltages of the four comparators are 0.1V, 1V, 10V, and 100V respectively.

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