Universal gate protection diode

Abstract

The embodiment of the invention relates to a universal gate protection diode. An embodiment metal oxide semiconductor (MOS) device includes: a MOS capacitor having a well and a gate, the MOS capacitor disposed in a semiconductor substrate of a first doping type; and a gate protection diode disposed in the semiconductor substrate. The gate protection diode includes a first region doped with a first doping type and coupled to a gate of the MOS capacitor. The gate protection diode includes a second region different from the well of the MOS capacitor and doped with a second doping type different from the first doping type.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to French Application No. 24 03640, filed on April 9, 2024, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments and implementations relate to the field of semiconductor components, and more specifically to the field of gate protection diodes. BACKGROUND

[0004] A gate is present in a Metal Oxide Semiconductor (MOS) component, such as a MOS capacitor or a MOS transistor, containing a MOS capacitance.

[0005] The manufacturing of these MOS components, and more generally of Metal Oxide Semiconductor (MOS) circuits, involves plasma processes, in particular for depositing and etching layers, for example layers of integrated circuit interconnects parts located above a substrate, generally denoted by the acronym BEOL for “Back-End Of Line”.

[0006] However, these methods can cause damages due to plasma charges bombarding the metal lines of the integrated circuit interconnects parts. Indeed, when these metal lines are connected to the gate structure of a MOS capacitor, charges are accumulated at the gate structure; a high electric field is generated through the gate and the substrate can deteriorate the gate oxide.

[0007] It is known to reduce damages from plasma charges by using a gate protection diode, Figure 1 Two examples are shown in the figure for N-channel MOS (NMOS) transistors and P-channel MOS (PMOS) transistors. A gate protection diode 10 is integrated in the same substrate 20 as the MOS transistor 30 to be protected, next to the MOS transistor 30, and shares the same N or P doped body or well 11. The gate 31 of the MOS transistor is connected to the other side of the diode 12, which thus has the same P or N doping as the gate.

[0008] In this way, between the gate and the substrate, the diode has a lower impedance than the MOS transistor, whatever its polarization. In this way, the diode, which is passivated, eliminates the charges accumulated at the polarization of the gate towards the substrate. On the other hand, when the MOS transistor is inversely polarized (at its gate), the diode becomes blocking, which is the case of the normal use of MOSFET transistors (FET stands for “Field Effect Transistor”).

[0009] However, such gate protection diodes are not satisfactory for certain applications, such as simple use of intrinsically symmetrical MOS capacitors, and use of "power switch" type MOSFET transistors, where the gate of the MOS transistor can be used according to both the inversion and accumulation polarizations.

[0010] In the case of accumulation polarization, the gate protection diode is in forward polarization (and thus conductive), and a leakage current flows through the diode, causing unnecessary current consumption, and in some cases, functional problems of the application.

[0011] There is thus a need to provide an improved gate protection diode, which allows the gate of a MOS component to be used in both polarizations, without excessive power consumption. SUMMARY

[0012] According to one aspect, a metal-oxide-semiconductor (MOS) device is provided in a semiconductor substrate of a first doping type, the MOS device comprising: a MOS capacitor having a well and a gate; and a gate protection diode comprising a first region doped with the first doping type and adapted to be connected to the gate of the MOS capacitor, the gate protection diode comprising a second region different from the well of the MOS capacitor and doped with a second doping type different from the first doping type. The second region thus forms a well of the gate protection diode.

[0013] "Different" is defined to mean that the region of interest is separated by an undoped region (e.g. STI shallow trench isolation) or by a differently doped region.

[0014] By separating the well of the MOS capacitor to be protected from the well of the gate protection diode, the gate protection diode has two P-N junctions - and thus two diodes in series - with opposite directions or head-to-tail in the electrical diagram: the P-N junction of the diode, and the opposite junction between the second region and the substrate. Due to their reverse bias (one of the two diodes in series is conducting, the other is blocking), only a small leakage current can flow, limited by the blocking diode, whatever the polarization applied to the gate. This low current allows the elimination of the plasma charge accumulated during the manufacturing of the MOS circuit, while avoiding high leakage currents when using the MOS component in either gate polarization. The MOS device designed in this way is also protected.

[0015] The two opposite P-N junctions free the device from the constraints of the relative polarisation of the gate protection diode and the MOS capacitor. Thus, unlike known protection diodes, the same type of gate protection diode can be used to protect MOS components regardless of their gate polarisation. This gate protection diode is thus intrinsically "universal". In addition, in an advantageous embodiment, the well of the MOS capacitor is conventionally doped with a first type of doping, opposite to the doping type of the well of the gate protection diode.

[0016] In addition, it is also possible to protect several MOS components simultaneously with the same universal gate protection diode, the gates of these MOS components being at the same potential regardless of the applied polarisation.

[0017] In addition, the complexity of the design of this gate protection diode is not changed since no new junction is created - only the well of the MOS capacitor and the well of the gate protection diode must be separated.

[0018] A metal-oxide-semiconductor (MOS) integrated circuit comprising a MOS device as defined above is also proposed.

[0019] According to a second aspect, a method for manufacturing a protected metal-oxide-semiconductor (MOS) device is proposed, the method comprising forming a MOS capacitor having a well and a gate in a semiconductor substrate of a first doping type, and forming a gate protection diode in the semiconductor substrate, the gate protection diode comprising a first region doped with the first doping type and adapted to be connected to the gate of the MOS capacitor, and a second region different from the well of the MOS capacitor and doped with a second doping type different from the first doping type.

[0020] The method has the same advantages as the device described above.

[0021] Optional features of the embodiments are defined in the appended claims. Some of these features are explained below with reference to the device, which can be translated into features of the method.

[0022] In one embodiment, the second region of the gate protection diode is floating, i.e. it is neither polarised to the supply voltage VDD nor to ground. This arrangement prevents short-circuiting of the second junction and thus any leakage current.

[0023] In another embodiment, the MOS device further comprises a first doped barrier of a first doping type between the gate protection diode and the MOS capacitor, and a second doped barrier of a second doping type between the first barrier and the MOS capacitor. In this way, the gate protection diode and the MOS capacitor are spaced apart, contributing to reduce the risk of forming a parasitic thyristor (or "latch-up") due to the PNPN structure formed by the well of the protection diode and the MOS capacitor.

[0024] In a particular feature, the first and second barriers form a ring around the gate protection diode. A full protection against the risk of parasitic paths is thus achieved, contributing to the integration design of the universal gate protection diode in an integrated circuit.

[0025] The first and second barriers are preferably polarized, one to ground and the other to the supply voltage. The second barrier thus imposes a stable polarization area in the substrate between the gate protection diode and the MOS capacitor. This stable intermediate polarization actively contributes to reduce the risk of forming a PNPN parasitic thyristor.

[0026] According to one particular feature, the first barrier is polarized like the substrate, i.e. at the same potential. According to a corresponding feature, the second barrier is polarized by the ground and the supply voltage at another potential.

[0027] As explained below, the first and second barriers can be separated by an undoped area, typically an isolated STI trench.

[0028] In one embodiment representing a preferred application, the MOS capacitor forms part of a MOS field effect transistor (MOSFET). This is the MOS capacitor formed by the gate of the transistor and its substrate, creating a conductive channel of the transistor.

[0029] In one embodiment, different types of transistors in the same circuit can be protected by the universal gate protection diode. In addition, in the integrated circuit mentioned above, the MOS capacitor of the first MOS device can form part of an NMOS transistor, and the circuit can comprise a second MOS device as defined above, sharing the same substrate as the first MOS device, the MOS capacitor of the second MOS device forming part of a PMOS transistor.

[0030] In a particular embodiment, each of the first and second MOS devices comprises a first ring around the corresponding gate protection diode and doped with a first type of doping, and comprises a second ring around the first ring and doped with a second type of doping. BRIEF DESCRIPTION OF DRAWINGS

[0031] Other advantages and features of the present application will become apparent from the detailed description of non-limiting embodiments and implementations, and from the drawings, in which:

[0032] Figure 1 A conventional gate protection diode is shown;

[0033] Figure 2 A semiconductor device formed of an N-type transistor (NMOS) protected by a generic gate protection diode is shown in cross-section according to an embodiment;

[0034] Figure 3 A semiconductor device formed of a P-type transistor (PMOS) protected by the same generic gate protection diode is shown in cross-section according to an embodiment;

[0035] Figure 4 A final electrical diagram of two diodes in series according to an embodiment is shown;

[0036] Figure 5 A final electrical diagram of still two diodes in series according to an embodiment is shown, the two diodes in series being connected head-to-tail but in reverse order;

[0037] Figure 6 Steps for manufacturing a semiconductor device according to an embodiment are shown using a flowchart;

[0038] Figure 7 A semiconductor device according to various embodiments is shown in cross-section;

[0039] Figure 8 Implementations and embodiments of the present application are schematically shown.

[0040] For the sake of clarity, in the various drawings, the same elements have been denoted by the same reference numerals. Moreover, the various drawings are not drawn to scale, as is common in representations of integrated circuits. DETAILED DESCRIPTION

[0041] Figure 2 A semiconductor device 100 formed of an N-type transistor (NMOS) 130 protected by a generic gate protection diode 110 is shown in cross-section. Figure 3 A semiconductor device 100 formed of a P-type transistor (PMOS) 130 protected by the same generic gate protection diode 110 is shown in cross-section.

[0042] These devices can each form part of an integrated circuit (not shown here for reasons of clarity), or can even form part of the same integrated circuit.

[0043] Although the illustrated device shows a transistor protected by a gate protection diode, any other MOS component with a MOS capacitor between the gate and the body or "well" can be used with the general gate protection diode described below. This is especially true for MOS capacitors, whose diffusion region (carrying the gate) can be of the same or opposite doping type as its well, which is not the case for MOS transistors, which require opposite doping types between the gate and the well.

[0044] Traditionally, in a semiconductor substrate 120 (e.g. a lightly doped silicon substrate), an isolation trench 140 surrounds the active area in which the transistor 130 and the general gate protection diode 110 are formed. The isolation trench 140 is for example a narrow and shallow trench, for example filled with silicon oxide, often abbreviated as STI (shallow trench isolation).

[0045] To form the transistor 130, the active area is doped in a first region according to one doping type (P for NMOS transistors and N for PMOS transistors) to form the well 131 of the transistor, which first region 131 is covered with a gate insulator (not shown, typically silicon dioxide Si02) and a metal or polysilicon gate 132 doped with the other doping type (N for NMOS transistors and P for PMOS transistors). Thus, the gate 132 and the well 131 have opposite doping. The gate insulator well structure thus forms a MOS capacitor, denoted 139.

[0046] A second and third region of the active area, not covered by the gate 132, are doped with the other doping type (N for NMOS transistors and P for PMOS transistors) to form the source 133 and the drain 134 of the transistor 130.

[0047] The general gate protection diode 110 can be formed in the active area adjacent to the active area of the transistor 130 to be protected, or for example as shown in Figure 7 or Figure 8 in a more distant active area. The general gate protection diode 110 has a first doped region 112 at the surface of the active area and a second region 111 of opposite doping at the depth of the active area, so as to form a PN junction.

[0048] To form the general gate protection diode 110, the active area is doped in depth in a second region according to a doping type opposite to the doping type of the transistor 130 to form the body or well 111 of the diode 110. In the figure, the transistor 130 is P-doped. In addition, the body 111 of the diode 110 is N-doped.

[0049] The doping is performed so that the well 111 of the diode 110 is different from the well 131 of the transistor 130. This physical separation of the regions can be caused in particular by the spacing between the respective active regions due to the isolation trench or trenches 140.

[0050] In the figure, the shallowest parts of the wells 111, 131 are separated by at least one isolation trench 140, while the deepest parts of the wells 111, 131 are separated only by at least a portion of the substrate 120. In one embodiment, the entire depth of the wells 111, 131 is separated by at least one isolation trench 140.

[0051] The active region is also surface-doped in the first region in the same doping type as the doping type of the transistor 130, to form a diffusion region 112 of the diode 110. In the figure, the diffusion region 112 of the diode 110 is P-doped, like the substrate 120.

[0052] The gate 132 of the transistor 130 is electrically connected to the diffusion region 112 of the diode 110. A metal line 150 is shown in the figure, which typically has the form of a metal track in any layer of the BEOL integrated circuit interconnect portion located above the substrate.

[0053] In the proposed gate-protected diode 110 structure, the diffusion region 112-well 111 (here PN) junction defines a junction opposite to the well 111-substrate 120 (here NP) junction. As Figure 4 is shown, the resulting electrical diagram is that of two diodes in series, end to end.

[0054] The well 111 is set to a floating potential, so as to not generate a leakage current. This can be achieved by the physical separation of the well 111 from the well 131, which will be polarized during the operation of the transistor 130. The gate-protected diode 110 is said to be floating.

[0055] Thus, a gate discharge current, even a small current (of the order of hundreds of nA or of several μΑ), can be established between the gate 132 and the substrate 120 via the two junctions of the gate-protected diode 110, in order to eliminate the plasma charge accumulated at the gate 132 towards the substrate 120. Typically, the substrate 120 is polarized via an electrical contact on its bottom face (not shown). Typically, the P-type substrate 120 is connected to ground GND. The substrate 120 is also polarized to ground GND through the top face by means of various P-type well connections, which are themselves polarized to GND.

[0056] In operation, the regions of the transistor 130 are polarized, typically the source 133 and the P-type well 131 Figure 2 are connected to ground GND Figure 2the NMOS in Figure 1) or polarized to the supply voltage VDD Figure 3 the PMOS in Figure 1) and the drain 134 is polarized in the opposite way to the supply voltage VDD Figure 2 the NMOS in Figure 1) or to ground GND Figure 3 the PMOS in Figure 1).

[0057] When the gate 131 of the transistor 130 is polarized, whether polarized, accumulated or inverted, Figure 4 one of the two diodes in Figure 1 becomes blocking. Therefore, a very small current leaks through the gate protection diode 110.

[0058] This is why the same gate protection diode 110 can be used for NMOS and PMOS transistors (or more generally, capacitors), as shown in Figure 2 and Figure 3

[0059] Although these figures show a P-type substrate 120, similar considerations can be made in the case of an N-type substrate, which is typically polarized to the supply voltage VDD via an electrical contact on its bottom face (not shown). The only limitation is to produce an NPN 110 diode structure instead of the PNP structure shown in these figures. To achieve this, the diffusion region 112 and the well 111 of the diode 110 are doped in the opposite way.

[0060] Figure 5 The final electrical diagram is shown, in which there are still two diodes in series, which are connected end to end, but in reverse order.

[0061] Figure 6 The steps for manufacturing the semiconductor device 100 are illustrated using a flowchart.

[0062] The process starts with a step S1, called step 600, of obtaining a substrate 120 with a main doping of DP type (N or P). The counter-doping is called DI (P or N, respectively).

[0063] In a step S2, called 610, isolation trenches 140 are formed in the substrate 120, creating active regions between each pair of trenches. For example, a pattern of trenches is etched into the substrate 120, in which one or more dielectric materials, such as silicon dioxide SiO2, are deposited. The excess dielectric material can be removed using appropriate techniques, such as chemical mechanical planarization.

[0064] ​In a step S3, referred to as 620, the MOS transistor 130 or any MOS component (NMOS or PMOS) with a MOS capacitor 139 is formed in one of the active areas. To achieve this, the well 131 as well as the source 133 and drain 134 can be formed by ion implantation. The gate insulator and gate 132 are then deposited on the upper surface of the well 131 using conventional techniques, in succession. Conventional source, drain and substrate electrodes are also created to achieve their polarization.

[0065] In a step S4, referred to as 630, the gate protection diode 110 is formed in another of the active areas.

[0066] Again, ion implantation techniques can be used to form the well 111 deep and the diffusion region 112 at the surface. In the generic gate protection diode 110, the well 111 is DI doped, while the diffusion region 112 is DP doped. In addition, the well 111 is formed separately from the well 131 of the transistor 130 of the other active area.

[0067] A surface electrode in contact with the diffusion region 112 can also be deposited.

[0068] Of course, the order of steps 610-630 can be different depending on the techniques used to form the transistor 130, the diode 110 and the trench 140.

[0069] Then, a step S5, referred to as 640, comprises electrically connecting the gate protection diode 110 to the transistor 130 to be protected, usually by connecting the gate 131 to the electrode of the diffusion region 112.

[0070] Since the purpose of the gate protection diode 110 is to discharge the gate 131 during the plasma process used to form the integrated circuit interconnection part BEOL, the electrical connection between the gate 131 and the diffusion region 121 is preferably made in the first metal layer (or one of the frontmost layers) of the integrated circuit interconnection part.

[0071] Figure 6 These steps in the method can form part of a more general process for manufacturing a semiconductor integrated circuit.

[0072] Thus, the same generic gate protection diode 110 can be electrically connected (via its diffusion region 112) to two or more MOS components of an integrated circuit, each equipped with a MOS capacitor 139, as long as their gates are polarized at the same potential. These components can also be of different types (PMOS or NMOS).

[0073] Figure 7A semiconductor device 100 according to various embodiments is shown in cross-section.

[0074] In these embodiments, a semiconductor barrier is arranged between the gate protection diode 110 and the MOS component 130 to be protected (in this case a PMOS transistor). In the example shown, the barrier is a P-type barrier. Figure 7 In the example shown, the barrier is a P-type barrier. Figure 3 The configuration shown is repeated.

[0075] A first barrier 160, doped like the substrate 120 (in the example P), is arranged in the substrate 120 between the gate protection diode 110 and the MOS capacitor 139, and a second barrier 170, having a reverse doping (in the example N), is arranged in the substrate 120 between the first barrier layer 160 and the MOS capacitor 139.

[0076] These barriers 160, 170 have a depth similar to the depth of the gate protection diode 110 and the MOS component 130, and have a width of the order of μm (micrometers). In the figure, they are separated by the isolation trench 140. In addition, these barriers 160, 170 can be formed by ion implantation in the two active areas delimited by the isolation trench 140 formed in step 610.

[0077] Also, in the example shown in the figure, the first barrier 160 is located in the active area immediately adjacent to the gate protection diode, while the second barrier 170 is located in the next active area. Of course, other configurations are possible, in which a greater number of isolation trenches 140 separate the gate protection diode 110, the first barrier 160 and the second barrier 170.

[0078] As shown in the figure by the double references 160 and 170 on either side of the gate protection diode 110, the first and second barriers can each be configured to form a closed figure around the gate protection diode 110. Preferably, the first and second barriers form a ring (seen from above) around the gate protection diode. Other shapes, such as a rectangle or a square (in plan view), can be used in addition to the ring shape.

[0079] In operation, the first barrier 160 is polarized like the substrate to ground in the example shown, while the second barrier 170 is oppositely polarized to the supply voltage VDD in the example shown, so as to provide a stable polarization area between the diode 110 and the MOS component 130.

[0080] When the well 131 of the MOS component 130 is doped like the second barrier 170, a spacer region 180, which is doped like and polarized like the substrate, is also formed between the second barrier 170 and the MOS component 130, as shown. This spacer region 180 can be formed below the isolation trench 140 separating the second barrier 170 from the MOS component 130 (as shown), or can be formed as an additional barrier in the active region between the two isolation trenches 140 separating the second barrier 170 from the MOS component 130.

[0081] With respect to Figure 7 The described embodiments are also applicable to Figure 2 configurations, where NMOS transistors 130 are used instead of PMOS transistors. In this case, the well 131 is not doped like the second barrier 170; the spacer region 180 can be omitted, and the MOS components 130 can be placed in close proximity to the second barrier 170 (via the isolation trench 140), i.e. their wells can be in contact. This configuration is shown in Figure 8 .

[0082] In case a spacer is still required, the spacer region 180 can be maintained, which then comprises one or more pairs of contiguous counter-doped sub-regions, in order to maintain the alternative doping from the well 111 of the gate protection diode 110 to the well 131 of the NMOS transistor 130.

[0083] The various embodiments presented in connection with the above figures are also applicable to configurations using an N-type substrate instead of a P-type substrate. In this case, an NPN diode 110 structure is used instead of a PNP structure. In addition, the first barrier 160 Figure 7 or Figure 8 is then N-type, typically connected to the supply voltage, while the second barrier 170 is P-type, typically connected to ground.

Claims

1. A metal oxide semiconductor (MOS) device, comprising: a MOS capacitor having a well and a gate, wherein the MOS capacitor is disposed in a semiconductor substrate of a first doping type; as well as a gate protection diode disposed in the semiconductor substrate, the gate protection diode including a first region doped with the first doping type and coupled to the gate of the MOS capacitor, the gate protection diode including a second region different from the well of the MOS capacitor and doped with a second doping type different from the first doping type. 2 . The apparatus of claim 1 , wherein the second region of the gate protection diode is floating.

3. The apparatus according to claim 1, further comprising: a first barrier element doped with the first doping type, the first barrier element being between the gate protection diode and the MOS capacitor; as well as A second barrier is doped with the second doping type, and the second barrier is between the first barrier and the MOS capacitor. The apparatus of claim 3 , wherein the first and second barriers form a ring surrounding the gate protection diode.

5. The apparatus of claim 3 , wherein the first blocking member and the semiconductor substrate are coupled to a first potential node, and the second blocking member is coupled to a second potential node, the first potential node being a ground node or a supply voltage node, and the second potential node being the other of the ground node or the supply voltage node. 6 . The apparatus of claim 3 , wherein the first blocking member and the semiconductor substrate are coupled to a ground node or a supply voltage node, and the second blocking member is coupled to the other of the ground node or the supply voltage node.

7. The apparatus of claim 1, wherein the well of the MOS capacitor is doped with the first doping type.

8. The apparatus of claim 1, wherein the MOS capacitor forms part of a MOS field effect transistor.

9. A metal oxide semiconductor (MOS) integrated circuit comprising the MOS field effect transistor according to claim 8.

10. A circuit comprising: An N-channel metal oxide semiconductor (NMOS) transistor, the NMOS transistor having a well and a gate, the NMOS transistor being disposed in a semiconductor substrate of a first doping type; a first gate protection diode disposed in the semiconductor substrate, the first gate protection diode including a first region doped with the first doping type and coupled to the gate of the NMOS transistor, and the first gate protection diode including a second region different from the well of the NMOS transistor and doped with a second doping type different from the first doping type; a P-channel metal oxide semiconductor (PMOS) transistor, the PMOS transistor having a well and a gate, the PMOS transistor being disposed in the semiconductor substrate of the first doping type; as well as a second gate protection diode disposed in the semiconductor substrate, the second gate protection diode including a third region doped with the first doping type and coupled to the gate of the PMOS transistor, and the second gate protection diode including a fourth region different from the well of the PMOS transistor and doped with the second doping type.

11. The circuit of claim 10 , wherein each of the NMOS transistor and the PMOS transistor includes a first ring surrounding the corresponding first gate protection diode or the second gate protection diode and being doped with the first doping type, and each of the NMOS transistor and the PMOS transistor includes a second ring surrounding the first ring and being doped with the second doping type.

12. The circuit of claim 11, wherein the first loop and the second loop are polarized, one of the first loop and the second loop is coupled to a ground node, and the other of the first loop and the second loop is coupled to a supply voltage node.

13. The circuit of claim 11 , wherein the first ring and the semiconductor substrate are coupled to a first potential node, and the second ring is coupled to a second potential node, the first potential node being a ground node or a supply voltage node, and the second potential node being the other of the ground node or the supply voltage node.

14. A method of manufacturing a protected metal oxide semiconductor (MOS) device, the method comprising: forming a MOS capacitor in a semiconductor substrate of a first doping type, the MOS capacitor having a well and a gate; as well as A gate protection diode is formed in the semiconductor substrate, the gate protection diode including a first region doped with the first doping type and coupled to the gate of the MOS capacitor, and a second region different from the well of the MOS capacitor and doped with a second doping type different from the first doping type.

15. The method according to claim 14, further comprising: a first barrier element doped with the first doping type, the first barrier element being between the gate protection diode and the MOS capacitor; as well as A second barrier is doped with the second doping type, and the second barrier is between the first barrier and the MOS capacitor. The method of claim 15 , wherein the first barrier and the second barrier form a ring surrounding the gate protection diode.

17. The method of claim 15, wherein the first and second blocking members are polarized, one of the first and second blocking members is coupled to a ground node, and the other of the first and second blocking members is coupled to a supply voltage node.

18. The method of claim 15 , wherein the first blocking member and the semiconductor substrate are coupled to a first potential node, and the second blocking member is coupled to a second potential node, the first potential node being a ground node or a supply voltage node, and the second potential node being the other of the ground node or the supply voltage node.

19. The method of claim 14, wherein the well of the MOS capacitor is doped with the first doping type.

20. The method of claim 14, wherein the MOS capacitor forms part of a MOS field effect transistor.

Images