Large-exposure-field photoetching technology implementation method and chip-level chip interconnection method

Abstract

The invention discloses a photoetching technology implementation method with a large exposure field, a chip-level chip interconnection method and photoetching equipment. The photoetching technology implementation method with the large exposure field is applied to photoetching equipment, the photoetching equipment comprises a projection system with a reduction ratio of 0.1-2.5 times, and the method comprises the following steps: loading a to-be-exposed substrate with a pattern on an objective table, aligning through an alignment mark on the substrate, and offsetting a set offset distance; executing first exposure, and transferring a preset pattern of the mask to a first exposure area of the substrate through a projection system; the substrate or the mask plate is transversely stepped by M times of the transverse size of the original pattern unit or longitudinally stepped by N times of the longitudinal size of the original pattern unit, second exposure is executed, and the preset pattern is transferred to a second exposure area of the substrate through the projection system; and continuously executing transverse stepping or longitudinal stepping and second exposure until the exposure of the target area on the substrate is completed. According to the scheme, a large-size exposure field can be formed, and high-density interconnection of integrated circuits is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photoetching machines, in particular to a photoetching technology implementation method for a large exposure field, a photoetching technology implementation method for a large exposure field, a chip-level chip interconnection method and a photoetching device. BACKGROUND

[0002] In modern semiconductor manufacturing, photoetching technology is a key step to realize high-density integrated circuits. The photoetching process forms the required circuit structure by accurately transferring the pattern on the mask to the photoresist on the silicon wafer surface. With the continuous improvement of integrated circuit integration, the requirement for the minimum critical dimension (CD) is becoming more and more stringent. In the pattern exposure of a photoetching machine, the limit of the minimum critical dimension can be theoretically estimated by the Rayleigh rule for resolution, as shown in formula (1): Formula (1) Wherein, is the wavelength of the light source of the photoetching machine used, is the numerical aperture of the photoetching machine projection system used for exposure, is a regulation factor depending on the photoetching process, also known as Rayleigh constant, is the minimum size of the pattern. As can be seen from formula (1), there are three ways to reduce the minimum size of the pattern: shortening the exposure wavelength , increasing the numerical aperture , or reducing . It is difficult and costly to reduce the minimum size of the pattern by the above three ways. In addition, with the continuous reduction of device size, the leakage problem caused by quantum tunneling effect is becoming more and more serious, which limits the feasibility of further reducing the minimum size of the pattern. Therefore, it is no longer feasible to simply rely on reducing the key size of the device to increase the number of transistors.

[0003] In order to accommodate more transistors, it is extremely important to manufacture larger chips. However, the maximum exposure field size of the traditional photoetching machine is limited to about 26mm × 33mm, which cannot meet the demand of manufacturing larger size chips. In some liquid crystal panel fields, large exposure field has also been realized, but the line size obtained by this method is too wide, which is difficult to meet the high-density integration demand of integrated circuits. Therefore, how to realize large exposure field has become a technical problem to be solved in photoetching technology. SUMMARY

[0004] The application provides a large-exposure-field photolithography technology implementation method, a large-exposure-field photolithography technology implementation method, a chip-level chip interconnection method and a photolithography device, which can form a large-size exposure field, realize high-density interconnection of integrated circuits, and provide photolithography technology support for high-density interconnection integration of multiple large chips. The specific scheme is as follows. In a first aspect, the embodiments of the application provide a large-exposure-field photolithography technology implementation method applied to a photolithography device, wherein the photolithography device comprises a projection system with a reduction ratio of 0.1 to 2.5 times, and the method comprises the following steps: loading a patterned substrate to be exposed into a stage of the photolithography device, aligning through alignment marks on the substrate, and offsetting by a set offset distance; performing first exposure, transferring a preset pattern on a mask to a first exposure area on the substrate through the projection system, and the first exposure area covers at least M*N original pattern unit corresponding pattern areas; stepping the substrate by M times of the lateral size of the original pattern unit in the lateral direction, or stepping the substrate by N times of the longitudinal size of the original pattern unit in the longitudinal direction, aligning through the alignment marks on the substrate, and offsetting by a set offset distance; performing second exposure, transferring a preset pattern on a mask to a second exposure area on the substrate through the projection system, and the second exposure area covers at least M*N original pattern unit corresponding pattern areas; continuously performing the lateral or longitudinal stepping and the second exposure until the exposure of all target areas of the substrate is completed; wherein at least one of M and N is an integer greater than or equal to 2.

[0005] Optionally, when the alignment marks on the substrate are alignment marks set for the projection system with a reduction ratio of 0.1 to 2.5 times, the set offset distance is 0.

[0006] Optionally, the reduction ratio of the projection system comprises any one of 0.1, 0.125, 0.2, 0.25, 0.4, 0.5, 1.0, 1.25, 2 and 2.5 times.

[0007] Optionally, the size of the first exposure area is M*N times of 26mm*33mm.

[0008] Optionally, the original pattern unit corresponding pattern area is a pattern area formed by exposure of a projection system with a reduction ratio of 4 to 10 times.

[0009] Optionally, the substrate is one of a silicon substrate, a germanium substrate, a compound semiconductor substrate, a ceramic carrier plate, a glass carrier plate, a quartz carrier plate, a silicon carrier plate and a metal carrier plate.

[0010] Optionally, the substrate is loaded with one or more of a silicon substrate, a germanium substrate, and a compound semiconductor substrate.

[0011] Optionally, the original pattern unit is one or more of an integrated circuit pattern, an optical path pattern, a microfluidic channel, a metal wiring, a via, and a sensor pattern.

[0012] Optionally, the original pattern unit is an integrated circuit pattern unit.

[0013] Optionally, the lithography apparatus includes a light source, and the method further includes: if the light source is a mercury lamp or a light source generated by an excimer laser, filling a liquid immersion medium between the projection system and the substrate on the stage.

[0014] Optionally, the stage is one or two, and each of the stages is loaded with a substrate to be exposed.

[0015] Optionally, when the stage is two, the method further includes: controlling the two stages to move to the projection system in turn to complete exposure.

[0016] Optionally, the two stages include a first stage and a second stage, and the method further includes: controlling the second stage to perform the steps of loading and unloading a silicon wafer and pre-alignment during the alignment and exposure performed by the first stage.

[0017] Optionally, the lithography apparatus includes a light source, and the method further includes: if the light source is an EUV light source, the projection system is a reflective projection system.

[0018] In a second aspect, an implementation of a method for implementing a lithography technology with a large exposure field is provided, and the method is applied to a lithography apparatus, the lithography apparatus includes a projection system with a reduction ratio of 0.1 to 2.5, and the method includes: loading a substrate to be exposed with a pattern onto a stage of the lithography apparatus, performing alignment through alignment marks on the substrate, and offsetting a set offset distance; performing a first exposure to transfer a preset pattern on a mask to a first exposure area on the substrate through the projection system, and the first exposure area covers at least M×N original pattern unit corresponding pattern areas; stepping the substrate along a lateral direction by a sum of lateral dimensions of M original pattern units, or along a longitudinal direction by a sum of longitudinal dimensions of N original pattern units, performing alignment through alignment marks on the substrate, and offsetting a set offset distance; performing a second exposure by transferring the preset pattern on the mask to a second exposure area on the substrate through the projection system, the second exposure area covering at least the corresponding pattern area of the M*N original pattern units; continuously performing the lateral stepping or longitudinal stepping and the second exposure until the exposure of all target areas on the substrate is completed; wherein at least part of the original pattern units in the M*N original pattern units have different sizes; and at least one of M and N is an integer greater than or equal to 2.

[0019] In a third aspect, an embodiment of the present application provides a chip-level chip interconnection method, comprising: providing a substrate, and forming a semiconductor structure comprising at least two semiconductor chips on the substrate, each semiconductor chip having formed chip-in interconnection, and no interconnection between the semiconductor chips; performing a photolithography step of interconnection between the at least two semiconductor chips by the large-exposure-field photolithography technology implementation method as in any of the first aspect.

[0020] In a fourth aspect, an embodiment of the present application provides a photolithography device, comprising a projection system with a reduction ratio of 0.1 to 2.5.

[0021] Compared with the prior art, the present application has the following advantages: The large-exposure-field photolithography technology implementation method provided by the first embodiment of the present application, after alignment through the alignment mark on the substrate and offset by a set offset distance, the substrate will be aligned with the preset pattern on the mask; then, the preset pattern on the mask is transferred to a first exposure area on the substrate through the projection system, since the projection system has a reduction ratio of 0.1 to 2.5, thus, the formed first exposure area will cover at least the corresponding pattern area of the M*N original pattern units, and at least one of M and N is an integer greater than or equal to 2. Then, one of the substrate or the mask is stepped by M times the lateral size of the original pattern unit in the lateral direction, or stepped by N times the longitudinal size of the original pattern unit in the longitudinal direction, and a second exposure is performed, the preset pattern on the mask is transferred to a second exposure area on the substrate through the projection system, thus, the formed second exposure area will cover at least the corresponding pattern area of the M*N original pattern units; the above steps of stepping by M times the corresponding image size of the original pattern unit in the lateral direction or stepping by N times the corresponding image size of the original pattern unit in the longitudinal direction and the second exposure are continuously performed until the exposure of all target areas on the substrate is completed.

[0022] It can be seen that the method for implementing the lithography technology of a large exposure field provided in the embodiment of the present application forms a large-size exposure field through a projection system with a reduction ratio of 0.1 to 2.5 times, compensates for the alignment deviation caused by the inconsistent projection ratio of the projection system through the offset distance set by offsetting, overcomes the image overlapping problem when a plurality of images are covered by stepping the original image unit by the original image unit stepping distance through the lateral stepping of the lateral size of the original image unit by M times and the longitudinal stepping of the longitudinal size of the original image unit by N times, and well implements the alignment, covering and stepping of M×N original image units. And the method continuously steps, aligns, offsets and exposes to complete the exposure of the target region on the substrate, thereby realizing the high-density interconnection of integrated circuits and providing lithography technology support for the high-density interconnection integration of multiple large chips. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 FIG. 1 is a structural diagram of a lithography device to which the method for implementing the lithography technology of a large exposure field provided in the embodiment of the present application is applied.

[0024] Figure 2 FIG. 2 is a schematic diagram of an example in which an integrated circuit is loaded on a carrier plate in the method for implementing the lithography technology of a large exposure field provided in the embodiment of the present application.

[0025] Figure 3 FIG. 3 is a cross-sectional schematic diagram of a logic device of an integrated circuit.

[0026] Figure 4 FIG. 4 is a structural diagram of a lithography device based on an EUV light source provided in the embodiment of the present application.

[0027] Figure 5 FIG. 5 is a flowchart of a method for implementing the lithography technology of a large exposure field provided in the embodiment of the present application.

[0028] Figure 6 FIG. 6 is a schematic diagram of an example in which an image region corresponding to M×N original image units is covered in the method for implementing the lithography technology of a large exposure field provided in the embodiment of the present application.

[0029] Figure 7 FIG. 7 is a schematic diagram of an example of a second exposure region in the method for implementing the lithography technology of a large exposure field provided in the embodiment of the present application.

[0030] Figure 8 FIG. 8 is a schematic diagram of an example in which a plurality of original image units with different sizes are included in an M×N chip group in the method for implementing the lithography technology of a large exposure field provided in the embodiment of the present application.

[0031] Figure 9 FIG. 9 is a schematic diagram of an example of a composite original image unit in the method for implementing the lithography technology of a large exposure field provided in the embodiment of the present application. DETAILED DESCRIPTION

[0032] In the following description, numerous specific details are set forth to provide a thorough understanding of the present application. However, the present application can be practiced without the specific details. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure aspects of the present application.

[0033] It should be noted that the terms "first", "second", "third", and the like in the description and in the claims of the present application are used for distinguishing between similar objects and not necessarily for describing a sequential or chronological order. The use of such terms in the description is therefore not to be construed as implying a specific order or sequence. Also, the terms "comprises", "comprising", "has", "having", "includes", "including", and the like, are to be construed open-ended, for example, in the sense that they allow for out of the process, method, system, product or apparatus to include a series of steps or elements not expressly listed or inherent to such process, method, system, product or apparatus. Thus, such terms are to be interpreted as specifying "at least the following" or "one or more" of the enumerated steps or elements.

[0034] It should be understood that, in the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" is only a description of the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects. "Including A, B and / or C" means including any one or any two or three of A, B and C.

[0035] It should be understood that, in the embodiments of the present application, "B corresponding to A", "B corresponding to A", "A corresponding to B", or "B corresponding to A" means that B is associated with A, and B can be determined according to A. Determining B according to A does not mean that B is determined only according to A, but also can be determined according to A and / or other information.

[0036] Based on the reasons mentioned in the background, in order to form a large exposure field, realize high-density interconnection of integrated circuits, and provide lithography technology support for high-density interconnection integration of multiple large chips, the present application provides a large exposure field lithography technology implementation method, which is applied to a lithography device.

[0037] First, the application scenario of the large exposure field lithography technology implementation method provided by the embodiments of the present application is introduced: The method provided by the embodiments of the present application can be applied to top layer or sub-top layer photolithography process, which is a step in the back-end of integrated circuit manufacturing, and is mainly used for forming the uppermost metal interconnection and contact hole structure. Since the top layer photolithography does not involve fine transistor structure, the minimum critical dimension requirement is relatively low, and the method of the large exposure field photolithography technology provided by the embodiments of the present application can be used to realize the method, the exposure field of large size is formed, the exposure times are reduced, the photolithography process efficiency is improved, and the purpose of high-density interconnection of multiple large chips is achieved. It should be noted that although the line size (usually 0.1 micrometer level (such as 0.1 micrometer to tens of micrometers)) of the method of the large exposure field photolithography technology provided by the present application is relatively thick compared with the line size (usually nanometer level (such as several nanometers to tens of nanometers)) of the traditional photolithography machine (such as EUV photolithography machine), the line size obtained by the present application can be several orders of magnitude thinner than the line size (usually 0.1 millimeter level or larger) of the interconnection between multiple large chips realized by the traditional packaging.

[0038] As shown in Figure 1 is a structure diagram of an example of a photolithography equipment to which the method of the large exposure field photolithography technology provided by the embodiments of the present application is applied. The photolithography equipment includes: a light source 100 for providing exposure light beams required by photolithography; the light source type of the light source 100 can include but is not limited to one of a mercury lamp, an excimer laser, and an extreme ultraviolet (EUV) light source. The mercury lamp can emit light of multiple discrete wavelengths, including g-line (436 nm), i-line (365 nm), etc., which are suitable for photolithography processes with different resolution requirements; the excimer laser can generate ultraviolet light with shorter wavelength, such as KrF (248 nm), ArF (193 nm), etc., and the short wavelength helps to improve the photolithography resolution and is suitable for fine patterning requirements; the wavelength of the EUV light source is 13.5 nm, which is much shorter than the traditional DUV light source. This makes it possible to perform photolithography at extremely high resolution, which is suitable for the most advanced semiconductor manufacturing process. The generation method of the EUV light source includes but is not limited to converting a material into a plasma state with at least one element (such as xenon, lithium or tin) having one or more emission lines in the EUV range; a mask 200 for providing a preset pattern required by exposure; 0.1 to 2.5 times reduction ratio of a projection system 300 for transferring a preset pattern on the mask 200 to the substrate 500 to be exposed; optionally, the reduction ratio of the projection system 300 can include at least any one of 0.1, 0.125, 0.2, 0.25, 0.4, 0.5, 1.0, 1.25, 2, 2.5 times, and the required reduction ratio can be selected according to the minimum critical dimension requirement and the size requirement of the exposure field (i.e., the first exposure area and the second exposure area) to be formed, which is not limited in the present application.

[0039] A substrate table 400 for loading the substrate 500 and completing the stepping of the substrate 500.

[0040] The substrate 500 can be a silicon wafer with integrated circuit patterns, a carrier plate with integrated circuits, or a carrier plate without integrated circuits. The carrier plate includes but is not limited to one of a ceramic carrier plate, a glass carrier plate, a quartz carrier plate, a silicon carrier plate, and a metal carrier plate.

[0041] The substrate 500 can be a composite substrate composed of an integrated circuit substrate (including a silicon substrate, a germanium substrate, a compound semiconductor, etc.) and a carrier plate (including a ceramic carrier plate, or a glass carrier plate, or a quartz carrier plate, or a silicon carrier plate, or a metal carrier plate, etc.) for supporting the integrated circuit substrate. By using the implementation method of the photolithography technology provided in the present application, the KGD (know good die) chip can be accurately bonded to the carrier plate, and the composite substrate can be further interconnected at high density. The KGD (know good die) chip refers to an independent chip verified as normal function in wafer-level testing, which has good function and reliability before being integrated into a more complex system.

[0042] The substrate 500 can also be loaded with one or more of a silicon substrate, a germanium substrate, a compound semiconductor substrate, and a carrier plate. The longitudinal dimensions of the single original pattern units respectively existing on the silicon substrate, the germanium substrate, and the compound semiconductor substrate are the same or different, and the transverse dimensions of the single original pattern units respectively existing on the silicon substrate, the germanium substrate, and the compound semiconductor substrate are the same or different.

[0043] In this way, multiple small silicon wafers or small carrier plates can be installed on a large carrier plate to improve efficiency, and different models of small silicon wafers or small carrier plates can be installed on a large carrier plate to achieve high-density interconnection of different models of small silicon wafers or small carrier plates in a large-size chip mode.

[0044] In the structure that the substrate 500 is a substrate 502 loaded with a plurality of silicon substrates, or a plurality of germanium substrates, or a plurality of compound semiconductor substrates, or a plurality of carrier boards, the silicon substrates are the same or not the same, and / or the germanium substrates are the same or not the same, and / or the compound semiconductors are the same or not the same, and / or the carrier boards are the same or not the same. The silicon substrates, germanium substrates, compound semiconductor substrates, and carrier boards can be placed according to actual needs, which are not limited in the present application.

[0045] The carrier board without integrated circuits will form one or more layers of metal wiring and / or optical path wiring after completing one exposure or multiple exposures, and the formed metal wiring and / or optical path wiring is used to connect integrated circuits, sensors, or optoelectronic devices in subsequent stages. Then, the exposure and lithography can be performed using the method provided by the large exposure field lithography technology embodiment of the present application.

[0046] The original pattern unit is one or more of an integrated circuit pattern, an optical path pattern, a microfluidic channel, metal wiring, a via, and a sensor pattern. The original pattern unit can be an integrated circuit pattern unit.

[0047] There can be one or more silicon wafers and / or one or more carrier boards on the carrier board. In this way, multiple small silicon wafers or small carrier boards can be installed on a large carrier board to improve efficiency, and different models of small silicon wafers or small carrier boards can be installed on a large carrier board to achieve high-density interconnection of different models of small silicon wafers or small carrier boards in a large-size chip mode.

[0048] The size of the carrier board can be 40 mm to 4000 mm, such as 40 mm, 80 mm, 100 mm, 150 mm, 300 mm, 600 mm, 1200 mm, 2400 mm, 3000 mm, 3600 mm, or 4000 mm, etc.

[0049] The carrier board can be circular or square. Compared with a square carrier board, a circular carrier board has a higher matching degree with a silicon wafer; compared with a circular carrier board, a square carrier board has a higher utilization rate.

[0050] The substrate 500 further includes a primary alignment device 510 for primary alignment of the substrate. It should be noted that when the substrate 500 does not have a primary alignment device 510, alignment can also be performed by the shape of the carrier board itself.

[0051] It should be noted that for thinned integrated circuits, it is often difficult to clamp due to too large warpage or too thin. In this case, as shown in FIG. 6, a carrier board 600 is used to clamp the thinned integrated circuit 500, and the carrier board 600 is used as a carrier board for the integrated circuit 500. Figure 2, which is a schematic diagram of an example of an integrated circuit being loaded on a carrier in the implementation method of the large exposure field lithography technology provided by an embodiment of the present application. The thinned integrated circuit 503 can be loaded on the carrier 502 .

[0052] The integrated circuit pattern can be a single-layer integrated circuit pattern or a multi-layer integrated circuit pattern. As three-dimensional integrated circuit technology becomes increasingly mature, the large exposure field lithography method provided in the embodiments of the present application can also be applied to chips with stacked multi-layer integrated circuits. In other words, the method provided in the embodiments of the present application can also be effectively implemented under the condition of complex structures formed after multi-layer circuit integration.

[0053] In the multi-layer integrated circuit pattern, the materials of the integrated circuit patterns in different layers can be the same or different. In this way, large exposure sizes such as silicon-based-silicon-based, silicon-based-compound semiconductor, silicon-based-carbon-based, and silicon-based-germanium-silicon semiconductor can be integrated together to form a complex large chip.

[0054] like Figure 3 Figure 2 shows a schematic cross-sectional view of a logic device in an integrated circuit. In the large exposure field lithography method provided in the embodiments of the present application, the integrated circuit on the substrate to be exposed can be an integrated circuit that has completed the front-end of line (FEOL) and back-end of line (BEOL) processes, and / or an integrated circuit that has partially completed the front-end of line (FEOL) and back-end of line (BEOL) processes. The specific process step to start intervention can be selected based on actual needs to achieve the desired effect.

[0055] The type of integrated circuit may include, but is not limited to, at least one of an integrated circuit with integrated electrical functions, an integrated circuit with integrated optical / photoelectric functions, and an integrated circuit with integrated sensor functions. In other words, the large exposure field lithography method provided in the embodiments of this application can be applied to any of these integrated circuits for further large exposure field exposure integration. The type of integrated circuit may be selected based on actual needs and is not specifically limited in this application.

[0056] exist Figure 1 In the photolithography device shown, the light source 100 forms an exposure beam through the illumination system. The exposure beam passes through the mask 200, and transfers the preset pattern on the mask 200 to the substrate 500 loaded on the stage 400 through the projection system 300. Thereafter, photolithography is performed on the photoresist material to form an exposure field pattern.

[0057] It should be noted that if the light source of the light source 100 is an EUV light source, the projection system 300 is a reflective projection system, as shown in Figure 4 The structure diagram of the photolithography equipment based on the EUV light source provided by the embodiment of the present application is shown in Figure 4 In the photolithography equipment shown in the figure, the light source 100 forms an exposure light beam through an illumination system, the exposure light beam passes through the mask plate 200, the preset pattern on the mask plate 200 is reflected to the substrate 500 loaded on the object table 400 through the reflective projection system 300, and then the photolithography is performed on the photoresist material to form an exposure field pattern. In this way, the problem that the extreme ultraviolet light (EUV) is easily absorbed by the light-transmitting material, causing the exposure light beam to be unable to reach the substrate, is avoided.

[0058] If the light source of the light source 100 is a mercury lamp or a light source generated by a quasi-molecular laser, the projection system 300 and the substrate 500 are filled with an immersion liquid (such as deionized water, etc.). Compared with the traditional photolithography method in which the exposure light beam directly reaches the surface of the silicon wafer from the projection system, the present application increases the refractive index of the medium by filling the immersion liquid, improves the numerical aperture NA of the optical system, and thus reduces the minimum critical dimension.

[0059] The above is the introduction of the photolithography equipment provided by the embodiment of the present application.

[0060] It should be noted that the photolithography technology implementation method of the large exposure field provided by the present application is mainly used to solve the interconnection between multiple large chips close to the exposure field limit (about 26mm*33mm) of the traditional integrated circuit, but after the new pattern is manufactured by the present application, the new alignment structure of the new pattern manufactured by the present application can also be used for alignment and exposure; or the large exposure field characteristic of the present application is directly used to manufacture patterns on the substrate without integrated circuit patterns, so as to efficiently manufacture larger chips than the chips manufactured by the traditional photolithography method or manufacture a carrier board with higher density lines under the premise of ensuring a large area. These are the intended purposes of the present application, which will not be described here.

[0061] The technical solutions of the present application will be described in detail through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0062] As shown in Figure 5 The flow chart of the photolithography technology implementation method of the large exposure field provided by the first embodiment of the present application is shown in the figure, which includes steps S101-S105: Step S101: loading a substrate with patterns to be exposed to the object table of the photolithography equipment, aligning through the alignment marks on the substrate, and offsetting a set offset distance; This step is used to preliminarily position the substrate when the patterned substrate to be exposed is initially loaded to the stage.

[0063] The substrate has alignment marks (as shown in FIG. 5) such as laser stepping alignment marks (LSA) and / or field image alignment marks (FIA) on it, or alignment marks designed for the alignment system of the photolithography equipment involved in this application. Figure 6 There can be one or more alignment marks on the substrate, which can be arranged in the scribe lane to avoid affecting the functional area of the chip.

[0064] Specifically, before starting the photolithography, the wafer is transferred from the carrier to the stage of the photolithography equipment by a mechanical arm or a vacuum suction system, at this time, the wafer is roughly placed at a certain position on the stage; then, the wafer is scanned by a high-resolution camera or other sensors installed on the photolithography equipment, and the preliminary alignment is performed by the primary alignment device 510 or the shape features of the substrate, and if necessary, the accurate alignment of the substrate is performed by one or more alignment marks of the alignment marks 520, and the preparation work of the substrate to be exposed is performed. Then the stage sends the exposure area of the substrate to the projection system, and the accurate alignment is performed by one or more alignment marks of the alignment marks 520 on the substrate.

[0065] It should be noted that since the photolithography equipment used in this application is a large exposure field photolithography equipment, the exposure field size is different from that of the photolithography equipment for making the original pattern, and there is generally an alignment offset problem, therefore, the offset distance needs to be set in advance, and the alignment and exposure are performed according to the offset position. That is, after the accurate alignment is performed by one or more alignment marks of the alignment marks 520 on the substrate, the set offset distance is offset. It should be noted that the setting of this offset distance can be set in the wafer alignment offset, or in the mask alignment offset, or a part of it is set for the wafer and a part of it is set for the mask, all of which can achieve the purpose of offsetting the set offset distance.

[0066] In an optional embodiment, the alignment marks on the substrate are alignment marks set for the projection system with a reduction ratio of 0.1 to 2.5 times. That is, when making the original pattern, the photolithography equipment with the projection system with a reduction ratio of 0.1 to 2.5 times is considered to be compatible, and the alignment marks are specially set for it, and the set alignment marks have considered the offset value. In this case, the offset distance of the photolithography equipment can be set to 0.

[0067] It should be noted that in FIG. 5, the alignment marks 520 are shown as being arranged on the substrate, but the alignment marks 520 can also be arranged on the mask, and the alignment marks 520 on the mask can be arranged in the scribe lane to avoid affecting the functional area of the chip. Figure 6In the figure, the alignment mark 520 is only shown at the original graphic unit 620. In actual application, each original graphic unit (such as 610, 620, 630, 640) has its own alignment mark. Figure 6 The markings shown are for simplicity of illustration. Furthermore, in actual use, typically only the alignment mark 520 of one of the original graphic units (e.g., 620) is used (and if necessary, the alignment marks of multiple original graphic units can be used simultaneously to better ensure alignment accuracy over a large exposure field).

[0068] Step S102: performing a first exposure, transferring the preset pattern on the mask to a first exposure area on the substrate through the projection system, wherein the first exposure area covers at least M×N pattern areas corresponding to the original pattern units; Wherein, at least one of M and N is an integer greater than or equal to 2, and M and N may be the same or different. This application does not impose any restrictions on the specific values ​​of M and N. For example, to interconnect two chips horizontally, M may be selected to be 2 and N may be selected to be 1; for another example, to interconnect three chips horizontally, M may be selected to be 3 and N may be selected to be 1; for another example, to interconnect two chips vertically, M may be selected to be 1 and N may be selected to be 2; for another example, to interconnect four chips arranged in a 2×2 matrix (i.e., two chips distributed horizontally and two chips distributed vertically), M may be selected to be 2 and N may be selected to be 2; for another example, to interconnect 12 chips arranged in a 3×4 matrix (i.e., three chips distributed horizontally and four chips distributed vertically), M may be selected to be 3 and N may be selected to be 4.

[0069] The original graphic unit here generally refers to a single large chip integrated circuit that is close to the maximum size of the exposure field of a traditional lithography machine (such as a DUV (deep ultraviolet) lithography machine) (approximately 26mm*33mm). This application mainly breaks through the maximum size limit of the exposure field of a traditional lithography machine and connects multiple large chips (such as a single chip size close to 26mm*33mm) with high-density lines.

[0070] This step is used to project and expose the preset pattern on the mask to the area to be exposed on the substrate.

[0071] The reduction ratio of the projection system is 0.1 to 2.5 times, which means that the projection system can magnify the preset pattern on the mask by 10 times or reduce it by 2.5 times and project it onto the substrate.

[0072] Optionally, the reduction ratio of the projection system is 0.1 times. In this case, if the width of the line on the mask is 50 nanometers, a 0.5 micron line will be formed on the substrate after projection through the projection system.

[0073] Optionally, the reduction ratio of the projection system is 0.125 times, in which case, if the width of the line on the mask is 50 nanometers, then after projection by the projection system, a line of 0.4 micrometers will be formed on the substrate.

[0074] Optionally, the reduction ratio of the projection system is 0.2 times, in which case, if the width of the line on the mask is 50 nanometers, then after projection by the projection system, a line of 0.25 micrometers will be formed on the substrate.

[0075] Optionally, the reduction ratio of the projection system is 0.25 times, in which case, if the width of the line on the mask is 50 nanometers, then after projection by the projection system, a line of 0.2 micrometers will be formed on the substrate.

[0076] Optionally, the reduction ratio of the projection system is 0.4 times, in which case, if the width of the line on the mask is 50 nanometers, then after projection by the projection system, a line of 0.125 micrometers will be formed on the substrate.

[0077] Optionally, the reduction ratio of the projection system is 0.5 times, in which case, if the width of the line on the mask is 50 nanometers, then after projection by the projection system, a line of 0.1 micrometers will be formed on the substrate.

[0078] Optionally, the reduction ratio of the projection system is 1 times, in which case, if the width of the line on the mask is 50 nanometers, then after projection by the projection system, a line of 50 nanometers will be formed on the substrate.

[0079] Optionally, the reduction ratio of the projection system is 1.25 times, in which case, if the width of the line on the mask is 50 nanometers, then after projection by the projection system, a line of 40 nanometers will be formed on the substrate.

[0080] Optionally, the reduction ratio of the projection system is 2 times, in which case, if the width of the line on the mask is 50 nanometers, then after projection by the projection system, a line of 25 nanometers will be formed on the substrate.

[0081] Optionally, the reduction ratio of the projection system is 2.5 times, in which case, if the width of the line on the mask is 50 nanometers, then after projection by the projection system, a line of 20 nanometers will be formed on the substrate.

[0082] The preset pattern on the mask is transferred to the first exposure area on the substrate by the projection system, and the first exposure area formed by one-time exposure covers at least M (lateral) × N (vertical) original pattern unit corresponding pattern areas. The original pattern unit corresponding pattern area refers to a single-time exposure pattern area formed by a conventional projection system with a reduction ratio of 4 to 10 or other reduction ratios. For example, the original pattern unit corresponding pattern area is a single-time exposure pattern area formed by a projection system with a reduction ratio of 4; for another example, the original pattern unit corresponding pattern area is a single-time exposure pattern area formed by a projection system with a reduction ratio of 5; for another example, the original pattern unit corresponding pattern area is a single-time exposure pattern area formed by a projection system with a reduction ratio of 8; for another example, the original pattern unit corresponding pattern area is a single-time exposure pattern area formed by a projection system with a reduction ratio of 10. That is, the exposure field of one-time exposure of the present application covers at least two conventional exposure pattern areas (covers the scribe lane area between the two conventional exposure pattern areas), and by increasing the area of single-time exposure, more original pattern unit corresponding pattern areas can be covered at one time, thereby realizing inter-chip interconnection.

[0083] When the method provided in the embodiments of the present application is applied to top layer photolithography, the original pattern unit corresponding pattern area can be understood as a pattern area formed by one-time exposure in the previous layer photolithography.

[0084] It should be noted that a projection system with a reduction ratio of 4 to 10 is generally used in the previous layer photolithography. Taking a projection system with a reduction ratio of 5 as an example, after synchronous scanning movement of the workpiece table and the mask table, the maximum size of the exposure field formed by exposure is generally 26 mm × 33 mm. In this case, the maximum size of the original pattern unit corresponding pattern area is generally less than or equal to 26 mm × 33 mm.

[0085] That is, taking the maximum 26 mm × 33 mm as an example, the first exposure area formed in the step covers at least two 26 mm × 33 mm single-time exposure pattern areas. Specifically, the first exposure area can cover 1, 2, 3 or 4 or the like number of 26 mm × 33 mm single-time exposure pattern areas in the lateral direction, and can also cover 1, 2, 3 or 4 or the like number of 26 mm × 33 mm single-time exposure pattern areas in the vertical direction. When the first exposure area covers 1 26 mm × 33 mm single-time exposure pattern area in the lateral direction, it will cover 2, 3 or 4 or the like number of 26 mm × 33 mm single-time exposure pattern areas in the vertical direction; when the first exposure area covers 1 26 mm × 33 mm single-time exposure pattern area in the vertical direction, it will cover 2, 3 or 4 or the like number of 26 mm × 33 mm single-time exposure pattern areas in the lateral direction.

[0086] It should be noted that the above 26mm x 33mm is a special example, and the original pattern unit corresponding to the pattern area can also be less than 26mm x 33mm. That is, the first exposure area formed in this step can cover at least two single exposure pattern areas less than 26mm x 33mm. Specifically, the first exposure area can cover one, two, three, or four, etc. number of single exposure pattern areas less than 26mm x 33mm in the horizontal direction, and can also cover one, two, three, or four, etc. number of single exposure pattern areas less than 26mm x 33mm in the vertical direction. When the first exposure area covers one single exposure pattern area less than 26mm x 33mm in the horizontal direction, it will cover two, three, or four, etc. number of single exposure pattern areas less than 26mm x 33mm in the vertical direction; when the first exposure area covers one single exposure pattern area less than 26mm x 33mm in the vertical direction, it will cover two, three, or four, etc. number of single exposure pattern areas less than 26mm x 33mm in the horizontal direction.

[0087] As shown in Figure 6 , it is an example of covering M x N original pattern unit corresponding image areas in the large exposure field lithography technology implementation method provided by the embodiment of the application. By using the lithography equipment shown in Figure 1 or the lithography equipment shown in Figure 4 , the preset pattern on the mask 200 can be transferred to the first exposure area 700 of the substrate 500, and the first exposure area covers 2 x 2 original pattern unit corresponding pattern areas, specifically, it covers 2 original pattern unit corresponding pattern areas in the horizontal direction, which are the front layer pattern 610 and the front layer pattern 620, respectively, and covers 2 original pattern unit corresponding pattern areas in the vertical direction, which are the front layer pattern 630 and the front layer pattern 640, respectively.

[0088] Through this step, a single exposure can cover M x N original pattern unit corresponding pattern areas to obtain a large-size first exposure area. In this way, the multiple chips can now be connected to tens of thousands or even hundreds of thousands of lines, greatly improving the communication capability between chips and enabling high-density interconnection between multiple chips.

[0089] In the prior art, when implementing chip interconnection, the main way is to implement it through the on-board interconnection, which is usually implemented through the circuit board interconnection after packaging. This way not only has a complex structure, but also has a large size. In the use process, the signal needs to be transmitted through a long circuit board path, which will cause high signal delay. In addition, the long-distance wiring is easy to be affected by problems such as electromagnetic interference, which will cause signal distortion. The long line and driving circuit will also cause large capacitive load, which will inevitably increase power consumption. Compared with the prior art, the large exposure field photolithography technology implementation method provided by the present application can realize chip-level interconnection. In this way, multiple chips can be connected together in the process of chip manufacturing. In the use process, since the interconnection distance is shortened, the signal transmission time will be significantly reduced, and the risk of signal distortion can be reduced, the signal integrity can be improved, and the parasitic load can be reduced, thereby reducing the power consumption.

[0090] Step S103: Step the substrate along the lateral direction by M times the lateral size of the original pattern unit, or along the longitudinal direction by N times the longitudinal size of the original pattern unit, align through the alignment mark on the substrate, and offset by a set offset distance.

[0091] This step is used to step the substrate after the first exposure area is exposed, to provide a good basis for exposing the second exposure area adjacent to the first exposure area on the substrate.

[0092] Before performing the second exposure, the target stepping mode can be selected according to the needs, and the target stepping mode is a lateral stepping mode or a longitudinal stepping mode. In this way, the objective table can be controlled to step according to the target stepping mode.

[0093] In step S102, after performing the first exposure, the size of the first exposure area formed covers at least M (lateral) x N (longitudinal) original pattern unit corresponding pattern areas. In this way, when the target stepping mode is a lateral stepping mode, the stepping distance is M times the lateral size of the original pattern unit; when the target stepping mode is a longitudinal stepping mode, the stepping distance is N times the longitudinal size of the original pattern unit.

[0094] Specifically, when the target stepping mode is a lateral stepping mode, the objective table is controlled to step laterally by M times the lateral size of the original pattern unit, so that the substrate steps laterally by M times the lateral size of the original pattern unit; when the target stepping mode is a longitudinal stepping mode, the objective table is controlled to step longitudinally by N times the longitudinal size of the original pattern unit, so that the substrate steps longitudinally by N times the longitudinal size of the original pattern unit.

[0095] It should be noted that the lateral dimension of the original graphic unit and the longitudinal dimension of the original graphic unit can be the same or different. For example, the lateral dimension of the original graphic unit is 26 mm (including the scribe lane), and the longitudinal dimension of the original graphic unit is 33 mm (including the scribe lane). For another example, the lateral dimension of the original graphic unit and the longitudinal dimension of the original graphic unit are both 25 mm (including the scribe lane).

[0096] In this way, after the stepping is completed, the alignment is performed through the alignment mark on the substrate according to the method of step S101, and a preset offset distance is offset. The alignment and offset distance can refer to the foregoing description related to step S101, and will not be described here.

[0097] Step S104: performing second exposure, transferring a preset pattern on a mask to a second exposure area on the substrate through the projection system, the second exposure area covering at least MxN original graphic unit corresponding pattern areas.

[0098] This step is used to expose and form a second exposure area adjacent to the first exposure area on the substrate.

[0099] By performing the second exposure, the projection system can transfer a preset pattern on a mask to a second exposure area on the substrate. As shown in Figure 7 FIG. 6 is a schematic diagram of an example of a second exposure area in a large exposure field lithography technology implementation method provided by an embodiment of the present application. After the substrate 500 or the mask is stepped by 2 times the size of the original graphic unit corresponding image in the longitudinal direction, and alignment or alignment offset is performed through the second alignment mark, the second exposure is performed. Through the projection system with a magnification of 0.1 times to 2.5 times, a preset pattern on a mask is transferred to a second exposure area 710 adjacent to the first exposure area 700 in the longitudinal direction on the substrate. The second exposure area 710 also covers 2x2 original graphic unit corresponding pattern areas. Generally, 710 and 700 will appropriately overlap in the functional pattern area to prevent the occurrence of uncontrolled (irrelevant) patterns.

[0100] Through this step, after the first exposure area is formed on the substrate by exposure, the substrate is first stepped, and when stepping in the lateral direction, the stepping distance is the size of the pattern area covered by the first exposure area in the lateral direction, and when stepping in the longitudinal direction, the stepping distance is the size of the pattern area covered by the first exposure area in the longitudinal direction, which can avoid the functional pattern area of the second exposure area formed by the second exposure and the first exposure area from overlapping. Then, the alignment mark is aligned and offset by a preset offset distance to ensure the accurate alignment between the mask and the corresponding exposure position of the second exposure area to be formed on the substrate, thereby ensuring the effectiveness of the second exposure.

[0101] Step S105: continuously performing the lateral stepping or longitudinal stepping and the second exposure until the exposure of all target regions on the substrate is completed.

[0102] This step is used to continuously step to complete the exposure of all target regions on the substrate.

[0103] The target region can be the entire region on the substrate or a partial region set on the substrate, and the present application does not limit this.

[0104] After the completion of the second exposure in step S104, the substrate is stepped by M times the lateral size of the original pattern unit in the lateral direction or by N times the longitudinal size of the original pattern unit in the longitudinal direction; then, alignment or alignment offset is performed using the alignment marks on the substrate; and second exposure is performed again, so that the preset pattern on the mask can be transferred to a third exposure region on the substrate by the projection system, the third exposure region covering at least MxN original pattern unit corresponding pattern regions, and the third exposure region and the second exposure region being adjacent. In this way, the steps of stepping, alignment or alignment offset, and re-exposure are performed after each exposure, so that continuous exposure of multiple exposure regions on the substrate, each covering at least MxN original pattern unit corresponding pattern regions, can be achieved, and the stepped distance can effectively avoid overlapping of functional patterns between exposure regions.

[0105] In this way, after each exposure, the steps of stepping, alignment or alignment offset, and re-exposure are performed, so that continuous exposure of multiple exposure regions on the substrate, each covering at least MxN original pattern unit corresponding pattern regions, can be achieved, and the stepped distance can effectively avoid overlapping of functional patterns between exposure regions.

[0106] In an optional embodiment, the object table is one or two, and when the object table is two, each of the object tables is loaded with a substrate to be exposed.

[0107] When the object table is two, the multiple object tables can also be controlled to move to the projection system in turn to complete exposure.

[0108] In this way, during exposure of one object table, the other object table can perform other preparation work, such as loading of the substrate, preliminary alignment of the substrate, and the like. In an example, the multiple object tables include a first object table and a second object table, and during exposure of the first object table, the second object table can be controlled to perform steps of loading and unloading of a silicon wafer and preliminary alignment, where the preliminary alignment refers to preliminary alignment by alignment marks on a substrate to be exposed loaded on the second object table.

[0109] For example, the lithography machine includes a stage a and a stage b, during the alignment and exposure performed by the stage a, the stage b is controlled to perform the steps of wafer loading and unloading and pre-alignment, and correspondingly, during the alignment and exposure performed by the stage b, the stage a is controlled to perform the steps of wafer loading and unloading and pre-alignment. In this way, after the exposure of the first stage is completed, the exposure of the second stage can be started immediately, effectively reducing the time when the lithography machine is in an idle state; on the other hand, the time consumed by the switching between the stages is shorter than the time consumed by the substrate replacement and the preliminary alignment performed by a single stage, and almost seamless work flow can be achieved, thereby improving the lithography efficiency.

[0110] In an alternative embodiment, the stages are three to thirty. Each of the stages has the substrate, and the three to thirty stages are moved to the projection system in turn to complete the exposure. In this way, on the one hand, the time when the lithography machine is in an idle state can be effectively reduced, and the lithography efficiency is improved; on the other hand, since the exposure field of the lithography machine used in the present application is already very large, when a circular substrate is used as a carrier plate, a great waste is caused. For the hard and brittle substrates such as ceramic and glass, the traditional cutting process can cause edge damage or cracks. In the present application, the single substrate is independently exposed, the problem that the ceramic and glass substrates are difficult to be cut without damage is avoided, and the production flexibility is improved.

[0111] The method for implementing the lithography technology with a large exposure field provided in the first embodiment of the present application is as follows: after the alignment is performed through the alignment mark on the substrate and the substrate is offset by a preset offset distance, the substrate will be aligned with the preset pattern on the mask; then, the preset pattern on the mask is transferred to a first exposure area on the substrate through the projection system. Since the projection system has a reduction ratio of 0.1 to 2.5, the first exposure area formed will cover at least MxN original pattern unit corresponding pattern areas, and at least one of M and N is an integer greater than or equal to 2. Then, one of the substrate or the mask is stepped by M times the lateral size of the original pattern unit in the lateral direction or stepped by N times the longitudinal size of the original pattern unit in the longitudinal direction, and the second exposure is performed. The preset pattern on the mask is transferred to a second exposure area on the substrate through the projection system. In this way, the second exposure area formed will cover at least MxN original pattern unit corresponding pattern areas. The steps of the lateral step of M times the lateral size of the original pattern unit or the longitudinal step of N times the longitudinal size of the original pattern unit and the second exposure are continuously performed until the exposure of all target areas on the substrate is completed.

[0112] It can be seen that the method for implementing the photolithography technology of a large exposure field provided in the embodiment of the present application forms a large-size exposure field through a projection system with a reduction ratio of 0.1 to 2.5 times, compensates for the alignment deviation caused by the inconsistent projection ratio of the projection system through the offset distance set by offsetting, overcomes the image overlapping problem when a plurality of patterns are covered once by stepping the original pattern unit by the original pattern unit stepping distance through the lateral stepping of the lateral size of the original pattern unit by M times and the longitudinal stepping of the longitudinal size of the original pattern unit by N times, and well implements the pattern alignment, covering and stepping of M x N original pattern units. The method further continuously steps, aligns, offsets and exposes to complete the exposure of the target region on the substrate, thereby realizing the high-density interconnection of integrated circuits and providing photolithography technology support for the high-density interconnection integration of multiple large chips.

[0113] The second embodiment of the present application provides a method for implementing the photolithography technology of a large exposure field, which is applied to a photolithography device including a projection system with a reduction ratio of 0.1 to 2.5 times.

[0114] Before introducing the method for implementing the photolithography technology of a large exposure field provided in the second embodiment of the present application, the application scenario of the method for implementing the photolithography technology of a large exposure field provided in the second embodiment of the present application is introduced. The second embodiment of the present application can integrate different types of chips (such as GPUs and high-speed memories) together and support optical communication access. Specifically, first, a computing chip (such as a GPU) and a storage chip (such as a DRAM) are cut and attached to a carrier board, which can include a part of interconnection lines designed in advance to realize preliminary electrical connection; then, the method for implementing the photolithography technology of a large exposure field provided in the second embodiment of the present application is used to further interconnect the chips attached to the carrier board.

[0115] The method for implementing the photolithography technology of a large exposure field provided in the second embodiment of the present application interconnects chips of different sizes (such as GPUs and DRAMs), allows different functional modules to be optimized and designed according to their specific needs, and realizes cooperative work through efficient interconnection technology. It has at least the following advantages: first, each chip can be optimized and designed for its specific function, for example, a GPU can focus on computationally intensive tasks, and a DRAM is designed for providing high-bandwidth memory access, which can ensure that each component achieves better performance in its responsible task; second, by interconnecting different types of chips, such as directly connecting a GPU to a cache or a memory DRAM, data transmission delay can be greatly reduced, communication lines can be increased, and data transmission efficiency can be improved; third, the data transmission distance is effectively shortened, and the energy loss caused by long-distance transmission is reduced.

[0116] The method for implementing the photolithography technology of a large exposure field provided in the second embodiment of the present application specifically includes the following steps: loading the substrate with the pattern to be exposed onto a stage of the lithography apparatus, aligning by alignment marks on the substrate and offsetting by a set offset distance; performing a first exposure, transferring a preset pattern on a mask to a first exposure area on the substrate by the projection system, the first exposure area covering at least MxN original pattern unit corresponding pattern areas; loading the substrate with the pattern to be exposed onto a stage of the lithography apparatus, aligning by alignment marks on the substrate and offsetting by a set offset distance; performing a first exposure, transferring a preset pattern on a mask to a first exposure area on the substrate by the projection system, the first exposure area covering at least MxN original pattern unit corresponding pattern areas; continuously performing the lateral stepping or longitudinal stepping and the second exposure until the exposure of all target areas on the substrate is completed; wherein at least part of the MxN original pattern units have different sizes; and at least one of M and N is an integer greater than or equal to 2.

[0117] The steps of "loading the substrate with the pattern to be exposed onto a stage of the lithography apparatus, aligning by alignment marks on the substrate and offsetting by a set offset distance" and "performing a first exposure, transferring a preset pattern on a mask to a first exposure area on the substrate by the projection system, the first exposure area covering at least MxN original pattern unit corresponding pattern areas" are the same as steps S101 and S102 in the first embodiment of the present application, and the related descriptions of the corresponding steps in the first embodiment of the present application can be referred to, which will not be repeated here.

[0118] The difference between the first embodiment of the present application and the second embodiment of the present application is that: in the lithography technology implementation method of the large exposure field provided by the first embodiment of the present application, the sizes of the original pattern units on the substrate are all the same. In the second embodiment of the present application, the original first pattern unit in the original pattern unit may be, for example, a GPU, the original second pattern unit may be, for example, a DRAM, and the original third pattern unit may be, for example, a communication module. The sizes of the original first pattern unit, the original second pattern unit and the original third pattern unit are the same or different. That is, the sizes of the original pattern units in the second embodiment of the present application are not all the same, and there are original pattern units with different sizes.

[0119] Specifically, the vertical dimensions of the original first graphic unit, the original second graphic unit, and the original third graphic unit are the same or different. That is, the vertical dimensions of the original first graphic unit and the original second graphic unit are the same or different, the vertical dimensions of the original first graphic unit and the original third graphic unit are the same or different, and the vertical dimensions of the original second graphic unit and the original third graphic unit are the same or different.

[0120] Accordingly, the original first graphic unit, the original second graphic unit, and the original third graphic unit have the same or different horizontal dimensions. That is, the original first graphic unit and the original second graphic unit have the same or different horizontal dimensions, the original first graphic unit and the original third graphic unit have the same or different horizontal dimensions, and the original second graphic unit and the original third graphic unit have the same or different horizontal dimensions.

[0121] When the longitudinal dimensions corresponding to the original first graphic unit, the original second graphic unit, and the original third graphic unit are different, after the exposure of the first exposure area covering at least the graphic areas corresponding to M×N original graphic units is completed through the mask, the preset pattern on the mask can be transferred to the exposure area longitudinally adjacent to the first exposure area by stepping the substrate longitudinally by the sum of the longitudinal dimensions of N original graphic units, and performing alignment, biasing, and exposure.

[0122] like Figure 8 , is a schematic diagram of an example of an M×N chipset including multiple original graphic units of different sizes in a method for implementing a large exposure field lithography technology provided by an embodiment of the present application. The 2×2 chipset includes original graphic unit 610, original graphic unit 620, original graphic unit 630, and original graphic unit 640. After selecting a first mask to complete exposure of the exposure area covering the original graphic units 610, 620, 630, and 640, the substrate can be moved longitudinally by the sum of the longitudinal dimensions of the original graphic unit 610 and the original graphic unit 630, thereby performing exposure of the exposure area corresponding to the original graphic units 610, 620, 630, and 640 in the exposure area longitudinally adjacent to the exposure area 700.

[0123] Accordingly, after the exposure of the first exposure area covering at least M×N graphic areas corresponding to the original graphic units is completed through the mask, the preset pattern on the mask can be transferred to the exposure area laterally adjacent to the first exposure area by stepping the substrate laterally by the sum of the lateral dimensions of the M original graphic units and performing alignment, biasing and exposure.

[0124] Combined with attachment Figure 8For illustration, the 2×2 chipset includes original graphic unit 610, original graphic unit 620, original graphic unit 630, and original graphic unit 640. After selecting a first mask to complete exposure of the exposure area covering original graphic units 610, 620, 630, and 640, the substrate can be laterally shifted by the sum of the lateral dimensions of original graphic unit 610 and original graphic unit 620, thereby performing exposure of the exposure area corresponding to original graphic units 610, 620, 630, and 640 in an exposure area laterally adjacent to exposure area 700.

[0125] Optionally, the original graphic unit includes a composite original graphic unit, and the composite original graphic unit includes at least two graphic units of the original first graphic unit, the original second graphic unit, and the original third graphic unit.

[0126] like Figure 9 , which is a schematic diagram of an example of composite original graphic units in the large exposure field lithography technology implementation method provided in an embodiment of the present application, wherein the original graphic unit 630 and the original graphic unit 640 are both composite original graphic units, wherein the original graphic unit 630 includes the original graphic unit 6301 and the original graphic unit 6302, and the original graphic unit 640 includes the original graphic unit 6401 and the original graphic unit 6402.

[0127] It should be noted that the embodiment of different graphics unit sizes mainly occurs when different chips are installed on the carrier board, and even the chips come from different manufacturers. For example, when multiple rows and columns (M and N are both greater than or equal to 2) with different graphics unit sizes appear at the same time, the sum of the horizontal dimensions of the M original graphics units, or the sum of the vertical dimensions of the N original graphics units, is not necessarily equal and cannot be mechanically added. For example, if mechanically added, Figure 8 For example, the cumulative vertical dimensions of the left side (e.g., 610, 630) and the right side (e.g., 620, 640) may not be equal, nor may the cumulative horizontal dimensions of the top side (e.g., 610, 620) and the bottom side (e.g., 630, 640) be equal. To overcome this, when placing the graphics on the carrier board, it is necessary to plan the vertical and horizontal dimensions of the original graphics (e.g., using the large original graphic unit size as a reference for planning). Any gaps should be filled and polished to prevent exposure depth of field issues.

[0128] The third embodiment of the present application further provides a chip-level chip interconnection method, comprising the following steps: A substrate is provided, on which a semiconductor structure including at least two semiconductor chips is formed. Inter-chip interconnection is formed in each semiconductor chip, and there is no interconnection between the semiconductor chips.

[0129] The method for implementing the large-exposure-field photolithography technology provided in the first embodiment of the present application or the method for implementing the large-exposure-field photolithography technology provided in the second embodiment of the present application can realize the photolithography step of interconnection between the at least two semiconductor chips.

[0130] In the present embodiment, 2, 3, 4, 6, 8 or 9 semiconductor chips have been fabricated on the substrate through photolithography, etching, deposition and other processes. Moreover, the internal metal layer (such as copper interconnection line) inside each semiconductor chip has formed intra-chip interconnection, but there is no interconnection between semiconductor chips.

[0131] The at least two semiconductor chips can be arranged laterally, longitudinally or in a matrix. For example, the semiconductor structure formed on the substrate includes 2×1 semiconductor chips; for another example, the semiconductor structure formed on the substrate includes 1×2 semiconductor chips; for still another example, the semiconductor structure formed on the substrate includes 2×3 semiconductor chips.

[0132] Each semiconductor chip can be a single-exposure pattern area formed by a projection system with a reduction ratio of 4-10 times or other reduction ratios. For example, each semiconductor chip is a single-exposure pattern area formed by a projection system with a reduction ratio of 4 times; for another example, each semiconductor chip is a single-exposure pattern area formed by a projection system with a reduction ratio of 5 times; for still another example, each semiconductor chip is a single-exposure pattern area formed by a projection system with a reduction ratio of 8 times; for still another example, each semiconductor chip is a single-exposure pattern area formed by a projection system with a reduction ratio of 10 times.

[0133] Taking the reduction ratio of the projection system as 5 times for example, the size of each semiconductor chip formed is generally at most 26 mm×33 mm.

[0134] It should be understood that the size of each semiconductor chip formed can also be less than 26 mm×33 mm, such as 25 mm×30 mm, etc., and the present application does not limit the specific size of the semiconductor chip.

[0135] A single semiconductor chip can be understood as a pattern area corresponding to the original pattern unit in the method for implementing the large-exposure-field photolithography technology provided in the first embodiment of the present application.

[0136] In the case where the substrate as described above is provided, the photolithography step of interconnection between the at least two semiconductor chips can be realized through the method for implementing the large-exposure-field photolithography technology provided in the first embodiment of the present application.

[0137] It should be noted that, as to the method for implementing the lithography technology of the large exposure field provided by the first embodiment of the present application, the lithography step for implementing the interconnection between the at least two semiconductor chips can refer to the foregoing description of the method for implementing the lithography technology of the large exposure field provided by the first embodiment of the present application or the method for implementing the lithography technology of the large exposure field provided by the second embodiment of the present application, which will not be repeated here.

[0138] It can be seen that, by the chip-level chip interconnection method provided by the embodiments of the present application, high-density interconnection of integrated circuits can be implemented, and the lithography technology support is provided for high-density interconnection integration of multiple large chips.

[0139] The fourth embodiment of the present application further provides a lithography apparatus including a projection system with a reduction ratio of 0.1 to 2.5. The lithography apparatus has been described in detail in the foregoing, which will not be repeated here.

[0140] It can be seen that, by the lithography apparatus provided by the embodiments of the present application, the projection system with a reduction ratio of 0.1 to 2.5 is used to form a large-size exposure field on the substrate by one-time exposure, thereby implementing high-density interconnection of integrated circuits and providing lithography technology support for high-density interconnection integration of multiple large chips.

[0141] It should be noted that, in addition to being used in the top layer or sub-top layer lithography process to implement high-density interconnection of multiple large chips, the lithography apparatus provided by the embodiments of the present application can also be applied to the first layer lithography STI (also referred to as shallow trench isolation). The STI is a step performed in the initial stage of integrated circuit manufacturing, mainly used to create a shallow trench on the surface of a silicon wafer and fill the trench with insulating material to isolate different active regions (such as the source and drain of a transistor). By the lithography apparatus provided by the embodiments of the present application, more areas can be covered at one time in the STI stage, thereby improving production efficiency.

[0142] Although the present application is disclosed with the preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims of the present application.

Claims

1. A method for implementing a large exposure field lithography technology, characterized in that: Applied to a lithographic apparatus, the lithographic apparatus comprising a projection system with a reduction ratio of 0.1 to 2.5 times, the method comprising: Loading a patterned substrate to be exposed onto the stage of the photolithography equipment, aligning the substrate using alignment marks on the substrate, and offsetting the substrate by a set offset distance; Performing a first exposure, transferring the preset pattern on the mask to a first exposure area on the substrate through the projection system, wherein the first exposure area covers at least M×N pattern areas corresponding to the original pattern units; Stepping the substrate in a lateral direction by M times the lateral size of the original graphic unit, or in a longitudinal direction by N times the longitudinal size of the original graphic unit, aligning the substrate using alignment marks on the substrate, and offsetting the substrate by a set offset distance; Performing a second exposure, transferring the preset pattern on the mask to a second exposure area on the substrate through the projection system, wherein the second exposure area covers at least M×N pattern areas corresponding to the original pattern units; Continuously performing the lateral stepping or longitudinal stepping and the second exposure until exposure of all target areas of the substrate is completed; Wherein, at least one of M and N is an integer greater than or equal to 2.

2. The method according to claim 1, characterized in that Also includes: When the alignment mark on the substrate is an alignment mark set for the projection system with a reduction ratio of 0.1 to 2.5 times, the set offset distance is 0.

3. The method according to claim 1, characterized in that The reduction ratio of the projection system includes any one of 0.1, 0.125, 0.2, 0.25, 0.4, 0.5, 1.0, 1.25, 2 and 2.5 times.

4. The method according to claim 1, wherein The size of the first exposure area is M×N times of 26 mm×33 mm.

5. The method according to claim 1, wherein There are one or two loading platforms, and each loading platform is respectively loaded with a substrate to be exposed.

6. The method according to claim 5, characterized in that When there are two loading platforms, the method further includes: The two loading stages are controlled to move in turn under the projection system to complete exposure.

7. The method according to claim 6, characterized in that The two loading platforms include a first loading platform and a second loading platform, and the method further includes: While the first stage is performing alignment and exposure, the second stage is controlled to perform the steps of loading and unloading silicon wafers and pre-alignment.

8. A method for implementing a large exposure field lithography technique, characterized in that: Applied to a lithographic apparatus, the lithographic apparatus comprising a projection system with a reduction ratio of 0.1 to 2.5 times, the method comprising: Loading a patterned substrate to be exposed onto the stage of the photolithography equipment, aligning the substrate using alignment marks on the substrate, and offsetting the substrate by a set offset distance; Performing a first exposure, transferring the preset pattern on the mask to a first exposure area on the substrate through the projection system, wherein the first exposure area covers at least M×N pattern areas corresponding to the original pattern units; Stepping the substrate in a lateral direction by the sum of the lateral dimensions of M original graphic units, or in a longitudinal direction by the sum of the longitudinal dimensions of N original graphic units, aligning the substrate using alignment marks on the substrate, and offsetting the substrate by a set offset distance; Performing a second exposure, transferring the preset pattern on the mask to a second exposure area on the substrate through the projection system, wherein the second exposure area covers at least M×N pattern areas corresponding to the original pattern units; Continuously performing the lateral stepping or longitudinal stepping and the second exposure until exposure of all target areas of the substrate is completed; Among them, at least some of the M×N original graphic units have different sizes; and at least one of M and N is an integer greater than or equal to 2.

9. A chip-level chip interconnection method, characterized in that: include; Providing a substrate, forming a semiconductor structure including at least two semiconductor chips on the substrate, wherein each semiconductor chip has formed intra-chip interconnection, and there is no interconnection between the semiconductor chips; The photolithography step of interconnecting the at least two semiconductor chips is achieved by the large exposure field photolithography method according to any one of claims 1 to 8.

10. A photolithography apparatus, characterized in that: Includes projection systems with reduction ratios from 0.1 to 2.5 times.

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