IEEE754 standard single-precision floating-point number comparator based on PLD
By designing a PLD-based IEEE754 standard single-precision floating-point comparator and employing sign bit, exponent bit, and fractional bit judgment modules, the problems of uncertain resource consumption and poor reliability in existing technologies are solved. This results in a resource-saving, portable, and highly reliable floating-point comparator suitable for various chip platforms.
Patent Information
- Application Number
- CN202510825942.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-19
- Publication Date
- 2025-10-17
AI Technical Summary
The existing PLD-based IEEE754 standard single-precision floating-point comparator design method is unclear, resource usage is uncertain, and it has poor portability, modifiability, and verifiability, making it difficult to meet the reliability and safety requirements of the civil aviation and IC fields.
A PLD-based IEEE 754 standard single-precision floating-point comparator was designed, including sign bit judgment, exponent bit judgment, and fraction bit judgment modules. It compares unsigned binary numbers with XOR operations and outputs results such as greater than, less than, and equal to. The design was completed using Verilog HDL and supports multi-channel parallel comparison and loop execution.
It achieves low resource consumption, high portability, high real-time performance, and high reliability. The LUT resource consumption is reduced by 36.1%~34.8%, the result output has no clock delay, the code coverage is 100%, and it is suitable for a variety of PLD and ASIC chips.
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Figure CN120803393A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the field of digital operation and computer architecture, and particularly relates to an IEEE754 standard single-precision floating-point number comparator based on a PLD. BACKGROUND
[0002] IEEE754 is the most widely used floating-point operation standard since the 1980s, and is adopted by many CPUs and floating-point operation units. IEEE754 specifies four ways of representing floating-point values: single-precision (32 bits), double-precision (64 bits), extended single-precision (more than 43 bits) and extended double-precision (more than 79 bits). Single-precision (32 bits) has small memory occupation, fast calculation speed, saved storage and transmission bandwidth, and has met the precision requirements of most scenes relative to other precision floating-point value representation methods specified by IEEE754.
[0003] At present, the IEEE754 standard single-precision floating-point number comparator based on a PLD is provided by the development tool of the PLD, and the design data of the IEEE754 standard single-precision floating-point number comparator is encrypted. At present, some PLDs on the market, such as most CPLDs, do not provide the IEEE754 standard single-precision floating-point number comparator, which undoubtedly forces users to change the scheme or replace other PLD chips with higher cost.
[0004] With the increasing difficulty of the PLD project to be implemented, the engineering quantity is also increased. Users have higher requirements for the reliability, portability, modifiability and even cost of the PLD project. The existing IEEE754 standard single-precision floating-point number comparator based on a PLD has unclear design method, uncertain resource occupation, poor portability, poor modifiability, poor verifiability and uncertain reliability. In the field of civil aviation and IC in China, it is required to fully verify to ensure the reliability and safety. SUMMARY
[0005] In view of the above problems in the prior art, the IEEE754 standard single-precision floating-point number comparator based on a PLD provided by the application solves the problems of unclear design method, uncertain resource occupation, poor portability, poor modifiability, poor verifiability and uncertain reliability of the existing comparator.
[0006] In order to achieve the above application purposes, the technical scheme adopted by the application is as follows: an IEEE754 standard single-precision floating-point number comparator based on a PLD, comprising: a sign bit judgment module: according to the IEEE754 standard single-precision floating-point number to be compared input by a user, the sign bit is compared, if the sign bit comparison result is obtained, the sign bit comparison result is input to a comparison result generation module, otherwise, an exponent bit judgment module is entered; The exponent bit judging module judges the exponent bits of the two IEEE754 standard single-precision floating-point numbers to be compared according to the user input, and inputs the exponent bit comparison result to the comparison result generating module if the exponent bit comparison result is obtained, or enters the decimal bit judging module. The decimal bit judging module judges the decimal bits of the two IEEE754 standard single-precision floating-point numbers to be compared according to the user input, obtains the decimal bit comparison result, and inputs the decimal bit comparison result to the comparison result generating module. The comparison result generating module outputs the comparison result of the two IEEE754 standard single-precision floating-point numbers to be compared to the user.
[0007] Further, the sign bit judging module compares the sign bits of the two IEEE754 standard single-precision floating-point numbers to be compared through XOR operation. If the XOR result is 1, the sign bit comparison result is obtained: the number with the sign bit of 0 is greater than the number with the sign bit of 1. If the XOR result is 0, the exponent bit judging module is entered.
[0008] Further, the exponent bit judging module compares the exponent bits of the two IEEE754 standard single-precision floating-point numbers to be compared as unsigned binary numbers, which specifically includes the following cases: When the sign bits are both 0, the exponent bit comparison result is obtained: the number with the greater exponent bit is greater. When the sign bits are both 1, the exponent bit comparison result is obtained: the number with the greater exponent bit is smaller. When the exponent bits are equal, the decimal bit judging module is entered.
[0009] Further, the decimal bit judging module compares the decimal bits of the two IEEE754 standard single-precision floating-point numbers to be compared as unsigned binary numbers, which specifically includes the following cases: When the sign bits are both 0, the decimal bit comparison result is obtained: the number with the greater decimal bit is greater. When the sign bits are both 1, the decimal bit comparison result is obtained: the number with the greater decimal bit is smaller. When the decimal bits are equal, the decimal bit comparison result is obtained: the two numbers are equal.
[0010] Further, the comparison result generating module outputs the comparison result including greater than, less than, equal to, greater than or equal to, less than or equal to, and not equal to.
[0011] Further, if the exponent bit judging module and the decimal bit judging module are combined into one judging module, the exponent bit and the decimal bit are combined together for comparison, which does not affect the comparison result.
[0012] Further, the index bit judging module and the decimal bit judging module can be combined into one judging module, and the judging module can be divided into multiple sub judging modules for comparison, and the comparison result is not affected.
[0013] Further, the comparison result generating module can be omitted, and the comparison result is output by the previous module, and the comparison result is not affected.
[0014] Further, the comparator can be duplicated into multiple paths, and the comparison of two IEEE754 standard single-precision floating-point numbers in multiple paths can be completed, and the comparison results of each path are output respectively, and the comparison result of each path is not affected.
[0015] Further, the comparator returns to the sign bit judging module after completing the comparison, and the comparison process is executed in a loop, and the comparison result of each loop is not affected.
[0016] The beneficial effects of the present application are: (1) Small resource occupation. The present application only uses LUT resources in the PLD, and the logic resources are deeply optimized. Experiments show that, compared with the IEEE754 standard single-precision floating-point number comparator (also only using LUT resources in the PLD) provided by the development tool (taking Vivado as an example) of the PLD, the LUT resource occupation of the single comparator after synthesis is reduced by 36.1%, and the LUT resource occupation after layout and routing is reduced by 34.8%.
[0017] (2) Strong portability. The present application is designed only using Verilog HDL. Verilog HDL is a hardware description language that can be recognized by the development tools of various PLDs and ASICs, so the present application can be used, ported and copied in all PLDs and ASICs. In addition, the internal modules of the present application can be used independently or partially, and the modules that are not needed can be removed.
[0018] (3) Strong real-time performance. The present application is designed only using combinational logic, so the result output is only the gate delay of the internal circuit of the PLD, without clock delay. Experiments show that, when the present application is used on the CPLD chip of Altera MAX II series, the time from the user input to the result output is within 15ns.
[0019] (4) Strong reliability. The present application is designed only using Verilog HDL. Experiments show that, in functional simulation, the comparison results output by the present application are all correct when random IEEE754 standard single-precision floating-point numbers are input, and the code coverage (statements, branches, conditions, expressions) can reach 100%, without redundant code. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 This is the flow chart of the IEEE754 standard single-precision floating-point comparator based on PLD. DETAILED DESCRIPTION
[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0022] like Figure 1 As shown, an IEEE754 standard single-precision floating-point comparator based on a PLD is characterized by comprising: Sign bit judgment module: Compare the sign bit according to the IEEE754 standard single-precision floating-point number to be compared input by the user. If the sign bit comparison result is obtained, the sign bit comparison result is input into the comparison result generation module; otherwise, it enters the exponent bit judgment module; Exponent bit judgment module: compares the exponent bit according to the IEEE754 standard single-precision floating-point number to be compared input by the user. If the exponent bit comparison result is obtained, the exponent bit comparison result is input into the comparison result generation module; otherwise, it enters the decimal place judgment module; Decimal place judgment module: compares the decimal places according to the IEEE754 standard single-precision floating-point number to be compared input by the user, obtains the decimal place comparison result, and inputs the decimal place comparison result into the comparison result generation module; Comparison result generation module: outputs the comparison result of the IEEE754 standard single-precision floating-point number to be compared to the user.
[0023] In one embodiment of the present invention, taking the case where a user inputs two IEEE 754 standard single-precision floating-point numbers to be compared and wants to obtain a comparison result as an example, the specific implementation is as follows: The sign bit judgment module compares the sign bits of two IEEE754 standard single-precision floating-point numbers to be compared through an exclusive OR operation. If the exclusive OR result is 1, the sign bit comparison result is obtained: the number with a sign bit of 0 is greater than the number with a sign bit of 1; if the exclusive OR result is 0, the exponent bit judgment module is entered.
[0024] In this embodiment, after the user inputs two IEEE754 standard single-precision floating-point numbers to be compared (hereinafter referred to as floating-point number A and floating-point number B), the sign bit judgment module takes the sign bit (32nd bit) of floating-point number A and floating-point number B respectively and performs an exclusive OR. If the exclusive OR result is 1, it means that one of floating-point numbers A and B is negative and the other is non-negative, and the comparison result is obtained: the floating-point number with a sign bit of 0 (the non-negative floating-point number) is greater than the floating-point number with a sign bit of 1 (entering the comparison result generation module). If the exclusive OR result is 0, it means that floating-point numbers A and B are both negative or non-negative, and no comparison result is obtained. At the same time, it needs to be passed to the exponent bit judgment module for judgment.
[0025] The index bit judging module compares the index bits of two IEEE754 standard single-precision floating-point numbers to be compared as unsigned binary numbers, and specifically includes the following cases: When the sign bits are both 0, the index bit comparison result is obtained: the number with larger index bit is larger; When the sign bits are both 1, the index bit comparison result is obtained: the number with larger index bit is smaller; When the index bits are equal, the decimal bit judging module is entered.
[0026] In the embodiment, the index bit judging module takes the index bits (31st~23rd) of the A floating-point number and the B floating-point number as unsigned binary numbers, and directly compares them to be greater than, equal to or less than. When the sign bits of the A and B floating-point numbers are both 0, and the index bit of the A floating-point number is greater than that of the B floating-point number, the comparison result is obtained: the floating-point number A is greater than the floating-point number B (entering the comparison result generating module). When the sign bits of the A and B floating-point numbers are both 0, and the index bit of the A floating-point number is less than that of the B floating-point number, the comparison result is obtained: the floating-point number A is less than the floating-point number B (entering the comparison result generating module). When the sign bits of the A and B floating-point numbers are both 1, and the index bit of the A floating-point number is greater than that of the B floating-point number, the comparison result is obtained: the floating-point number A is less than the floating-point number B (entering the comparison result generating module). When the sign bits of the A and B floating-point numbers are both 1, and the index bit of the A floating-point number is less than that of the B floating-point number, the comparison result is obtained: the floating-point number A is greater than the floating-point number B (entering the comparison result generating module). When the index bit of the A floating-point number is equal to that of the B floating-point number, the comparison result is not obtained, and needs to be further transmitted to the decimal bit judging module for judgment.
[0027] The decimal bit judging module compares the decimal bits of two IEEE754 standard single-precision floating-point numbers to be compared as unsigned binary numbers, and specifically includes the following cases: When the sign bits are both 0, the decimal bit comparison result is obtained: the number with larger decimal bit is larger; When the sign bits are both 1, the decimal bit comparison result is obtained: the number with larger decimal bit is smaller; When the decimal bits are equal, the decimal bit comparison result is obtained: the two numbers are equal.
[0028] In this embodiment, the decimal point judging module takes the decimal point (22th~1st) of the A floating point number and the B floating point number as unsigned binary numbers, and directly compares them to determine if they are greater than, equal to, or less than each other. When the A and B floating point numbers have the same sign bit of 0, and the decimal point of the A floating point number is greater than that of the B floating point number, the comparison result is that the floating point number A is greater than the floating point number B (entering the comparison result generating module). When the A and B floating point numbers have the same sign bit of 0, and the decimal point of the A floating point number is less than that of the B floating point number, the comparison result is that the floating point number A is less than the floating point number B (entering the comparison result generating module). When the A and B floating point numbers have the same sign bit of 1, and the decimal point of the A floating point number is greater than that of the B floating point number, the comparison result is that the floating point number A is less than the floating point number B (entering the comparison result generating module). When the A and B floating point numbers have the same sign bit of 1, and the decimal point of the A floating point number is less than that of the B floating point number, the comparison result is that the floating point number A is greater than the floating point number B (entering the comparison result generating module). When the decimal point of the A floating point number is equal to that of the B floating point number, the comparison result is that the floating point number A is equal to the floating point number B (entering the comparison result generating module).
[0029] The comparison result output by the comparison result generating module includes greater than, less than, equal to, greater than or equal to, less than or equal to, and not equal to.
[0030] If the exponent bit judging module and the decimal point judging module are combined into one judging module, the exponent bit and the decimal point are combined together for comparison, without affecting the comparison result.
[0031] If the exponent bit judging module and the decimal point judging module are combined into one judging module, the judging module is divided into multiple sub-judging modules for comparison, without affecting the comparison result.
[0032] The comparison result generating module can be omitted, and the comparison result is output by the previous module, without affecting the comparison result.
[0033] The comparator can be duplicated into multiple paths, and simultaneously complete the comparison of two IEEE754 standard single-precision floating point numbers in each path, and output the comparison result of each path, without affecting the comparison result of each path.
[0034] The comparator returns to the sign bit judging module after completing one comparison, and executes the comparison flow in a loop, without affecting the comparison result of each loop.
[0035] Those skilled in the art will appreciate that the embodiments described herein are presented for purposes of illustration and that the inventive principles are not limited to these particular embodiments. Other variations and modifications can be made to the embodiments without departing from the spirit and scope of the inventive principles.
Claims
1. An IEEE754 standard single-precision floating-point comparator based on PLD, characterized in that: include: Sign bit judgment module: Compare the sign bit according to the IEEE754 standard single-precision floating-point number to be compared input by the user. If the sign bit comparison result is obtained, the sign bit comparison result is input into the comparison result generation module; otherwise, it enters the exponent bit judgment module; Exponent bit judgment module: compares the exponent bit according to the IEEE754 standard single-precision floating-point number to be compared input by the user. If the exponent bit comparison result is obtained, the exponent bit comparison result is input into the comparison result generation module; otherwise, it enters the decimal place judgment module; Decimal place judgment module: compares the decimal places according to the IEEE754 standard single-precision floating-point number to be compared input by the user, obtains the decimal place comparison result, and inputs the decimal place comparison result into the comparison result generation module; Comparison result generation module: outputs the comparison result of the IEEE754 standard single-precision floating-point number to be compared to the user.
2. The IEEE754 standard single-precision floating-point comparator based on PLD according to claim 1, wherein The sign bit judgment module compares the sign bits of two IEEE754 standard single-precision floating-point numbers to be compared through an exclusive OR operation. If the exclusive OR result is 1, the sign bit comparison result is obtained: the number with a sign bit of 0 is greater than the number with a sign bit of 1; if the exclusive OR result is 0, the exponent bit judgment module is entered.
3. The IEEE754 standard single-precision floating-point comparator based on PLD according to claim 1, wherein The exponent bit judgment module regards the exponent bits of two IEEE754 standard single-precision floating-point numbers to be compared as unsigned binary numbers for comparison, specifically including the following situations: When the sign bits are both 0, the exponent bit comparison result is obtained: the number with the larger exponent bit is larger; When the sign bits are both 1, the exponent bit comparison result is obtained: the number with the larger exponent bit is smaller; When the exponents are equal, the module enters the decimal place judgment module.
4. The IEEE754 standard single-precision floating-point comparator based on PLD according to claim 1, wherein The decimal place determination module regards the decimal places of two IEEE754 standard single-precision floating-point numbers to be compared as unsigned binary numbers for comparison, specifically including the following situations: When the sign bits are both 0, the decimal comparison result is obtained: the number with the larger decimal place is larger; When the sign bits are both 1, the decimal comparison result is obtained: the number with the larger decimal place is smaller; When the decimal places are equal, the decimal place comparison result is obtained: the two numbers are equal.
5. The IEEE754 standard single-precision floating-point comparator based on PLD according to claim 1, wherein The comparison results output by the comparison result generating module include greater than, less than, equal to, greater than or equal to, less than or equal to, and not equal to.
6. The IEEE754 standard single-precision floating-point comparator based on PLD according to claim 1, wherein: If the exponent bit judgment module and the decimal bit judgment module are combined into one judgment module, the exponent bit and the decimal bit are combined together for comparison, which does not affect the comparison result.
7. The IEEE754 standard single-precision floating-point comparator based on PLD according to claim 1, wherein: If the exponent digit judgment module and the decimal digit judgment module are combined into one judgment module, the judgment module can be divided into multiple sub-judgment modules for comparison in sequence without affecting the comparison result.
8. The IEEE754 standard single-precision floating-point comparator based on PLD according to claim 1, wherein: The comparison result generating module can be omitted, and the comparison result is output by the previous module, which does not affect the comparison result.
9. The IEEE754 standard single-precision floating-point comparator based on PLD according to claim 1, wherein: The comparator can be replicated into multiple channels, and can simultaneously complete the comparison of two IEEE754 standard single-precision floating-point numbers in multiple channels, and output the comparison results of each channel respectively without affecting the comparison results of each channel.
10. The IEEE754 standard single-precision floating-point comparator based on PLD according to claim 1, wherein: After completing one comparison, the comparator returns to the sign bit judgment module to execute the comparison process in a loop, without affecting the comparison result of each loop.