Polycrystalline silicon sheet resistance matrix and design method thereof

Abstract

The invention discloses a design method of a polycrystalline silicon sheet resistance matrix and the polycrystalline silicon sheet resistance matrix, the structure of the polycrystalline silicon sheet resistance matrix is designed, the polycrystalline silicon sheet resistance matrix is set to have different predetermined critical dimensions based on the position of the polycrystalline silicon sheet resistance in the matrix, and the different dimensions are used for compensating the position related RS change introduced by LSA; lSA processing is performed on the matrix, employing a dual-scan approach from at least two symmetric directions (e.g., 45 degrees and 225 degrees) to enhance annealing uniformity. The invention further discloses a polycrystalline silicon sheet resistance matrix with corresponding structural characteristics, and the resistor units of the polycrystalline silicon sheet resistance matrix have different preset key sizes based on positions. Compensating critical dimension design is combined with a symmetric double-scanning LSA process, and the influence of the LSA and the position effect on the RS is counteracted by utilizing the influence of the dimension effect on the RS, so that the RS mismatch of the polycrystalline silicon resistor in the matrix is remarkably reduced, the resistor matching precision is improved, and the performance of an analog circuit depending on resistor matching is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a polysilicon thin layer resistance matrix and a design method thereof. BACKGROUND

[0002] In the design and manufacture of analog integrated circuits, resistor devices are indispensable basic elements. They are widely used in various functional modules, such as digital-to-analog converters (DACs), operational amplifiers, filters, etc. In order to achieve high precision and good performance, these analog circuits usually require the resistor devices used to have high consistency and matching.

[0003] In current semiconductor processes, polysilicon resistors are widely used due to their good compatibility with standard CMOS (Complementary Metal-Oxide-Semiconductor) processes, moderate and adjustable resistivity, etc. In order to save chip area and realize specific resistance network topology, polysilicon resistors are usually designed in the form of an array or matrix, i.e., a polysilicon resistance matrix.

[0004] In order to activate the doping ions and repair the implantation damage, and form polysilicon resistors with stable electrical characteristics, annealing treatment is usually required. Laser spike anneal (LSA) is an advanced annealing technology that uses high peak power and short duration laser pulses to rapidly heat and cool the wafer surface. Compared with traditional rapid thermal annealing (RTA), LSA has the advantages of low thermal budget and high activation efficiency, and is particularly suitable for advanced process nodes.

[0005] However, the application of LSA technology to the activation of polysilicon resistance matrices also brings new challenges. Research and production practice shows that after LSA treatment, the thin layer resistance (RS) values of each resistance unit in the polysilicon resistance matrix will exhibit obvious mismatch. This RS mismatch will directly affect the precise value of the resistance, and thus seriously deteriorate the performance of analog circuits that rely on resistance matching accuracy, such as causing the linearity of DACs to decrease, the output accuracy to decrease, etc.

[0006] In a polysilicon resistance matrix, the final RS value of a single polysilicon resistance cell is closely related to its specific location within the matrix. Experimental data show that polysilicon resistances usually located in the outer circle (edge) region of the matrix tend to have a higher RS value (trend up) after LSA. This may be due to the differences in heat dissipation conditions, stress state, or effective energy density under laser irradiation between the edge region and the center region.

[0007] The scanning path and incident direction of the laser beam during the LSA process have a significant impact on the heating uniformity of the polysilicon resistance. For LSA processes using single-direction scanning, the degree of laser irradiation (e.g., effective irradiation time, peak temperature, temperature rise and fall rate, etc.) of polysilicon resistances at different locations may be different. In particular, polysilicon resistances closer to the LSA source (laser incident starting point or path) may also exhibit a trend of higher RS values. Different LSA incident angles (e.g., 0 degrees, 90 degrees, 225 degrees, etc.) can result in different spatial distribution characteristics of RS within the matrix.

[0008] Local high temperatures during the LSA process can cause additional diffusion of doping ions (such as boron, phosphorus, arsenic, etc.), especially into the silicon substrate. This can reduce the effective carrier concentration on the surface of the polysilicon layer, resulting in an increase in its sheet resistance. The extent of this effect may also be influenced by the location of the resistance within the matrix and the specific parameters of the LSA.

[0009] Therefore, in the context of the prior art, how to further reduce the RS mismatch within the polysilicon resistance matrix after LSA activation to meet the stringent requirements of high-performance analog circuits for resistance matching accuracy is a technical problem that needs to be solved. SUMMARY

[0010] Specifically, in the prior art, polysilicon (poly) resistance matrices widely used in analog integrated circuits face the problem of sheet resistance (RS) mismatch when activated by the laser spike annealing (LSA) process. This RS mismatch is mainly due to the influence of the location of a single polysilicon resistance cell within the matrix on its RS value (e.g., outer circle resistances usually have a higher RS), and the influence of the LSA laser incident direction and scanning method (e.g., single-direction scanning or positions close to the LSA source may result in a higher RS). This RS mismatch can severely affect the performance of analog circuits (such as digital-to-analog converters (DAC)) that rely on accurate resistance matching.

[0011] Therefore, one purpose of the present application is to provide a design method for a polysilicon sheet resistance matrix and a corresponding polysilicon sheet resistance matrix, aiming to reduce the RS mismatch after LSA processing and improve the resistance matching accuracy.

[0012] To achieve the above object, the present application provides a design method of a polysilicon thin layer resistance (RS) matrix, which comprises the following steps:

[0013] Step one, designing the structure of the polysilicon thin layer resistance matrix, wherein, based on the position of the polysilicon thin layer resistance in the polysilicon thin layer resistance matrix, the polysilicon thin layer resistance is set to have different predetermined critical dimensions (CD).

[0014] Step two, performing laser spike annealing (LSA) processing on the polysilicon thin layer resistance matrix, wherein the laser spike annealing processing adopts a dual scan mode from at least two symmetric directions.

[0015] Through this method, first of all, in the design stage, the influence of LSA process and resistance position on RS is considered in advance, and the resistance unit with different critical dimensions (CD) is designed accordingly. The purpose of this position-based differentiated CD design is to use the influence of resistance size on RS to compensate or offset the position-related RS variation trend introduced by LSA processing. Then, in the LSA activation step, the dual scan mode in symmetric directions can provide more uniform annealing effect than the one-way scan, which itself helps to reduce systematic RS deviation. The combination of these two measures, that is, the synergistic effect of compensatory CD design and uniform LSA scanning mode, makes the size change influence on RS and the LSA and position effect on RS can offset each other, thereby significantly reducing the RS mismatch between different resistance units in the final matrix.

[0016] Preferably, in step one, the different predetermined critical dimensions are configured to compensate for the thin layer resistance variation related to the position of the polysilicon thin layer resistance in the polysilicon thin layer resistance matrix introduced by the laser spike annealing processing.

[0017] Preferably, in step one, the critical dimension of the polysilicon thin layer resistance located in the outer ring area of the polysilicon thin layer resistance matrix is different from that of the polysilicon thin layer resistance located in the inner ring area.

[0018] Preferably, in step one, the critical dimension of the polysilicon thin layer resistance decreases from the outer ring area to the inner ring area of the polysilicon thin layer resistance matrix.

[0019] Preferably, in step two, the at least two symmetric directions are, for example, two directions that are 180 degrees apart.

[0020] Preferably, in step two, the at least two symmetric directions are 45 degrees and 225 degrees.

[0021] Preferably, the method aims to reduce the sheet resistance mismatch between different polysilicon sheet resistances in the polysilicon sheet resistance matrix after the laser spike annealing treatment.

[0022] To achieve the above-mentioned object, the application further provides a polysilicon sheet resistance matrix, which comprises a plurality of polysilicon sheet resistances.

[0023] The polysilicon sheet resistances have different predetermined critical dimensions based on their positions in the polysilicon sheet resistance matrix.

[0024] The different predetermined critical dimensions are configured to reduce the sheet resistance mismatch between the plurality of polysilicon sheet resistances after performing the double-scan laser spike annealing treatment from at least two symmetric directions on the polysilicon sheet resistance matrix.

[0025] The structural features of the polysilicon sheet resistance matrix embody the above-mentioned design idea, that is, through the built-in position-based CD difference, the polysilicon sheet resistance matrix can achieve excellent RS matching after cooperating with the specific symmetric double-scan LSA process.

[0026] Preferably, the critical dimensions of the polysilicon sheet resistances located in the outer ring region of the polysilicon sheet resistance matrix are different from those of the polysilicon sheet resistances located in the inner ring region.

[0027] Preferably, the critical dimensions of the polysilicon sheet resistances decrease from the outer ring region to the inner ring region of the polysilicon sheet resistance matrix.

[0028] The application effectively offsets the RS non-uniformity caused by factors such as position and incident direction in the LSA process by combining the optimized LSA scanning mode (symmetric double scanning) and the compensatory resistance structure design (different CD based on position), and significantly reduces the RS mismatch within the polysilicon resistance matrix.

[0029] As described above, the design method of the polysilicon sheet resistance matrix and the polysilicon sheet resistance matrix of the application have the following beneficial effects:

[0030] The application combines the compensatory critical dimension design with the symmetric double-scan LSA process, uses the size effect on RS to offset the LSA and position effect on RS, thereby significantly reducing the RS mismatch of the polysilicon resistances in the matrix and improving the resistance matching accuracy, which is beneficial to improving the performance of analog circuits that rely on resistance matching. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1A schematic diagram showing a design method of a polysilicon thin-film resistance matrix according to the present application;

[0032] Figure 2 A schematic diagram showing a dual scan method according to the present application in two symmetrical directions;

[0033] Figure 3 A schematic diagram showing another dual scan method according to the present application in two symmetrical directions;

[0034] Figure 4 A schematic diagram showing a standard deviation trend chart according to the present application under different LSA scan conditions (e.g. BSL condition and 45+225 split condition);

[0035] Figure 5 A schematic diagram showing a range trend chart according to the present application under different LSA scan conditions (e.g. BSL condition and 45+225 split condition). DETAILED DESCRIPTION

[0036] The advantages and effects of the present application can be easily understood by those skilled in the art from the above description. The present application can also be implemented or applied in other different embodiments, and the details in the present description can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0037] The present application provides a design method of a polysilicon thin-film resistance matrix. The method aims to solve the problem that the polysilicon resistance matrix used in an analog circuit after laser spike annealing (LSA) treatment has significant differences (mismatch) in thin-film resistance (RS) of different resistance units due to the position of the resistance units in the matrix and the influence of the LSA incident direction in the prior art. Such mismatch can seriously affect the performance of analog circuits (such as digital-to-analog converters DAC) that rely on resistance matching accuracy. The present application effectively reduces such RS mismatch by combining a specific LSA scan method and a compensatory resistance size design.

[0038] Referring to Figure 1 , the method comprises the following steps:

[0039] Step one, designing the structure of the polysilicon thin-film resistance matrix, wherein the polysilicon thin-film resistance has different predetermined critical dimensions (CD) based on the position of the polysilicon thin-film resistance in the polysilicon thin-film resistance matrix. The key to this step is to pre-identify the RS non-uniformity rule that may be caused by the LSA process, and to use the influence of the resistance critical dimension (such as width or length) on the final resistance value for compensatory design.

[0040] In some embodiments, in step one, different predetermined critical dimensions are configured to compensate for thin layer resistance variations introduced by the laser spike anneal process, which are related to the locations of the polysilicon thin layer resistances within the polysilicon thin layer resistance matrix. Specifically, due to the thermal effects (e.g. high temperature causing ion diffusion into the wafer, reducing the number of surface carriers) and edge effects during the LSA process, it is generally observed that the polysilicon resistances RS at the outer ring of the matrix or near the LSA source tend to be higher. By designing different CDs (e.g. a CD value that can lower RS) at the locations where RS is expected to be higher, and another CD (e.g. a CD value that can raise RS) at the locations where RS is expected to be lower, the actual RS values after LSA can be made more uniform.

[0041] In some embodiments, in step one, the critical dimensions of the polysilicon thin layer resistances at the outer ring region of the polysilicon thin layer resistance matrix are different from those at the inner ring region. This is based on the general observation from experiments that the polysilicon RS at the outer ring of the matrix is more susceptible to being higher. Therefore, it is an effective compensation strategy to purposefully use different design dimensions for the inner and outer ring resistances.

[0042] In some embodiments, in step one, the critical dimensions of the polysilicon thin layer resistances decrease in a decreasing trend from the outer ring region to the inner ring region of the polysilicon thin layer resistance matrix. For example, the polysilicon resistances at the outer ring can be designed to have a relatively larger CD, while the polysilicon resistances at the inner ring have a relatively smaller CD. This design of decreasing CD from the outer to the inner, aims to utilize the inverse effect of CD size variation on thin layer resistance (the specific effect relationship depends on the doping type, concentration, process details, etc., but the key is the dependency), to offset the trend of higher RS at the outer ring caused by LSA. By precisely adjusting the CD differences of the inner and outer rings, and possibly the transition region, the RS variation across the entire matrix can be minimized. The specific size of the CD value difference for this gradient design can be optimized through simulation or experimental testing, based on the specific process platform, LSA parameters, and the target RS matching accuracy requirement.

[0043] Step two, performing a laser spike anneal (LSA) process on the polysilicon thin film resistance matrix, wherein the LSA process is performed in a dual scan manner from at least two symmetric directions. Compared with a single direction scan, a dual scan, especially a symmetric direction dual scan, can make the laser heat effect on the resistance units at different positions in the matrix more balanced. For example, if only scanning from 0 degree direction, the heat history of the resistances near the starting point of the 0 degree scan and the resistances far from the starting point can be different; while using symmetric direction (such as 0 degree and 180 degree, or 45 degree and 225 degree) scanning, this effect can be better averaged.

[0044] In some embodiments, referring to Figure 2 and Figure 3 , in step two, the at least two symmetric directions are two directions that are 180 degrees apart from each other. This strict symmetry helps to maximize the cancellation of systematic bias that can be introduced by a single direction scan.

[0045] In some embodiments, in step two, the at least two symmetric directions are 45 degree direction and 225 degree direction. This pair of specific symmetric directions is selected based on experimental verification. For example, to evaluate and optimize the specific effect of the LSA dual scan strategy on the uniformity of the thin film resistance, the following experimental verification process can be performed: first, a special test structure (test key) containing a plurality of polysilicon resistance matrices is manufactured on a test wafer. Then, these wafers with test structures are divided into different experimental groups (process split), and different LSA scan parameters are used for processing in different groups. For example, one group uses the baseline (BSL) scan method (which can be a single direction scan or other angle combination), and the other group uses the preferred 45 degree + 225 degree symmetric dual scan method of the present application. After processing, the thin film resistance (RS) values of the polysilicon resistances in the test structure on each wafer are accurately measured. Next, the large amount of RS data measured for each group (corresponding to one LSA scan condition) is statistically analyzed, and the key uniformity indicators, mainly the standard deviation (STD) and the range (the difference between the maximum and minimum values in a group of data), are calculated. The standard deviation reflects the overall dispersion of the data around the mean value, while the range reflects the fluctuation range of the data, both of which are important indicators for measuring RS uniformity, and the smaller the value, the better the uniformity. Finally, the statistical results (STD value and Range value) obtained under different LSA scan conditions (such as BSL condition and 45+225 split condition) are compared, and these comparison results are plotted into trend charts or bar charts, as shown in Figure 4 and Figure 5 , Figure 4a standard deviation trend chart, Figure 5 a range trend chart. By analyzing such charts, one can visually compare the effects of different LSA scanning strategies on the uniformity of RS. As explicitly shown in the example charts of Figure 4 and Figure 5 As explicitly shown in the example charts of FIG. 6 and FIG. 7, for the test structure treated with 45-degree + 225-degree symmetric split scanning, both the standard deviation and the range of RS are significantly lower than the results under the baseline (BSL) condition. This comparison result strongly demonstrates that the 45-degree + 225-degree symmetric split scanning approach can achieve the best (or at least significantly improved) intra-matrix RS uniformity. Therefore, the adoption of 45-degree and 225-degree as the symmetric split scanning directions in the preferred embodiments is supported by such experimental data, which can effectively improve the resistance consistency of the LSA annealed polysilicon thin-film resistors.

[0046] In some embodiments, the method aims to reduce the thin-film resistance mismatch between different polysilicon thin-film resistors in the polysilicon thin-film resistor matrix after the laser spike annealing treatment. The final technical effect is that, by combining the compensatory CD design of step one with the symmetric split scanning LSA process of step two, the size effect on RS and the position and direction effects introduced by LSA on RS can be mutually offset or significantly weakened. This makes the finally formed polysilicon resistor matrix have very low RS mismatch, thereby ensuring that the analog circuit (such as a DAC) based on the resistor matrix can achieve the high precision and high performance required by the design, such as improving linearity, reducing distortion, improving yield, etc.

[0047] The present application also provides a polysilicon thin-film resistor matrix. The polysilicon thin-film resistor matrix is the result of being designed and manufactured using the above method, or has corresponding structural features.

[0048] The polysilicon thin-film resistor matrix includes a plurality of polysilicon thin-film resistors.

[0049] Among them, based on the position of the polysilicon thin-film resistor in the polysilicon thin-film resistor matrix, the polysilicon thin-film resistor has different predetermined critical dimensions;

[0050] And the different predetermined critical dimensions are configured to reduce the thin-film resistance mismatch between the plurality of polysilicon thin-film resistors after performing a double scanning laser spike annealing treatment from at least two symmetric directions on the polysilicon thin-film resistor matrix. This structural feature is the key to achieving low RS mismatch.

[0051] In some embodiments, the critical dimension of the polysilicon thin layer resistors in the outer region of the polysilicon thin layer resistor matrix is different from the critical dimension of the polysilicon thin layer resistors in the inner region. This design of different CD in the inner and outer regions directly reflects the design idea of compensating the position effect of the LSA process.

[0052] In some embodiments, the critical dimension of the polysilicon thin layer resistors presents a decreasing trend from the outer region to the inner region of the polysilicon thin layer resistor matrix. This specific CD gradient distribution is a preferred way to achieve accurate compensation, which cooperates with the symmetric double scanning LSA process to ensure the high consistency of the resistance values in the matrix, so that the resistance matrix is particularly suitable for precise analog circuit applications with high requirements for matching accuracy.

[0053] In summary, the present application effectively solves the problem of mismatch of the polysilicon resistor matrix RS after LSA activation by innovatively combining the double scanning direction optimization of the LSA process and the compensatory resistance size design based on position, and provides a valuable technical solution for the design and manufacture of high-performance analog integrated circuits.

[0054] It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the present application in a schematic manner, and only show the components related to the present application in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be randomly changed in shape, number and proportion, and the layout pattern of the components may be more complex.

[0055] The above embodiments only illustratively explain the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for designing a polysilicon thin film resistor matrix, characterized in that: At least: Step 1: designing the structure of the polysilicon thin layer resistor matrix, wherein the polysilicon thin layer resistors are set to have different predetermined critical dimensions based on the positions of the polysilicon thin layer resistors within the polysilicon thin layer resistor matrix; Step 2: performing laser spike annealing on the polysilicon thin film resistor matrix, wherein the laser spike annealing adopts a double scanning method from at least two symmetrical directions.

2. The method for designing a polysilicon thin film resistor matrix according to claim 1, wherein: In step one, the different predetermined critical dimensions are configured to compensate for sheet resistance variations introduced by the laser spike annealing process that are related to positions of the polysilicon sheet resistors within the polysilicon sheet resistor matrix.

3. The method for designing a polysilicon sheet resistor matrix according to claim 1 or 2, wherein: In step 1, the critical dimensions of the polysilicon thin film resistors located in the outer region of the polysilicon thin film resistor matrix are set to be different from the critical dimensions of the polysilicon thin film resistors located in the inner region.

4. The method for designing a polysilicon sheet resistor matrix according to claim 3, wherein: In step 1, the critical dimensions of the polysilicon thin film resistors decrease from the outer region to the inner region of the polysilicon thin film resistor matrix.

5. The method for designing a polysilicon thin film resistor matrix according to claim 1, wherein: In step 2, the at least two symmetric directions are two directions that form an angle of 180 degrees with each other.

6. The method for designing a polysilicon thin film resistor matrix according to claim 5, wherein: In step 2, the at least two symmetric directions are a 45-degree direction and a 225-degree direction.

7. The method for designing a polysilicon thin film resistor matrix according to claim 1, wherein: The method aims to reduce the sheet resistance mismatch between different polysilicon sheet resistors in the polysilicon sheet resistor matrix after the laser spike annealing process.

8. A polysilicon thin film resistor matrix, characterized in that: include: multiple polysilicon sheet resistors; wherein the polysilicon thin sheet resistors have different predetermined critical dimensions based on positions of the polysilicon thin sheet resistors within the polysilicon thin sheet resistor matrix; Furthermore, the different predetermined critical dimensions are configured to reduce sheet resistance mismatch among the plurality of polysilicon sheet resistors after performing a double scanning laser spike annealing process on the polysilicon sheet resistor matrix from at least two symmetric directions.

9. The polysilicon thin film resistor matrix according to claim 8, characterized in that: The critical dimensions of the polysilicon thin film resistors located in the outer region of the polysilicon thin film resistor matrix are different from the critical dimensions of the polysilicon thin film resistors located in the inner region.

10. The polysilicon thin film resistor matrix according to claim 9, characterized in that: The critical dimensions of the polysilicon thin film resistors decrease from the outer circle area to the inner circle area of ​​the polysilicon thin film resistor matrix.

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